1 /*- 2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 3 * Copyright (c) 2004-2005 Atheros Communications, Inc. 4 * Copyright (c) 2006 Devicescape Software, Inc. 5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com> 6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu> 7 * 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 18 * redistribution must be conditioned upon including a substantially 19 * similar Disclaimer requirement for further binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * Alternatively, this software may be distributed under the terms of the 25 * GNU General Public License ("GPL") version 2 as published by the Free 26 * Software Foundation. 27 * 28 * NO WARRANTY 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 39 * THE POSSIBILITY OF SUCH DAMAGES. 40 * 41 */ 42 43 #include <linux/module.h> 44 #include <linux/delay.h> 45 #include <linux/dma-mapping.h> 46 #include <linux/hardirq.h> 47 #include <linux/if.h> 48 #include <linux/io.h> 49 #include <linux/netdevice.h> 50 #include <linux/cache.h> 51 #include <linux/ethtool.h> 52 #include <linux/uaccess.h> 53 #include <linux/slab.h> 54 #include <linux/etherdevice.h> 55 56 #include <net/ieee80211_radiotap.h> 57 58 #include <asm/unaligned.h> 59 60 #include "base.h" 61 #include "reg.h" 62 #include "debug.h" 63 #include "ani.h" 64 65 #define CREATE_TRACE_POINTS 66 #include "trace.h" 67 68 int ath5k_modparam_nohwcrypt; 69 module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO); 70 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 71 72 static int modparam_all_channels; 73 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO); 74 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use."); 75 76 static int modparam_fastchanswitch; 77 module_param_named(fastchanswitch, modparam_fastchanswitch, bool, S_IRUGO); 78 MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios."); 79 80 81 /* Module info */ 82 MODULE_AUTHOR("Jiri Slaby"); 83 MODULE_AUTHOR("Nick Kossifidis"); 84 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards."); 85 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards"); 86 MODULE_LICENSE("Dual BSD/GPL"); 87 88 static int ath5k_init(struct ieee80211_hw *hw); 89 static int ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan, 90 bool skip_pcu); 91 92 /* Known SREVs */ 93 static const struct ath5k_srev_name srev_names[] = { 94 #ifdef CONFIG_ATHEROS_AR231X 95 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 }, 96 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 }, 97 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 }, 98 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 }, 99 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 }, 100 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 }, 101 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 }, 102 #else 103 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 }, 104 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 }, 105 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A }, 106 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B }, 107 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 }, 108 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 }, 109 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 }, 110 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A }, 111 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 }, 112 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 }, 113 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 }, 114 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 }, 115 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 }, 116 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 }, 117 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 }, 118 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 }, 119 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 }, 120 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 }, 121 #endif 122 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN }, 123 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, 124 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, 125 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A }, 126 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, 127 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, 128 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, 129 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B }, 130 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, 131 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, 132 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B }, 133 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 }, 134 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 }, 135 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 }, 136 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 }, 137 #ifdef CONFIG_ATHEROS_AR231X 138 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 }, 139 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 }, 140 #endif 141 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, 142 }; 143 144 static const struct ieee80211_rate ath5k_rates[] = { 145 { .bitrate = 10, 146 .hw_value = ATH5K_RATE_CODE_1M, }, 147 { .bitrate = 20, 148 .hw_value = ATH5K_RATE_CODE_2M, 149 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE, 150 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 151 { .bitrate = 55, 152 .hw_value = ATH5K_RATE_CODE_5_5M, 153 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE, 154 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 155 { .bitrate = 110, 156 .hw_value = ATH5K_RATE_CODE_11M, 157 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE, 158 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 159 { .bitrate = 60, 160 .hw_value = ATH5K_RATE_CODE_6M, 161 .flags = 0 }, 162 { .bitrate = 90, 163 .hw_value = ATH5K_RATE_CODE_9M, 164 .flags = 0 }, 165 { .bitrate = 120, 166 .hw_value = ATH5K_RATE_CODE_12M, 167 .flags = 0 }, 168 { .bitrate = 180, 169 .hw_value = ATH5K_RATE_CODE_18M, 170 .flags = 0 }, 171 { .bitrate = 240, 172 .hw_value = ATH5K_RATE_CODE_24M, 173 .flags = 0 }, 174 { .bitrate = 360, 175 .hw_value = ATH5K_RATE_CODE_36M, 176 .flags = 0 }, 177 { .bitrate = 480, 178 .hw_value = ATH5K_RATE_CODE_48M, 179 .flags = 0 }, 180 { .bitrate = 540, 181 .hw_value = ATH5K_RATE_CODE_54M, 182 .flags = 0 }, 183 /* XR missing */ 184 }; 185 186 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp) 187 { 188 u64 tsf = ath5k_hw_get_tsf64(ah); 189 190 if ((tsf & 0x7fff) < rstamp) 191 tsf -= 0x8000; 192 193 return (tsf & ~0x7fff) | rstamp; 194 } 195 196 const char * 197 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val) 198 { 199 const char *name = "xxxxx"; 200 unsigned int i; 201 202 for (i = 0; i < ARRAY_SIZE(srev_names); i++) { 203 if (srev_names[i].sr_type != type) 204 continue; 205 206 if ((val & 0xf0) == srev_names[i].sr_val) 207 name = srev_names[i].sr_name; 208 209 if ((val & 0xff) == srev_names[i].sr_val) { 210 name = srev_names[i].sr_name; 211 break; 212 } 213 } 214 215 return name; 216 } 217 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset) 218 { 219 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; 220 return ath5k_hw_reg_read(ah, reg_offset); 221 } 222 223 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) 224 { 225 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; 226 ath5k_hw_reg_write(ah, val, reg_offset); 227 } 228 229 static const struct ath_ops ath5k_common_ops = { 230 .read = ath5k_ioread32, 231 .write = ath5k_iowrite32, 232 }; 233 234 /***********************\ 235 * Driver Initialization * 236 \***********************/ 237 238 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) 239 { 240 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 241 struct ath5k_softc *sc = hw->priv; 242 struct ath_regulatory *regulatory = ath5k_hw_regulatory(sc->ah); 243 244 return ath_reg_notifier_apply(wiphy, request, regulatory); 245 } 246 247 /********************\ 248 * Channel/mode setup * 249 \********************/ 250 251 /* 252 * Returns true for the channel numbers used without all_channels modparam. 253 */ 254 static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band) 255 { 256 if (band == IEEE80211_BAND_2GHZ && chan <= 14) 257 return true; 258 259 return /* UNII 1,2 */ 260 (((chan & 3) == 0 && chan >= 36 && chan <= 64) || 261 /* midband */ 262 ((chan & 3) == 0 && chan >= 100 && chan <= 140) || 263 /* UNII-3 */ 264 ((chan & 3) == 1 && chan >= 149 && chan <= 165) || 265 /* 802.11j 5.030-5.080 GHz (20MHz) */ 266 (chan == 8 || chan == 12 || chan == 16) || 267 /* 802.11j 4.9GHz (20MHz) */ 268 (chan == 184 || chan == 188 || chan == 192 || chan == 196)); 269 } 270 271 static unsigned int 272 ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels, 273 unsigned int mode, unsigned int max) 274 { 275 unsigned int count, size, chfreq, freq, ch; 276 enum ieee80211_band band; 277 278 switch (mode) { 279 case AR5K_MODE_11A: 280 /* 1..220, but 2GHz frequencies are filtered by check_channel */ 281 size = 220; 282 chfreq = CHANNEL_5GHZ; 283 band = IEEE80211_BAND_5GHZ; 284 break; 285 case AR5K_MODE_11B: 286 case AR5K_MODE_11G: 287 size = 26; 288 chfreq = CHANNEL_2GHZ; 289 band = IEEE80211_BAND_2GHZ; 290 break; 291 default: 292 ATH5K_WARN(ah->ah_sc, "bad mode, not copying channels\n"); 293 return 0; 294 } 295 296 count = 0; 297 for (ch = 1; ch <= size && count < max; ch++) { 298 freq = ieee80211_channel_to_frequency(ch, band); 299 300 if (freq == 0) /* mapping failed - not a standard channel */ 301 continue; 302 303 /* Check if channel is supported by the chipset */ 304 if (!ath5k_channel_ok(ah, freq, chfreq)) 305 continue; 306 307 if (!modparam_all_channels && 308 !ath5k_is_standard_channel(ch, band)) 309 continue; 310 311 /* Write channel info and increment counter */ 312 channels[count].center_freq = freq; 313 channels[count].band = band; 314 switch (mode) { 315 case AR5K_MODE_11A: 316 case AR5K_MODE_11G: 317 channels[count].hw_value = chfreq | CHANNEL_OFDM; 318 break; 319 case AR5K_MODE_11B: 320 channels[count].hw_value = CHANNEL_B; 321 } 322 323 count++; 324 } 325 326 return count; 327 } 328 329 static void 330 ath5k_setup_rate_idx(struct ath5k_softc *sc, struct ieee80211_supported_band *b) 331 { 332 u8 i; 333 334 for (i = 0; i < AR5K_MAX_RATES; i++) 335 sc->rate_idx[b->band][i] = -1; 336 337 for (i = 0; i < b->n_bitrates; i++) { 338 sc->rate_idx[b->band][b->bitrates[i].hw_value] = i; 339 if (b->bitrates[i].hw_value_short) 340 sc->rate_idx[b->band][b->bitrates[i].hw_value_short] = i; 341 } 342 } 343 344 static int 345 ath5k_setup_bands(struct ieee80211_hw *hw) 346 { 347 struct ath5k_softc *sc = hw->priv; 348 struct ath5k_hw *ah = sc->ah; 349 struct ieee80211_supported_band *sband; 350 int max_c, count_c = 0; 351 int i; 352 353 BUILD_BUG_ON(ARRAY_SIZE(sc->sbands) < IEEE80211_NUM_BANDS); 354 max_c = ARRAY_SIZE(sc->channels); 355 356 /* 2GHz band */ 357 sband = &sc->sbands[IEEE80211_BAND_2GHZ]; 358 sband->band = IEEE80211_BAND_2GHZ; 359 sband->bitrates = &sc->rates[IEEE80211_BAND_2GHZ][0]; 360 361 if (test_bit(AR5K_MODE_11G, sc->ah->ah_capabilities.cap_mode)) { 362 /* G mode */ 363 memcpy(sband->bitrates, &ath5k_rates[0], 364 sizeof(struct ieee80211_rate) * 12); 365 sband->n_bitrates = 12; 366 367 sband->channels = sc->channels; 368 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 369 AR5K_MODE_11G, max_c); 370 371 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; 372 count_c = sband->n_channels; 373 max_c -= count_c; 374 } else if (test_bit(AR5K_MODE_11B, sc->ah->ah_capabilities.cap_mode)) { 375 /* B mode */ 376 memcpy(sband->bitrates, &ath5k_rates[0], 377 sizeof(struct ieee80211_rate) * 4); 378 sband->n_bitrates = 4; 379 380 /* 5211 only supports B rates and uses 4bit rate codes 381 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B) 382 * fix them up here: 383 */ 384 if (ah->ah_version == AR5K_AR5211) { 385 for (i = 0; i < 4; i++) { 386 sband->bitrates[i].hw_value = 387 sband->bitrates[i].hw_value & 0xF; 388 sband->bitrates[i].hw_value_short = 389 sband->bitrates[i].hw_value_short & 0xF; 390 } 391 } 392 393 sband->channels = sc->channels; 394 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 395 AR5K_MODE_11B, max_c); 396 397 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; 398 count_c = sband->n_channels; 399 max_c -= count_c; 400 } 401 ath5k_setup_rate_idx(sc, sband); 402 403 /* 5GHz band, A mode */ 404 if (test_bit(AR5K_MODE_11A, sc->ah->ah_capabilities.cap_mode)) { 405 sband = &sc->sbands[IEEE80211_BAND_5GHZ]; 406 sband->band = IEEE80211_BAND_5GHZ; 407 sband->bitrates = &sc->rates[IEEE80211_BAND_5GHZ][0]; 408 409 memcpy(sband->bitrates, &ath5k_rates[4], 410 sizeof(struct ieee80211_rate) * 8); 411 sband->n_bitrates = 8; 412 413 sband->channels = &sc->channels[count_c]; 414 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 415 AR5K_MODE_11A, max_c); 416 417 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband; 418 } 419 ath5k_setup_rate_idx(sc, sband); 420 421 ath5k_debug_dump_bands(sc); 422 423 return 0; 424 } 425 426 /* 427 * Set/change channels. We always reset the chip. 428 * To accomplish this we must first cleanup any pending DMA, 429 * then restart stuff after a la ath5k_init. 430 * 431 * Called with sc->lock. 432 */ 433 int 434 ath5k_chan_set(struct ath5k_softc *sc, struct ieee80211_channel *chan) 435 { 436 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 437 "channel set, resetting (%u -> %u MHz)\n", 438 sc->curchan->center_freq, chan->center_freq); 439 440 /* 441 * To switch channels clear any pending DMA operations; 442 * wait long enough for the RX fifo to drain, reset the 443 * hardware at the new frequency, and then re-enable 444 * the relevant bits of the h/w. 445 */ 446 return ath5k_reset(sc, chan, true); 447 } 448 449 void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 450 { 451 struct ath5k_vif_iter_data *iter_data = data; 452 int i; 453 struct ath5k_vif *avf = (void *)vif->drv_priv; 454 455 if (iter_data->hw_macaddr) 456 for (i = 0; i < ETH_ALEN; i++) 457 iter_data->mask[i] &= 458 ~(iter_data->hw_macaddr[i] ^ mac[i]); 459 460 if (!iter_data->found_active) { 461 iter_data->found_active = true; 462 memcpy(iter_data->active_mac, mac, ETH_ALEN); 463 } 464 465 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr) 466 if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0) 467 iter_data->need_set_hw_addr = false; 468 469 if (!iter_data->any_assoc) { 470 if (avf->assoc) 471 iter_data->any_assoc = true; 472 } 473 474 /* Calculate combined mode - when APs are active, operate in AP mode. 475 * Otherwise use the mode of the new interface. This can currently 476 * only deal with combinations of APs and STAs. Only one ad-hoc 477 * interfaces is allowed. 478 */ 479 if (avf->opmode == NL80211_IFTYPE_AP) 480 iter_data->opmode = NL80211_IFTYPE_AP; 481 else { 482 if (avf->opmode == NL80211_IFTYPE_STATION) 483 iter_data->n_stas++; 484 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED) 485 iter_data->opmode = avf->opmode; 486 } 487 } 488 489 void 490 ath5k_update_bssid_mask_and_opmode(struct ath5k_softc *sc, 491 struct ieee80211_vif *vif) 492 { 493 struct ath_common *common = ath5k_hw_common(sc->ah); 494 struct ath5k_vif_iter_data iter_data; 495 u32 rfilt; 496 497 /* 498 * Use the hardware MAC address as reference, the hardware uses it 499 * together with the BSSID mask when matching addresses. 500 */ 501 iter_data.hw_macaddr = common->macaddr; 502 memset(&iter_data.mask, 0xff, ETH_ALEN); 503 iter_data.found_active = false; 504 iter_data.need_set_hw_addr = true; 505 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED; 506 iter_data.n_stas = 0; 507 508 if (vif) 509 ath5k_vif_iter(&iter_data, vif->addr, vif); 510 511 /* Get list of all active MAC addresses */ 512 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath5k_vif_iter, 513 &iter_data); 514 memcpy(sc->bssidmask, iter_data.mask, ETH_ALEN); 515 516 sc->opmode = iter_data.opmode; 517 if (sc->opmode == NL80211_IFTYPE_UNSPECIFIED) 518 /* Nothing active, default to station mode */ 519 sc->opmode = NL80211_IFTYPE_STATION; 520 521 ath5k_hw_set_opmode(sc->ah, sc->opmode); 522 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n", 523 sc->opmode, ath_opmode_to_string(sc->opmode)); 524 525 if (iter_data.need_set_hw_addr && iter_data.found_active) 526 ath5k_hw_set_lladdr(sc->ah, iter_data.active_mac); 527 528 if (ath5k_hw_hasbssidmask(sc->ah)) 529 ath5k_hw_set_bssid_mask(sc->ah, sc->bssidmask); 530 531 /* Set up RX Filter */ 532 if (iter_data.n_stas > 1) { 533 /* If you have multiple STA interfaces connected to 534 * different APs, ARPs are not received (most of the time?) 535 * Enabling PROMISC appears to fix that problem. 536 */ 537 sc->filter_flags |= AR5K_RX_FILTER_PROM; 538 } 539 540 rfilt = sc->filter_flags; 541 ath5k_hw_set_rx_filter(sc->ah, rfilt); 542 ATH5K_DBG(sc, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt); 543 } 544 545 static inline int 546 ath5k_hw_to_driver_rix(struct ath5k_softc *sc, int hw_rix) 547 { 548 int rix; 549 550 /* return base rate on errors */ 551 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES, 552 "hw_rix out of bounds: %x\n", hw_rix)) 553 return 0; 554 555 rix = sc->rate_idx[sc->curchan->band][hw_rix]; 556 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix)) 557 rix = 0; 558 559 return rix; 560 } 561 562 /***************\ 563 * Buffers setup * 564 \***************/ 565 566 static 567 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_softc *sc, dma_addr_t *skb_addr) 568 { 569 struct ath_common *common = ath5k_hw_common(sc->ah); 570 struct sk_buff *skb; 571 572 /* 573 * Allocate buffer with headroom_needed space for the 574 * fake physical layer header at the start. 575 */ 576 skb = ath_rxbuf_alloc(common, 577 common->rx_bufsize, 578 GFP_ATOMIC); 579 580 if (!skb) { 581 ATH5K_ERR(sc, "can't alloc skbuff of size %u\n", 582 common->rx_bufsize); 583 return NULL; 584 } 585 586 *skb_addr = dma_map_single(sc->dev, 587 skb->data, common->rx_bufsize, 588 DMA_FROM_DEVICE); 589 590 if (unlikely(dma_mapping_error(sc->dev, *skb_addr))) { 591 ATH5K_ERR(sc, "%s: DMA mapping failed\n", __func__); 592 dev_kfree_skb(skb); 593 return NULL; 594 } 595 return skb; 596 } 597 598 static int 599 ath5k_rxbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf) 600 { 601 struct ath5k_hw *ah = sc->ah; 602 struct sk_buff *skb = bf->skb; 603 struct ath5k_desc *ds; 604 int ret; 605 606 if (!skb) { 607 skb = ath5k_rx_skb_alloc(sc, &bf->skbaddr); 608 if (!skb) 609 return -ENOMEM; 610 bf->skb = skb; 611 } 612 613 /* 614 * Setup descriptors. For receive we always terminate 615 * the descriptor list with a self-linked entry so we'll 616 * not get overrun under high load (as can happen with a 617 * 5212 when ANI processing enables PHY error frames). 618 * 619 * To ensure the last descriptor is self-linked we create 620 * each descriptor as self-linked and add it to the end. As 621 * each additional descriptor is added the previous self-linked 622 * entry is "fixed" naturally. This should be safe even 623 * if DMA is happening. When processing RX interrupts we 624 * never remove/process the last, self-linked, entry on the 625 * descriptor list. This ensures the hardware always has 626 * someplace to write a new frame. 627 */ 628 ds = bf->desc; 629 ds->ds_link = bf->daddr; /* link to self */ 630 ds->ds_data = bf->skbaddr; 631 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0); 632 if (ret) { 633 ATH5K_ERR(sc, "%s: could not setup RX desc\n", __func__); 634 return ret; 635 } 636 637 if (sc->rxlink != NULL) 638 *sc->rxlink = bf->daddr; 639 sc->rxlink = &ds->ds_link; 640 return 0; 641 } 642 643 static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb) 644 { 645 struct ieee80211_hdr *hdr; 646 enum ath5k_pkt_type htype; 647 __le16 fc; 648 649 hdr = (struct ieee80211_hdr *)skb->data; 650 fc = hdr->frame_control; 651 652 if (ieee80211_is_beacon(fc)) 653 htype = AR5K_PKT_TYPE_BEACON; 654 else if (ieee80211_is_probe_resp(fc)) 655 htype = AR5K_PKT_TYPE_PROBE_RESP; 656 else if (ieee80211_is_atim(fc)) 657 htype = AR5K_PKT_TYPE_ATIM; 658 else if (ieee80211_is_pspoll(fc)) 659 htype = AR5K_PKT_TYPE_PSPOLL; 660 else 661 htype = AR5K_PKT_TYPE_NORMAL; 662 663 return htype; 664 } 665 666 static int 667 ath5k_txbuf_setup(struct ath5k_softc *sc, struct ath5k_buf *bf, 668 struct ath5k_txq *txq, int padsize) 669 { 670 struct ath5k_hw *ah = sc->ah; 671 struct ath5k_desc *ds = bf->desc; 672 struct sk_buff *skb = bf->skb; 673 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 674 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID; 675 struct ieee80211_rate *rate; 676 unsigned int mrr_rate[3], mrr_tries[3]; 677 int i, ret; 678 u16 hw_rate; 679 u16 cts_rate = 0; 680 u16 duration = 0; 681 u8 rc_flags; 682 683 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; 684 685 /* XXX endianness */ 686 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len, 687 DMA_TO_DEVICE); 688 689 rate = ieee80211_get_tx_rate(sc->hw, info); 690 if (!rate) { 691 ret = -EINVAL; 692 goto err_unmap; 693 } 694 695 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 696 flags |= AR5K_TXDESC_NOACK; 697 698 rc_flags = info->control.rates[0].flags; 699 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ? 700 rate->hw_value_short : rate->hw_value; 701 702 pktlen = skb->len; 703 704 /* FIXME: If we are in g mode and rate is a CCK rate 705 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta 706 * from tx power (value is in dB units already) */ 707 if (info->control.hw_key) { 708 keyidx = info->control.hw_key->hw_key_idx; 709 pktlen += info->control.hw_key->icv_len; 710 } 711 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) { 712 flags |= AR5K_TXDESC_RTSENA; 713 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value; 714 duration = le16_to_cpu(ieee80211_rts_duration(sc->hw, 715 info->control.vif, pktlen, info)); 716 } 717 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 718 flags |= AR5K_TXDESC_CTSENA; 719 cts_rate = ieee80211_get_rts_cts_rate(sc->hw, info)->hw_value; 720 duration = le16_to_cpu(ieee80211_ctstoself_duration(sc->hw, 721 info->control.vif, pktlen, info)); 722 } 723 ret = ah->ah_setup_tx_desc(ah, ds, pktlen, 724 ieee80211_get_hdrlen_from_skb(skb), padsize, 725 get_hw_packet_type(skb), 726 (sc->power_level * 2), 727 hw_rate, 728 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags, 729 cts_rate, duration); 730 if (ret) 731 goto err_unmap; 732 733 memset(mrr_rate, 0, sizeof(mrr_rate)); 734 memset(mrr_tries, 0, sizeof(mrr_tries)); 735 for (i = 0; i < 3; i++) { 736 rate = ieee80211_get_alt_retry_rate(sc->hw, info, i); 737 if (!rate) 738 break; 739 740 mrr_rate[i] = rate->hw_value; 741 mrr_tries[i] = info->control.rates[i + 1].count; 742 } 743 744 ath5k_hw_setup_mrr_tx_desc(ah, ds, 745 mrr_rate[0], mrr_tries[0], 746 mrr_rate[1], mrr_tries[1], 747 mrr_rate[2], mrr_tries[2]); 748 749 ds->ds_link = 0; 750 ds->ds_data = bf->skbaddr; 751 752 spin_lock_bh(&txq->lock); 753 list_add_tail(&bf->list, &txq->q); 754 txq->txq_len++; 755 if (txq->link == NULL) /* is this first packet? */ 756 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr); 757 else /* no, so only link it */ 758 *txq->link = bf->daddr; 759 760 txq->link = &ds->ds_link; 761 ath5k_hw_start_tx_dma(ah, txq->qnum); 762 mmiowb(); 763 spin_unlock_bh(&txq->lock); 764 765 return 0; 766 err_unmap: 767 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); 768 return ret; 769 } 770 771 /*******************\ 772 * Descriptors setup * 773 \*******************/ 774 775 static int 776 ath5k_desc_alloc(struct ath5k_softc *sc) 777 { 778 struct ath5k_desc *ds; 779 struct ath5k_buf *bf; 780 dma_addr_t da; 781 unsigned int i; 782 int ret; 783 784 /* allocate descriptors */ 785 sc->desc_len = sizeof(struct ath5k_desc) * 786 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1); 787 788 sc->desc = dma_alloc_coherent(sc->dev, sc->desc_len, 789 &sc->desc_daddr, GFP_KERNEL); 790 if (sc->desc == NULL) { 791 ATH5K_ERR(sc, "can't allocate descriptors\n"); 792 ret = -ENOMEM; 793 goto err; 794 } 795 ds = sc->desc; 796 da = sc->desc_daddr; 797 ATH5K_DBG(sc, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n", 798 ds, sc->desc_len, (unsigned long long)sc->desc_daddr); 799 800 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF, 801 sizeof(struct ath5k_buf), GFP_KERNEL); 802 if (bf == NULL) { 803 ATH5K_ERR(sc, "can't allocate bufptr\n"); 804 ret = -ENOMEM; 805 goto err_free; 806 } 807 sc->bufptr = bf; 808 809 INIT_LIST_HEAD(&sc->rxbuf); 810 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) { 811 bf->desc = ds; 812 bf->daddr = da; 813 list_add_tail(&bf->list, &sc->rxbuf); 814 } 815 816 INIT_LIST_HEAD(&sc->txbuf); 817 sc->txbuf_len = ATH_TXBUF; 818 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) { 819 bf->desc = ds; 820 bf->daddr = da; 821 list_add_tail(&bf->list, &sc->txbuf); 822 } 823 824 /* beacon buffers */ 825 INIT_LIST_HEAD(&sc->bcbuf); 826 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) { 827 bf->desc = ds; 828 bf->daddr = da; 829 list_add_tail(&bf->list, &sc->bcbuf); 830 } 831 832 return 0; 833 err_free: 834 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr); 835 err: 836 sc->desc = NULL; 837 return ret; 838 } 839 840 void 841 ath5k_txbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf) 842 { 843 BUG_ON(!bf); 844 if (!bf->skb) 845 return; 846 dma_unmap_single(sc->dev, bf->skbaddr, bf->skb->len, 847 DMA_TO_DEVICE); 848 dev_kfree_skb_any(bf->skb); 849 bf->skb = NULL; 850 bf->skbaddr = 0; 851 bf->desc->ds_data = 0; 852 } 853 854 void 855 ath5k_rxbuf_free_skb(struct ath5k_softc *sc, struct ath5k_buf *bf) 856 { 857 struct ath5k_hw *ah = sc->ah; 858 struct ath_common *common = ath5k_hw_common(ah); 859 860 BUG_ON(!bf); 861 if (!bf->skb) 862 return; 863 dma_unmap_single(sc->dev, bf->skbaddr, common->rx_bufsize, 864 DMA_FROM_DEVICE); 865 dev_kfree_skb_any(bf->skb); 866 bf->skb = NULL; 867 bf->skbaddr = 0; 868 bf->desc->ds_data = 0; 869 } 870 871 static void 872 ath5k_desc_free(struct ath5k_softc *sc) 873 { 874 struct ath5k_buf *bf; 875 876 list_for_each_entry(bf, &sc->txbuf, list) 877 ath5k_txbuf_free_skb(sc, bf); 878 list_for_each_entry(bf, &sc->rxbuf, list) 879 ath5k_rxbuf_free_skb(sc, bf); 880 list_for_each_entry(bf, &sc->bcbuf, list) 881 ath5k_txbuf_free_skb(sc, bf); 882 883 /* Free memory associated with all descriptors */ 884 dma_free_coherent(sc->dev, sc->desc_len, sc->desc, sc->desc_daddr); 885 sc->desc = NULL; 886 sc->desc_daddr = 0; 887 888 kfree(sc->bufptr); 889 sc->bufptr = NULL; 890 } 891 892 893 /**************\ 894 * Queues setup * 895 \**************/ 896 897 static struct ath5k_txq * 898 ath5k_txq_setup(struct ath5k_softc *sc, 899 int qtype, int subtype) 900 { 901 struct ath5k_hw *ah = sc->ah; 902 struct ath5k_txq *txq; 903 struct ath5k_txq_info qi = { 904 .tqi_subtype = subtype, 905 /* XXX: default values not correct for B and XR channels, 906 * but who cares? */ 907 .tqi_aifs = AR5K_TUNE_AIFS, 908 .tqi_cw_min = AR5K_TUNE_CWMIN, 909 .tqi_cw_max = AR5K_TUNE_CWMAX 910 }; 911 int qnum; 912 913 /* 914 * Enable interrupts only for EOL and DESC conditions. 915 * We mark tx descriptors to receive a DESC interrupt 916 * when a tx queue gets deep; otherwise we wait for the 917 * EOL to reap descriptors. Note that this is done to 918 * reduce interrupt load and this only defers reaping 919 * descriptors, never transmitting frames. Aside from 920 * reducing interrupts this also permits more concurrency. 921 * The only potential downside is if the tx queue backs 922 * up in which case the top half of the kernel may backup 923 * due to a lack of tx descriptors. 924 */ 925 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE | 926 AR5K_TXQ_FLAG_TXDESCINT_ENABLE; 927 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); 928 if (qnum < 0) { 929 /* 930 * NB: don't print a message, this happens 931 * normally on parts with too few tx queues 932 */ 933 return ERR_PTR(qnum); 934 } 935 if (qnum >= ARRAY_SIZE(sc->txqs)) { 936 ATH5K_ERR(sc, "hw qnum %u out of range, max %tu!\n", 937 qnum, ARRAY_SIZE(sc->txqs)); 938 ath5k_hw_release_tx_queue(ah, qnum); 939 return ERR_PTR(-EINVAL); 940 } 941 txq = &sc->txqs[qnum]; 942 if (!txq->setup) { 943 txq->qnum = qnum; 944 txq->link = NULL; 945 INIT_LIST_HEAD(&txq->q); 946 spin_lock_init(&txq->lock); 947 txq->setup = true; 948 txq->txq_len = 0; 949 txq->txq_max = ATH5K_TXQ_LEN_MAX; 950 txq->txq_poll_mark = false; 951 txq->txq_stuck = 0; 952 } 953 return &sc->txqs[qnum]; 954 } 955 956 static int 957 ath5k_beaconq_setup(struct ath5k_hw *ah) 958 { 959 struct ath5k_txq_info qi = { 960 /* XXX: default values not correct for B and XR channels, 961 * but who cares? */ 962 .tqi_aifs = AR5K_TUNE_AIFS, 963 .tqi_cw_min = AR5K_TUNE_CWMIN, 964 .tqi_cw_max = AR5K_TUNE_CWMAX, 965 /* NB: for dynamic turbo, don't enable any other interrupts */ 966 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE 967 }; 968 969 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); 970 } 971 972 static int 973 ath5k_beaconq_config(struct ath5k_softc *sc) 974 { 975 struct ath5k_hw *ah = sc->ah; 976 struct ath5k_txq_info qi; 977 int ret; 978 979 ret = ath5k_hw_get_tx_queueprops(ah, sc->bhalq, &qi); 980 if (ret) 981 goto err; 982 983 if (sc->opmode == NL80211_IFTYPE_AP || 984 sc->opmode == NL80211_IFTYPE_MESH_POINT) { 985 /* 986 * Always burst out beacon and CAB traffic 987 * (aifs = cwmin = cwmax = 0) 988 */ 989 qi.tqi_aifs = 0; 990 qi.tqi_cw_min = 0; 991 qi.tqi_cw_max = 0; 992 } else if (sc->opmode == NL80211_IFTYPE_ADHOC) { 993 /* 994 * Adhoc mode; backoff between 0 and (2 * cw_min). 995 */ 996 qi.tqi_aifs = 0; 997 qi.tqi_cw_min = 0; 998 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN; 999 } 1000 1001 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 1002 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n", 1003 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max); 1004 1005 ret = ath5k_hw_set_tx_queueprops(ah, sc->bhalq, &qi); 1006 if (ret) { 1007 ATH5K_ERR(sc, "%s: unable to update parameters for beacon " 1008 "hardware queue!\n", __func__); 1009 goto err; 1010 } 1011 ret = ath5k_hw_reset_tx_queue(ah, sc->bhalq); /* push to h/w */ 1012 if (ret) 1013 goto err; 1014 1015 /* reconfigure cabq with ready time to 80% of beacon_interval */ 1016 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); 1017 if (ret) 1018 goto err; 1019 1020 qi.tqi_ready_time = (sc->bintval * 80) / 100; 1021 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); 1022 if (ret) 1023 goto err; 1024 1025 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB); 1026 err: 1027 return ret; 1028 } 1029 1030 /** 1031 * ath5k_drain_tx_buffs - Empty tx buffers 1032 * 1033 * @sc The &struct ath5k_softc 1034 * 1035 * Empty tx buffers from all queues in preparation 1036 * of a reset or during shutdown. 1037 * 1038 * NB: this assumes output has been stopped and 1039 * we do not need to block ath5k_tx_tasklet 1040 */ 1041 static void 1042 ath5k_drain_tx_buffs(struct ath5k_softc *sc) 1043 { 1044 struct ath5k_txq *txq; 1045 struct ath5k_buf *bf, *bf0; 1046 int i; 1047 1048 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) { 1049 if (sc->txqs[i].setup) { 1050 txq = &sc->txqs[i]; 1051 spin_lock_bh(&txq->lock); 1052 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 1053 ath5k_debug_printtxbuf(sc, bf); 1054 1055 ath5k_txbuf_free_skb(sc, bf); 1056 1057 spin_lock_bh(&sc->txbuflock); 1058 list_move_tail(&bf->list, &sc->txbuf); 1059 sc->txbuf_len++; 1060 txq->txq_len--; 1061 spin_unlock_bh(&sc->txbuflock); 1062 } 1063 txq->link = NULL; 1064 txq->txq_poll_mark = false; 1065 spin_unlock_bh(&txq->lock); 1066 } 1067 } 1068 } 1069 1070 static void 1071 ath5k_txq_release(struct ath5k_softc *sc) 1072 { 1073 struct ath5k_txq *txq = sc->txqs; 1074 unsigned int i; 1075 1076 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++, txq++) 1077 if (txq->setup) { 1078 ath5k_hw_release_tx_queue(sc->ah, txq->qnum); 1079 txq->setup = false; 1080 } 1081 } 1082 1083 1084 /*************\ 1085 * RX Handling * 1086 \*************/ 1087 1088 /* 1089 * Enable the receive h/w following a reset. 1090 */ 1091 static int 1092 ath5k_rx_start(struct ath5k_softc *sc) 1093 { 1094 struct ath5k_hw *ah = sc->ah; 1095 struct ath_common *common = ath5k_hw_common(ah); 1096 struct ath5k_buf *bf; 1097 int ret; 1098 1099 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz); 1100 1101 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n", 1102 common->cachelsz, common->rx_bufsize); 1103 1104 spin_lock_bh(&sc->rxbuflock); 1105 sc->rxlink = NULL; 1106 list_for_each_entry(bf, &sc->rxbuf, list) { 1107 ret = ath5k_rxbuf_setup(sc, bf); 1108 if (ret != 0) { 1109 spin_unlock_bh(&sc->rxbuflock); 1110 goto err; 1111 } 1112 } 1113 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list); 1114 ath5k_hw_set_rxdp(ah, bf->daddr); 1115 spin_unlock_bh(&sc->rxbuflock); 1116 1117 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */ 1118 ath5k_update_bssid_mask_and_opmode(sc, NULL); /* set filters, etc. */ 1119 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ 1120 1121 return 0; 1122 err: 1123 return ret; 1124 } 1125 1126 /* 1127 * Disable the receive logic on PCU (DRU) 1128 * In preparation for a shutdown. 1129 * 1130 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop 1131 * does. 1132 */ 1133 static void 1134 ath5k_rx_stop(struct ath5k_softc *sc) 1135 { 1136 struct ath5k_hw *ah = sc->ah; 1137 1138 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ 1139 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */ 1140 1141 ath5k_debug_printrxbuffs(sc, ah); 1142 } 1143 1144 static unsigned int 1145 ath5k_rx_decrypted(struct ath5k_softc *sc, struct sk_buff *skb, 1146 struct ath5k_rx_status *rs) 1147 { 1148 struct ath5k_hw *ah = sc->ah; 1149 struct ath_common *common = ath5k_hw_common(ah); 1150 struct ieee80211_hdr *hdr = (void *)skb->data; 1151 unsigned int keyix, hlen; 1152 1153 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) && 1154 rs->rs_keyix != AR5K_RXKEYIX_INVALID) 1155 return RX_FLAG_DECRYPTED; 1156 1157 /* Apparently when a default key is used to decrypt the packet 1158 the hw does not set the index used to decrypt. In such cases 1159 get the index from the packet. */ 1160 hlen = ieee80211_hdrlen(hdr->frame_control); 1161 if (ieee80211_has_protected(hdr->frame_control) && 1162 !(rs->rs_status & AR5K_RXERR_DECRYPT) && 1163 skb->len >= hlen + 4) { 1164 keyix = skb->data[hlen + 3] >> 6; 1165 1166 if (test_bit(keyix, common->keymap)) 1167 return RX_FLAG_DECRYPTED; 1168 } 1169 1170 return 0; 1171 } 1172 1173 1174 static void 1175 ath5k_check_ibss_tsf(struct ath5k_softc *sc, struct sk_buff *skb, 1176 struct ieee80211_rx_status *rxs) 1177 { 1178 struct ath_common *common = ath5k_hw_common(sc->ah); 1179 u64 tsf, bc_tstamp; 1180 u32 hw_tu; 1181 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1182 1183 if (ieee80211_is_beacon(mgmt->frame_control) && 1184 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS && 1185 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) { 1186 /* 1187 * Received an IBSS beacon with the same BSSID. Hardware *must* 1188 * have updated the local TSF. We have to work around various 1189 * hardware bugs, though... 1190 */ 1191 tsf = ath5k_hw_get_tsf64(sc->ah); 1192 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp); 1193 hw_tu = TSF_TO_TU(tsf); 1194 1195 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 1196 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n", 1197 (unsigned long long)bc_tstamp, 1198 (unsigned long long)rxs->mactime, 1199 (unsigned long long)(rxs->mactime - bc_tstamp), 1200 (unsigned long long)tsf); 1201 1202 /* 1203 * Sometimes the HW will give us a wrong tstamp in the rx 1204 * status, causing the timestamp extension to go wrong. 1205 * (This seems to happen especially with beacon frames bigger 1206 * than 78 byte (incl. FCS)) 1207 * But we know that the receive timestamp must be later than the 1208 * timestamp of the beacon since HW must have synced to that. 1209 * 1210 * NOTE: here we assume mactime to be after the frame was 1211 * received, not like mac80211 which defines it at the start. 1212 */ 1213 if (bc_tstamp > rxs->mactime) { 1214 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 1215 "fixing mactime from %llx to %llx\n", 1216 (unsigned long long)rxs->mactime, 1217 (unsigned long long)tsf); 1218 rxs->mactime = tsf; 1219 } 1220 1221 /* 1222 * Local TSF might have moved higher than our beacon timers, 1223 * in that case we have to update them to continue sending 1224 * beacons. This also takes care of synchronizing beacon sending 1225 * times with other stations. 1226 */ 1227 if (hw_tu >= sc->nexttbtt) 1228 ath5k_beacon_update_timers(sc, bc_tstamp); 1229 1230 /* Check if the beacon timers are still correct, because a TSF 1231 * update might have created a window between them - for a 1232 * longer description see the comment of this function: */ 1233 if (!ath5k_hw_check_beacon_timers(sc->ah, sc->bintval)) { 1234 ath5k_beacon_update_timers(sc, bc_tstamp); 1235 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 1236 "fixed beacon timers after beacon receive\n"); 1237 } 1238 } 1239 } 1240 1241 static void 1242 ath5k_update_beacon_rssi(struct ath5k_softc *sc, struct sk_buff *skb, int rssi) 1243 { 1244 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1245 struct ath5k_hw *ah = sc->ah; 1246 struct ath_common *common = ath5k_hw_common(ah); 1247 1248 /* only beacons from our BSSID */ 1249 if (!ieee80211_is_beacon(mgmt->frame_control) || 1250 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0) 1251 return; 1252 1253 ewma_add(&ah->ah_beacon_rssi_avg, rssi); 1254 1255 /* in IBSS mode we should keep RSSI statistics per neighbour */ 1256 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */ 1257 } 1258 1259 /* 1260 * Compute padding position. skb must contain an IEEE 802.11 frame 1261 */ 1262 static int ath5k_common_padpos(struct sk_buff *skb) 1263 { 1264 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1265 __le16 frame_control = hdr->frame_control; 1266 int padpos = 24; 1267 1268 if (ieee80211_has_a4(frame_control)) 1269 padpos += ETH_ALEN; 1270 1271 if (ieee80211_is_data_qos(frame_control)) 1272 padpos += IEEE80211_QOS_CTL_LEN; 1273 1274 return padpos; 1275 } 1276 1277 /* 1278 * This function expects an 802.11 frame and returns the number of 1279 * bytes added, or -1 if we don't have enough header room. 1280 */ 1281 static int ath5k_add_padding(struct sk_buff *skb) 1282 { 1283 int padpos = ath5k_common_padpos(skb); 1284 int padsize = padpos & 3; 1285 1286 if (padsize && skb->len > padpos) { 1287 1288 if (skb_headroom(skb) < padsize) 1289 return -1; 1290 1291 skb_push(skb, padsize); 1292 memmove(skb->data, skb->data + padsize, padpos); 1293 return padsize; 1294 } 1295 1296 return 0; 1297 } 1298 1299 /* 1300 * The MAC header is padded to have 32-bit boundary if the 1301 * packet payload is non-zero. The general calculation for 1302 * padsize would take into account odd header lengths: 1303 * padsize = 4 - (hdrlen & 3); however, since only 1304 * even-length headers are used, padding can only be 0 or 2 1305 * bytes and we can optimize this a bit. We must not try to 1306 * remove padding from short control frames that do not have a 1307 * payload. 1308 * 1309 * This function expects an 802.11 frame and returns the number of 1310 * bytes removed. 1311 */ 1312 static int ath5k_remove_padding(struct sk_buff *skb) 1313 { 1314 int padpos = ath5k_common_padpos(skb); 1315 int padsize = padpos & 3; 1316 1317 if (padsize && skb->len >= padpos + padsize) { 1318 memmove(skb->data + padsize, skb->data, padpos); 1319 skb_pull(skb, padsize); 1320 return padsize; 1321 } 1322 1323 return 0; 1324 } 1325 1326 static void 1327 ath5k_receive_frame(struct ath5k_softc *sc, struct sk_buff *skb, 1328 struct ath5k_rx_status *rs) 1329 { 1330 struct ieee80211_rx_status *rxs; 1331 1332 ath5k_remove_padding(skb); 1333 1334 rxs = IEEE80211_SKB_RXCB(skb); 1335 1336 rxs->flag = 0; 1337 if (unlikely(rs->rs_status & AR5K_RXERR_MIC)) 1338 rxs->flag |= RX_FLAG_MMIC_ERROR; 1339 1340 /* 1341 * always extend the mac timestamp, since this information is 1342 * also needed for proper IBSS merging. 1343 * 1344 * XXX: it might be too late to do it here, since rs_tstamp is 1345 * 15bit only. that means TSF extension has to be done within 1346 * 32768usec (about 32ms). it might be necessary to move this to 1347 * the interrupt handler, like it is done in madwifi. 1348 * 1349 * Unfortunately we don't know when the hardware takes the rx 1350 * timestamp (beginning of phy frame, data frame, end of rx?). 1351 * The only thing we know is that it is hardware specific... 1352 * On AR5213 it seems the rx timestamp is at the end of the 1353 * frame, but I'm not sure. 1354 * 1355 * NOTE: mac80211 defines mactime at the beginning of the first 1356 * data symbol. Since we don't have any time references it's 1357 * impossible to comply to that. This affects IBSS merge only 1358 * right now, so it's not too bad... 1359 */ 1360 rxs->mactime = ath5k_extend_tsf(sc->ah, rs->rs_tstamp); 1361 rxs->flag |= RX_FLAG_MACTIME_MPDU; 1362 1363 rxs->freq = sc->curchan->center_freq; 1364 rxs->band = sc->curchan->band; 1365 1366 rxs->signal = sc->ah->ah_noise_floor + rs->rs_rssi; 1367 1368 rxs->antenna = rs->rs_antenna; 1369 1370 if (rs->rs_antenna > 0 && rs->rs_antenna < 5) 1371 sc->stats.antenna_rx[rs->rs_antenna]++; 1372 else 1373 sc->stats.antenna_rx[0]++; /* invalid */ 1374 1375 rxs->rate_idx = ath5k_hw_to_driver_rix(sc, rs->rs_rate); 1376 rxs->flag |= ath5k_rx_decrypted(sc, skb, rs); 1377 1378 if (rxs->rate_idx >= 0 && rs->rs_rate == 1379 sc->sbands[sc->curchan->band].bitrates[rxs->rate_idx].hw_value_short) 1380 rxs->flag |= RX_FLAG_SHORTPRE; 1381 1382 trace_ath5k_rx(sc, skb); 1383 1384 ath5k_update_beacon_rssi(sc, skb, rs->rs_rssi); 1385 1386 /* check beacons in IBSS mode */ 1387 if (sc->opmode == NL80211_IFTYPE_ADHOC) 1388 ath5k_check_ibss_tsf(sc, skb, rxs); 1389 1390 ieee80211_rx(sc->hw, skb); 1391 } 1392 1393 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not? 1394 * 1395 * Check if we want to further process this frame or not. Also update 1396 * statistics. Return true if we want this frame, false if not. 1397 */ 1398 static bool 1399 ath5k_receive_frame_ok(struct ath5k_softc *sc, struct ath5k_rx_status *rs) 1400 { 1401 sc->stats.rx_all_count++; 1402 sc->stats.rx_bytes_count += rs->rs_datalen; 1403 1404 if (unlikely(rs->rs_status)) { 1405 if (rs->rs_status & AR5K_RXERR_CRC) 1406 sc->stats.rxerr_crc++; 1407 if (rs->rs_status & AR5K_RXERR_FIFO) 1408 sc->stats.rxerr_fifo++; 1409 if (rs->rs_status & AR5K_RXERR_PHY) { 1410 sc->stats.rxerr_phy++; 1411 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32) 1412 sc->stats.rxerr_phy_code[rs->rs_phyerr]++; 1413 return false; 1414 } 1415 if (rs->rs_status & AR5K_RXERR_DECRYPT) { 1416 /* 1417 * Decrypt error. If the error occurred 1418 * because there was no hardware key, then 1419 * let the frame through so the upper layers 1420 * can process it. This is necessary for 5210 1421 * parts which have no way to setup a ``clear'' 1422 * key cache entry. 1423 * 1424 * XXX do key cache faulting 1425 */ 1426 sc->stats.rxerr_decrypt++; 1427 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID && 1428 !(rs->rs_status & AR5K_RXERR_CRC)) 1429 return true; 1430 } 1431 if (rs->rs_status & AR5K_RXERR_MIC) { 1432 sc->stats.rxerr_mic++; 1433 return true; 1434 } 1435 1436 /* reject any frames with non-crypto errors */ 1437 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT)) 1438 return false; 1439 } 1440 1441 if (unlikely(rs->rs_more)) { 1442 sc->stats.rxerr_jumbo++; 1443 return false; 1444 } 1445 return true; 1446 } 1447 1448 static void 1449 ath5k_set_current_imask(struct ath5k_softc *sc) 1450 { 1451 enum ath5k_int imask; 1452 unsigned long flags; 1453 1454 spin_lock_irqsave(&sc->irqlock, flags); 1455 imask = sc->imask; 1456 if (sc->rx_pending) 1457 imask &= ~AR5K_INT_RX_ALL; 1458 if (sc->tx_pending) 1459 imask &= ~AR5K_INT_TX_ALL; 1460 ath5k_hw_set_imr(sc->ah, imask); 1461 spin_unlock_irqrestore(&sc->irqlock, flags); 1462 } 1463 1464 static void 1465 ath5k_tasklet_rx(unsigned long data) 1466 { 1467 struct ath5k_rx_status rs = {}; 1468 struct sk_buff *skb, *next_skb; 1469 dma_addr_t next_skb_addr; 1470 struct ath5k_softc *sc = (void *)data; 1471 struct ath5k_hw *ah = sc->ah; 1472 struct ath_common *common = ath5k_hw_common(ah); 1473 struct ath5k_buf *bf; 1474 struct ath5k_desc *ds; 1475 int ret; 1476 1477 spin_lock(&sc->rxbuflock); 1478 if (list_empty(&sc->rxbuf)) { 1479 ATH5K_WARN(sc, "empty rx buf pool\n"); 1480 goto unlock; 1481 } 1482 do { 1483 bf = list_first_entry(&sc->rxbuf, struct ath5k_buf, list); 1484 BUG_ON(bf->skb == NULL); 1485 skb = bf->skb; 1486 ds = bf->desc; 1487 1488 /* bail if HW is still using self-linked descriptor */ 1489 if (ath5k_hw_get_rxdp(sc->ah) == bf->daddr) 1490 break; 1491 1492 ret = sc->ah->ah_proc_rx_desc(sc->ah, ds, &rs); 1493 if (unlikely(ret == -EINPROGRESS)) 1494 break; 1495 else if (unlikely(ret)) { 1496 ATH5K_ERR(sc, "error in processing rx descriptor\n"); 1497 sc->stats.rxerr_proc++; 1498 break; 1499 } 1500 1501 if (ath5k_receive_frame_ok(sc, &rs)) { 1502 next_skb = ath5k_rx_skb_alloc(sc, &next_skb_addr); 1503 1504 /* 1505 * If we can't replace bf->skb with a new skb under 1506 * memory pressure, just skip this packet 1507 */ 1508 if (!next_skb) 1509 goto next; 1510 1511 dma_unmap_single(sc->dev, bf->skbaddr, 1512 common->rx_bufsize, 1513 DMA_FROM_DEVICE); 1514 1515 skb_put(skb, rs.rs_datalen); 1516 1517 ath5k_receive_frame(sc, skb, &rs); 1518 1519 bf->skb = next_skb; 1520 bf->skbaddr = next_skb_addr; 1521 } 1522 next: 1523 list_move_tail(&bf->list, &sc->rxbuf); 1524 } while (ath5k_rxbuf_setup(sc, bf) == 0); 1525 unlock: 1526 spin_unlock(&sc->rxbuflock); 1527 sc->rx_pending = false; 1528 ath5k_set_current_imask(sc); 1529 } 1530 1531 1532 /*************\ 1533 * TX Handling * 1534 \*************/ 1535 1536 void 1537 ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb, 1538 struct ath5k_txq *txq) 1539 { 1540 struct ath5k_softc *sc = hw->priv; 1541 struct ath5k_buf *bf; 1542 unsigned long flags; 1543 int padsize; 1544 1545 trace_ath5k_tx(sc, skb, txq); 1546 1547 /* 1548 * The hardware expects the header padded to 4 byte boundaries. 1549 * If this is not the case, we add the padding after the header. 1550 */ 1551 padsize = ath5k_add_padding(skb); 1552 if (padsize < 0) { 1553 ATH5K_ERR(sc, "tx hdrlen not %%4: not enough" 1554 " headroom to pad"); 1555 goto drop_packet; 1556 } 1557 1558 if (txq->txq_len >= txq->txq_max && 1559 txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX) 1560 ieee80211_stop_queue(hw, txq->qnum); 1561 1562 spin_lock_irqsave(&sc->txbuflock, flags); 1563 if (list_empty(&sc->txbuf)) { 1564 ATH5K_ERR(sc, "no further txbuf available, dropping packet\n"); 1565 spin_unlock_irqrestore(&sc->txbuflock, flags); 1566 ieee80211_stop_queues(hw); 1567 goto drop_packet; 1568 } 1569 bf = list_first_entry(&sc->txbuf, struct ath5k_buf, list); 1570 list_del(&bf->list); 1571 sc->txbuf_len--; 1572 if (list_empty(&sc->txbuf)) 1573 ieee80211_stop_queues(hw); 1574 spin_unlock_irqrestore(&sc->txbuflock, flags); 1575 1576 bf->skb = skb; 1577 1578 if (ath5k_txbuf_setup(sc, bf, txq, padsize)) { 1579 bf->skb = NULL; 1580 spin_lock_irqsave(&sc->txbuflock, flags); 1581 list_add_tail(&bf->list, &sc->txbuf); 1582 sc->txbuf_len++; 1583 spin_unlock_irqrestore(&sc->txbuflock, flags); 1584 goto drop_packet; 1585 } 1586 return; 1587 1588 drop_packet: 1589 dev_kfree_skb_any(skb); 1590 } 1591 1592 static void 1593 ath5k_tx_frame_completed(struct ath5k_softc *sc, struct sk_buff *skb, 1594 struct ath5k_txq *txq, struct ath5k_tx_status *ts) 1595 { 1596 struct ieee80211_tx_info *info; 1597 u8 tries[3]; 1598 int i; 1599 1600 sc->stats.tx_all_count++; 1601 sc->stats.tx_bytes_count += skb->len; 1602 info = IEEE80211_SKB_CB(skb); 1603 1604 tries[0] = info->status.rates[0].count; 1605 tries[1] = info->status.rates[1].count; 1606 tries[2] = info->status.rates[2].count; 1607 1608 ieee80211_tx_info_clear_status(info); 1609 1610 for (i = 0; i < ts->ts_final_idx; i++) { 1611 struct ieee80211_tx_rate *r = 1612 &info->status.rates[i]; 1613 1614 r->count = tries[i]; 1615 } 1616 1617 info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry; 1618 info->status.rates[ts->ts_final_idx + 1].idx = -1; 1619 1620 if (unlikely(ts->ts_status)) { 1621 sc->stats.ack_fail++; 1622 if (ts->ts_status & AR5K_TXERR_FILT) { 1623 info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 1624 sc->stats.txerr_filt++; 1625 } 1626 if (ts->ts_status & AR5K_TXERR_XRETRY) 1627 sc->stats.txerr_retry++; 1628 if (ts->ts_status & AR5K_TXERR_FIFO) 1629 sc->stats.txerr_fifo++; 1630 } else { 1631 info->flags |= IEEE80211_TX_STAT_ACK; 1632 info->status.ack_signal = ts->ts_rssi; 1633 1634 /* count the successful attempt as well */ 1635 info->status.rates[ts->ts_final_idx].count++; 1636 } 1637 1638 /* 1639 * Remove MAC header padding before giving the frame 1640 * back to mac80211. 1641 */ 1642 ath5k_remove_padding(skb); 1643 1644 if (ts->ts_antenna > 0 && ts->ts_antenna < 5) 1645 sc->stats.antenna_tx[ts->ts_antenna]++; 1646 else 1647 sc->stats.antenna_tx[0]++; /* invalid */ 1648 1649 trace_ath5k_tx_complete(sc, skb, txq, ts); 1650 ieee80211_tx_status(sc->hw, skb); 1651 } 1652 1653 static void 1654 ath5k_tx_processq(struct ath5k_softc *sc, struct ath5k_txq *txq) 1655 { 1656 struct ath5k_tx_status ts = {}; 1657 struct ath5k_buf *bf, *bf0; 1658 struct ath5k_desc *ds; 1659 struct sk_buff *skb; 1660 int ret; 1661 1662 spin_lock(&txq->lock); 1663 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 1664 1665 txq->txq_poll_mark = false; 1666 1667 /* skb might already have been processed last time. */ 1668 if (bf->skb != NULL) { 1669 ds = bf->desc; 1670 1671 ret = sc->ah->ah_proc_tx_desc(sc->ah, ds, &ts); 1672 if (unlikely(ret == -EINPROGRESS)) 1673 break; 1674 else if (unlikely(ret)) { 1675 ATH5K_ERR(sc, 1676 "error %d while processing " 1677 "queue %u\n", ret, txq->qnum); 1678 break; 1679 } 1680 1681 skb = bf->skb; 1682 bf->skb = NULL; 1683 1684 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, 1685 DMA_TO_DEVICE); 1686 ath5k_tx_frame_completed(sc, skb, txq, &ts); 1687 } 1688 1689 /* 1690 * It's possible that the hardware can say the buffer is 1691 * completed when it hasn't yet loaded the ds_link from 1692 * host memory and moved on. 1693 * Always keep the last descriptor to avoid HW races... 1694 */ 1695 if (ath5k_hw_get_txdp(sc->ah, txq->qnum) != bf->daddr) { 1696 spin_lock(&sc->txbuflock); 1697 list_move_tail(&bf->list, &sc->txbuf); 1698 sc->txbuf_len++; 1699 txq->txq_len--; 1700 spin_unlock(&sc->txbuflock); 1701 } 1702 } 1703 spin_unlock(&txq->lock); 1704 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4) 1705 ieee80211_wake_queue(sc->hw, txq->qnum); 1706 } 1707 1708 static void 1709 ath5k_tasklet_tx(unsigned long data) 1710 { 1711 int i; 1712 struct ath5k_softc *sc = (void *)data; 1713 1714 for (i = 0; i < AR5K_NUM_TX_QUEUES; i++) 1715 if (sc->txqs[i].setup && (sc->ah->ah_txq_isr & BIT(i))) 1716 ath5k_tx_processq(sc, &sc->txqs[i]); 1717 1718 sc->tx_pending = false; 1719 ath5k_set_current_imask(sc); 1720 } 1721 1722 1723 /*****************\ 1724 * Beacon handling * 1725 \*****************/ 1726 1727 /* 1728 * Setup the beacon frame for transmit. 1729 */ 1730 static int 1731 ath5k_beacon_setup(struct ath5k_softc *sc, struct ath5k_buf *bf) 1732 { 1733 struct sk_buff *skb = bf->skb; 1734 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1735 struct ath5k_hw *ah = sc->ah; 1736 struct ath5k_desc *ds; 1737 int ret = 0; 1738 u8 antenna; 1739 u32 flags; 1740 const int padsize = 0; 1741 1742 bf->skbaddr = dma_map_single(sc->dev, skb->data, skb->len, 1743 DMA_TO_DEVICE); 1744 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] " 1745 "skbaddr %llx\n", skb, skb->data, skb->len, 1746 (unsigned long long)bf->skbaddr); 1747 1748 if (dma_mapping_error(sc->dev, bf->skbaddr)) { 1749 ATH5K_ERR(sc, "beacon DMA mapping failed\n"); 1750 return -EIO; 1751 } 1752 1753 ds = bf->desc; 1754 antenna = ah->ah_tx_ant; 1755 1756 flags = AR5K_TXDESC_NOACK; 1757 if (sc->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) { 1758 ds->ds_link = bf->daddr; /* self-linked */ 1759 flags |= AR5K_TXDESC_VEOL; 1760 } else 1761 ds->ds_link = 0; 1762 1763 /* 1764 * If we use multiple antennas on AP and use 1765 * the Sectored AP scenario, switch antenna every 1766 * 4 beacons to make sure everybody hears our AP. 1767 * When a client tries to associate, hw will keep 1768 * track of the tx antenna to be used for this client 1769 * automatically, based on ACKed packets. 1770 * 1771 * Note: AP still listens and transmits RTS on the 1772 * default antenna which is supposed to be an omni. 1773 * 1774 * Note2: On sectored scenarios it's possible to have 1775 * multiple antennas (1 omni -- the default -- and 14 1776 * sectors), so if we choose to actually support this 1777 * mode, we need to allow the user to set how many antennas 1778 * we have and tweak the code below to send beacons 1779 * on all of them. 1780 */ 1781 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP) 1782 antenna = sc->bsent & 4 ? 2 : 1; 1783 1784 1785 /* FIXME: If we are in g mode and rate is a CCK rate 1786 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta 1787 * from tx power (value is in dB units already) */ 1788 ds->ds_data = bf->skbaddr; 1789 ret = ah->ah_setup_tx_desc(ah, ds, skb->len, 1790 ieee80211_get_hdrlen_from_skb(skb), padsize, 1791 AR5K_PKT_TYPE_BEACON, (sc->power_level * 2), 1792 ieee80211_get_tx_rate(sc->hw, info)->hw_value, 1793 1, AR5K_TXKEYIX_INVALID, 1794 antenna, flags, 0, 0); 1795 if (ret) 1796 goto err_unmap; 1797 1798 return 0; 1799 err_unmap: 1800 dma_unmap_single(sc->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); 1801 return ret; 1802 } 1803 1804 /* 1805 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc, 1806 * this is called only once at config_bss time, for AP we do it every 1807 * SWBA interrupt so that the TIM will reflect buffered frames. 1808 * 1809 * Called with the beacon lock. 1810 */ 1811 int 1812 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1813 { 1814 int ret; 1815 struct ath5k_softc *sc = hw->priv; 1816 struct ath5k_vif *avf = (void *)vif->drv_priv; 1817 struct sk_buff *skb; 1818 1819 if (WARN_ON(!vif)) { 1820 ret = -EINVAL; 1821 goto out; 1822 } 1823 1824 skb = ieee80211_beacon_get(hw, vif); 1825 1826 if (!skb) { 1827 ret = -ENOMEM; 1828 goto out; 1829 } 1830 1831 ath5k_txbuf_free_skb(sc, avf->bbuf); 1832 avf->bbuf->skb = skb; 1833 ret = ath5k_beacon_setup(sc, avf->bbuf); 1834 if (ret) 1835 avf->bbuf->skb = NULL; 1836 out: 1837 return ret; 1838 } 1839 1840 /* 1841 * Transmit a beacon frame at SWBA. Dynamic updates to the 1842 * frame contents are done as needed and the slot time is 1843 * also adjusted based on current state. 1844 * 1845 * This is called from software irq context (beacontq tasklets) 1846 * or user context from ath5k_beacon_config. 1847 */ 1848 static void 1849 ath5k_beacon_send(struct ath5k_softc *sc) 1850 { 1851 struct ath5k_hw *ah = sc->ah; 1852 struct ieee80211_vif *vif; 1853 struct ath5k_vif *avf; 1854 struct ath5k_buf *bf; 1855 struct sk_buff *skb; 1856 1857 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "in beacon_send\n"); 1858 1859 /* 1860 * Check if the previous beacon has gone out. If 1861 * not, don't don't try to post another: skip this 1862 * period and wait for the next. Missed beacons 1863 * indicate a problem and should not occur. If we 1864 * miss too many consecutive beacons reset the device. 1865 */ 1866 if (unlikely(ath5k_hw_num_tx_pending(ah, sc->bhalq) != 0)) { 1867 sc->bmisscount++; 1868 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 1869 "missed %u consecutive beacons\n", sc->bmisscount); 1870 if (sc->bmisscount > 10) { /* NB: 10 is a guess */ 1871 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 1872 "stuck beacon time (%u missed)\n", 1873 sc->bmisscount); 1874 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 1875 "stuck beacon, resetting\n"); 1876 ieee80211_queue_work(sc->hw, &sc->reset_work); 1877 } 1878 return; 1879 } 1880 if (unlikely(sc->bmisscount != 0)) { 1881 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 1882 "resume beacon xmit after %u misses\n", 1883 sc->bmisscount); 1884 sc->bmisscount = 0; 1885 } 1886 1887 if ((sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) || 1888 sc->opmode == NL80211_IFTYPE_MESH_POINT) { 1889 u64 tsf = ath5k_hw_get_tsf64(ah); 1890 u32 tsftu = TSF_TO_TU(tsf); 1891 int slot = ((tsftu % sc->bintval) * ATH_BCBUF) / sc->bintval; 1892 vif = sc->bslot[(slot + 1) % ATH_BCBUF]; 1893 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 1894 "tsf %llx tsftu %x intval %u slot %u vif %p\n", 1895 (unsigned long long)tsf, tsftu, sc->bintval, slot, vif); 1896 } else /* only one interface */ 1897 vif = sc->bslot[0]; 1898 1899 if (!vif) 1900 return; 1901 1902 avf = (void *)vif->drv_priv; 1903 bf = avf->bbuf; 1904 if (unlikely(bf->skb == NULL || sc->opmode == NL80211_IFTYPE_STATION || 1905 sc->opmode == NL80211_IFTYPE_MONITOR)) { 1906 ATH5K_WARN(sc, "bf=%p bf_skb=%p\n", bf, bf ? bf->skb : NULL); 1907 return; 1908 } 1909 1910 /* 1911 * Stop any current dma and put the new frame on the queue. 1912 * This should never fail since we check above that no frames 1913 * are still pending on the queue. 1914 */ 1915 if (unlikely(ath5k_hw_stop_beacon_queue(ah, sc->bhalq))) { 1916 ATH5K_WARN(sc, "beacon queue %u didn't start/stop ?\n", sc->bhalq); 1917 /* NB: hw still stops DMA, so proceed */ 1918 } 1919 1920 /* refresh the beacon for AP or MESH mode */ 1921 if (sc->opmode == NL80211_IFTYPE_AP || 1922 sc->opmode == NL80211_IFTYPE_MESH_POINT) 1923 ath5k_beacon_update(sc->hw, vif); 1924 1925 trace_ath5k_tx(sc, bf->skb, &sc->txqs[sc->bhalq]); 1926 1927 ath5k_hw_set_txdp(ah, sc->bhalq, bf->daddr); 1928 ath5k_hw_start_tx_dma(ah, sc->bhalq); 1929 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n", 1930 sc->bhalq, (unsigned long long)bf->daddr, bf->desc); 1931 1932 skb = ieee80211_get_buffered_bc(sc->hw, vif); 1933 while (skb) { 1934 ath5k_tx_queue(sc->hw, skb, sc->cabq); 1935 1936 if (sc->cabq->txq_len >= sc->cabq->txq_max) 1937 break; 1938 1939 skb = ieee80211_get_buffered_bc(sc->hw, vif); 1940 } 1941 1942 sc->bsent++; 1943 } 1944 1945 /** 1946 * ath5k_beacon_update_timers - update beacon timers 1947 * 1948 * @sc: struct ath5k_softc pointer we are operating on 1949 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a 1950 * beacon timer update based on the current HW TSF. 1951 * 1952 * Calculate the next target beacon transmit time (TBTT) based on the timestamp 1953 * of a received beacon or the current local hardware TSF and write it to the 1954 * beacon timer registers. 1955 * 1956 * This is called in a variety of situations, e.g. when a beacon is received, 1957 * when a TSF update has been detected, but also when an new IBSS is created or 1958 * when we otherwise know we have to update the timers, but we keep it in this 1959 * function to have it all together in one place. 1960 */ 1961 void 1962 ath5k_beacon_update_timers(struct ath5k_softc *sc, u64 bc_tsf) 1963 { 1964 struct ath5k_hw *ah = sc->ah; 1965 u32 nexttbtt, intval, hw_tu, bc_tu; 1966 u64 hw_tsf; 1967 1968 intval = sc->bintval & AR5K_BEACON_PERIOD; 1969 if (sc->opmode == NL80211_IFTYPE_AP && sc->num_ap_vifs > 1) { 1970 intval /= ATH_BCBUF; /* staggered multi-bss beacons */ 1971 if (intval < 15) 1972 ATH5K_WARN(sc, "intval %u is too low, min 15\n", 1973 intval); 1974 } 1975 if (WARN_ON(!intval)) 1976 return; 1977 1978 /* beacon TSF converted to TU */ 1979 bc_tu = TSF_TO_TU(bc_tsf); 1980 1981 /* current TSF converted to TU */ 1982 hw_tsf = ath5k_hw_get_tsf64(ah); 1983 hw_tu = TSF_TO_TU(hw_tsf); 1984 1985 #define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3) 1986 /* We use FUDGE to make sure the next TBTT is ahead of the current TU. 1987 * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer 1988 * configuration we need to make sure it is bigger than that. */ 1989 1990 if (bc_tsf == -1) { 1991 /* 1992 * no beacons received, called internally. 1993 * just need to refresh timers based on HW TSF. 1994 */ 1995 nexttbtt = roundup(hw_tu + FUDGE, intval); 1996 } else if (bc_tsf == 0) { 1997 /* 1998 * no beacon received, probably called by ath5k_reset_tsf(). 1999 * reset TSF to start with 0. 2000 */ 2001 nexttbtt = intval; 2002 intval |= AR5K_BEACON_RESET_TSF; 2003 } else if (bc_tsf > hw_tsf) { 2004 /* 2005 * beacon received, SW merge happened but HW TSF not yet updated. 2006 * not possible to reconfigure timers yet, but next time we 2007 * receive a beacon with the same BSSID, the hardware will 2008 * automatically update the TSF and then we need to reconfigure 2009 * the timers. 2010 */ 2011 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2012 "need to wait for HW TSF sync\n"); 2013 return; 2014 } else { 2015 /* 2016 * most important case for beacon synchronization between STA. 2017 * 2018 * beacon received and HW TSF has been already updated by HW. 2019 * update next TBTT based on the TSF of the beacon, but make 2020 * sure it is ahead of our local TSF timer. 2021 */ 2022 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval); 2023 } 2024 #undef FUDGE 2025 2026 sc->nexttbtt = nexttbtt; 2027 2028 intval |= AR5K_BEACON_ENA; 2029 ath5k_hw_init_beacon(ah, nexttbtt, intval); 2030 2031 /* 2032 * debugging output last in order to preserve the time critical aspect 2033 * of this function 2034 */ 2035 if (bc_tsf == -1) 2036 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2037 "reconfigured timers based on HW TSF\n"); 2038 else if (bc_tsf == 0) 2039 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2040 "reset HW TSF and timers\n"); 2041 else 2042 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2043 "updated timers based on beacon TSF\n"); 2044 2045 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, 2046 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n", 2047 (unsigned long long) bc_tsf, 2048 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt); 2049 ATH5K_DBG_UNLIMIT(sc, ATH5K_DEBUG_BEACON, "intval %u %s %s\n", 2050 intval & AR5K_BEACON_PERIOD, 2051 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "", 2052 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : ""); 2053 } 2054 2055 /** 2056 * ath5k_beacon_config - Configure the beacon queues and interrupts 2057 * 2058 * @sc: struct ath5k_softc pointer we are operating on 2059 * 2060 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA 2061 * interrupts to detect TSF updates only. 2062 */ 2063 void 2064 ath5k_beacon_config(struct ath5k_softc *sc) 2065 { 2066 struct ath5k_hw *ah = sc->ah; 2067 unsigned long flags; 2068 2069 spin_lock_irqsave(&sc->block, flags); 2070 sc->bmisscount = 0; 2071 sc->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA); 2072 2073 if (sc->enable_beacon) { 2074 /* 2075 * In IBSS mode we use a self-linked tx descriptor and let the 2076 * hardware send the beacons automatically. We have to load it 2077 * only once here. 2078 * We use the SWBA interrupt only to keep track of the beacon 2079 * timers in order to detect automatic TSF updates. 2080 */ 2081 ath5k_beaconq_config(sc); 2082 2083 sc->imask |= AR5K_INT_SWBA; 2084 2085 if (sc->opmode == NL80211_IFTYPE_ADHOC) { 2086 if (ath5k_hw_hasveol(ah)) 2087 ath5k_beacon_send(sc); 2088 } else 2089 ath5k_beacon_update_timers(sc, -1); 2090 } else { 2091 ath5k_hw_stop_beacon_queue(sc->ah, sc->bhalq); 2092 } 2093 2094 ath5k_hw_set_imr(ah, sc->imask); 2095 mmiowb(); 2096 spin_unlock_irqrestore(&sc->block, flags); 2097 } 2098 2099 static void ath5k_tasklet_beacon(unsigned long data) 2100 { 2101 struct ath5k_softc *sc = (struct ath5k_softc *) data; 2102 2103 /* 2104 * Software beacon alert--time to send a beacon. 2105 * 2106 * In IBSS mode we use this interrupt just to 2107 * keep track of the next TBTT (target beacon 2108 * transmission time) in order to detect whether 2109 * automatic TSF updates happened. 2110 */ 2111 if (sc->opmode == NL80211_IFTYPE_ADHOC) { 2112 /* XXX: only if VEOL supported */ 2113 u64 tsf = ath5k_hw_get_tsf64(sc->ah); 2114 sc->nexttbtt += sc->bintval; 2115 ATH5K_DBG(sc, ATH5K_DEBUG_BEACON, 2116 "SWBA nexttbtt: %x hw_tu: %x " 2117 "TSF: %llx\n", 2118 sc->nexttbtt, 2119 TSF_TO_TU(tsf), 2120 (unsigned long long) tsf); 2121 } else { 2122 spin_lock(&sc->block); 2123 ath5k_beacon_send(sc); 2124 spin_unlock(&sc->block); 2125 } 2126 } 2127 2128 2129 /********************\ 2130 * Interrupt handling * 2131 \********************/ 2132 2133 static void 2134 ath5k_intr_calibration_poll(struct ath5k_hw *ah) 2135 { 2136 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) && 2137 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL)) { 2138 /* run ANI only when full calibration is not active */ 2139 ah->ah_cal_next_ani = jiffies + 2140 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI); 2141 tasklet_schedule(&ah->ah_sc->ani_tasklet); 2142 2143 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) { 2144 ah->ah_cal_next_full = jiffies + 2145 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL); 2146 tasklet_schedule(&ah->ah_sc->calib); 2147 } 2148 /* we could use SWI to generate enough interrupts to meet our 2149 * calibration interval requirements, if necessary: 2150 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */ 2151 } 2152 2153 static void 2154 ath5k_schedule_rx(struct ath5k_softc *sc) 2155 { 2156 sc->rx_pending = true; 2157 tasklet_schedule(&sc->rxtq); 2158 } 2159 2160 static void 2161 ath5k_schedule_tx(struct ath5k_softc *sc) 2162 { 2163 sc->tx_pending = true; 2164 tasklet_schedule(&sc->txtq); 2165 } 2166 2167 static irqreturn_t 2168 ath5k_intr(int irq, void *dev_id) 2169 { 2170 struct ath5k_softc *sc = dev_id; 2171 struct ath5k_hw *ah = sc->ah; 2172 enum ath5k_int status; 2173 unsigned int counter = 1000; 2174 2175 if (unlikely(test_bit(ATH_STAT_INVALID, sc->status) || 2176 ((ath5k_get_bus_type(ah) != ATH_AHB) && 2177 !ath5k_hw_is_intr_pending(ah)))) 2178 return IRQ_NONE; 2179 2180 do { 2181 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ 2182 ATH5K_DBG(sc, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n", 2183 status, sc->imask); 2184 if (unlikely(status & AR5K_INT_FATAL)) { 2185 /* 2186 * Fatal errors are unrecoverable. 2187 * Typically these are caused by DMA errors. 2188 */ 2189 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 2190 "fatal int, resetting\n"); 2191 ieee80211_queue_work(sc->hw, &sc->reset_work); 2192 } else if (unlikely(status & AR5K_INT_RXORN)) { 2193 /* 2194 * Receive buffers are full. Either the bus is busy or 2195 * the CPU is not fast enough to process all received 2196 * frames. 2197 * Older chipsets need a reset to come out of this 2198 * condition, but we treat it as RX for newer chips. 2199 * We don't know exactly which versions need a reset - 2200 * this guess is copied from the HAL. 2201 */ 2202 sc->stats.rxorn_intr++; 2203 if (ah->ah_mac_srev < AR5K_SREV_AR5212) { 2204 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 2205 "rx overrun, resetting\n"); 2206 ieee80211_queue_work(sc->hw, &sc->reset_work); 2207 } else 2208 ath5k_schedule_rx(sc); 2209 } else { 2210 if (status & AR5K_INT_SWBA) 2211 tasklet_hi_schedule(&sc->beacontq); 2212 2213 if (status & AR5K_INT_RXEOL) { 2214 /* 2215 * NB: the hardware should re-read the link when 2216 * RXE bit is written, but it doesn't work at 2217 * least on older hardware revs. 2218 */ 2219 sc->stats.rxeol_intr++; 2220 } 2221 if (status & AR5K_INT_TXURN) { 2222 /* bump tx trigger level */ 2223 ath5k_hw_update_tx_triglevel(ah, true); 2224 } 2225 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR)) 2226 ath5k_schedule_rx(sc); 2227 if (status & (AR5K_INT_TXOK | AR5K_INT_TXDESC 2228 | AR5K_INT_TXERR | AR5K_INT_TXEOL)) 2229 ath5k_schedule_tx(sc); 2230 if (status & AR5K_INT_BMISS) { 2231 /* TODO */ 2232 } 2233 if (status & AR5K_INT_MIB) { 2234 sc->stats.mib_intr++; 2235 ath5k_hw_update_mib_counters(ah); 2236 ath5k_ani_mib_intr(ah); 2237 } 2238 if (status & AR5K_INT_GPIO) 2239 tasklet_schedule(&sc->rf_kill.toggleq); 2240 2241 } 2242 2243 if (ath5k_get_bus_type(ah) == ATH_AHB) 2244 break; 2245 2246 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0); 2247 2248 if (sc->rx_pending || sc->tx_pending) 2249 ath5k_set_current_imask(sc); 2250 2251 if (unlikely(!counter)) 2252 ATH5K_WARN(sc, "too many interrupts, giving up for now\n"); 2253 2254 ath5k_intr_calibration_poll(ah); 2255 2256 return IRQ_HANDLED; 2257 } 2258 2259 /* 2260 * Periodically recalibrate the PHY to account 2261 * for temperature/environment changes. 2262 */ 2263 static void 2264 ath5k_tasklet_calibrate(unsigned long data) 2265 { 2266 struct ath5k_softc *sc = (void *)data; 2267 struct ath5k_hw *ah = sc->ah; 2268 2269 /* Only full calibration for now */ 2270 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL; 2271 2272 ATH5K_DBG(sc, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n", 2273 ieee80211_frequency_to_channel(sc->curchan->center_freq), 2274 sc->curchan->hw_value); 2275 2276 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) { 2277 /* 2278 * Rfgain is out of bounds, reset the chip 2279 * to load new gain values. 2280 */ 2281 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "calibration, resetting\n"); 2282 ieee80211_queue_work(sc->hw, &sc->reset_work); 2283 } 2284 if (ath5k_hw_phy_calibrate(ah, sc->curchan)) 2285 ATH5K_ERR(sc, "calibration of channel %u failed\n", 2286 ieee80211_frequency_to_channel( 2287 sc->curchan->center_freq)); 2288 2289 /* Noise floor calibration interrupts rx/tx path while I/Q calibration 2290 * doesn't. 2291 * TODO: We should stop TX here, so that it doesn't interfere. 2292 * Note that stopping the queues is not enough to stop TX! */ 2293 if (time_is_before_eq_jiffies(ah->ah_cal_next_nf)) { 2294 ah->ah_cal_next_nf = jiffies + 2295 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_NF); 2296 ath5k_hw_update_noise_floor(ah); 2297 } 2298 2299 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL; 2300 } 2301 2302 2303 static void 2304 ath5k_tasklet_ani(unsigned long data) 2305 { 2306 struct ath5k_softc *sc = (void *)data; 2307 struct ath5k_hw *ah = sc->ah; 2308 2309 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI; 2310 ath5k_ani_calibration(ah); 2311 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI; 2312 } 2313 2314 2315 static void 2316 ath5k_tx_complete_poll_work(struct work_struct *work) 2317 { 2318 struct ath5k_softc *sc = container_of(work, struct ath5k_softc, 2319 tx_complete_work.work); 2320 struct ath5k_txq *txq; 2321 int i; 2322 bool needreset = false; 2323 2324 mutex_lock(&sc->lock); 2325 2326 for (i = 0; i < ARRAY_SIZE(sc->txqs); i++) { 2327 if (sc->txqs[i].setup) { 2328 txq = &sc->txqs[i]; 2329 spin_lock_bh(&txq->lock); 2330 if (txq->txq_len > 1) { 2331 if (txq->txq_poll_mark) { 2332 ATH5K_DBG(sc, ATH5K_DEBUG_XMIT, 2333 "TX queue stuck %d\n", 2334 txq->qnum); 2335 needreset = true; 2336 txq->txq_stuck++; 2337 spin_unlock_bh(&txq->lock); 2338 break; 2339 } else { 2340 txq->txq_poll_mark = true; 2341 } 2342 } 2343 spin_unlock_bh(&txq->lock); 2344 } 2345 } 2346 2347 if (needreset) { 2348 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 2349 "TX queues stuck, resetting\n"); 2350 ath5k_reset(sc, NULL, true); 2351 } 2352 2353 mutex_unlock(&sc->lock); 2354 2355 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 2356 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); 2357 } 2358 2359 2360 /*************************\ 2361 * Initialization routines * 2362 \*************************/ 2363 2364 int __devinit 2365 ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops) 2366 { 2367 struct ieee80211_hw *hw = sc->hw; 2368 struct ath_common *common; 2369 int ret; 2370 int csz; 2371 2372 /* Initialize driver private data */ 2373 SET_IEEE80211_DEV(hw, sc->dev); 2374 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 2375 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | 2376 IEEE80211_HW_SIGNAL_DBM | 2377 IEEE80211_HW_REPORTS_TX_ACK_STATUS; 2378 2379 hw->wiphy->interface_modes = 2380 BIT(NL80211_IFTYPE_AP) | 2381 BIT(NL80211_IFTYPE_STATION) | 2382 BIT(NL80211_IFTYPE_ADHOC) | 2383 BIT(NL80211_IFTYPE_MESH_POINT); 2384 2385 /* both antennas can be configured as RX or TX */ 2386 hw->wiphy->available_antennas_tx = 0x3; 2387 hw->wiphy->available_antennas_rx = 0x3; 2388 2389 hw->extra_tx_headroom = 2; 2390 hw->channel_change_time = 5000; 2391 2392 /* 2393 * Mark the device as detached to avoid processing 2394 * interrupts until setup is complete. 2395 */ 2396 __set_bit(ATH_STAT_INVALID, sc->status); 2397 2398 sc->opmode = NL80211_IFTYPE_STATION; 2399 sc->bintval = 1000; 2400 mutex_init(&sc->lock); 2401 spin_lock_init(&sc->rxbuflock); 2402 spin_lock_init(&sc->txbuflock); 2403 spin_lock_init(&sc->block); 2404 spin_lock_init(&sc->irqlock); 2405 2406 /* Setup interrupt handler */ 2407 ret = request_irq(sc->irq, ath5k_intr, IRQF_SHARED, "ath", sc); 2408 if (ret) { 2409 ATH5K_ERR(sc, "request_irq failed\n"); 2410 goto err; 2411 } 2412 2413 /* If we passed the test, malloc an ath5k_hw struct */ 2414 sc->ah = kzalloc(sizeof(struct ath5k_hw), GFP_KERNEL); 2415 if (!sc->ah) { 2416 ret = -ENOMEM; 2417 ATH5K_ERR(sc, "out of memory\n"); 2418 goto err_irq; 2419 } 2420 2421 sc->ah->ah_sc = sc; 2422 sc->ah->ah_iobase = sc->iobase; 2423 common = ath5k_hw_common(sc->ah); 2424 common->ops = &ath5k_common_ops; 2425 common->bus_ops = bus_ops; 2426 common->ah = sc->ah; 2427 common->hw = hw; 2428 common->priv = sc; 2429 common->clockrate = 40; 2430 2431 /* 2432 * Cache line size is used to size and align various 2433 * structures used to communicate with the hardware. 2434 */ 2435 ath5k_read_cachesize(common, &csz); 2436 common->cachelsz = csz << 2; /* convert to bytes */ 2437 2438 spin_lock_init(&common->cc_lock); 2439 2440 /* Initialize device */ 2441 ret = ath5k_hw_init(sc); 2442 if (ret) 2443 goto err_free_ah; 2444 2445 /* set up multi-rate retry capabilities */ 2446 if (sc->ah->ah_version == AR5K_AR5212) { 2447 hw->max_rates = 4; 2448 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT, 2449 AR5K_INIT_RETRY_LONG); 2450 } 2451 2452 hw->vif_data_size = sizeof(struct ath5k_vif); 2453 2454 /* Finish private driver data initialization */ 2455 ret = ath5k_init(hw); 2456 if (ret) 2457 goto err_ah; 2458 2459 ATH5K_INFO(sc, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n", 2460 ath5k_chip_name(AR5K_VERSION_MAC, sc->ah->ah_mac_srev), 2461 sc->ah->ah_mac_srev, 2462 sc->ah->ah_phy_revision); 2463 2464 if (!sc->ah->ah_single_chip) { 2465 /* Single chip radio (!RF5111) */ 2466 if (sc->ah->ah_radio_5ghz_revision && 2467 !sc->ah->ah_radio_2ghz_revision) { 2468 /* No 5GHz support -> report 2GHz radio */ 2469 if (!test_bit(AR5K_MODE_11A, 2470 sc->ah->ah_capabilities.cap_mode)) { 2471 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n", 2472 ath5k_chip_name(AR5K_VERSION_RAD, 2473 sc->ah->ah_radio_5ghz_revision), 2474 sc->ah->ah_radio_5ghz_revision); 2475 /* No 2GHz support (5110 and some 2476 * 5GHz only cards) -> report 5GHz radio */ 2477 } else if (!test_bit(AR5K_MODE_11B, 2478 sc->ah->ah_capabilities.cap_mode)) { 2479 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n", 2480 ath5k_chip_name(AR5K_VERSION_RAD, 2481 sc->ah->ah_radio_5ghz_revision), 2482 sc->ah->ah_radio_5ghz_revision); 2483 /* Multiband radio */ 2484 } else { 2485 ATH5K_INFO(sc, "RF%s multiband radio found" 2486 " (0x%x)\n", 2487 ath5k_chip_name(AR5K_VERSION_RAD, 2488 sc->ah->ah_radio_5ghz_revision), 2489 sc->ah->ah_radio_5ghz_revision); 2490 } 2491 } 2492 /* Multi chip radio (RF5111 - RF2111) -> 2493 * report both 2GHz/5GHz radios */ 2494 else if (sc->ah->ah_radio_5ghz_revision && 2495 sc->ah->ah_radio_2ghz_revision) { 2496 ATH5K_INFO(sc, "RF%s 5GHz radio found (0x%x)\n", 2497 ath5k_chip_name(AR5K_VERSION_RAD, 2498 sc->ah->ah_radio_5ghz_revision), 2499 sc->ah->ah_radio_5ghz_revision); 2500 ATH5K_INFO(sc, "RF%s 2GHz radio found (0x%x)\n", 2501 ath5k_chip_name(AR5K_VERSION_RAD, 2502 sc->ah->ah_radio_2ghz_revision), 2503 sc->ah->ah_radio_2ghz_revision); 2504 } 2505 } 2506 2507 ath5k_debug_init_device(sc); 2508 2509 /* ready to process interrupts */ 2510 __clear_bit(ATH_STAT_INVALID, sc->status); 2511 2512 return 0; 2513 err_ah: 2514 ath5k_hw_deinit(sc->ah); 2515 err_free_ah: 2516 kfree(sc->ah); 2517 err_irq: 2518 free_irq(sc->irq, sc); 2519 err: 2520 return ret; 2521 } 2522 2523 static int 2524 ath5k_stop_locked(struct ath5k_softc *sc) 2525 { 2526 struct ath5k_hw *ah = sc->ah; 2527 2528 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "invalid %u\n", 2529 test_bit(ATH_STAT_INVALID, sc->status)); 2530 2531 /* 2532 * Shutdown the hardware and driver: 2533 * stop output from above 2534 * disable interrupts 2535 * turn off timers 2536 * turn off the radio 2537 * clear transmit machinery 2538 * clear receive machinery 2539 * drain and release tx queues 2540 * reclaim beacon resources 2541 * power down hardware 2542 * 2543 * Note that some of this work is not possible if the 2544 * hardware is gone (invalid). 2545 */ 2546 ieee80211_stop_queues(sc->hw); 2547 2548 if (!test_bit(ATH_STAT_INVALID, sc->status)) { 2549 ath5k_led_off(sc); 2550 ath5k_hw_set_imr(ah, 0); 2551 synchronize_irq(sc->irq); 2552 ath5k_rx_stop(sc); 2553 ath5k_hw_dma_stop(ah); 2554 ath5k_drain_tx_buffs(sc); 2555 ath5k_hw_phy_disable(ah); 2556 } 2557 2558 return 0; 2559 } 2560 2561 int 2562 ath5k_init_hw(struct ath5k_softc *sc) 2563 { 2564 struct ath5k_hw *ah = sc->ah; 2565 struct ath_common *common = ath5k_hw_common(ah); 2566 int ret, i; 2567 2568 mutex_lock(&sc->lock); 2569 2570 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "mode %d\n", sc->opmode); 2571 2572 /* 2573 * Stop anything previously setup. This is safe 2574 * no matter this is the first time through or not. 2575 */ 2576 ath5k_stop_locked(sc); 2577 2578 /* 2579 * The basic interface to setting the hardware in a good 2580 * state is ``reset''. On return the hardware is known to 2581 * be powered up and with interrupts disabled. This must 2582 * be followed by initialization of the appropriate bits 2583 * and then setup of the interrupt mask. 2584 */ 2585 sc->curchan = sc->hw->conf.channel; 2586 sc->imask = AR5K_INT_RXOK | AR5K_INT_RXERR | AR5K_INT_RXEOL | 2587 AR5K_INT_RXORN | AR5K_INT_TXDESC | AR5K_INT_TXEOL | 2588 AR5K_INT_FATAL | AR5K_INT_GLOBAL | AR5K_INT_MIB; 2589 2590 ret = ath5k_reset(sc, NULL, false); 2591 if (ret) 2592 goto done; 2593 2594 ath5k_rfkill_hw_start(ah); 2595 2596 /* 2597 * Reset the key cache since some parts do not reset the 2598 * contents on initial power up or resume from suspend. 2599 */ 2600 for (i = 0; i < common->keymax; i++) 2601 ath_hw_keyreset(common, (u16) i); 2602 2603 /* Use higher rates for acks instead of base 2604 * rate */ 2605 ah->ah_ack_bitrate_high = true; 2606 2607 for (i = 0; i < ARRAY_SIZE(sc->bslot); i++) 2608 sc->bslot[i] = NULL; 2609 2610 ret = 0; 2611 done: 2612 mmiowb(); 2613 mutex_unlock(&sc->lock); 2614 2615 ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 2616 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); 2617 2618 return ret; 2619 } 2620 2621 static void ath5k_stop_tasklets(struct ath5k_softc *sc) 2622 { 2623 sc->rx_pending = false; 2624 sc->tx_pending = false; 2625 tasklet_kill(&sc->rxtq); 2626 tasklet_kill(&sc->txtq); 2627 tasklet_kill(&sc->calib); 2628 tasklet_kill(&sc->beacontq); 2629 tasklet_kill(&sc->ani_tasklet); 2630 } 2631 2632 /* 2633 * Stop the device, grabbing the top-level lock to protect 2634 * against concurrent entry through ath5k_init (which can happen 2635 * if another thread does a system call and the thread doing the 2636 * stop is preempted). 2637 */ 2638 int 2639 ath5k_stop_hw(struct ath5k_softc *sc) 2640 { 2641 int ret; 2642 2643 mutex_lock(&sc->lock); 2644 ret = ath5k_stop_locked(sc); 2645 if (ret == 0 && !test_bit(ATH_STAT_INVALID, sc->status)) { 2646 /* 2647 * Don't set the card in full sleep mode! 2648 * 2649 * a) When the device is in this state it must be carefully 2650 * woken up or references to registers in the PCI clock 2651 * domain may freeze the bus (and system). This varies 2652 * by chip and is mostly an issue with newer parts 2653 * (madwifi sources mentioned srev >= 0x78) that go to 2654 * sleep more quickly. 2655 * 2656 * b) On older chips full sleep results a weird behaviour 2657 * during wakeup. I tested various cards with srev < 0x78 2658 * and they don't wake up after module reload, a second 2659 * module reload is needed to bring the card up again. 2660 * 2661 * Until we figure out what's going on don't enable 2662 * full chip reset on any chip (this is what Legacy HAL 2663 * and Sam's HAL do anyway). Instead Perform a full reset 2664 * on the device (same as initial state after attach) and 2665 * leave it idle (keep MAC/BB on warm reset) */ 2666 ret = ath5k_hw_on_hold(sc->ah); 2667 2668 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, 2669 "putting device to sleep\n"); 2670 } 2671 2672 mmiowb(); 2673 mutex_unlock(&sc->lock); 2674 2675 ath5k_stop_tasklets(sc); 2676 2677 cancel_delayed_work_sync(&sc->tx_complete_work); 2678 2679 ath5k_rfkill_hw_stop(sc->ah); 2680 2681 return ret; 2682 } 2683 2684 /* 2685 * Reset the hardware. If chan is not NULL, then also pause rx/tx 2686 * and change to the given channel. 2687 * 2688 * This should be called with sc->lock. 2689 */ 2690 static int 2691 ath5k_reset(struct ath5k_softc *sc, struct ieee80211_channel *chan, 2692 bool skip_pcu) 2693 { 2694 struct ath5k_hw *ah = sc->ah; 2695 struct ath_common *common = ath5k_hw_common(ah); 2696 int ret, ani_mode; 2697 bool fast; 2698 2699 ATH5K_DBG(sc, ATH5K_DEBUG_RESET, "resetting\n"); 2700 2701 ath5k_hw_set_imr(ah, 0); 2702 synchronize_irq(sc->irq); 2703 ath5k_stop_tasklets(sc); 2704 2705 /* Save ani mode and disable ANI during 2706 * reset. If we don't we might get false 2707 * PHY error interrupts. */ 2708 ani_mode = ah->ah_sc->ani_state.ani_mode; 2709 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF); 2710 2711 /* We are going to empty hw queues 2712 * so we should also free any remaining 2713 * tx buffers */ 2714 ath5k_drain_tx_buffs(sc); 2715 if (chan) 2716 sc->curchan = chan; 2717 2718 fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0; 2719 2720 ret = ath5k_hw_reset(ah, sc->opmode, sc->curchan, fast, skip_pcu); 2721 if (ret) { 2722 ATH5K_ERR(sc, "can't reset hardware (%d)\n", ret); 2723 goto err; 2724 } 2725 2726 ret = ath5k_rx_start(sc); 2727 if (ret) { 2728 ATH5K_ERR(sc, "can't start recv logic\n"); 2729 goto err; 2730 } 2731 2732 ath5k_ani_init(ah, ani_mode); 2733 2734 ah->ah_cal_next_full = jiffies + msecs_to_jiffies(100); 2735 ah->ah_cal_next_ani = jiffies; 2736 ah->ah_cal_next_nf = jiffies; 2737 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8); 2738 2739 /* clear survey data and cycle counters */ 2740 memset(&sc->survey, 0, sizeof(sc->survey)); 2741 spin_lock_bh(&common->cc_lock); 2742 ath_hw_cycle_counters_update(common); 2743 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 2744 memset(&common->cc_ani, 0, sizeof(common->cc_ani)); 2745 spin_unlock_bh(&common->cc_lock); 2746 2747 /* 2748 * Change channels and update the h/w rate map if we're switching; 2749 * e.g. 11a to 11b/g. 2750 * 2751 * We may be doing a reset in response to an ioctl that changes the 2752 * channel so update any state that might change as a result. 2753 * 2754 * XXX needed? 2755 */ 2756 /* ath5k_chan_change(sc, c); */ 2757 2758 ath5k_beacon_config(sc); 2759 /* intrs are enabled by ath5k_beacon_config */ 2760 2761 ieee80211_wake_queues(sc->hw); 2762 2763 return 0; 2764 err: 2765 return ret; 2766 } 2767 2768 static void ath5k_reset_work(struct work_struct *work) 2769 { 2770 struct ath5k_softc *sc = container_of(work, struct ath5k_softc, 2771 reset_work); 2772 2773 mutex_lock(&sc->lock); 2774 ath5k_reset(sc, NULL, true); 2775 mutex_unlock(&sc->lock); 2776 } 2777 2778 static int __devinit 2779 ath5k_init(struct ieee80211_hw *hw) 2780 { 2781 2782 struct ath5k_softc *sc = hw->priv; 2783 struct ath5k_hw *ah = sc->ah; 2784 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 2785 struct ath5k_txq *txq; 2786 u8 mac[ETH_ALEN] = {}; 2787 int ret; 2788 2789 2790 /* 2791 * Check if the MAC has multi-rate retry support. 2792 * We do this by trying to setup a fake extended 2793 * descriptor. MACs that don't have support will 2794 * return false w/o doing anything. MACs that do 2795 * support it will return true w/o doing anything. 2796 */ 2797 ret = ath5k_hw_setup_mrr_tx_desc(ah, NULL, 0, 0, 0, 0, 0, 0); 2798 2799 if (ret < 0) 2800 goto err; 2801 if (ret > 0) 2802 __set_bit(ATH_STAT_MRRETRY, sc->status); 2803 2804 /* 2805 * Collect the channel list. The 802.11 layer 2806 * is responsible for filtering this list based 2807 * on settings like the phy mode and regulatory 2808 * domain restrictions. 2809 */ 2810 ret = ath5k_setup_bands(hw); 2811 if (ret) { 2812 ATH5K_ERR(sc, "can't get channels\n"); 2813 goto err; 2814 } 2815 2816 /* 2817 * Allocate tx+rx descriptors and populate the lists. 2818 */ 2819 ret = ath5k_desc_alloc(sc); 2820 if (ret) { 2821 ATH5K_ERR(sc, "can't allocate descriptors\n"); 2822 goto err; 2823 } 2824 2825 /* 2826 * Allocate hardware transmit queues: one queue for 2827 * beacon frames and one data queue for each QoS 2828 * priority. Note that hw functions handle resetting 2829 * these queues at the needed time. 2830 */ 2831 ret = ath5k_beaconq_setup(ah); 2832 if (ret < 0) { 2833 ATH5K_ERR(sc, "can't setup a beacon xmit queue\n"); 2834 goto err_desc; 2835 } 2836 sc->bhalq = ret; 2837 sc->cabq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_CAB, 0); 2838 if (IS_ERR(sc->cabq)) { 2839 ATH5K_ERR(sc, "can't setup cab queue\n"); 2840 ret = PTR_ERR(sc->cabq); 2841 goto err_bhal; 2842 } 2843 2844 /* 5211 and 5212 usually support 10 queues but we better rely on the 2845 * capability information */ 2846 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) { 2847 /* This order matches mac80211's queue priority, so we can 2848 * directly use the mac80211 queue number without any mapping */ 2849 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO); 2850 if (IS_ERR(txq)) { 2851 ATH5K_ERR(sc, "can't setup xmit queue\n"); 2852 ret = PTR_ERR(txq); 2853 goto err_queues; 2854 } 2855 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI); 2856 if (IS_ERR(txq)) { 2857 ATH5K_ERR(sc, "can't setup xmit queue\n"); 2858 ret = PTR_ERR(txq); 2859 goto err_queues; 2860 } 2861 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); 2862 if (IS_ERR(txq)) { 2863 ATH5K_ERR(sc, "can't setup xmit queue\n"); 2864 ret = PTR_ERR(txq); 2865 goto err_queues; 2866 } 2867 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); 2868 if (IS_ERR(txq)) { 2869 ATH5K_ERR(sc, "can't setup xmit queue\n"); 2870 ret = PTR_ERR(txq); 2871 goto err_queues; 2872 } 2873 hw->queues = 4; 2874 } else { 2875 /* older hardware (5210) can only support one data queue */ 2876 txq = ath5k_txq_setup(sc, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); 2877 if (IS_ERR(txq)) { 2878 ATH5K_ERR(sc, "can't setup xmit queue\n"); 2879 ret = PTR_ERR(txq); 2880 goto err_queues; 2881 } 2882 hw->queues = 1; 2883 } 2884 2885 tasklet_init(&sc->rxtq, ath5k_tasklet_rx, (unsigned long)sc); 2886 tasklet_init(&sc->txtq, ath5k_tasklet_tx, (unsigned long)sc); 2887 tasklet_init(&sc->calib, ath5k_tasklet_calibrate, (unsigned long)sc); 2888 tasklet_init(&sc->beacontq, ath5k_tasklet_beacon, (unsigned long)sc); 2889 tasklet_init(&sc->ani_tasklet, ath5k_tasklet_ani, (unsigned long)sc); 2890 2891 INIT_WORK(&sc->reset_work, ath5k_reset_work); 2892 INIT_DELAYED_WORK(&sc->tx_complete_work, ath5k_tx_complete_poll_work); 2893 2894 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac); 2895 if (ret) { 2896 ATH5K_ERR(sc, "unable to read address from EEPROM\n"); 2897 goto err_queues; 2898 } 2899 2900 SET_IEEE80211_PERM_ADDR(hw, mac); 2901 memcpy(&sc->lladdr, mac, ETH_ALEN); 2902 /* All MAC address bits matter for ACKs */ 2903 ath5k_update_bssid_mask_and_opmode(sc, NULL); 2904 2905 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain; 2906 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier); 2907 if (ret) { 2908 ATH5K_ERR(sc, "can't initialize regulatory system\n"); 2909 goto err_queues; 2910 } 2911 2912 ret = ieee80211_register_hw(hw); 2913 if (ret) { 2914 ATH5K_ERR(sc, "can't register ieee80211 hw\n"); 2915 goto err_queues; 2916 } 2917 2918 if (!ath_is_world_regd(regulatory)) 2919 regulatory_hint(hw->wiphy, regulatory->alpha2); 2920 2921 ath5k_init_leds(sc); 2922 2923 ath5k_sysfs_register(sc); 2924 2925 return 0; 2926 err_queues: 2927 ath5k_txq_release(sc); 2928 err_bhal: 2929 ath5k_hw_release_tx_queue(ah, sc->bhalq); 2930 err_desc: 2931 ath5k_desc_free(sc); 2932 err: 2933 return ret; 2934 } 2935 2936 void 2937 ath5k_deinit_softc(struct ath5k_softc *sc) 2938 { 2939 struct ieee80211_hw *hw = sc->hw; 2940 2941 /* 2942 * NB: the order of these is important: 2943 * o call the 802.11 layer before detaching ath5k_hw to 2944 * ensure callbacks into the driver to delete global 2945 * key cache entries can be handled 2946 * o reclaim the tx queue data structures after calling 2947 * the 802.11 layer as we'll get called back to reclaim 2948 * node state and potentially want to use them 2949 * o to cleanup the tx queues the hal is called, so detach 2950 * it last 2951 * XXX: ??? detach ath5k_hw ??? 2952 * Other than that, it's straightforward... 2953 */ 2954 ieee80211_unregister_hw(hw); 2955 ath5k_desc_free(sc); 2956 ath5k_txq_release(sc); 2957 ath5k_hw_release_tx_queue(sc->ah, sc->bhalq); 2958 ath5k_unregister_leds(sc); 2959 2960 ath5k_sysfs_unregister(sc); 2961 /* 2962 * NB: can't reclaim these until after ieee80211_ifdetach 2963 * returns because we'll get called back to reclaim node 2964 * state and potentially want to use them. 2965 */ 2966 ath5k_hw_deinit(sc->ah); 2967 kfree(sc->ah); 2968 free_irq(sc->irq, sc); 2969 } 2970 2971 bool 2972 ath5k_any_vif_assoc(struct ath5k_softc *sc) 2973 { 2974 struct ath5k_vif_iter_data iter_data; 2975 iter_data.hw_macaddr = NULL; 2976 iter_data.any_assoc = false; 2977 iter_data.need_set_hw_addr = false; 2978 iter_data.found_active = true; 2979 2980 ieee80211_iterate_active_interfaces_atomic(sc->hw, ath5k_vif_iter, 2981 &iter_data); 2982 return iter_data.any_assoc; 2983 } 2984 2985 void 2986 ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable) 2987 { 2988 struct ath5k_softc *sc = hw->priv; 2989 struct ath5k_hw *ah = sc->ah; 2990 u32 rfilt; 2991 rfilt = ath5k_hw_get_rx_filter(ah); 2992 if (enable) 2993 rfilt |= AR5K_RX_FILTER_BEACON; 2994 else 2995 rfilt &= ~AR5K_RX_FILTER_BEACON; 2996 ath5k_hw_set_rx_filter(ah, rfilt); 2997 sc->filter_flags = rfilt; 2998 } 2999