1 /*- 2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 3 * Copyright (c) 2004-2005 Atheros Communications, Inc. 4 * Copyright (c) 2006 Devicescape Software, Inc. 5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com> 6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu> 7 * 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 18 * redistribution must be conditioned upon including a substantially 19 * similar Disclaimer requirement for further binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * Alternatively, this software may be distributed under the terms of the 25 * GNU General Public License ("GPL") version 2 as published by the Free 26 * Software Foundation. 27 * 28 * NO WARRANTY 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 39 * THE POSSIBILITY OF SUCH DAMAGES. 40 * 41 */ 42 43 #include <linux/module.h> 44 #include <linux/delay.h> 45 #include <linux/dma-mapping.h> 46 #include <linux/hardirq.h> 47 #include <linux/if.h> 48 #include <linux/io.h> 49 #include <linux/netdevice.h> 50 #include <linux/cache.h> 51 #include <linux/ethtool.h> 52 #include <linux/uaccess.h> 53 #include <linux/slab.h> 54 #include <linux/etherdevice.h> 55 #include <linux/nl80211.h> 56 57 #include <net/ieee80211_radiotap.h> 58 59 #include <asm/unaligned.h> 60 61 #include "base.h" 62 #include "reg.h" 63 #include "debug.h" 64 #include "ani.h" 65 #include "ath5k.h" 66 #include "../regd.h" 67 68 #define CREATE_TRACE_POINTS 69 #include "trace.h" 70 71 bool ath5k_modparam_nohwcrypt; 72 module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO); 73 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 74 75 static bool modparam_all_channels; 76 module_param_named(all_channels, modparam_all_channels, bool, S_IRUGO); 77 MODULE_PARM_DESC(all_channels, "Expose all channels the device can use."); 78 79 static bool modparam_fastchanswitch; 80 module_param_named(fastchanswitch, modparam_fastchanswitch, bool, S_IRUGO); 81 MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios."); 82 83 static bool ath5k_modparam_no_hw_rfkill_switch; 84 module_param_named(no_hw_rfkill_switch, ath5k_modparam_no_hw_rfkill_switch, 85 bool, S_IRUGO); 86 MODULE_PARM_DESC(no_hw_rfkill_switch, "Ignore the GPIO RFKill switch state"); 87 88 89 /* Module info */ 90 MODULE_AUTHOR("Jiri Slaby"); 91 MODULE_AUTHOR("Nick Kossifidis"); 92 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards."); 93 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards"); 94 MODULE_LICENSE("Dual BSD/GPL"); 95 96 static int ath5k_init(struct ieee80211_hw *hw); 97 static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan, 98 bool skip_pcu); 99 100 /* Known SREVs */ 101 static const struct ath5k_srev_name srev_names[] = { 102 #ifdef CONFIG_ATHEROS_AR231X 103 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 }, 104 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 }, 105 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 }, 106 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 }, 107 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 }, 108 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 }, 109 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 }, 110 #else 111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 }, 112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 }, 113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A }, 114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B }, 115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 }, 116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 }, 117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 }, 118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A }, 119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 }, 120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 }, 121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 }, 122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 }, 123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 }, 124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 }, 125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 }, 126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 }, 127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 }, 128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 }, 129 #endif 130 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN }, 131 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, 132 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, 133 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A }, 134 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, 135 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, 136 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, 137 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B }, 138 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, 139 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, 140 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B }, 141 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 }, 142 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 }, 143 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 }, 144 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 }, 145 #ifdef CONFIG_ATHEROS_AR231X 146 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 }, 147 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 }, 148 #endif 149 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, 150 }; 151 152 static const struct ieee80211_rate ath5k_rates[] = { 153 { .bitrate = 10, 154 .hw_value = ATH5K_RATE_CODE_1M, }, 155 { .bitrate = 20, 156 .hw_value = ATH5K_RATE_CODE_2M, 157 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE, 158 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 159 { .bitrate = 55, 160 .hw_value = ATH5K_RATE_CODE_5_5M, 161 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE, 162 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 163 { .bitrate = 110, 164 .hw_value = ATH5K_RATE_CODE_11M, 165 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE, 166 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 167 { .bitrate = 60, 168 .hw_value = ATH5K_RATE_CODE_6M, 169 .flags = 0 }, 170 { .bitrate = 90, 171 .hw_value = ATH5K_RATE_CODE_9M, 172 .flags = 0 }, 173 { .bitrate = 120, 174 .hw_value = ATH5K_RATE_CODE_12M, 175 .flags = 0 }, 176 { .bitrate = 180, 177 .hw_value = ATH5K_RATE_CODE_18M, 178 .flags = 0 }, 179 { .bitrate = 240, 180 .hw_value = ATH5K_RATE_CODE_24M, 181 .flags = 0 }, 182 { .bitrate = 360, 183 .hw_value = ATH5K_RATE_CODE_36M, 184 .flags = 0 }, 185 { .bitrate = 480, 186 .hw_value = ATH5K_RATE_CODE_48M, 187 .flags = 0 }, 188 { .bitrate = 540, 189 .hw_value = ATH5K_RATE_CODE_54M, 190 .flags = 0 }, 191 }; 192 193 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp) 194 { 195 u64 tsf = ath5k_hw_get_tsf64(ah); 196 197 if ((tsf & 0x7fff) < rstamp) 198 tsf -= 0x8000; 199 200 return (tsf & ~0x7fff) | rstamp; 201 } 202 203 const char * 204 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val) 205 { 206 const char *name = "xxxxx"; 207 unsigned int i; 208 209 for (i = 0; i < ARRAY_SIZE(srev_names); i++) { 210 if (srev_names[i].sr_type != type) 211 continue; 212 213 if ((val & 0xf0) == srev_names[i].sr_val) 214 name = srev_names[i].sr_name; 215 216 if ((val & 0xff) == srev_names[i].sr_val) { 217 name = srev_names[i].sr_name; 218 break; 219 } 220 } 221 222 return name; 223 } 224 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset) 225 { 226 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; 227 return ath5k_hw_reg_read(ah, reg_offset); 228 } 229 230 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) 231 { 232 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; 233 ath5k_hw_reg_write(ah, val, reg_offset); 234 } 235 236 static const struct ath_ops ath5k_common_ops = { 237 .read = ath5k_ioread32, 238 .write = ath5k_iowrite32, 239 }; 240 241 /***********************\ 242 * Driver Initialization * 243 \***********************/ 244 245 static int ath5k_reg_notifier(struct wiphy *wiphy, struct regulatory_request *request) 246 { 247 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 248 struct ath5k_hw *ah = hw->priv; 249 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 250 251 return ath_reg_notifier_apply(wiphy, request, regulatory); 252 } 253 254 /********************\ 255 * Channel/mode setup * 256 \********************/ 257 258 /* 259 * Returns true for the channel numbers used without all_channels modparam. 260 */ 261 static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band) 262 { 263 if (band == IEEE80211_BAND_2GHZ && chan <= 14) 264 return true; 265 266 return /* UNII 1,2 */ 267 (((chan & 3) == 0 && chan >= 36 && chan <= 64) || 268 /* midband */ 269 ((chan & 3) == 0 && chan >= 100 && chan <= 140) || 270 /* UNII-3 */ 271 ((chan & 3) == 1 && chan >= 149 && chan <= 165) || 272 /* 802.11j 5.030-5.080 GHz (20MHz) */ 273 (chan == 8 || chan == 12 || chan == 16) || 274 /* 802.11j 4.9GHz (20MHz) */ 275 (chan == 184 || chan == 188 || chan == 192 || chan == 196)); 276 } 277 278 static unsigned int 279 ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels, 280 unsigned int mode, unsigned int max) 281 { 282 unsigned int count, size, freq, ch; 283 enum ieee80211_band band; 284 285 switch (mode) { 286 case AR5K_MODE_11A: 287 /* 1..220, but 2GHz frequencies are filtered by check_channel */ 288 size = 220; 289 band = IEEE80211_BAND_5GHZ; 290 break; 291 case AR5K_MODE_11B: 292 case AR5K_MODE_11G: 293 size = 26; 294 band = IEEE80211_BAND_2GHZ; 295 break; 296 default: 297 ATH5K_WARN(ah, "bad mode, not copying channels\n"); 298 return 0; 299 } 300 301 count = 0; 302 for (ch = 1; ch <= size && count < max; ch++) { 303 freq = ieee80211_channel_to_frequency(ch, band); 304 305 if (freq == 0) /* mapping failed - not a standard channel */ 306 continue; 307 308 /* Write channel info, needed for ath5k_channel_ok() */ 309 channels[count].center_freq = freq; 310 channels[count].band = band; 311 channels[count].hw_value = mode; 312 313 /* Check if channel is supported by the chipset */ 314 if (!ath5k_channel_ok(ah, &channels[count])) 315 continue; 316 317 if (!modparam_all_channels && 318 !ath5k_is_standard_channel(ch, band)) 319 continue; 320 321 count++; 322 } 323 324 return count; 325 } 326 327 static void 328 ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b) 329 { 330 u8 i; 331 332 for (i = 0; i < AR5K_MAX_RATES; i++) 333 ah->rate_idx[b->band][i] = -1; 334 335 for (i = 0; i < b->n_bitrates; i++) { 336 ah->rate_idx[b->band][b->bitrates[i].hw_value] = i; 337 if (b->bitrates[i].hw_value_short) 338 ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i; 339 } 340 } 341 342 static int 343 ath5k_setup_bands(struct ieee80211_hw *hw) 344 { 345 struct ath5k_hw *ah = hw->priv; 346 struct ieee80211_supported_band *sband; 347 int max_c, count_c = 0; 348 int i; 349 350 BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < IEEE80211_NUM_BANDS); 351 max_c = ARRAY_SIZE(ah->channels); 352 353 /* 2GHz band */ 354 sband = &ah->sbands[IEEE80211_BAND_2GHZ]; 355 sband->band = IEEE80211_BAND_2GHZ; 356 sband->bitrates = &ah->rates[IEEE80211_BAND_2GHZ][0]; 357 358 if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) { 359 /* G mode */ 360 memcpy(sband->bitrates, &ath5k_rates[0], 361 sizeof(struct ieee80211_rate) * 12); 362 sband->n_bitrates = 12; 363 364 sband->channels = ah->channels; 365 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 366 AR5K_MODE_11G, max_c); 367 368 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; 369 count_c = sband->n_channels; 370 max_c -= count_c; 371 } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) { 372 /* B mode */ 373 memcpy(sband->bitrates, &ath5k_rates[0], 374 sizeof(struct ieee80211_rate) * 4); 375 sband->n_bitrates = 4; 376 377 /* 5211 only supports B rates and uses 4bit rate codes 378 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B) 379 * fix them up here: 380 */ 381 if (ah->ah_version == AR5K_AR5211) { 382 for (i = 0; i < 4; i++) { 383 sband->bitrates[i].hw_value = 384 sband->bitrates[i].hw_value & 0xF; 385 sband->bitrates[i].hw_value_short = 386 sband->bitrates[i].hw_value_short & 0xF; 387 } 388 } 389 390 sband->channels = ah->channels; 391 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 392 AR5K_MODE_11B, max_c); 393 394 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; 395 count_c = sband->n_channels; 396 max_c -= count_c; 397 } 398 ath5k_setup_rate_idx(ah, sband); 399 400 /* 5GHz band, A mode */ 401 if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) { 402 sband = &ah->sbands[IEEE80211_BAND_5GHZ]; 403 sband->band = IEEE80211_BAND_5GHZ; 404 sband->bitrates = &ah->rates[IEEE80211_BAND_5GHZ][0]; 405 406 memcpy(sband->bitrates, &ath5k_rates[4], 407 sizeof(struct ieee80211_rate) * 8); 408 sband->n_bitrates = 8; 409 410 sband->channels = &ah->channels[count_c]; 411 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 412 AR5K_MODE_11A, max_c); 413 414 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband; 415 } 416 ath5k_setup_rate_idx(ah, sband); 417 418 ath5k_debug_dump_bands(ah); 419 420 return 0; 421 } 422 423 /* 424 * Set/change channels. We always reset the chip. 425 * To accomplish this we must first cleanup any pending DMA, 426 * then restart stuff after a la ath5k_init. 427 * 428 * Called with ah->lock. 429 */ 430 int 431 ath5k_chan_set(struct ath5k_hw *ah, struct ieee80211_channel *chan) 432 { 433 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 434 "channel set, resetting (%u -> %u MHz)\n", 435 ah->curchan->center_freq, chan->center_freq); 436 437 /* 438 * To switch channels clear any pending DMA operations; 439 * wait long enough for the RX fifo to drain, reset the 440 * hardware at the new frequency, and then re-enable 441 * the relevant bits of the h/w. 442 */ 443 return ath5k_reset(ah, chan, true); 444 } 445 446 void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 447 { 448 struct ath5k_vif_iter_data *iter_data = data; 449 int i; 450 struct ath5k_vif *avf = (void *)vif->drv_priv; 451 452 if (iter_data->hw_macaddr) 453 for (i = 0; i < ETH_ALEN; i++) 454 iter_data->mask[i] &= 455 ~(iter_data->hw_macaddr[i] ^ mac[i]); 456 457 if (!iter_data->found_active) { 458 iter_data->found_active = true; 459 memcpy(iter_data->active_mac, mac, ETH_ALEN); 460 } 461 462 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr) 463 if (compare_ether_addr(iter_data->hw_macaddr, mac) == 0) 464 iter_data->need_set_hw_addr = false; 465 466 if (!iter_data->any_assoc) { 467 if (avf->assoc) 468 iter_data->any_assoc = true; 469 } 470 471 /* Calculate combined mode - when APs are active, operate in AP mode. 472 * Otherwise use the mode of the new interface. This can currently 473 * only deal with combinations of APs and STAs. Only one ad-hoc 474 * interfaces is allowed. 475 */ 476 if (avf->opmode == NL80211_IFTYPE_AP) 477 iter_data->opmode = NL80211_IFTYPE_AP; 478 else { 479 if (avf->opmode == NL80211_IFTYPE_STATION) 480 iter_data->n_stas++; 481 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED) 482 iter_data->opmode = avf->opmode; 483 } 484 } 485 486 void 487 ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah, 488 struct ieee80211_vif *vif) 489 { 490 struct ath_common *common = ath5k_hw_common(ah); 491 struct ath5k_vif_iter_data iter_data; 492 u32 rfilt; 493 494 /* 495 * Use the hardware MAC address as reference, the hardware uses it 496 * together with the BSSID mask when matching addresses. 497 */ 498 iter_data.hw_macaddr = common->macaddr; 499 memset(&iter_data.mask, 0xff, ETH_ALEN); 500 iter_data.found_active = false; 501 iter_data.need_set_hw_addr = true; 502 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED; 503 iter_data.n_stas = 0; 504 505 if (vif) 506 ath5k_vif_iter(&iter_data, vif->addr, vif); 507 508 /* Get list of all active MAC addresses */ 509 ieee80211_iterate_active_interfaces_atomic(ah->hw, ath5k_vif_iter, 510 &iter_data); 511 memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN); 512 513 ah->opmode = iter_data.opmode; 514 if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED) 515 /* Nothing active, default to station mode */ 516 ah->opmode = NL80211_IFTYPE_STATION; 517 518 ath5k_hw_set_opmode(ah, ah->opmode); 519 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n", 520 ah->opmode, ath_opmode_to_string(ah->opmode)); 521 522 if (iter_data.need_set_hw_addr && iter_data.found_active) 523 ath5k_hw_set_lladdr(ah, iter_data.active_mac); 524 525 if (ath5k_hw_hasbssidmask(ah)) 526 ath5k_hw_set_bssid_mask(ah, ah->bssidmask); 527 528 /* Set up RX Filter */ 529 if (iter_data.n_stas > 1) { 530 /* If you have multiple STA interfaces connected to 531 * different APs, ARPs are not received (most of the time?) 532 * Enabling PROMISC appears to fix that problem. 533 */ 534 ah->filter_flags |= AR5K_RX_FILTER_PROM; 535 } 536 537 rfilt = ah->filter_flags; 538 ath5k_hw_set_rx_filter(ah, rfilt); 539 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt); 540 } 541 542 static inline int 543 ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix) 544 { 545 int rix; 546 547 /* return base rate on errors */ 548 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES, 549 "hw_rix out of bounds: %x\n", hw_rix)) 550 return 0; 551 552 rix = ah->rate_idx[ah->curchan->band][hw_rix]; 553 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix)) 554 rix = 0; 555 556 return rix; 557 } 558 559 /***************\ 560 * Buffers setup * 561 \***************/ 562 563 static 564 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr) 565 { 566 struct ath_common *common = ath5k_hw_common(ah); 567 struct sk_buff *skb; 568 569 /* 570 * Allocate buffer with headroom_needed space for the 571 * fake physical layer header at the start. 572 */ 573 skb = ath_rxbuf_alloc(common, 574 common->rx_bufsize, 575 GFP_ATOMIC); 576 577 if (!skb) { 578 ATH5K_ERR(ah, "can't alloc skbuff of size %u\n", 579 common->rx_bufsize); 580 return NULL; 581 } 582 583 *skb_addr = dma_map_single(ah->dev, 584 skb->data, common->rx_bufsize, 585 DMA_FROM_DEVICE); 586 587 if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) { 588 ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__); 589 dev_kfree_skb(skb); 590 return NULL; 591 } 592 return skb; 593 } 594 595 static int 596 ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf) 597 { 598 struct sk_buff *skb = bf->skb; 599 struct ath5k_desc *ds; 600 int ret; 601 602 if (!skb) { 603 skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr); 604 if (!skb) 605 return -ENOMEM; 606 bf->skb = skb; 607 } 608 609 /* 610 * Setup descriptors. For receive we always terminate 611 * the descriptor list with a self-linked entry so we'll 612 * not get overrun under high load (as can happen with a 613 * 5212 when ANI processing enables PHY error frames). 614 * 615 * To ensure the last descriptor is self-linked we create 616 * each descriptor as self-linked and add it to the end. As 617 * each additional descriptor is added the previous self-linked 618 * entry is "fixed" naturally. This should be safe even 619 * if DMA is happening. When processing RX interrupts we 620 * never remove/process the last, self-linked, entry on the 621 * descriptor list. This ensures the hardware always has 622 * someplace to write a new frame. 623 */ 624 ds = bf->desc; 625 ds->ds_link = bf->daddr; /* link to self */ 626 ds->ds_data = bf->skbaddr; 627 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0); 628 if (ret) { 629 ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__); 630 return ret; 631 } 632 633 if (ah->rxlink != NULL) 634 *ah->rxlink = bf->daddr; 635 ah->rxlink = &ds->ds_link; 636 return 0; 637 } 638 639 static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb) 640 { 641 struct ieee80211_hdr *hdr; 642 enum ath5k_pkt_type htype; 643 __le16 fc; 644 645 hdr = (struct ieee80211_hdr *)skb->data; 646 fc = hdr->frame_control; 647 648 if (ieee80211_is_beacon(fc)) 649 htype = AR5K_PKT_TYPE_BEACON; 650 else if (ieee80211_is_probe_resp(fc)) 651 htype = AR5K_PKT_TYPE_PROBE_RESP; 652 else if (ieee80211_is_atim(fc)) 653 htype = AR5K_PKT_TYPE_ATIM; 654 else if (ieee80211_is_pspoll(fc)) 655 htype = AR5K_PKT_TYPE_PSPOLL; 656 else 657 htype = AR5K_PKT_TYPE_NORMAL; 658 659 return htype; 660 } 661 662 static int 663 ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf, 664 struct ath5k_txq *txq, int padsize) 665 { 666 struct ath5k_desc *ds = bf->desc; 667 struct sk_buff *skb = bf->skb; 668 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 669 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID; 670 struct ieee80211_rate *rate; 671 unsigned int mrr_rate[3], mrr_tries[3]; 672 int i, ret; 673 u16 hw_rate; 674 u16 cts_rate = 0; 675 u16 duration = 0; 676 u8 rc_flags; 677 678 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; 679 680 /* XXX endianness */ 681 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len, 682 DMA_TO_DEVICE); 683 684 rate = ieee80211_get_tx_rate(ah->hw, info); 685 if (!rate) { 686 ret = -EINVAL; 687 goto err_unmap; 688 } 689 690 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 691 flags |= AR5K_TXDESC_NOACK; 692 693 rc_flags = info->control.rates[0].flags; 694 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ? 695 rate->hw_value_short : rate->hw_value; 696 697 pktlen = skb->len; 698 699 /* FIXME: If we are in g mode and rate is a CCK rate 700 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta 701 * from tx power (value is in dB units already) */ 702 if (info->control.hw_key) { 703 keyidx = info->control.hw_key->hw_key_idx; 704 pktlen += info->control.hw_key->icv_len; 705 } 706 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) { 707 flags |= AR5K_TXDESC_RTSENA; 708 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value; 709 duration = le16_to_cpu(ieee80211_rts_duration(ah->hw, 710 info->control.vif, pktlen, info)); 711 } 712 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 713 flags |= AR5K_TXDESC_CTSENA; 714 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value; 715 duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw, 716 info->control.vif, pktlen, info)); 717 } 718 ret = ah->ah_setup_tx_desc(ah, ds, pktlen, 719 ieee80211_get_hdrlen_from_skb(skb), padsize, 720 get_hw_packet_type(skb), 721 (ah->power_level * 2), 722 hw_rate, 723 info->control.rates[0].count, keyidx, ah->ah_tx_ant, flags, 724 cts_rate, duration); 725 if (ret) 726 goto err_unmap; 727 728 /* Set up MRR descriptor */ 729 if (ah->ah_capabilities.cap_has_mrr_support) { 730 memset(mrr_rate, 0, sizeof(mrr_rate)); 731 memset(mrr_tries, 0, sizeof(mrr_tries)); 732 for (i = 0; i < 3; i++) { 733 rate = ieee80211_get_alt_retry_rate(ah->hw, info, i); 734 if (!rate) 735 break; 736 737 mrr_rate[i] = rate->hw_value; 738 mrr_tries[i] = info->control.rates[i + 1].count; 739 } 740 741 ath5k_hw_setup_mrr_tx_desc(ah, ds, 742 mrr_rate[0], mrr_tries[0], 743 mrr_rate[1], mrr_tries[1], 744 mrr_rate[2], mrr_tries[2]); 745 } 746 747 ds->ds_link = 0; 748 ds->ds_data = bf->skbaddr; 749 750 spin_lock_bh(&txq->lock); 751 list_add_tail(&bf->list, &txq->q); 752 txq->txq_len++; 753 if (txq->link == NULL) /* is this first packet? */ 754 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr); 755 else /* no, so only link it */ 756 *txq->link = bf->daddr; 757 758 txq->link = &ds->ds_link; 759 ath5k_hw_start_tx_dma(ah, txq->qnum); 760 mmiowb(); 761 spin_unlock_bh(&txq->lock); 762 763 return 0; 764 err_unmap: 765 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); 766 return ret; 767 } 768 769 /*******************\ 770 * Descriptors setup * 771 \*******************/ 772 773 static int 774 ath5k_desc_alloc(struct ath5k_hw *ah) 775 { 776 struct ath5k_desc *ds; 777 struct ath5k_buf *bf; 778 dma_addr_t da; 779 unsigned int i; 780 int ret; 781 782 /* allocate descriptors */ 783 ah->desc_len = sizeof(struct ath5k_desc) * 784 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1); 785 786 ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len, 787 &ah->desc_daddr, GFP_KERNEL); 788 if (ah->desc == NULL) { 789 ATH5K_ERR(ah, "can't allocate descriptors\n"); 790 ret = -ENOMEM; 791 goto err; 792 } 793 ds = ah->desc; 794 da = ah->desc_daddr; 795 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n", 796 ds, ah->desc_len, (unsigned long long)ah->desc_daddr); 797 798 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF, 799 sizeof(struct ath5k_buf), GFP_KERNEL); 800 if (bf == NULL) { 801 ATH5K_ERR(ah, "can't allocate bufptr\n"); 802 ret = -ENOMEM; 803 goto err_free; 804 } 805 ah->bufptr = bf; 806 807 INIT_LIST_HEAD(&ah->rxbuf); 808 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) { 809 bf->desc = ds; 810 bf->daddr = da; 811 list_add_tail(&bf->list, &ah->rxbuf); 812 } 813 814 INIT_LIST_HEAD(&ah->txbuf); 815 ah->txbuf_len = ATH_TXBUF; 816 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) { 817 bf->desc = ds; 818 bf->daddr = da; 819 list_add_tail(&bf->list, &ah->txbuf); 820 } 821 822 /* beacon buffers */ 823 INIT_LIST_HEAD(&ah->bcbuf); 824 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) { 825 bf->desc = ds; 826 bf->daddr = da; 827 list_add_tail(&bf->list, &ah->bcbuf); 828 } 829 830 return 0; 831 err_free: 832 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr); 833 err: 834 ah->desc = NULL; 835 return ret; 836 } 837 838 void 839 ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf) 840 { 841 BUG_ON(!bf); 842 if (!bf->skb) 843 return; 844 dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len, 845 DMA_TO_DEVICE); 846 dev_kfree_skb_any(bf->skb); 847 bf->skb = NULL; 848 bf->skbaddr = 0; 849 bf->desc->ds_data = 0; 850 } 851 852 void 853 ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf) 854 { 855 struct ath_common *common = ath5k_hw_common(ah); 856 857 BUG_ON(!bf); 858 if (!bf->skb) 859 return; 860 dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize, 861 DMA_FROM_DEVICE); 862 dev_kfree_skb_any(bf->skb); 863 bf->skb = NULL; 864 bf->skbaddr = 0; 865 bf->desc->ds_data = 0; 866 } 867 868 static void 869 ath5k_desc_free(struct ath5k_hw *ah) 870 { 871 struct ath5k_buf *bf; 872 873 list_for_each_entry(bf, &ah->txbuf, list) 874 ath5k_txbuf_free_skb(ah, bf); 875 list_for_each_entry(bf, &ah->rxbuf, list) 876 ath5k_rxbuf_free_skb(ah, bf); 877 list_for_each_entry(bf, &ah->bcbuf, list) 878 ath5k_txbuf_free_skb(ah, bf); 879 880 /* Free memory associated with all descriptors */ 881 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr); 882 ah->desc = NULL; 883 ah->desc_daddr = 0; 884 885 kfree(ah->bufptr); 886 ah->bufptr = NULL; 887 } 888 889 890 /**************\ 891 * Queues setup * 892 \**************/ 893 894 static struct ath5k_txq * 895 ath5k_txq_setup(struct ath5k_hw *ah, 896 int qtype, int subtype) 897 { 898 struct ath5k_txq *txq; 899 struct ath5k_txq_info qi = { 900 .tqi_subtype = subtype, 901 /* XXX: default values not correct for B and XR channels, 902 * but who cares? */ 903 .tqi_aifs = AR5K_TUNE_AIFS, 904 .tqi_cw_min = AR5K_TUNE_CWMIN, 905 .tqi_cw_max = AR5K_TUNE_CWMAX 906 }; 907 int qnum; 908 909 /* 910 * Enable interrupts only for EOL and DESC conditions. 911 * We mark tx descriptors to receive a DESC interrupt 912 * when a tx queue gets deep; otherwise we wait for the 913 * EOL to reap descriptors. Note that this is done to 914 * reduce interrupt load and this only defers reaping 915 * descriptors, never transmitting frames. Aside from 916 * reducing interrupts this also permits more concurrency. 917 * The only potential downside is if the tx queue backs 918 * up in which case the top half of the kernel may backup 919 * due to a lack of tx descriptors. 920 */ 921 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE | 922 AR5K_TXQ_FLAG_TXDESCINT_ENABLE; 923 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); 924 if (qnum < 0) { 925 /* 926 * NB: don't print a message, this happens 927 * normally on parts with too few tx queues 928 */ 929 return ERR_PTR(qnum); 930 } 931 txq = &ah->txqs[qnum]; 932 if (!txq->setup) { 933 txq->qnum = qnum; 934 txq->link = NULL; 935 INIT_LIST_HEAD(&txq->q); 936 spin_lock_init(&txq->lock); 937 txq->setup = true; 938 txq->txq_len = 0; 939 txq->txq_max = ATH5K_TXQ_LEN_MAX; 940 txq->txq_poll_mark = false; 941 txq->txq_stuck = 0; 942 } 943 return &ah->txqs[qnum]; 944 } 945 946 static int 947 ath5k_beaconq_setup(struct ath5k_hw *ah) 948 { 949 struct ath5k_txq_info qi = { 950 /* XXX: default values not correct for B and XR channels, 951 * but who cares? */ 952 .tqi_aifs = AR5K_TUNE_AIFS, 953 .tqi_cw_min = AR5K_TUNE_CWMIN, 954 .tqi_cw_max = AR5K_TUNE_CWMAX, 955 /* NB: for dynamic turbo, don't enable any other interrupts */ 956 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE 957 }; 958 959 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); 960 } 961 962 static int 963 ath5k_beaconq_config(struct ath5k_hw *ah) 964 { 965 struct ath5k_txq_info qi; 966 int ret; 967 968 ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi); 969 if (ret) 970 goto err; 971 972 if (ah->opmode == NL80211_IFTYPE_AP || 973 ah->opmode == NL80211_IFTYPE_MESH_POINT) { 974 /* 975 * Always burst out beacon and CAB traffic 976 * (aifs = cwmin = cwmax = 0) 977 */ 978 qi.tqi_aifs = 0; 979 qi.tqi_cw_min = 0; 980 qi.tqi_cw_max = 0; 981 } else if (ah->opmode == NL80211_IFTYPE_ADHOC) { 982 /* 983 * Adhoc mode; backoff between 0 and (2 * cw_min). 984 */ 985 qi.tqi_aifs = 0; 986 qi.tqi_cw_min = 0; 987 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN; 988 } 989 990 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 991 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n", 992 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max); 993 994 ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi); 995 if (ret) { 996 ATH5K_ERR(ah, "%s: unable to update parameters for beacon " 997 "hardware queue!\n", __func__); 998 goto err; 999 } 1000 ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq); /* push to h/w */ 1001 if (ret) 1002 goto err; 1003 1004 /* reconfigure cabq with ready time to 80% of beacon_interval */ 1005 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); 1006 if (ret) 1007 goto err; 1008 1009 qi.tqi_ready_time = (ah->bintval * 80) / 100; 1010 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); 1011 if (ret) 1012 goto err; 1013 1014 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB); 1015 err: 1016 return ret; 1017 } 1018 1019 /** 1020 * ath5k_drain_tx_buffs - Empty tx buffers 1021 * 1022 * @ah The &struct ath5k_hw 1023 * 1024 * Empty tx buffers from all queues in preparation 1025 * of a reset or during shutdown. 1026 * 1027 * NB: this assumes output has been stopped and 1028 * we do not need to block ath5k_tx_tasklet 1029 */ 1030 static void 1031 ath5k_drain_tx_buffs(struct ath5k_hw *ah) 1032 { 1033 struct ath5k_txq *txq; 1034 struct ath5k_buf *bf, *bf0; 1035 int i; 1036 1037 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) { 1038 if (ah->txqs[i].setup) { 1039 txq = &ah->txqs[i]; 1040 spin_lock_bh(&txq->lock); 1041 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 1042 ath5k_debug_printtxbuf(ah, bf); 1043 1044 ath5k_txbuf_free_skb(ah, bf); 1045 1046 spin_lock_bh(&ah->txbuflock); 1047 list_move_tail(&bf->list, &ah->txbuf); 1048 ah->txbuf_len++; 1049 txq->txq_len--; 1050 spin_unlock_bh(&ah->txbuflock); 1051 } 1052 txq->link = NULL; 1053 txq->txq_poll_mark = false; 1054 spin_unlock_bh(&txq->lock); 1055 } 1056 } 1057 } 1058 1059 static void 1060 ath5k_txq_release(struct ath5k_hw *ah) 1061 { 1062 struct ath5k_txq *txq = ah->txqs; 1063 unsigned int i; 1064 1065 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++) 1066 if (txq->setup) { 1067 ath5k_hw_release_tx_queue(ah, txq->qnum); 1068 txq->setup = false; 1069 } 1070 } 1071 1072 1073 /*************\ 1074 * RX Handling * 1075 \*************/ 1076 1077 /* 1078 * Enable the receive h/w following a reset. 1079 */ 1080 static int 1081 ath5k_rx_start(struct ath5k_hw *ah) 1082 { 1083 struct ath_common *common = ath5k_hw_common(ah); 1084 struct ath5k_buf *bf; 1085 int ret; 1086 1087 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz); 1088 1089 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n", 1090 common->cachelsz, common->rx_bufsize); 1091 1092 spin_lock_bh(&ah->rxbuflock); 1093 ah->rxlink = NULL; 1094 list_for_each_entry(bf, &ah->rxbuf, list) { 1095 ret = ath5k_rxbuf_setup(ah, bf); 1096 if (ret != 0) { 1097 spin_unlock_bh(&ah->rxbuflock); 1098 goto err; 1099 } 1100 } 1101 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list); 1102 ath5k_hw_set_rxdp(ah, bf->daddr); 1103 spin_unlock_bh(&ah->rxbuflock); 1104 1105 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */ 1106 ath5k_update_bssid_mask_and_opmode(ah, NULL); /* set filters, etc. */ 1107 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ 1108 1109 return 0; 1110 err: 1111 return ret; 1112 } 1113 1114 /* 1115 * Disable the receive logic on PCU (DRU) 1116 * In preparation for a shutdown. 1117 * 1118 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop 1119 * does. 1120 */ 1121 static void 1122 ath5k_rx_stop(struct ath5k_hw *ah) 1123 { 1124 1125 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ 1126 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */ 1127 1128 ath5k_debug_printrxbuffs(ah); 1129 } 1130 1131 static unsigned int 1132 ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb, 1133 struct ath5k_rx_status *rs) 1134 { 1135 struct ath_common *common = ath5k_hw_common(ah); 1136 struct ieee80211_hdr *hdr = (void *)skb->data; 1137 unsigned int keyix, hlen; 1138 1139 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) && 1140 rs->rs_keyix != AR5K_RXKEYIX_INVALID) 1141 return RX_FLAG_DECRYPTED; 1142 1143 /* Apparently when a default key is used to decrypt the packet 1144 the hw does not set the index used to decrypt. In such cases 1145 get the index from the packet. */ 1146 hlen = ieee80211_hdrlen(hdr->frame_control); 1147 if (ieee80211_has_protected(hdr->frame_control) && 1148 !(rs->rs_status & AR5K_RXERR_DECRYPT) && 1149 skb->len >= hlen + 4) { 1150 keyix = skb->data[hlen + 3] >> 6; 1151 1152 if (test_bit(keyix, common->keymap)) 1153 return RX_FLAG_DECRYPTED; 1154 } 1155 1156 return 0; 1157 } 1158 1159 1160 static void 1161 ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb, 1162 struct ieee80211_rx_status *rxs) 1163 { 1164 struct ath_common *common = ath5k_hw_common(ah); 1165 u64 tsf, bc_tstamp; 1166 u32 hw_tu; 1167 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1168 1169 if (ieee80211_is_beacon(mgmt->frame_control) && 1170 le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS && 1171 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) == 0) { 1172 /* 1173 * Received an IBSS beacon with the same BSSID. Hardware *must* 1174 * have updated the local TSF. We have to work around various 1175 * hardware bugs, though... 1176 */ 1177 tsf = ath5k_hw_get_tsf64(ah); 1178 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp); 1179 hw_tu = TSF_TO_TU(tsf); 1180 1181 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 1182 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n", 1183 (unsigned long long)bc_tstamp, 1184 (unsigned long long)rxs->mactime, 1185 (unsigned long long)(rxs->mactime - bc_tstamp), 1186 (unsigned long long)tsf); 1187 1188 /* 1189 * Sometimes the HW will give us a wrong tstamp in the rx 1190 * status, causing the timestamp extension to go wrong. 1191 * (This seems to happen especially with beacon frames bigger 1192 * than 78 byte (incl. FCS)) 1193 * But we know that the receive timestamp must be later than the 1194 * timestamp of the beacon since HW must have synced to that. 1195 * 1196 * NOTE: here we assume mactime to be after the frame was 1197 * received, not like mac80211 which defines it at the start. 1198 */ 1199 if (bc_tstamp > rxs->mactime) { 1200 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 1201 "fixing mactime from %llx to %llx\n", 1202 (unsigned long long)rxs->mactime, 1203 (unsigned long long)tsf); 1204 rxs->mactime = tsf; 1205 } 1206 1207 /* 1208 * Local TSF might have moved higher than our beacon timers, 1209 * in that case we have to update them to continue sending 1210 * beacons. This also takes care of synchronizing beacon sending 1211 * times with other stations. 1212 */ 1213 if (hw_tu >= ah->nexttbtt) 1214 ath5k_beacon_update_timers(ah, bc_tstamp); 1215 1216 /* Check if the beacon timers are still correct, because a TSF 1217 * update might have created a window between them - for a 1218 * longer description see the comment of this function: */ 1219 if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) { 1220 ath5k_beacon_update_timers(ah, bc_tstamp); 1221 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 1222 "fixed beacon timers after beacon receive\n"); 1223 } 1224 } 1225 } 1226 1227 static void 1228 ath5k_update_beacon_rssi(struct ath5k_hw *ah, struct sk_buff *skb, int rssi) 1229 { 1230 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1231 struct ath_common *common = ath5k_hw_common(ah); 1232 1233 /* only beacons from our BSSID */ 1234 if (!ieee80211_is_beacon(mgmt->frame_control) || 1235 memcmp(mgmt->bssid, common->curbssid, ETH_ALEN) != 0) 1236 return; 1237 1238 ewma_add(&ah->ah_beacon_rssi_avg, rssi); 1239 1240 /* in IBSS mode we should keep RSSI statistics per neighbour */ 1241 /* le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS */ 1242 } 1243 1244 /* 1245 * Compute padding position. skb must contain an IEEE 802.11 frame 1246 */ 1247 static int ath5k_common_padpos(struct sk_buff *skb) 1248 { 1249 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1250 __le16 frame_control = hdr->frame_control; 1251 int padpos = 24; 1252 1253 if (ieee80211_has_a4(frame_control)) 1254 padpos += ETH_ALEN; 1255 1256 if (ieee80211_is_data_qos(frame_control)) 1257 padpos += IEEE80211_QOS_CTL_LEN; 1258 1259 return padpos; 1260 } 1261 1262 /* 1263 * This function expects an 802.11 frame and returns the number of 1264 * bytes added, or -1 if we don't have enough header room. 1265 */ 1266 static int ath5k_add_padding(struct sk_buff *skb) 1267 { 1268 int padpos = ath5k_common_padpos(skb); 1269 int padsize = padpos & 3; 1270 1271 if (padsize && skb->len > padpos) { 1272 1273 if (skb_headroom(skb) < padsize) 1274 return -1; 1275 1276 skb_push(skb, padsize); 1277 memmove(skb->data, skb->data + padsize, padpos); 1278 return padsize; 1279 } 1280 1281 return 0; 1282 } 1283 1284 /* 1285 * The MAC header is padded to have 32-bit boundary if the 1286 * packet payload is non-zero. The general calculation for 1287 * padsize would take into account odd header lengths: 1288 * padsize = 4 - (hdrlen & 3); however, since only 1289 * even-length headers are used, padding can only be 0 or 2 1290 * bytes and we can optimize this a bit. We must not try to 1291 * remove padding from short control frames that do not have a 1292 * payload. 1293 * 1294 * This function expects an 802.11 frame and returns the number of 1295 * bytes removed. 1296 */ 1297 static int ath5k_remove_padding(struct sk_buff *skb) 1298 { 1299 int padpos = ath5k_common_padpos(skb); 1300 int padsize = padpos & 3; 1301 1302 if (padsize && skb->len >= padpos + padsize) { 1303 memmove(skb->data + padsize, skb->data, padpos); 1304 skb_pull(skb, padsize); 1305 return padsize; 1306 } 1307 1308 return 0; 1309 } 1310 1311 static void 1312 ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb, 1313 struct ath5k_rx_status *rs) 1314 { 1315 struct ieee80211_rx_status *rxs; 1316 1317 ath5k_remove_padding(skb); 1318 1319 rxs = IEEE80211_SKB_RXCB(skb); 1320 1321 rxs->flag = 0; 1322 if (unlikely(rs->rs_status & AR5K_RXERR_MIC)) 1323 rxs->flag |= RX_FLAG_MMIC_ERROR; 1324 1325 /* 1326 * always extend the mac timestamp, since this information is 1327 * also needed for proper IBSS merging. 1328 * 1329 * XXX: it might be too late to do it here, since rs_tstamp is 1330 * 15bit only. that means TSF extension has to be done within 1331 * 32768usec (about 32ms). it might be necessary to move this to 1332 * the interrupt handler, like it is done in madwifi. 1333 * 1334 * Unfortunately we don't know when the hardware takes the rx 1335 * timestamp (beginning of phy frame, data frame, end of rx?). 1336 * The only thing we know is that it is hardware specific... 1337 * On AR5213 it seems the rx timestamp is at the end of the 1338 * frame, but I'm not sure. 1339 * 1340 * NOTE: mac80211 defines mactime at the beginning of the first 1341 * data symbol. Since we don't have any time references it's 1342 * impossible to comply to that. This affects IBSS merge only 1343 * right now, so it's not too bad... 1344 */ 1345 rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp); 1346 rxs->flag |= RX_FLAG_MACTIME_MPDU; 1347 1348 rxs->freq = ah->curchan->center_freq; 1349 rxs->band = ah->curchan->band; 1350 1351 rxs->signal = ah->ah_noise_floor + rs->rs_rssi; 1352 1353 rxs->antenna = rs->rs_antenna; 1354 1355 if (rs->rs_antenna > 0 && rs->rs_antenna < 5) 1356 ah->stats.antenna_rx[rs->rs_antenna]++; 1357 else 1358 ah->stats.antenna_rx[0]++; /* invalid */ 1359 1360 rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate); 1361 rxs->flag |= ath5k_rx_decrypted(ah, skb, rs); 1362 1363 if (rxs->rate_idx >= 0 && rs->rs_rate == 1364 ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short) 1365 rxs->flag |= RX_FLAG_SHORTPRE; 1366 1367 trace_ath5k_rx(ah, skb); 1368 1369 ath5k_update_beacon_rssi(ah, skb, rs->rs_rssi); 1370 1371 /* check beacons in IBSS mode */ 1372 if (ah->opmode == NL80211_IFTYPE_ADHOC) 1373 ath5k_check_ibss_tsf(ah, skb, rxs); 1374 1375 ieee80211_rx(ah->hw, skb); 1376 } 1377 1378 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not? 1379 * 1380 * Check if we want to further process this frame or not. Also update 1381 * statistics. Return true if we want this frame, false if not. 1382 */ 1383 static bool 1384 ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs) 1385 { 1386 ah->stats.rx_all_count++; 1387 ah->stats.rx_bytes_count += rs->rs_datalen; 1388 1389 if (unlikely(rs->rs_status)) { 1390 if (rs->rs_status & AR5K_RXERR_CRC) 1391 ah->stats.rxerr_crc++; 1392 if (rs->rs_status & AR5K_RXERR_FIFO) 1393 ah->stats.rxerr_fifo++; 1394 if (rs->rs_status & AR5K_RXERR_PHY) { 1395 ah->stats.rxerr_phy++; 1396 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32) 1397 ah->stats.rxerr_phy_code[rs->rs_phyerr]++; 1398 return false; 1399 } 1400 if (rs->rs_status & AR5K_RXERR_DECRYPT) { 1401 /* 1402 * Decrypt error. If the error occurred 1403 * because there was no hardware key, then 1404 * let the frame through so the upper layers 1405 * can process it. This is necessary for 5210 1406 * parts which have no way to setup a ``clear'' 1407 * key cache entry. 1408 * 1409 * XXX do key cache faulting 1410 */ 1411 ah->stats.rxerr_decrypt++; 1412 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID && 1413 !(rs->rs_status & AR5K_RXERR_CRC)) 1414 return true; 1415 } 1416 if (rs->rs_status & AR5K_RXERR_MIC) { 1417 ah->stats.rxerr_mic++; 1418 return true; 1419 } 1420 1421 /* reject any frames with non-crypto errors */ 1422 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT)) 1423 return false; 1424 } 1425 1426 if (unlikely(rs->rs_more)) { 1427 ah->stats.rxerr_jumbo++; 1428 return false; 1429 } 1430 return true; 1431 } 1432 1433 static void 1434 ath5k_set_current_imask(struct ath5k_hw *ah) 1435 { 1436 enum ath5k_int imask; 1437 unsigned long flags; 1438 1439 spin_lock_irqsave(&ah->irqlock, flags); 1440 imask = ah->imask; 1441 if (ah->rx_pending) 1442 imask &= ~AR5K_INT_RX_ALL; 1443 if (ah->tx_pending) 1444 imask &= ~AR5K_INT_TX_ALL; 1445 ath5k_hw_set_imr(ah, imask); 1446 spin_unlock_irqrestore(&ah->irqlock, flags); 1447 } 1448 1449 static void 1450 ath5k_tasklet_rx(unsigned long data) 1451 { 1452 struct ath5k_rx_status rs = {}; 1453 struct sk_buff *skb, *next_skb; 1454 dma_addr_t next_skb_addr; 1455 struct ath5k_hw *ah = (void *)data; 1456 struct ath_common *common = ath5k_hw_common(ah); 1457 struct ath5k_buf *bf; 1458 struct ath5k_desc *ds; 1459 int ret; 1460 1461 spin_lock(&ah->rxbuflock); 1462 if (list_empty(&ah->rxbuf)) { 1463 ATH5K_WARN(ah, "empty rx buf pool\n"); 1464 goto unlock; 1465 } 1466 do { 1467 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list); 1468 BUG_ON(bf->skb == NULL); 1469 skb = bf->skb; 1470 ds = bf->desc; 1471 1472 /* bail if HW is still using self-linked descriptor */ 1473 if (ath5k_hw_get_rxdp(ah) == bf->daddr) 1474 break; 1475 1476 ret = ah->ah_proc_rx_desc(ah, ds, &rs); 1477 if (unlikely(ret == -EINPROGRESS)) 1478 break; 1479 else if (unlikely(ret)) { 1480 ATH5K_ERR(ah, "error in processing rx descriptor\n"); 1481 ah->stats.rxerr_proc++; 1482 break; 1483 } 1484 1485 if (ath5k_receive_frame_ok(ah, &rs)) { 1486 next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr); 1487 1488 /* 1489 * If we can't replace bf->skb with a new skb under 1490 * memory pressure, just skip this packet 1491 */ 1492 if (!next_skb) 1493 goto next; 1494 1495 dma_unmap_single(ah->dev, bf->skbaddr, 1496 common->rx_bufsize, 1497 DMA_FROM_DEVICE); 1498 1499 skb_put(skb, rs.rs_datalen); 1500 1501 ath5k_receive_frame(ah, skb, &rs); 1502 1503 bf->skb = next_skb; 1504 bf->skbaddr = next_skb_addr; 1505 } 1506 next: 1507 list_move_tail(&bf->list, &ah->rxbuf); 1508 } while (ath5k_rxbuf_setup(ah, bf) == 0); 1509 unlock: 1510 spin_unlock(&ah->rxbuflock); 1511 ah->rx_pending = false; 1512 ath5k_set_current_imask(ah); 1513 } 1514 1515 1516 /*************\ 1517 * TX Handling * 1518 \*************/ 1519 1520 void 1521 ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb, 1522 struct ath5k_txq *txq) 1523 { 1524 struct ath5k_hw *ah = hw->priv; 1525 struct ath5k_buf *bf; 1526 unsigned long flags; 1527 int padsize; 1528 1529 trace_ath5k_tx(ah, skb, txq); 1530 1531 /* 1532 * The hardware expects the header padded to 4 byte boundaries. 1533 * If this is not the case, we add the padding after the header. 1534 */ 1535 padsize = ath5k_add_padding(skb); 1536 if (padsize < 0) { 1537 ATH5K_ERR(ah, "tx hdrlen not %%4: not enough" 1538 " headroom to pad"); 1539 goto drop_packet; 1540 } 1541 1542 if (txq->txq_len >= txq->txq_max && 1543 txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX) 1544 ieee80211_stop_queue(hw, txq->qnum); 1545 1546 spin_lock_irqsave(&ah->txbuflock, flags); 1547 if (list_empty(&ah->txbuf)) { 1548 ATH5K_ERR(ah, "no further txbuf available, dropping packet\n"); 1549 spin_unlock_irqrestore(&ah->txbuflock, flags); 1550 ieee80211_stop_queues(hw); 1551 goto drop_packet; 1552 } 1553 bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list); 1554 list_del(&bf->list); 1555 ah->txbuf_len--; 1556 if (list_empty(&ah->txbuf)) 1557 ieee80211_stop_queues(hw); 1558 spin_unlock_irqrestore(&ah->txbuflock, flags); 1559 1560 bf->skb = skb; 1561 1562 if (ath5k_txbuf_setup(ah, bf, txq, padsize)) { 1563 bf->skb = NULL; 1564 spin_lock_irqsave(&ah->txbuflock, flags); 1565 list_add_tail(&bf->list, &ah->txbuf); 1566 ah->txbuf_len++; 1567 spin_unlock_irqrestore(&ah->txbuflock, flags); 1568 goto drop_packet; 1569 } 1570 return; 1571 1572 drop_packet: 1573 dev_kfree_skb_any(skb); 1574 } 1575 1576 static void 1577 ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb, 1578 struct ath5k_txq *txq, struct ath5k_tx_status *ts) 1579 { 1580 struct ieee80211_tx_info *info; 1581 u8 tries[3]; 1582 int i; 1583 1584 ah->stats.tx_all_count++; 1585 ah->stats.tx_bytes_count += skb->len; 1586 info = IEEE80211_SKB_CB(skb); 1587 1588 tries[0] = info->status.rates[0].count; 1589 tries[1] = info->status.rates[1].count; 1590 tries[2] = info->status.rates[2].count; 1591 1592 ieee80211_tx_info_clear_status(info); 1593 1594 for (i = 0; i < ts->ts_final_idx; i++) { 1595 struct ieee80211_tx_rate *r = 1596 &info->status.rates[i]; 1597 1598 r->count = tries[i]; 1599 } 1600 1601 info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry; 1602 info->status.rates[ts->ts_final_idx + 1].idx = -1; 1603 1604 if (unlikely(ts->ts_status)) { 1605 ah->stats.ack_fail++; 1606 if (ts->ts_status & AR5K_TXERR_FILT) { 1607 info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 1608 ah->stats.txerr_filt++; 1609 } 1610 if (ts->ts_status & AR5K_TXERR_XRETRY) 1611 ah->stats.txerr_retry++; 1612 if (ts->ts_status & AR5K_TXERR_FIFO) 1613 ah->stats.txerr_fifo++; 1614 } else { 1615 info->flags |= IEEE80211_TX_STAT_ACK; 1616 info->status.ack_signal = ts->ts_rssi; 1617 1618 /* count the successful attempt as well */ 1619 info->status.rates[ts->ts_final_idx].count++; 1620 } 1621 1622 /* 1623 * Remove MAC header padding before giving the frame 1624 * back to mac80211. 1625 */ 1626 ath5k_remove_padding(skb); 1627 1628 if (ts->ts_antenna > 0 && ts->ts_antenna < 5) 1629 ah->stats.antenna_tx[ts->ts_antenna]++; 1630 else 1631 ah->stats.antenna_tx[0]++; /* invalid */ 1632 1633 trace_ath5k_tx_complete(ah, skb, txq, ts); 1634 ieee80211_tx_status(ah->hw, skb); 1635 } 1636 1637 static void 1638 ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq) 1639 { 1640 struct ath5k_tx_status ts = {}; 1641 struct ath5k_buf *bf, *bf0; 1642 struct ath5k_desc *ds; 1643 struct sk_buff *skb; 1644 int ret; 1645 1646 spin_lock(&txq->lock); 1647 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 1648 1649 txq->txq_poll_mark = false; 1650 1651 /* skb might already have been processed last time. */ 1652 if (bf->skb != NULL) { 1653 ds = bf->desc; 1654 1655 ret = ah->ah_proc_tx_desc(ah, ds, &ts); 1656 if (unlikely(ret == -EINPROGRESS)) 1657 break; 1658 else if (unlikely(ret)) { 1659 ATH5K_ERR(ah, 1660 "error %d while processing " 1661 "queue %u\n", ret, txq->qnum); 1662 break; 1663 } 1664 1665 skb = bf->skb; 1666 bf->skb = NULL; 1667 1668 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, 1669 DMA_TO_DEVICE); 1670 ath5k_tx_frame_completed(ah, skb, txq, &ts); 1671 } 1672 1673 /* 1674 * It's possible that the hardware can say the buffer is 1675 * completed when it hasn't yet loaded the ds_link from 1676 * host memory and moved on. 1677 * Always keep the last descriptor to avoid HW races... 1678 */ 1679 if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) { 1680 spin_lock(&ah->txbuflock); 1681 list_move_tail(&bf->list, &ah->txbuf); 1682 ah->txbuf_len++; 1683 txq->txq_len--; 1684 spin_unlock(&ah->txbuflock); 1685 } 1686 } 1687 spin_unlock(&txq->lock); 1688 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4) 1689 ieee80211_wake_queue(ah->hw, txq->qnum); 1690 } 1691 1692 static void 1693 ath5k_tasklet_tx(unsigned long data) 1694 { 1695 int i; 1696 struct ath5k_hw *ah = (void *)data; 1697 1698 for (i = 0; i < AR5K_NUM_TX_QUEUES; i++) 1699 if (ah->txqs[i].setup && (ah->ah_txq_isr_txok_all & BIT(i))) 1700 ath5k_tx_processq(ah, &ah->txqs[i]); 1701 1702 ah->tx_pending = false; 1703 ath5k_set_current_imask(ah); 1704 } 1705 1706 1707 /*****************\ 1708 * Beacon handling * 1709 \*****************/ 1710 1711 /* 1712 * Setup the beacon frame for transmit. 1713 */ 1714 static int 1715 ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf) 1716 { 1717 struct sk_buff *skb = bf->skb; 1718 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1719 struct ath5k_desc *ds; 1720 int ret = 0; 1721 u8 antenna; 1722 u32 flags; 1723 const int padsize = 0; 1724 1725 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len, 1726 DMA_TO_DEVICE); 1727 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] " 1728 "skbaddr %llx\n", skb, skb->data, skb->len, 1729 (unsigned long long)bf->skbaddr); 1730 1731 if (dma_mapping_error(ah->dev, bf->skbaddr)) { 1732 ATH5K_ERR(ah, "beacon DMA mapping failed\n"); 1733 dev_kfree_skb_any(skb); 1734 bf->skb = NULL; 1735 return -EIO; 1736 } 1737 1738 ds = bf->desc; 1739 antenna = ah->ah_tx_ant; 1740 1741 flags = AR5K_TXDESC_NOACK; 1742 if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) { 1743 ds->ds_link = bf->daddr; /* self-linked */ 1744 flags |= AR5K_TXDESC_VEOL; 1745 } else 1746 ds->ds_link = 0; 1747 1748 /* 1749 * If we use multiple antennas on AP and use 1750 * the Sectored AP scenario, switch antenna every 1751 * 4 beacons to make sure everybody hears our AP. 1752 * When a client tries to associate, hw will keep 1753 * track of the tx antenna to be used for this client 1754 * automatically, based on ACKed packets. 1755 * 1756 * Note: AP still listens and transmits RTS on the 1757 * default antenna which is supposed to be an omni. 1758 * 1759 * Note2: On sectored scenarios it's possible to have 1760 * multiple antennas (1 omni -- the default -- and 14 1761 * sectors), so if we choose to actually support this 1762 * mode, we need to allow the user to set how many antennas 1763 * we have and tweak the code below to send beacons 1764 * on all of them. 1765 */ 1766 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP) 1767 antenna = ah->bsent & 4 ? 2 : 1; 1768 1769 1770 /* FIXME: If we are in g mode and rate is a CCK rate 1771 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta 1772 * from tx power (value is in dB units already) */ 1773 ds->ds_data = bf->skbaddr; 1774 ret = ah->ah_setup_tx_desc(ah, ds, skb->len, 1775 ieee80211_get_hdrlen_from_skb(skb), padsize, 1776 AR5K_PKT_TYPE_BEACON, (ah->power_level * 2), 1777 ieee80211_get_tx_rate(ah->hw, info)->hw_value, 1778 1, AR5K_TXKEYIX_INVALID, 1779 antenna, flags, 0, 0); 1780 if (ret) 1781 goto err_unmap; 1782 1783 return 0; 1784 err_unmap: 1785 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); 1786 return ret; 1787 } 1788 1789 /* 1790 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc, 1791 * this is called only once at config_bss time, for AP we do it every 1792 * SWBA interrupt so that the TIM will reflect buffered frames. 1793 * 1794 * Called with the beacon lock. 1795 */ 1796 int 1797 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1798 { 1799 int ret; 1800 struct ath5k_hw *ah = hw->priv; 1801 struct ath5k_vif *avf = (void *)vif->drv_priv; 1802 struct sk_buff *skb; 1803 1804 if (WARN_ON(!vif)) { 1805 ret = -EINVAL; 1806 goto out; 1807 } 1808 1809 skb = ieee80211_beacon_get(hw, vif); 1810 1811 if (!skb) { 1812 ret = -ENOMEM; 1813 goto out; 1814 } 1815 1816 ath5k_txbuf_free_skb(ah, avf->bbuf); 1817 avf->bbuf->skb = skb; 1818 ret = ath5k_beacon_setup(ah, avf->bbuf); 1819 out: 1820 return ret; 1821 } 1822 1823 /* 1824 * Transmit a beacon frame at SWBA. Dynamic updates to the 1825 * frame contents are done as needed and the slot time is 1826 * also adjusted based on current state. 1827 * 1828 * This is called from software irq context (beacontq tasklets) 1829 * or user context from ath5k_beacon_config. 1830 */ 1831 static void 1832 ath5k_beacon_send(struct ath5k_hw *ah) 1833 { 1834 struct ieee80211_vif *vif; 1835 struct ath5k_vif *avf; 1836 struct ath5k_buf *bf; 1837 struct sk_buff *skb; 1838 int err; 1839 1840 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n"); 1841 1842 /* 1843 * Check if the previous beacon has gone out. If 1844 * not, don't don't try to post another: skip this 1845 * period and wait for the next. Missed beacons 1846 * indicate a problem and should not occur. If we 1847 * miss too many consecutive beacons reset the device. 1848 */ 1849 if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) { 1850 ah->bmisscount++; 1851 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 1852 "missed %u consecutive beacons\n", ah->bmisscount); 1853 if (ah->bmisscount > 10) { /* NB: 10 is a guess */ 1854 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 1855 "stuck beacon time (%u missed)\n", 1856 ah->bmisscount); 1857 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 1858 "stuck beacon, resetting\n"); 1859 ieee80211_queue_work(ah->hw, &ah->reset_work); 1860 } 1861 return; 1862 } 1863 if (unlikely(ah->bmisscount != 0)) { 1864 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 1865 "resume beacon xmit after %u misses\n", 1866 ah->bmisscount); 1867 ah->bmisscount = 0; 1868 } 1869 1870 if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs + 1871 ah->num_mesh_vifs > 1) || 1872 ah->opmode == NL80211_IFTYPE_MESH_POINT) { 1873 u64 tsf = ath5k_hw_get_tsf64(ah); 1874 u32 tsftu = TSF_TO_TU(tsf); 1875 int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval; 1876 vif = ah->bslot[(slot + 1) % ATH_BCBUF]; 1877 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 1878 "tsf %llx tsftu %x intval %u slot %u vif %p\n", 1879 (unsigned long long)tsf, tsftu, ah->bintval, slot, vif); 1880 } else /* only one interface */ 1881 vif = ah->bslot[0]; 1882 1883 if (!vif) 1884 return; 1885 1886 avf = (void *)vif->drv_priv; 1887 bf = avf->bbuf; 1888 1889 /* 1890 * Stop any current dma and put the new frame on the queue. 1891 * This should never fail since we check above that no frames 1892 * are still pending on the queue. 1893 */ 1894 if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) { 1895 ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq); 1896 /* NB: hw still stops DMA, so proceed */ 1897 } 1898 1899 /* refresh the beacon for AP or MESH mode */ 1900 if (ah->opmode == NL80211_IFTYPE_AP || 1901 ah->opmode == NL80211_IFTYPE_MESH_POINT) { 1902 err = ath5k_beacon_update(ah->hw, vif); 1903 if (err) 1904 return; 1905 } 1906 1907 if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION || 1908 ah->opmode == NL80211_IFTYPE_MONITOR)) { 1909 ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf->skb); 1910 return; 1911 } 1912 1913 trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]); 1914 1915 ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr); 1916 ath5k_hw_start_tx_dma(ah, ah->bhalq); 1917 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n", 1918 ah->bhalq, (unsigned long long)bf->daddr, bf->desc); 1919 1920 skb = ieee80211_get_buffered_bc(ah->hw, vif); 1921 while (skb) { 1922 ath5k_tx_queue(ah->hw, skb, ah->cabq); 1923 1924 if (ah->cabq->txq_len >= ah->cabq->txq_max) 1925 break; 1926 1927 skb = ieee80211_get_buffered_bc(ah->hw, vif); 1928 } 1929 1930 ah->bsent++; 1931 } 1932 1933 /** 1934 * ath5k_beacon_update_timers - update beacon timers 1935 * 1936 * @ah: struct ath5k_hw pointer we are operating on 1937 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a 1938 * beacon timer update based on the current HW TSF. 1939 * 1940 * Calculate the next target beacon transmit time (TBTT) based on the timestamp 1941 * of a received beacon or the current local hardware TSF and write it to the 1942 * beacon timer registers. 1943 * 1944 * This is called in a variety of situations, e.g. when a beacon is received, 1945 * when a TSF update has been detected, but also when an new IBSS is created or 1946 * when we otherwise know we have to update the timers, but we keep it in this 1947 * function to have it all together in one place. 1948 */ 1949 void 1950 ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf) 1951 { 1952 u32 nexttbtt, intval, hw_tu, bc_tu; 1953 u64 hw_tsf; 1954 1955 intval = ah->bintval & AR5K_BEACON_PERIOD; 1956 if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs 1957 + ah->num_mesh_vifs > 1) { 1958 intval /= ATH_BCBUF; /* staggered multi-bss beacons */ 1959 if (intval < 15) 1960 ATH5K_WARN(ah, "intval %u is too low, min 15\n", 1961 intval); 1962 } 1963 if (WARN_ON(!intval)) 1964 return; 1965 1966 /* beacon TSF converted to TU */ 1967 bc_tu = TSF_TO_TU(bc_tsf); 1968 1969 /* current TSF converted to TU */ 1970 hw_tsf = ath5k_hw_get_tsf64(ah); 1971 hw_tu = TSF_TO_TU(hw_tsf); 1972 1973 #define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3) 1974 /* We use FUDGE to make sure the next TBTT is ahead of the current TU. 1975 * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer 1976 * configuration we need to make sure it is bigger than that. */ 1977 1978 if (bc_tsf == -1) { 1979 /* 1980 * no beacons received, called internally. 1981 * just need to refresh timers based on HW TSF. 1982 */ 1983 nexttbtt = roundup(hw_tu + FUDGE, intval); 1984 } else if (bc_tsf == 0) { 1985 /* 1986 * no beacon received, probably called by ath5k_reset_tsf(). 1987 * reset TSF to start with 0. 1988 */ 1989 nexttbtt = intval; 1990 intval |= AR5K_BEACON_RESET_TSF; 1991 } else if (bc_tsf > hw_tsf) { 1992 /* 1993 * beacon received, SW merge happened but HW TSF not yet updated. 1994 * not possible to reconfigure timers yet, but next time we 1995 * receive a beacon with the same BSSID, the hardware will 1996 * automatically update the TSF and then we need to reconfigure 1997 * the timers. 1998 */ 1999 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2000 "need to wait for HW TSF sync\n"); 2001 return; 2002 } else { 2003 /* 2004 * most important case for beacon synchronization between STA. 2005 * 2006 * beacon received and HW TSF has been already updated by HW. 2007 * update next TBTT based on the TSF of the beacon, but make 2008 * sure it is ahead of our local TSF timer. 2009 */ 2010 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval); 2011 } 2012 #undef FUDGE 2013 2014 ah->nexttbtt = nexttbtt; 2015 2016 intval |= AR5K_BEACON_ENA; 2017 ath5k_hw_init_beacon_timers(ah, nexttbtt, intval); 2018 2019 /* 2020 * debugging output last in order to preserve the time critical aspect 2021 * of this function 2022 */ 2023 if (bc_tsf == -1) 2024 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2025 "reconfigured timers based on HW TSF\n"); 2026 else if (bc_tsf == 0) 2027 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2028 "reset HW TSF and timers\n"); 2029 else 2030 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2031 "updated timers based on beacon TSF\n"); 2032 2033 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2034 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n", 2035 (unsigned long long) bc_tsf, 2036 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt); 2037 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n", 2038 intval & AR5K_BEACON_PERIOD, 2039 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "", 2040 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : ""); 2041 } 2042 2043 /** 2044 * ath5k_beacon_config - Configure the beacon queues and interrupts 2045 * 2046 * @ah: struct ath5k_hw pointer we are operating on 2047 * 2048 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA 2049 * interrupts to detect TSF updates only. 2050 */ 2051 void 2052 ath5k_beacon_config(struct ath5k_hw *ah) 2053 { 2054 unsigned long flags; 2055 2056 spin_lock_irqsave(&ah->block, flags); 2057 ah->bmisscount = 0; 2058 ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA); 2059 2060 if (ah->enable_beacon) { 2061 /* 2062 * In IBSS mode we use a self-linked tx descriptor and let the 2063 * hardware send the beacons automatically. We have to load it 2064 * only once here. 2065 * We use the SWBA interrupt only to keep track of the beacon 2066 * timers in order to detect automatic TSF updates. 2067 */ 2068 ath5k_beaconq_config(ah); 2069 2070 ah->imask |= AR5K_INT_SWBA; 2071 2072 if (ah->opmode == NL80211_IFTYPE_ADHOC) { 2073 if (ath5k_hw_hasveol(ah)) 2074 ath5k_beacon_send(ah); 2075 } else 2076 ath5k_beacon_update_timers(ah, -1); 2077 } else { 2078 ath5k_hw_stop_beacon_queue(ah, ah->bhalq); 2079 } 2080 2081 ath5k_hw_set_imr(ah, ah->imask); 2082 mmiowb(); 2083 spin_unlock_irqrestore(&ah->block, flags); 2084 } 2085 2086 static void ath5k_tasklet_beacon(unsigned long data) 2087 { 2088 struct ath5k_hw *ah = (struct ath5k_hw *) data; 2089 2090 /* 2091 * Software beacon alert--time to send a beacon. 2092 * 2093 * In IBSS mode we use this interrupt just to 2094 * keep track of the next TBTT (target beacon 2095 * transmission time) in order to detect whether 2096 * automatic TSF updates happened. 2097 */ 2098 if (ah->opmode == NL80211_IFTYPE_ADHOC) { 2099 /* XXX: only if VEOL supported */ 2100 u64 tsf = ath5k_hw_get_tsf64(ah); 2101 ah->nexttbtt += ah->bintval; 2102 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 2103 "SWBA nexttbtt: %x hw_tu: %x " 2104 "TSF: %llx\n", 2105 ah->nexttbtt, 2106 TSF_TO_TU(tsf), 2107 (unsigned long long) tsf); 2108 } else { 2109 spin_lock(&ah->block); 2110 ath5k_beacon_send(ah); 2111 spin_unlock(&ah->block); 2112 } 2113 } 2114 2115 2116 /********************\ 2117 * Interrupt handling * 2118 \********************/ 2119 2120 static void 2121 ath5k_intr_calibration_poll(struct ath5k_hw *ah) 2122 { 2123 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) && 2124 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) && 2125 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) { 2126 2127 /* Run ANI only when calibration is not active */ 2128 2129 ah->ah_cal_next_ani = jiffies + 2130 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI); 2131 tasklet_schedule(&ah->ani_tasklet); 2132 2133 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_short) && 2134 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) && 2135 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) { 2136 2137 /* Run calibration only when another calibration 2138 * is not running. 2139 * 2140 * Note: This is for both full/short calibration, 2141 * if it's time for a full one, ath5k_calibrate_work will deal 2142 * with it. */ 2143 2144 ah->ah_cal_next_short = jiffies + 2145 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT); 2146 ieee80211_queue_work(ah->hw, &ah->calib_work); 2147 } 2148 /* we could use SWI to generate enough interrupts to meet our 2149 * calibration interval requirements, if necessary: 2150 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */ 2151 } 2152 2153 static void 2154 ath5k_schedule_rx(struct ath5k_hw *ah) 2155 { 2156 ah->rx_pending = true; 2157 tasklet_schedule(&ah->rxtq); 2158 } 2159 2160 static void 2161 ath5k_schedule_tx(struct ath5k_hw *ah) 2162 { 2163 ah->tx_pending = true; 2164 tasklet_schedule(&ah->txtq); 2165 } 2166 2167 static irqreturn_t 2168 ath5k_intr(int irq, void *dev_id) 2169 { 2170 struct ath5k_hw *ah = dev_id; 2171 enum ath5k_int status; 2172 unsigned int counter = 1000; 2173 2174 2175 /* 2176 * If hw is not ready (or detached) and we get an 2177 * interrupt, or if we have no interrupts pending 2178 * (that means it's not for us) skip it. 2179 * 2180 * NOTE: Group 0/1 PCI interface registers are not 2181 * supported on WiSOCs, so we can't check for pending 2182 * interrupts (ISR belongs to another register group 2183 * so we are ok). 2184 */ 2185 if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) || 2186 ((ath5k_get_bus_type(ah) != ATH_AHB) && 2187 !ath5k_hw_is_intr_pending(ah)))) 2188 return IRQ_NONE; 2189 2190 /** Main loop **/ 2191 do { 2192 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ 2193 2194 ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n", 2195 status, ah->imask); 2196 2197 /* 2198 * Fatal hw error -> Log and reset 2199 * 2200 * Fatal errors are unrecoverable so we have to 2201 * reset the card. These errors include bus and 2202 * dma errors. 2203 */ 2204 if (unlikely(status & AR5K_INT_FATAL)) { 2205 2206 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2207 "fatal int, resetting\n"); 2208 ieee80211_queue_work(ah->hw, &ah->reset_work); 2209 2210 /* 2211 * RX Overrun -> Count and reset if needed 2212 * 2213 * Receive buffers are full. Either the bus is busy or 2214 * the CPU is not fast enough to process all received 2215 * frames. 2216 */ 2217 } else if (unlikely(status & AR5K_INT_RXORN)) { 2218 2219 /* 2220 * Older chipsets need a reset to come out of this 2221 * condition, but we treat it as RX for newer chips. 2222 * We don't know exactly which versions need a reset 2223 * this guess is copied from the HAL. 2224 */ 2225 ah->stats.rxorn_intr++; 2226 2227 if (ah->ah_mac_srev < AR5K_SREV_AR5212) { 2228 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2229 "rx overrun, resetting\n"); 2230 ieee80211_queue_work(ah->hw, &ah->reset_work); 2231 } else 2232 ath5k_schedule_rx(ah); 2233 2234 } else { 2235 2236 /* Software Beacon Alert -> Schedule beacon tasklet */ 2237 if (status & AR5K_INT_SWBA) 2238 tasklet_hi_schedule(&ah->beacontq); 2239 2240 /* 2241 * No more RX descriptors -> Just count 2242 * 2243 * NB: the hardware should re-read the link when 2244 * RXE bit is written, but it doesn't work at 2245 * least on older hardware revs. 2246 */ 2247 if (status & AR5K_INT_RXEOL) 2248 ah->stats.rxeol_intr++; 2249 2250 2251 /* TX Underrun -> Bump tx trigger level */ 2252 if (status & AR5K_INT_TXURN) 2253 ath5k_hw_update_tx_triglevel(ah, true); 2254 2255 /* RX -> Schedule rx tasklet */ 2256 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR)) 2257 ath5k_schedule_rx(ah); 2258 2259 /* TX -> Schedule tx tasklet */ 2260 if (status & (AR5K_INT_TXOK 2261 | AR5K_INT_TXDESC 2262 | AR5K_INT_TXERR 2263 | AR5K_INT_TXEOL)) 2264 ath5k_schedule_tx(ah); 2265 2266 /* Missed beacon -> TODO 2267 if (status & AR5K_INT_BMISS) 2268 */ 2269 2270 /* MIB event -> Update counters and notify ANI */ 2271 if (status & AR5K_INT_MIB) { 2272 ah->stats.mib_intr++; 2273 ath5k_hw_update_mib_counters(ah); 2274 ath5k_ani_mib_intr(ah); 2275 } 2276 2277 /* GPIO -> Notify RFKill layer */ 2278 if (status & AR5K_INT_GPIO) 2279 tasklet_schedule(&ah->rf_kill.toggleq); 2280 2281 } 2282 2283 if (ath5k_get_bus_type(ah) == ATH_AHB) 2284 break; 2285 2286 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0); 2287 2288 /* 2289 * Until we handle rx/tx interrupts mask them on IMR 2290 * 2291 * NOTE: ah->(rx/tx)_pending are set when scheduling the tasklets 2292 * and unset after we 've handled the interrupts. 2293 */ 2294 if (ah->rx_pending || ah->tx_pending) 2295 ath5k_set_current_imask(ah); 2296 2297 if (unlikely(!counter)) 2298 ATH5K_WARN(ah, "too many interrupts, giving up for now\n"); 2299 2300 /* Fire up calibration poll */ 2301 ath5k_intr_calibration_poll(ah); 2302 2303 return IRQ_HANDLED; 2304 } 2305 2306 /* 2307 * Periodically recalibrate the PHY to account 2308 * for temperature/environment changes. 2309 */ 2310 static void 2311 ath5k_calibrate_work(struct work_struct *work) 2312 { 2313 struct ath5k_hw *ah = container_of(work, struct ath5k_hw, 2314 calib_work); 2315 2316 /* Should we run a full calibration ? */ 2317 if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) { 2318 2319 ah->ah_cal_next_full = jiffies + 2320 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL); 2321 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL; 2322 2323 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, 2324 "running full calibration\n"); 2325 2326 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) { 2327 /* 2328 * Rfgain is out of bounds, reset the chip 2329 * to load new gain values. 2330 */ 2331 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2332 "got new rfgain, resetting\n"); 2333 ieee80211_queue_work(ah->hw, &ah->reset_work); 2334 } 2335 } else 2336 ah->ah_cal_mask |= AR5K_CALIBRATION_SHORT; 2337 2338 2339 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n", 2340 ieee80211_frequency_to_channel(ah->curchan->center_freq), 2341 ah->curchan->hw_value); 2342 2343 if (ath5k_hw_phy_calibrate(ah, ah->curchan)) 2344 ATH5K_ERR(ah, "calibration of channel %u failed\n", 2345 ieee80211_frequency_to_channel( 2346 ah->curchan->center_freq)); 2347 2348 /* Clear calibration flags */ 2349 if (ah->ah_cal_mask & AR5K_CALIBRATION_FULL) 2350 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL; 2351 else if (ah->ah_cal_mask & AR5K_CALIBRATION_SHORT) 2352 ah->ah_cal_mask &= ~AR5K_CALIBRATION_SHORT; 2353 } 2354 2355 2356 static void 2357 ath5k_tasklet_ani(unsigned long data) 2358 { 2359 struct ath5k_hw *ah = (void *)data; 2360 2361 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI; 2362 ath5k_ani_calibration(ah); 2363 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI; 2364 } 2365 2366 2367 static void 2368 ath5k_tx_complete_poll_work(struct work_struct *work) 2369 { 2370 struct ath5k_hw *ah = container_of(work, struct ath5k_hw, 2371 tx_complete_work.work); 2372 struct ath5k_txq *txq; 2373 int i; 2374 bool needreset = false; 2375 2376 mutex_lock(&ah->lock); 2377 2378 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) { 2379 if (ah->txqs[i].setup) { 2380 txq = &ah->txqs[i]; 2381 spin_lock_bh(&txq->lock); 2382 if (txq->txq_len > 1) { 2383 if (txq->txq_poll_mark) { 2384 ATH5K_DBG(ah, ATH5K_DEBUG_XMIT, 2385 "TX queue stuck %d\n", 2386 txq->qnum); 2387 needreset = true; 2388 txq->txq_stuck++; 2389 spin_unlock_bh(&txq->lock); 2390 break; 2391 } else { 2392 txq->txq_poll_mark = true; 2393 } 2394 } 2395 spin_unlock_bh(&txq->lock); 2396 } 2397 } 2398 2399 if (needreset) { 2400 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2401 "TX queues stuck, resetting\n"); 2402 ath5k_reset(ah, NULL, true); 2403 } 2404 2405 mutex_unlock(&ah->lock); 2406 2407 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work, 2408 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); 2409 } 2410 2411 2412 /*************************\ 2413 * Initialization routines * 2414 \*************************/ 2415 2416 int __devinit 2417 ath5k_init_ah(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops) 2418 { 2419 struct ieee80211_hw *hw = ah->hw; 2420 struct ath_common *common; 2421 int ret; 2422 int csz; 2423 2424 /* Initialize driver private data */ 2425 SET_IEEE80211_DEV(hw, ah->dev); 2426 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 2427 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | 2428 IEEE80211_HW_SIGNAL_DBM | 2429 IEEE80211_HW_REPORTS_TX_ACK_STATUS; 2430 2431 hw->wiphy->interface_modes = 2432 BIT(NL80211_IFTYPE_AP) | 2433 BIT(NL80211_IFTYPE_STATION) | 2434 BIT(NL80211_IFTYPE_ADHOC) | 2435 BIT(NL80211_IFTYPE_MESH_POINT); 2436 2437 /* SW support for IBSS_RSN is provided by mac80211 */ 2438 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; 2439 2440 /* both antennas can be configured as RX or TX */ 2441 hw->wiphy->available_antennas_tx = 0x3; 2442 hw->wiphy->available_antennas_rx = 0x3; 2443 2444 hw->extra_tx_headroom = 2; 2445 hw->channel_change_time = 5000; 2446 2447 /* 2448 * Mark the device as detached to avoid processing 2449 * interrupts until setup is complete. 2450 */ 2451 __set_bit(ATH_STAT_INVALID, ah->status); 2452 2453 ah->opmode = NL80211_IFTYPE_STATION; 2454 ah->bintval = 1000; 2455 mutex_init(&ah->lock); 2456 spin_lock_init(&ah->rxbuflock); 2457 spin_lock_init(&ah->txbuflock); 2458 spin_lock_init(&ah->block); 2459 spin_lock_init(&ah->irqlock); 2460 2461 /* Setup interrupt handler */ 2462 ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah); 2463 if (ret) { 2464 ATH5K_ERR(ah, "request_irq failed\n"); 2465 goto err; 2466 } 2467 2468 common = ath5k_hw_common(ah); 2469 common->ops = &ath5k_common_ops; 2470 common->bus_ops = bus_ops; 2471 common->ah = ah; 2472 common->hw = hw; 2473 common->priv = ah; 2474 common->clockrate = 40; 2475 2476 /* 2477 * Cache line size is used to size and align various 2478 * structures used to communicate with the hardware. 2479 */ 2480 ath5k_read_cachesize(common, &csz); 2481 common->cachelsz = csz << 2; /* convert to bytes */ 2482 2483 spin_lock_init(&common->cc_lock); 2484 2485 /* Initialize device */ 2486 ret = ath5k_hw_init(ah); 2487 if (ret) 2488 goto err_irq; 2489 2490 /* Set up multi-rate retry capabilities */ 2491 if (ah->ah_capabilities.cap_has_mrr_support) { 2492 hw->max_rates = 4; 2493 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT, 2494 AR5K_INIT_RETRY_LONG); 2495 } 2496 2497 hw->vif_data_size = sizeof(struct ath5k_vif); 2498 2499 /* Finish private driver data initialization */ 2500 ret = ath5k_init(hw); 2501 if (ret) 2502 goto err_ah; 2503 2504 ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n", 2505 ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev), 2506 ah->ah_mac_srev, 2507 ah->ah_phy_revision); 2508 2509 if (!ah->ah_single_chip) { 2510 /* Single chip radio (!RF5111) */ 2511 if (ah->ah_radio_5ghz_revision && 2512 !ah->ah_radio_2ghz_revision) { 2513 /* No 5GHz support -> report 2GHz radio */ 2514 if (!test_bit(AR5K_MODE_11A, 2515 ah->ah_capabilities.cap_mode)) { 2516 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n", 2517 ath5k_chip_name(AR5K_VERSION_RAD, 2518 ah->ah_radio_5ghz_revision), 2519 ah->ah_radio_5ghz_revision); 2520 /* No 2GHz support (5110 and some 2521 * 5GHz only cards) -> report 5GHz radio */ 2522 } else if (!test_bit(AR5K_MODE_11B, 2523 ah->ah_capabilities.cap_mode)) { 2524 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n", 2525 ath5k_chip_name(AR5K_VERSION_RAD, 2526 ah->ah_radio_5ghz_revision), 2527 ah->ah_radio_5ghz_revision); 2528 /* Multiband radio */ 2529 } else { 2530 ATH5K_INFO(ah, "RF%s multiband radio found" 2531 " (0x%x)\n", 2532 ath5k_chip_name(AR5K_VERSION_RAD, 2533 ah->ah_radio_5ghz_revision), 2534 ah->ah_radio_5ghz_revision); 2535 } 2536 } 2537 /* Multi chip radio (RF5111 - RF2111) -> 2538 * report both 2GHz/5GHz radios */ 2539 else if (ah->ah_radio_5ghz_revision && 2540 ah->ah_radio_2ghz_revision) { 2541 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n", 2542 ath5k_chip_name(AR5K_VERSION_RAD, 2543 ah->ah_radio_5ghz_revision), 2544 ah->ah_radio_5ghz_revision); 2545 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n", 2546 ath5k_chip_name(AR5K_VERSION_RAD, 2547 ah->ah_radio_2ghz_revision), 2548 ah->ah_radio_2ghz_revision); 2549 } 2550 } 2551 2552 ath5k_debug_init_device(ah); 2553 2554 /* ready to process interrupts */ 2555 __clear_bit(ATH_STAT_INVALID, ah->status); 2556 2557 return 0; 2558 err_ah: 2559 ath5k_hw_deinit(ah); 2560 err_irq: 2561 free_irq(ah->irq, ah); 2562 err: 2563 return ret; 2564 } 2565 2566 static int 2567 ath5k_stop_locked(struct ath5k_hw *ah) 2568 { 2569 2570 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n", 2571 test_bit(ATH_STAT_INVALID, ah->status)); 2572 2573 /* 2574 * Shutdown the hardware and driver: 2575 * stop output from above 2576 * disable interrupts 2577 * turn off timers 2578 * turn off the radio 2579 * clear transmit machinery 2580 * clear receive machinery 2581 * drain and release tx queues 2582 * reclaim beacon resources 2583 * power down hardware 2584 * 2585 * Note that some of this work is not possible if the 2586 * hardware is gone (invalid). 2587 */ 2588 ieee80211_stop_queues(ah->hw); 2589 2590 if (!test_bit(ATH_STAT_INVALID, ah->status)) { 2591 ath5k_led_off(ah); 2592 ath5k_hw_set_imr(ah, 0); 2593 synchronize_irq(ah->irq); 2594 ath5k_rx_stop(ah); 2595 ath5k_hw_dma_stop(ah); 2596 ath5k_drain_tx_buffs(ah); 2597 ath5k_hw_phy_disable(ah); 2598 } 2599 2600 return 0; 2601 } 2602 2603 int ath5k_start(struct ieee80211_hw *hw) 2604 { 2605 struct ath5k_hw *ah = hw->priv; 2606 struct ath_common *common = ath5k_hw_common(ah); 2607 int ret, i; 2608 2609 mutex_lock(&ah->lock); 2610 2611 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode); 2612 2613 /* 2614 * Stop anything previously setup. This is safe 2615 * no matter this is the first time through or not. 2616 */ 2617 ath5k_stop_locked(ah); 2618 2619 /* 2620 * The basic interface to setting the hardware in a good 2621 * state is ``reset''. On return the hardware is known to 2622 * be powered up and with interrupts disabled. This must 2623 * be followed by initialization of the appropriate bits 2624 * and then setup of the interrupt mask. 2625 */ 2626 ah->curchan = ah->hw->conf.channel; 2627 ah->imask = AR5K_INT_RXOK 2628 | AR5K_INT_RXERR 2629 | AR5K_INT_RXEOL 2630 | AR5K_INT_RXORN 2631 | AR5K_INT_TXDESC 2632 | AR5K_INT_TXEOL 2633 | AR5K_INT_FATAL 2634 | AR5K_INT_GLOBAL 2635 | AR5K_INT_MIB; 2636 2637 ret = ath5k_reset(ah, NULL, false); 2638 if (ret) 2639 goto done; 2640 2641 if (!ath5k_modparam_no_hw_rfkill_switch) 2642 ath5k_rfkill_hw_start(ah); 2643 2644 /* 2645 * Reset the key cache since some parts do not reset the 2646 * contents on initial power up or resume from suspend. 2647 */ 2648 for (i = 0; i < common->keymax; i++) 2649 ath_hw_keyreset(common, (u16) i); 2650 2651 /* Use higher rates for acks instead of base 2652 * rate */ 2653 ah->ah_ack_bitrate_high = true; 2654 2655 for (i = 0; i < ARRAY_SIZE(ah->bslot); i++) 2656 ah->bslot[i] = NULL; 2657 2658 ret = 0; 2659 done: 2660 mmiowb(); 2661 mutex_unlock(&ah->lock); 2662 2663 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work, 2664 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); 2665 2666 return ret; 2667 } 2668 2669 static void ath5k_stop_tasklets(struct ath5k_hw *ah) 2670 { 2671 ah->rx_pending = false; 2672 ah->tx_pending = false; 2673 tasklet_kill(&ah->rxtq); 2674 tasklet_kill(&ah->txtq); 2675 tasklet_kill(&ah->beacontq); 2676 tasklet_kill(&ah->ani_tasklet); 2677 } 2678 2679 /* 2680 * Stop the device, grabbing the top-level lock to protect 2681 * against concurrent entry through ath5k_init (which can happen 2682 * if another thread does a system call and the thread doing the 2683 * stop is preempted). 2684 */ 2685 void ath5k_stop(struct ieee80211_hw *hw) 2686 { 2687 struct ath5k_hw *ah = hw->priv; 2688 int ret; 2689 2690 mutex_lock(&ah->lock); 2691 ret = ath5k_stop_locked(ah); 2692 if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) { 2693 /* 2694 * Don't set the card in full sleep mode! 2695 * 2696 * a) When the device is in this state it must be carefully 2697 * woken up or references to registers in the PCI clock 2698 * domain may freeze the bus (and system). This varies 2699 * by chip and is mostly an issue with newer parts 2700 * (madwifi sources mentioned srev >= 0x78) that go to 2701 * sleep more quickly. 2702 * 2703 * b) On older chips full sleep results a weird behaviour 2704 * during wakeup. I tested various cards with srev < 0x78 2705 * and they don't wake up after module reload, a second 2706 * module reload is needed to bring the card up again. 2707 * 2708 * Until we figure out what's going on don't enable 2709 * full chip reset on any chip (this is what Legacy HAL 2710 * and Sam's HAL do anyway). Instead Perform a full reset 2711 * on the device (same as initial state after attach) and 2712 * leave it idle (keep MAC/BB on warm reset) */ 2713 ret = ath5k_hw_on_hold(ah); 2714 2715 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2716 "putting device to sleep\n"); 2717 } 2718 2719 mmiowb(); 2720 mutex_unlock(&ah->lock); 2721 2722 ath5k_stop_tasklets(ah); 2723 2724 cancel_delayed_work_sync(&ah->tx_complete_work); 2725 2726 if (!ath5k_modparam_no_hw_rfkill_switch) 2727 ath5k_rfkill_hw_stop(ah); 2728 } 2729 2730 /* 2731 * Reset the hardware. If chan is not NULL, then also pause rx/tx 2732 * and change to the given channel. 2733 * 2734 * This should be called with ah->lock. 2735 */ 2736 static int 2737 ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan, 2738 bool skip_pcu) 2739 { 2740 struct ath_common *common = ath5k_hw_common(ah); 2741 int ret, ani_mode; 2742 bool fast; 2743 2744 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n"); 2745 2746 ath5k_hw_set_imr(ah, 0); 2747 synchronize_irq(ah->irq); 2748 ath5k_stop_tasklets(ah); 2749 2750 /* Save ani mode and disable ANI during 2751 * reset. If we don't we might get false 2752 * PHY error interrupts. */ 2753 ani_mode = ah->ani_state.ani_mode; 2754 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF); 2755 2756 /* We are going to empty hw queues 2757 * so we should also free any remaining 2758 * tx buffers */ 2759 ath5k_drain_tx_buffs(ah); 2760 if (chan) 2761 ah->curchan = chan; 2762 2763 fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0; 2764 2765 ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu); 2766 if (ret) { 2767 ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret); 2768 goto err; 2769 } 2770 2771 ret = ath5k_rx_start(ah); 2772 if (ret) { 2773 ATH5K_ERR(ah, "can't start recv logic\n"); 2774 goto err; 2775 } 2776 2777 ath5k_ani_init(ah, ani_mode); 2778 2779 /* 2780 * Set calibration intervals 2781 * 2782 * Note: We don't need to run calibration imediately 2783 * since some initial calibration is done on reset 2784 * even for fast channel switching. Also on scanning 2785 * this will get set again and again and it won't get 2786 * executed unless we connect somewhere and spend some 2787 * time on the channel (that's what calibration needs 2788 * anyway to be accurate). 2789 */ 2790 ah->ah_cal_next_full = jiffies + 2791 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL); 2792 ah->ah_cal_next_ani = jiffies + 2793 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI); 2794 ah->ah_cal_next_short = jiffies + 2795 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT); 2796 2797 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8); 2798 2799 /* clear survey data and cycle counters */ 2800 memset(&ah->survey, 0, sizeof(ah->survey)); 2801 spin_lock_bh(&common->cc_lock); 2802 ath_hw_cycle_counters_update(common); 2803 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 2804 memset(&common->cc_ani, 0, sizeof(common->cc_ani)); 2805 spin_unlock_bh(&common->cc_lock); 2806 2807 /* 2808 * Change channels and update the h/w rate map if we're switching; 2809 * e.g. 11a to 11b/g. 2810 * 2811 * We may be doing a reset in response to an ioctl that changes the 2812 * channel so update any state that might change as a result. 2813 * 2814 * XXX needed? 2815 */ 2816 /* ath5k_chan_change(ah, c); */ 2817 2818 ath5k_beacon_config(ah); 2819 /* intrs are enabled by ath5k_beacon_config */ 2820 2821 ieee80211_wake_queues(ah->hw); 2822 2823 return 0; 2824 err: 2825 return ret; 2826 } 2827 2828 static void ath5k_reset_work(struct work_struct *work) 2829 { 2830 struct ath5k_hw *ah = container_of(work, struct ath5k_hw, 2831 reset_work); 2832 2833 mutex_lock(&ah->lock); 2834 ath5k_reset(ah, NULL, true); 2835 mutex_unlock(&ah->lock); 2836 } 2837 2838 static int __devinit 2839 ath5k_init(struct ieee80211_hw *hw) 2840 { 2841 2842 struct ath5k_hw *ah = hw->priv; 2843 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 2844 struct ath5k_txq *txq; 2845 u8 mac[ETH_ALEN] = {}; 2846 int ret; 2847 2848 2849 /* 2850 * Collect the channel list. The 802.11 layer 2851 * is responsible for filtering this list based 2852 * on settings like the phy mode and regulatory 2853 * domain restrictions. 2854 */ 2855 ret = ath5k_setup_bands(hw); 2856 if (ret) { 2857 ATH5K_ERR(ah, "can't get channels\n"); 2858 goto err; 2859 } 2860 2861 /* 2862 * Allocate tx+rx descriptors and populate the lists. 2863 */ 2864 ret = ath5k_desc_alloc(ah); 2865 if (ret) { 2866 ATH5K_ERR(ah, "can't allocate descriptors\n"); 2867 goto err; 2868 } 2869 2870 /* 2871 * Allocate hardware transmit queues: one queue for 2872 * beacon frames and one data queue for each QoS 2873 * priority. Note that hw functions handle resetting 2874 * these queues at the needed time. 2875 */ 2876 ret = ath5k_beaconq_setup(ah); 2877 if (ret < 0) { 2878 ATH5K_ERR(ah, "can't setup a beacon xmit queue\n"); 2879 goto err_desc; 2880 } 2881 ah->bhalq = ret; 2882 ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0); 2883 if (IS_ERR(ah->cabq)) { 2884 ATH5K_ERR(ah, "can't setup cab queue\n"); 2885 ret = PTR_ERR(ah->cabq); 2886 goto err_bhal; 2887 } 2888 2889 /* 5211 and 5212 usually support 10 queues but we better rely on the 2890 * capability information */ 2891 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) { 2892 /* This order matches mac80211's queue priority, so we can 2893 * directly use the mac80211 queue number without any mapping */ 2894 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO); 2895 if (IS_ERR(txq)) { 2896 ATH5K_ERR(ah, "can't setup xmit queue\n"); 2897 ret = PTR_ERR(txq); 2898 goto err_queues; 2899 } 2900 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI); 2901 if (IS_ERR(txq)) { 2902 ATH5K_ERR(ah, "can't setup xmit queue\n"); 2903 ret = PTR_ERR(txq); 2904 goto err_queues; 2905 } 2906 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); 2907 if (IS_ERR(txq)) { 2908 ATH5K_ERR(ah, "can't setup xmit queue\n"); 2909 ret = PTR_ERR(txq); 2910 goto err_queues; 2911 } 2912 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); 2913 if (IS_ERR(txq)) { 2914 ATH5K_ERR(ah, "can't setup xmit queue\n"); 2915 ret = PTR_ERR(txq); 2916 goto err_queues; 2917 } 2918 hw->queues = 4; 2919 } else { 2920 /* older hardware (5210) can only support one data queue */ 2921 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); 2922 if (IS_ERR(txq)) { 2923 ATH5K_ERR(ah, "can't setup xmit queue\n"); 2924 ret = PTR_ERR(txq); 2925 goto err_queues; 2926 } 2927 hw->queues = 1; 2928 } 2929 2930 tasklet_init(&ah->rxtq, ath5k_tasklet_rx, (unsigned long)ah); 2931 tasklet_init(&ah->txtq, ath5k_tasklet_tx, (unsigned long)ah); 2932 tasklet_init(&ah->beacontq, ath5k_tasklet_beacon, (unsigned long)ah); 2933 tasklet_init(&ah->ani_tasklet, ath5k_tasklet_ani, (unsigned long)ah); 2934 2935 INIT_WORK(&ah->reset_work, ath5k_reset_work); 2936 INIT_WORK(&ah->calib_work, ath5k_calibrate_work); 2937 INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work); 2938 2939 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac); 2940 if (ret) { 2941 ATH5K_ERR(ah, "unable to read address from EEPROM\n"); 2942 goto err_queues; 2943 } 2944 2945 SET_IEEE80211_PERM_ADDR(hw, mac); 2946 /* All MAC address bits matter for ACKs */ 2947 ath5k_update_bssid_mask_and_opmode(ah, NULL); 2948 2949 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain; 2950 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier); 2951 if (ret) { 2952 ATH5K_ERR(ah, "can't initialize regulatory system\n"); 2953 goto err_queues; 2954 } 2955 2956 ret = ieee80211_register_hw(hw); 2957 if (ret) { 2958 ATH5K_ERR(ah, "can't register ieee80211 hw\n"); 2959 goto err_queues; 2960 } 2961 2962 if (!ath_is_world_regd(regulatory)) 2963 regulatory_hint(hw->wiphy, regulatory->alpha2); 2964 2965 ath5k_init_leds(ah); 2966 2967 ath5k_sysfs_register(ah); 2968 2969 return 0; 2970 err_queues: 2971 ath5k_txq_release(ah); 2972 err_bhal: 2973 ath5k_hw_release_tx_queue(ah, ah->bhalq); 2974 err_desc: 2975 ath5k_desc_free(ah); 2976 err: 2977 return ret; 2978 } 2979 2980 void 2981 ath5k_deinit_ah(struct ath5k_hw *ah) 2982 { 2983 struct ieee80211_hw *hw = ah->hw; 2984 2985 /* 2986 * NB: the order of these is important: 2987 * o call the 802.11 layer before detaching ath5k_hw to 2988 * ensure callbacks into the driver to delete global 2989 * key cache entries can be handled 2990 * o reclaim the tx queue data structures after calling 2991 * the 802.11 layer as we'll get called back to reclaim 2992 * node state and potentially want to use them 2993 * o to cleanup the tx queues the hal is called, so detach 2994 * it last 2995 * XXX: ??? detach ath5k_hw ??? 2996 * Other than that, it's straightforward... 2997 */ 2998 ieee80211_unregister_hw(hw); 2999 ath5k_desc_free(ah); 3000 ath5k_txq_release(ah); 3001 ath5k_hw_release_tx_queue(ah, ah->bhalq); 3002 ath5k_unregister_leds(ah); 3003 3004 ath5k_sysfs_unregister(ah); 3005 /* 3006 * NB: can't reclaim these until after ieee80211_ifdetach 3007 * returns because we'll get called back to reclaim node 3008 * state and potentially want to use them. 3009 */ 3010 ath5k_hw_deinit(ah); 3011 free_irq(ah->irq, ah); 3012 } 3013 3014 bool 3015 ath5k_any_vif_assoc(struct ath5k_hw *ah) 3016 { 3017 struct ath5k_vif_iter_data iter_data; 3018 iter_data.hw_macaddr = NULL; 3019 iter_data.any_assoc = false; 3020 iter_data.need_set_hw_addr = false; 3021 iter_data.found_active = true; 3022 3023 ieee80211_iterate_active_interfaces_atomic(ah->hw, ath5k_vif_iter, 3024 &iter_data); 3025 return iter_data.any_assoc; 3026 } 3027 3028 void 3029 ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable) 3030 { 3031 struct ath5k_hw *ah = hw->priv; 3032 u32 rfilt; 3033 rfilt = ath5k_hw_get_rx_filter(ah); 3034 if (enable) 3035 rfilt |= AR5K_RX_FILTER_BEACON; 3036 else 3037 rfilt &= ~AR5K_RX_FILTER_BEACON; 3038 ath5k_hw_set_rx_filter(ah, rfilt); 3039 ah->filter_flags = rfilt; 3040 } 3041