1 /*- 2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 3 * Copyright (c) 2004-2005 Atheros Communications, Inc. 4 * Copyright (c) 2006 Devicescape Software, Inc. 5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com> 6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu> 7 * 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 18 * redistribution must be conditioned upon including a substantially 19 * similar Disclaimer requirement for further binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * Alternatively, this software may be distributed under the terms of the 25 * GNU General Public License ("GPL") version 2 as published by the Free 26 * Software Foundation. 27 * 28 * NO WARRANTY 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 39 * THE POSSIBILITY OF SUCH DAMAGES. 40 * 41 */ 42 43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 44 45 #include <linux/module.h> 46 #include <linux/delay.h> 47 #include <linux/dma-mapping.h> 48 #include <linux/hardirq.h> 49 #include <linux/if.h> 50 #include <linux/io.h> 51 #include <linux/netdevice.h> 52 #include <linux/cache.h> 53 #include <linux/ethtool.h> 54 #include <linux/uaccess.h> 55 #include <linux/slab.h> 56 #include <linux/etherdevice.h> 57 #include <linux/nl80211.h> 58 59 #include <net/cfg80211.h> 60 #include <net/ieee80211_radiotap.h> 61 62 #include <asm/unaligned.h> 63 64 #include <net/mac80211.h> 65 #include "base.h" 66 #include "reg.h" 67 #include "debug.h" 68 #include "ani.h" 69 #include "ath5k.h" 70 #include "../regd.h" 71 72 #define CREATE_TRACE_POINTS 73 #include "trace.h" 74 75 bool ath5k_modparam_nohwcrypt; 76 module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, S_IRUGO); 77 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 78 79 static bool modparam_fastchanswitch; 80 module_param_named(fastchanswitch, modparam_fastchanswitch, bool, S_IRUGO); 81 MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios."); 82 83 static bool ath5k_modparam_no_hw_rfkill_switch; 84 module_param_named(no_hw_rfkill_switch, ath5k_modparam_no_hw_rfkill_switch, 85 bool, S_IRUGO); 86 MODULE_PARM_DESC(no_hw_rfkill_switch, "Ignore the GPIO RFKill switch state"); 87 88 89 /* Module info */ 90 MODULE_AUTHOR("Jiri Slaby"); 91 MODULE_AUTHOR("Nick Kossifidis"); 92 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards."); 93 MODULE_SUPPORTED_DEVICE("Atheros 5xxx WLAN cards"); 94 MODULE_LICENSE("Dual BSD/GPL"); 95 96 static int ath5k_init(struct ieee80211_hw *hw); 97 static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan, 98 bool skip_pcu); 99 100 /* Known SREVs */ 101 static const struct ath5k_srev_name srev_names[] = { 102 #ifdef CONFIG_ATHEROS_AR231X 103 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 }, 104 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 }, 105 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 }, 106 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 }, 107 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 }, 108 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 }, 109 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 }, 110 #else 111 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 }, 112 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 }, 113 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A }, 114 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B }, 115 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 }, 116 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 }, 117 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 }, 118 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A }, 119 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 }, 120 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 }, 121 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 }, 122 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 }, 123 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 }, 124 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 }, 125 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 }, 126 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 }, 127 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 }, 128 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 }, 129 #endif 130 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN }, 131 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, 132 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, 133 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A }, 134 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, 135 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, 136 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, 137 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B }, 138 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, 139 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, 140 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B }, 141 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 }, 142 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 }, 143 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 }, 144 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 }, 145 #ifdef CONFIG_ATHEROS_AR231X 146 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 }, 147 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 }, 148 #endif 149 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, 150 }; 151 152 static const struct ieee80211_rate ath5k_rates[] = { 153 { .bitrate = 10, 154 .hw_value = ATH5K_RATE_CODE_1M, }, 155 { .bitrate = 20, 156 .hw_value = ATH5K_RATE_CODE_2M, 157 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE, 158 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 159 { .bitrate = 55, 160 .hw_value = ATH5K_RATE_CODE_5_5M, 161 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE, 162 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 163 { .bitrate = 110, 164 .hw_value = ATH5K_RATE_CODE_11M, 165 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE, 166 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 167 { .bitrate = 60, 168 .hw_value = ATH5K_RATE_CODE_6M, 169 .flags = IEEE80211_RATE_SUPPORTS_5MHZ | 170 IEEE80211_RATE_SUPPORTS_10MHZ }, 171 { .bitrate = 90, 172 .hw_value = ATH5K_RATE_CODE_9M, 173 .flags = IEEE80211_RATE_SUPPORTS_5MHZ | 174 IEEE80211_RATE_SUPPORTS_10MHZ }, 175 { .bitrate = 120, 176 .hw_value = ATH5K_RATE_CODE_12M, 177 .flags = IEEE80211_RATE_SUPPORTS_5MHZ | 178 IEEE80211_RATE_SUPPORTS_10MHZ }, 179 { .bitrate = 180, 180 .hw_value = ATH5K_RATE_CODE_18M, 181 .flags = IEEE80211_RATE_SUPPORTS_5MHZ | 182 IEEE80211_RATE_SUPPORTS_10MHZ }, 183 { .bitrate = 240, 184 .hw_value = ATH5K_RATE_CODE_24M, 185 .flags = IEEE80211_RATE_SUPPORTS_5MHZ | 186 IEEE80211_RATE_SUPPORTS_10MHZ }, 187 { .bitrate = 360, 188 .hw_value = ATH5K_RATE_CODE_36M, 189 .flags = IEEE80211_RATE_SUPPORTS_5MHZ | 190 IEEE80211_RATE_SUPPORTS_10MHZ }, 191 { .bitrate = 480, 192 .hw_value = ATH5K_RATE_CODE_48M, 193 .flags = IEEE80211_RATE_SUPPORTS_5MHZ | 194 IEEE80211_RATE_SUPPORTS_10MHZ }, 195 { .bitrate = 540, 196 .hw_value = ATH5K_RATE_CODE_54M, 197 .flags = IEEE80211_RATE_SUPPORTS_5MHZ | 198 IEEE80211_RATE_SUPPORTS_10MHZ }, 199 }; 200 201 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp) 202 { 203 u64 tsf = ath5k_hw_get_tsf64(ah); 204 205 if ((tsf & 0x7fff) < rstamp) 206 tsf -= 0x8000; 207 208 return (tsf & ~0x7fff) | rstamp; 209 } 210 211 const char * 212 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val) 213 { 214 const char *name = "xxxxx"; 215 unsigned int i; 216 217 for (i = 0; i < ARRAY_SIZE(srev_names); i++) { 218 if (srev_names[i].sr_type != type) 219 continue; 220 221 if ((val & 0xf0) == srev_names[i].sr_val) 222 name = srev_names[i].sr_name; 223 224 if ((val & 0xff) == srev_names[i].sr_val) { 225 name = srev_names[i].sr_name; 226 break; 227 } 228 } 229 230 return name; 231 } 232 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset) 233 { 234 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; 235 return ath5k_hw_reg_read(ah, reg_offset); 236 } 237 238 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) 239 { 240 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; 241 ath5k_hw_reg_write(ah, val, reg_offset); 242 } 243 244 static const struct ath_ops ath5k_common_ops = { 245 .read = ath5k_ioread32, 246 .write = ath5k_iowrite32, 247 }; 248 249 /***********************\ 250 * Driver Initialization * 251 \***********************/ 252 253 static void ath5k_reg_notifier(struct wiphy *wiphy, 254 struct regulatory_request *request) 255 { 256 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 257 struct ath5k_hw *ah = hw->priv; 258 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 259 260 ath_reg_notifier_apply(wiphy, request, regulatory); 261 } 262 263 /********************\ 264 * Channel/mode setup * 265 \********************/ 266 267 /* 268 * Returns true for the channel numbers used. 269 */ 270 #ifdef CONFIG_ATH5K_TEST_CHANNELS 271 static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band) 272 { 273 return true; 274 } 275 276 #else 277 static bool ath5k_is_standard_channel(short chan, enum ieee80211_band band) 278 { 279 if (band == IEEE80211_BAND_2GHZ && chan <= 14) 280 return true; 281 282 return /* UNII 1,2 */ 283 (((chan & 3) == 0 && chan >= 36 && chan <= 64) || 284 /* midband */ 285 ((chan & 3) == 0 && chan >= 100 && chan <= 140) || 286 /* UNII-3 */ 287 ((chan & 3) == 1 && chan >= 149 && chan <= 165) || 288 /* 802.11j 5.030-5.080 GHz (20MHz) */ 289 (chan == 8 || chan == 12 || chan == 16) || 290 /* 802.11j 4.9GHz (20MHz) */ 291 (chan == 184 || chan == 188 || chan == 192 || chan == 196)); 292 } 293 #endif 294 295 static unsigned int 296 ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels, 297 unsigned int mode, unsigned int max) 298 { 299 unsigned int count, size, freq, ch; 300 enum ieee80211_band band; 301 302 switch (mode) { 303 case AR5K_MODE_11A: 304 /* 1..220, but 2GHz frequencies are filtered by check_channel */ 305 size = 220; 306 band = IEEE80211_BAND_5GHZ; 307 break; 308 case AR5K_MODE_11B: 309 case AR5K_MODE_11G: 310 size = 26; 311 band = IEEE80211_BAND_2GHZ; 312 break; 313 default: 314 ATH5K_WARN(ah, "bad mode, not copying channels\n"); 315 return 0; 316 } 317 318 count = 0; 319 for (ch = 1; ch <= size && count < max; ch++) { 320 freq = ieee80211_channel_to_frequency(ch, band); 321 322 if (freq == 0) /* mapping failed - not a standard channel */ 323 continue; 324 325 /* Write channel info, needed for ath5k_channel_ok() */ 326 channels[count].center_freq = freq; 327 channels[count].band = band; 328 channels[count].hw_value = mode; 329 330 /* Check if channel is supported by the chipset */ 331 if (!ath5k_channel_ok(ah, &channels[count])) 332 continue; 333 334 if (!ath5k_is_standard_channel(ch, band)) 335 continue; 336 337 count++; 338 } 339 340 return count; 341 } 342 343 static void 344 ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b) 345 { 346 u8 i; 347 348 for (i = 0; i < AR5K_MAX_RATES; i++) 349 ah->rate_idx[b->band][i] = -1; 350 351 for (i = 0; i < b->n_bitrates; i++) { 352 ah->rate_idx[b->band][b->bitrates[i].hw_value] = i; 353 if (b->bitrates[i].hw_value_short) 354 ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i; 355 } 356 } 357 358 static int 359 ath5k_setup_bands(struct ieee80211_hw *hw) 360 { 361 struct ath5k_hw *ah = hw->priv; 362 struct ieee80211_supported_band *sband; 363 int max_c, count_c = 0; 364 int i; 365 366 BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < IEEE80211_NUM_BANDS); 367 max_c = ARRAY_SIZE(ah->channels); 368 369 /* 2GHz band */ 370 sband = &ah->sbands[IEEE80211_BAND_2GHZ]; 371 sband->band = IEEE80211_BAND_2GHZ; 372 sband->bitrates = &ah->rates[IEEE80211_BAND_2GHZ][0]; 373 374 if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) { 375 /* G mode */ 376 memcpy(sband->bitrates, &ath5k_rates[0], 377 sizeof(struct ieee80211_rate) * 12); 378 sband->n_bitrates = 12; 379 380 sband->channels = ah->channels; 381 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 382 AR5K_MODE_11G, max_c); 383 384 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; 385 count_c = sband->n_channels; 386 max_c -= count_c; 387 } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) { 388 /* B mode */ 389 memcpy(sband->bitrates, &ath5k_rates[0], 390 sizeof(struct ieee80211_rate) * 4); 391 sband->n_bitrates = 4; 392 393 /* 5211 only supports B rates and uses 4bit rate codes 394 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B) 395 * fix them up here: 396 */ 397 if (ah->ah_version == AR5K_AR5211) { 398 for (i = 0; i < 4; i++) { 399 sband->bitrates[i].hw_value = 400 sband->bitrates[i].hw_value & 0xF; 401 sband->bitrates[i].hw_value_short = 402 sband->bitrates[i].hw_value_short & 0xF; 403 } 404 } 405 406 sband->channels = ah->channels; 407 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 408 AR5K_MODE_11B, max_c); 409 410 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband; 411 count_c = sband->n_channels; 412 max_c -= count_c; 413 } 414 ath5k_setup_rate_idx(ah, sband); 415 416 /* 5GHz band, A mode */ 417 if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) { 418 sband = &ah->sbands[IEEE80211_BAND_5GHZ]; 419 sband->band = IEEE80211_BAND_5GHZ; 420 sband->bitrates = &ah->rates[IEEE80211_BAND_5GHZ][0]; 421 422 memcpy(sband->bitrates, &ath5k_rates[4], 423 sizeof(struct ieee80211_rate) * 8); 424 sband->n_bitrates = 8; 425 426 sband->channels = &ah->channels[count_c]; 427 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 428 AR5K_MODE_11A, max_c); 429 430 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = sband; 431 } 432 ath5k_setup_rate_idx(ah, sband); 433 434 ath5k_debug_dump_bands(ah); 435 436 return 0; 437 } 438 439 /* 440 * Set/change channels. We always reset the chip. 441 * To accomplish this we must first cleanup any pending DMA, 442 * then restart stuff after a la ath5k_init. 443 * 444 * Called with ah->lock. 445 */ 446 int 447 ath5k_chan_set(struct ath5k_hw *ah, struct cfg80211_chan_def *chandef) 448 { 449 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 450 "channel set, resetting (%u -> %u MHz)\n", 451 ah->curchan->center_freq, chandef->chan->center_freq); 452 453 switch (chandef->width) { 454 case NL80211_CHAN_WIDTH_20: 455 case NL80211_CHAN_WIDTH_20_NOHT: 456 ah->ah_bwmode = AR5K_BWMODE_DEFAULT; 457 break; 458 case NL80211_CHAN_WIDTH_5: 459 ah->ah_bwmode = AR5K_BWMODE_5MHZ; 460 break; 461 case NL80211_CHAN_WIDTH_10: 462 ah->ah_bwmode = AR5K_BWMODE_10MHZ; 463 break; 464 default: 465 WARN_ON(1); 466 return -EINVAL; 467 } 468 469 /* 470 * To switch channels clear any pending DMA operations; 471 * wait long enough for the RX fifo to drain, reset the 472 * hardware at the new frequency, and then re-enable 473 * the relevant bits of the h/w. 474 */ 475 return ath5k_reset(ah, chandef->chan, true); 476 } 477 478 void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 479 { 480 struct ath5k_vif_iter_data *iter_data = data; 481 int i; 482 struct ath5k_vif *avf = (void *)vif->drv_priv; 483 484 if (iter_data->hw_macaddr) 485 for (i = 0; i < ETH_ALEN; i++) 486 iter_data->mask[i] &= 487 ~(iter_data->hw_macaddr[i] ^ mac[i]); 488 489 if (!iter_data->found_active) { 490 iter_data->found_active = true; 491 memcpy(iter_data->active_mac, mac, ETH_ALEN); 492 } 493 494 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr) 495 if (ether_addr_equal(iter_data->hw_macaddr, mac)) 496 iter_data->need_set_hw_addr = false; 497 498 if (!iter_data->any_assoc) { 499 if (avf->assoc) 500 iter_data->any_assoc = true; 501 } 502 503 /* Calculate combined mode - when APs are active, operate in AP mode. 504 * Otherwise use the mode of the new interface. This can currently 505 * only deal with combinations of APs and STAs. Only one ad-hoc 506 * interfaces is allowed. 507 */ 508 if (avf->opmode == NL80211_IFTYPE_AP) 509 iter_data->opmode = NL80211_IFTYPE_AP; 510 else { 511 if (avf->opmode == NL80211_IFTYPE_STATION) 512 iter_data->n_stas++; 513 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED) 514 iter_data->opmode = avf->opmode; 515 } 516 } 517 518 void 519 ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah, 520 struct ieee80211_vif *vif) 521 { 522 struct ath_common *common = ath5k_hw_common(ah); 523 struct ath5k_vif_iter_data iter_data; 524 u32 rfilt; 525 526 /* 527 * Use the hardware MAC address as reference, the hardware uses it 528 * together with the BSSID mask when matching addresses. 529 */ 530 iter_data.hw_macaddr = common->macaddr; 531 memset(&iter_data.mask, 0xff, ETH_ALEN); 532 iter_data.found_active = false; 533 iter_data.need_set_hw_addr = true; 534 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED; 535 iter_data.n_stas = 0; 536 537 if (vif) 538 ath5k_vif_iter(&iter_data, vif->addr, vif); 539 540 /* Get list of all active MAC addresses */ 541 ieee80211_iterate_active_interfaces_atomic( 542 ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 543 ath5k_vif_iter, &iter_data); 544 memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN); 545 546 ah->opmode = iter_data.opmode; 547 if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED) 548 /* Nothing active, default to station mode */ 549 ah->opmode = NL80211_IFTYPE_STATION; 550 551 ath5k_hw_set_opmode(ah, ah->opmode); 552 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n", 553 ah->opmode, ath_opmode_to_string(ah->opmode)); 554 555 if (iter_data.need_set_hw_addr && iter_data.found_active) 556 ath5k_hw_set_lladdr(ah, iter_data.active_mac); 557 558 if (ath5k_hw_hasbssidmask(ah)) 559 ath5k_hw_set_bssid_mask(ah, ah->bssidmask); 560 561 /* Set up RX Filter */ 562 if (iter_data.n_stas > 1) { 563 /* If you have multiple STA interfaces connected to 564 * different APs, ARPs are not received (most of the time?) 565 * Enabling PROMISC appears to fix that problem. 566 */ 567 ah->filter_flags |= AR5K_RX_FILTER_PROM; 568 } 569 570 rfilt = ah->filter_flags; 571 ath5k_hw_set_rx_filter(ah, rfilt); 572 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt); 573 } 574 575 static inline int 576 ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix) 577 { 578 int rix; 579 580 /* return base rate on errors */ 581 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES, 582 "hw_rix out of bounds: %x\n", hw_rix)) 583 return 0; 584 585 rix = ah->rate_idx[ah->curchan->band][hw_rix]; 586 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix)) 587 rix = 0; 588 589 return rix; 590 } 591 592 /***************\ 593 * Buffers setup * 594 \***************/ 595 596 static 597 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr) 598 { 599 struct ath_common *common = ath5k_hw_common(ah); 600 struct sk_buff *skb; 601 602 /* 603 * Allocate buffer with headroom_needed space for the 604 * fake physical layer header at the start. 605 */ 606 skb = ath_rxbuf_alloc(common, 607 common->rx_bufsize, 608 GFP_ATOMIC); 609 610 if (!skb) { 611 ATH5K_ERR(ah, "can't alloc skbuff of size %u\n", 612 common->rx_bufsize); 613 return NULL; 614 } 615 616 *skb_addr = dma_map_single(ah->dev, 617 skb->data, common->rx_bufsize, 618 DMA_FROM_DEVICE); 619 620 if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) { 621 ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__); 622 dev_kfree_skb(skb); 623 return NULL; 624 } 625 return skb; 626 } 627 628 static int 629 ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf) 630 { 631 struct sk_buff *skb = bf->skb; 632 struct ath5k_desc *ds; 633 int ret; 634 635 if (!skb) { 636 skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr); 637 if (!skb) 638 return -ENOMEM; 639 bf->skb = skb; 640 } 641 642 /* 643 * Setup descriptors. For receive we always terminate 644 * the descriptor list with a self-linked entry so we'll 645 * not get overrun under high load (as can happen with a 646 * 5212 when ANI processing enables PHY error frames). 647 * 648 * To ensure the last descriptor is self-linked we create 649 * each descriptor as self-linked and add it to the end. As 650 * each additional descriptor is added the previous self-linked 651 * entry is "fixed" naturally. This should be safe even 652 * if DMA is happening. When processing RX interrupts we 653 * never remove/process the last, self-linked, entry on the 654 * descriptor list. This ensures the hardware always has 655 * someplace to write a new frame. 656 */ 657 ds = bf->desc; 658 ds->ds_link = bf->daddr; /* link to self */ 659 ds->ds_data = bf->skbaddr; 660 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0); 661 if (ret) { 662 ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__); 663 return ret; 664 } 665 666 if (ah->rxlink != NULL) 667 *ah->rxlink = bf->daddr; 668 ah->rxlink = &ds->ds_link; 669 return 0; 670 } 671 672 static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb) 673 { 674 struct ieee80211_hdr *hdr; 675 enum ath5k_pkt_type htype; 676 __le16 fc; 677 678 hdr = (struct ieee80211_hdr *)skb->data; 679 fc = hdr->frame_control; 680 681 if (ieee80211_is_beacon(fc)) 682 htype = AR5K_PKT_TYPE_BEACON; 683 else if (ieee80211_is_probe_resp(fc)) 684 htype = AR5K_PKT_TYPE_PROBE_RESP; 685 else if (ieee80211_is_atim(fc)) 686 htype = AR5K_PKT_TYPE_ATIM; 687 else if (ieee80211_is_pspoll(fc)) 688 htype = AR5K_PKT_TYPE_PSPOLL; 689 else 690 htype = AR5K_PKT_TYPE_NORMAL; 691 692 return htype; 693 } 694 695 static struct ieee80211_rate * 696 ath5k_get_rate(const struct ieee80211_hw *hw, 697 const struct ieee80211_tx_info *info, 698 struct ath5k_buf *bf, int idx) 699 { 700 /* 701 * convert a ieee80211_tx_rate RC-table entry to 702 * the respective ieee80211_rate struct 703 */ 704 if (bf->rates[idx].idx < 0) { 705 return NULL; 706 } 707 708 return &hw->wiphy->bands[info->band]->bitrates[ bf->rates[idx].idx ]; 709 } 710 711 static u16 712 ath5k_get_rate_hw_value(const struct ieee80211_hw *hw, 713 const struct ieee80211_tx_info *info, 714 struct ath5k_buf *bf, int idx) 715 { 716 struct ieee80211_rate *rate; 717 u16 hw_rate; 718 u8 rc_flags; 719 720 rate = ath5k_get_rate(hw, info, bf, idx); 721 if (!rate) 722 return 0; 723 724 rc_flags = bf->rates[idx].flags; 725 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ? 726 rate->hw_value_short : rate->hw_value; 727 728 return hw_rate; 729 } 730 731 static int 732 ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf, 733 struct ath5k_txq *txq, int padsize, 734 struct ieee80211_tx_control *control) 735 { 736 struct ath5k_desc *ds = bf->desc; 737 struct sk_buff *skb = bf->skb; 738 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 739 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID; 740 struct ieee80211_rate *rate; 741 unsigned int mrr_rate[3], mrr_tries[3]; 742 int i, ret; 743 u16 hw_rate; 744 u16 cts_rate = 0; 745 u16 duration = 0; 746 u8 rc_flags; 747 748 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; 749 750 /* XXX endianness */ 751 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len, 752 DMA_TO_DEVICE); 753 754 ieee80211_get_tx_rates(info->control.vif, (control) ? control->sta : NULL, skb, bf->rates, 755 ARRAY_SIZE(bf->rates)); 756 757 rate = ath5k_get_rate(ah->hw, info, bf, 0); 758 759 if (!rate) { 760 ret = -EINVAL; 761 goto err_unmap; 762 } 763 764 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 765 flags |= AR5K_TXDESC_NOACK; 766 767 rc_flags = info->control.rates[0].flags; 768 769 hw_rate = ath5k_get_rate_hw_value(ah->hw, info, bf, 0); 770 771 pktlen = skb->len; 772 773 /* FIXME: If we are in g mode and rate is a CCK rate 774 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta 775 * from tx power (value is in dB units already) */ 776 if (info->control.hw_key) { 777 keyidx = info->control.hw_key->hw_key_idx; 778 pktlen += info->control.hw_key->icv_len; 779 } 780 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) { 781 flags |= AR5K_TXDESC_RTSENA; 782 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value; 783 duration = le16_to_cpu(ieee80211_rts_duration(ah->hw, 784 info->control.vif, pktlen, info)); 785 } 786 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 787 flags |= AR5K_TXDESC_CTSENA; 788 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value; 789 duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw, 790 info->control.vif, pktlen, info)); 791 } 792 793 ret = ah->ah_setup_tx_desc(ah, ds, pktlen, 794 ieee80211_get_hdrlen_from_skb(skb), padsize, 795 get_hw_packet_type(skb), 796 (ah->ah_txpower.txp_requested * 2), 797 hw_rate, 798 bf->rates[0].count, keyidx, ah->ah_tx_ant, flags, 799 cts_rate, duration); 800 if (ret) 801 goto err_unmap; 802 803 /* Set up MRR descriptor */ 804 if (ah->ah_capabilities.cap_has_mrr_support) { 805 memset(mrr_rate, 0, sizeof(mrr_rate)); 806 memset(mrr_tries, 0, sizeof(mrr_tries)); 807 808 for (i = 0; i < 3; i++) { 809 810 rate = ath5k_get_rate(ah->hw, info, bf, i); 811 if (!rate) 812 break; 813 814 mrr_rate[i] = ath5k_get_rate_hw_value(ah->hw, info, bf, i); 815 mrr_tries[i] = bf->rates[i].count; 816 } 817 818 ath5k_hw_setup_mrr_tx_desc(ah, ds, 819 mrr_rate[0], mrr_tries[0], 820 mrr_rate[1], mrr_tries[1], 821 mrr_rate[2], mrr_tries[2]); 822 } 823 824 ds->ds_link = 0; 825 ds->ds_data = bf->skbaddr; 826 827 spin_lock_bh(&txq->lock); 828 list_add_tail(&bf->list, &txq->q); 829 txq->txq_len++; 830 if (txq->link == NULL) /* is this first packet? */ 831 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr); 832 else /* no, so only link it */ 833 *txq->link = bf->daddr; 834 835 txq->link = &ds->ds_link; 836 ath5k_hw_start_tx_dma(ah, txq->qnum); 837 mmiowb(); 838 spin_unlock_bh(&txq->lock); 839 840 return 0; 841 err_unmap: 842 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); 843 return ret; 844 } 845 846 /*******************\ 847 * Descriptors setup * 848 \*******************/ 849 850 static int 851 ath5k_desc_alloc(struct ath5k_hw *ah) 852 { 853 struct ath5k_desc *ds; 854 struct ath5k_buf *bf; 855 dma_addr_t da; 856 unsigned int i; 857 int ret; 858 859 /* allocate descriptors */ 860 ah->desc_len = sizeof(struct ath5k_desc) * 861 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1); 862 863 ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len, 864 &ah->desc_daddr, GFP_KERNEL); 865 if (ah->desc == NULL) { 866 ATH5K_ERR(ah, "can't allocate descriptors\n"); 867 ret = -ENOMEM; 868 goto err; 869 } 870 ds = ah->desc; 871 da = ah->desc_daddr; 872 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n", 873 ds, ah->desc_len, (unsigned long long)ah->desc_daddr); 874 875 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF, 876 sizeof(struct ath5k_buf), GFP_KERNEL); 877 if (bf == NULL) { 878 ATH5K_ERR(ah, "can't allocate bufptr\n"); 879 ret = -ENOMEM; 880 goto err_free; 881 } 882 ah->bufptr = bf; 883 884 INIT_LIST_HEAD(&ah->rxbuf); 885 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) { 886 bf->desc = ds; 887 bf->daddr = da; 888 list_add_tail(&bf->list, &ah->rxbuf); 889 } 890 891 INIT_LIST_HEAD(&ah->txbuf); 892 ah->txbuf_len = ATH_TXBUF; 893 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) { 894 bf->desc = ds; 895 bf->daddr = da; 896 list_add_tail(&bf->list, &ah->txbuf); 897 } 898 899 /* beacon buffers */ 900 INIT_LIST_HEAD(&ah->bcbuf); 901 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) { 902 bf->desc = ds; 903 bf->daddr = da; 904 list_add_tail(&bf->list, &ah->bcbuf); 905 } 906 907 return 0; 908 err_free: 909 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr); 910 err: 911 ah->desc = NULL; 912 return ret; 913 } 914 915 void 916 ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf) 917 { 918 BUG_ON(!bf); 919 if (!bf->skb) 920 return; 921 dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len, 922 DMA_TO_DEVICE); 923 ieee80211_free_txskb(ah->hw, bf->skb); 924 bf->skb = NULL; 925 bf->skbaddr = 0; 926 bf->desc->ds_data = 0; 927 } 928 929 void 930 ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf) 931 { 932 struct ath_common *common = ath5k_hw_common(ah); 933 934 BUG_ON(!bf); 935 if (!bf->skb) 936 return; 937 dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize, 938 DMA_FROM_DEVICE); 939 dev_kfree_skb_any(bf->skb); 940 bf->skb = NULL; 941 bf->skbaddr = 0; 942 bf->desc->ds_data = 0; 943 } 944 945 static void 946 ath5k_desc_free(struct ath5k_hw *ah) 947 { 948 struct ath5k_buf *bf; 949 950 list_for_each_entry(bf, &ah->txbuf, list) 951 ath5k_txbuf_free_skb(ah, bf); 952 list_for_each_entry(bf, &ah->rxbuf, list) 953 ath5k_rxbuf_free_skb(ah, bf); 954 list_for_each_entry(bf, &ah->bcbuf, list) 955 ath5k_txbuf_free_skb(ah, bf); 956 957 /* Free memory associated with all descriptors */ 958 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr); 959 ah->desc = NULL; 960 ah->desc_daddr = 0; 961 962 kfree(ah->bufptr); 963 ah->bufptr = NULL; 964 } 965 966 967 /**************\ 968 * Queues setup * 969 \**************/ 970 971 static struct ath5k_txq * 972 ath5k_txq_setup(struct ath5k_hw *ah, 973 int qtype, int subtype) 974 { 975 struct ath5k_txq *txq; 976 struct ath5k_txq_info qi = { 977 .tqi_subtype = subtype, 978 /* XXX: default values not correct for B and XR channels, 979 * but who cares? */ 980 .tqi_aifs = AR5K_TUNE_AIFS, 981 .tqi_cw_min = AR5K_TUNE_CWMIN, 982 .tqi_cw_max = AR5K_TUNE_CWMAX 983 }; 984 int qnum; 985 986 /* 987 * Enable interrupts only for EOL and DESC conditions. 988 * We mark tx descriptors to receive a DESC interrupt 989 * when a tx queue gets deep; otherwise we wait for the 990 * EOL to reap descriptors. Note that this is done to 991 * reduce interrupt load and this only defers reaping 992 * descriptors, never transmitting frames. Aside from 993 * reducing interrupts this also permits more concurrency. 994 * The only potential downside is if the tx queue backs 995 * up in which case the top half of the kernel may backup 996 * due to a lack of tx descriptors. 997 */ 998 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE | 999 AR5K_TXQ_FLAG_TXDESCINT_ENABLE; 1000 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); 1001 if (qnum < 0) { 1002 /* 1003 * NB: don't print a message, this happens 1004 * normally on parts with too few tx queues 1005 */ 1006 return ERR_PTR(qnum); 1007 } 1008 txq = &ah->txqs[qnum]; 1009 if (!txq->setup) { 1010 txq->qnum = qnum; 1011 txq->link = NULL; 1012 INIT_LIST_HEAD(&txq->q); 1013 spin_lock_init(&txq->lock); 1014 txq->setup = true; 1015 txq->txq_len = 0; 1016 txq->txq_max = ATH5K_TXQ_LEN_MAX; 1017 txq->txq_poll_mark = false; 1018 txq->txq_stuck = 0; 1019 } 1020 return &ah->txqs[qnum]; 1021 } 1022 1023 static int 1024 ath5k_beaconq_setup(struct ath5k_hw *ah) 1025 { 1026 struct ath5k_txq_info qi = { 1027 /* XXX: default values not correct for B and XR channels, 1028 * but who cares? */ 1029 .tqi_aifs = AR5K_TUNE_AIFS, 1030 .tqi_cw_min = AR5K_TUNE_CWMIN, 1031 .tqi_cw_max = AR5K_TUNE_CWMAX, 1032 /* NB: for dynamic turbo, don't enable any other interrupts */ 1033 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE 1034 }; 1035 1036 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); 1037 } 1038 1039 static int 1040 ath5k_beaconq_config(struct ath5k_hw *ah) 1041 { 1042 struct ath5k_txq_info qi; 1043 int ret; 1044 1045 ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi); 1046 if (ret) 1047 goto err; 1048 1049 if (ah->opmode == NL80211_IFTYPE_AP || 1050 ah->opmode == NL80211_IFTYPE_MESH_POINT) { 1051 /* 1052 * Always burst out beacon and CAB traffic 1053 * (aifs = cwmin = cwmax = 0) 1054 */ 1055 qi.tqi_aifs = 0; 1056 qi.tqi_cw_min = 0; 1057 qi.tqi_cw_max = 0; 1058 } else if (ah->opmode == NL80211_IFTYPE_ADHOC) { 1059 /* 1060 * Adhoc mode; backoff between 0 and (2 * cw_min). 1061 */ 1062 qi.tqi_aifs = 0; 1063 qi.tqi_cw_min = 0; 1064 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN; 1065 } 1066 1067 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 1068 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n", 1069 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max); 1070 1071 ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi); 1072 if (ret) { 1073 ATH5K_ERR(ah, "%s: unable to update parameters for beacon " 1074 "hardware queue!\n", __func__); 1075 goto err; 1076 } 1077 ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq); /* push to h/w */ 1078 if (ret) 1079 goto err; 1080 1081 /* reconfigure cabq with ready time to 80% of beacon_interval */ 1082 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); 1083 if (ret) 1084 goto err; 1085 1086 qi.tqi_ready_time = (ah->bintval * 80) / 100; 1087 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); 1088 if (ret) 1089 goto err; 1090 1091 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB); 1092 err: 1093 return ret; 1094 } 1095 1096 /** 1097 * ath5k_drain_tx_buffs - Empty tx buffers 1098 * 1099 * @ah The &struct ath5k_hw 1100 * 1101 * Empty tx buffers from all queues in preparation 1102 * of a reset or during shutdown. 1103 * 1104 * NB: this assumes output has been stopped and 1105 * we do not need to block ath5k_tx_tasklet 1106 */ 1107 static void 1108 ath5k_drain_tx_buffs(struct ath5k_hw *ah) 1109 { 1110 struct ath5k_txq *txq; 1111 struct ath5k_buf *bf, *bf0; 1112 int i; 1113 1114 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) { 1115 if (ah->txqs[i].setup) { 1116 txq = &ah->txqs[i]; 1117 spin_lock_bh(&txq->lock); 1118 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 1119 ath5k_debug_printtxbuf(ah, bf); 1120 1121 ath5k_txbuf_free_skb(ah, bf); 1122 1123 spin_lock(&ah->txbuflock); 1124 list_move_tail(&bf->list, &ah->txbuf); 1125 ah->txbuf_len++; 1126 txq->txq_len--; 1127 spin_unlock(&ah->txbuflock); 1128 } 1129 txq->link = NULL; 1130 txq->txq_poll_mark = false; 1131 spin_unlock_bh(&txq->lock); 1132 } 1133 } 1134 } 1135 1136 static void 1137 ath5k_txq_release(struct ath5k_hw *ah) 1138 { 1139 struct ath5k_txq *txq = ah->txqs; 1140 unsigned int i; 1141 1142 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++) 1143 if (txq->setup) { 1144 ath5k_hw_release_tx_queue(ah, txq->qnum); 1145 txq->setup = false; 1146 } 1147 } 1148 1149 1150 /*************\ 1151 * RX Handling * 1152 \*************/ 1153 1154 /* 1155 * Enable the receive h/w following a reset. 1156 */ 1157 static int 1158 ath5k_rx_start(struct ath5k_hw *ah) 1159 { 1160 struct ath_common *common = ath5k_hw_common(ah); 1161 struct ath5k_buf *bf; 1162 int ret; 1163 1164 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz); 1165 1166 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n", 1167 common->cachelsz, common->rx_bufsize); 1168 1169 spin_lock_bh(&ah->rxbuflock); 1170 ah->rxlink = NULL; 1171 list_for_each_entry(bf, &ah->rxbuf, list) { 1172 ret = ath5k_rxbuf_setup(ah, bf); 1173 if (ret != 0) { 1174 spin_unlock_bh(&ah->rxbuflock); 1175 goto err; 1176 } 1177 } 1178 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list); 1179 ath5k_hw_set_rxdp(ah, bf->daddr); 1180 spin_unlock_bh(&ah->rxbuflock); 1181 1182 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */ 1183 ath5k_update_bssid_mask_and_opmode(ah, NULL); /* set filters, etc. */ 1184 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ 1185 1186 return 0; 1187 err: 1188 return ret; 1189 } 1190 1191 /* 1192 * Disable the receive logic on PCU (DRU) 1193 * In preparation for a shutdown. 1194 * 1195 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop 1196 * does. 1197 */ 1198 static void 1199 ath5k_rx_stop(struct ath5k_hw *ah) 1200 { 1201 1202 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ 1203 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */ 1204 1205 ath5k_debug_printrxbuffs(ah); 1206 } 1207 1208 static unsigned int 1209 ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb, 1210 struct ath5k_rx_status *rs) 1211 { 1212 struct ath_common *common = ath5k_hw_common(ah); 1213 struct ieee80211_hdr *hdr = (void *)skb->data; 1214 unsigned int keyix, hlen; 1215 1216 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) && 1217 rs->rs_keyix != AR5K_RXKEYIX_INVALID) 1218 return RX_FLAG_DECRYPTED; 1219 1220 /* Apparently when a default key is used to decrypt the packet 1221 the hw does not set the index used to decrypt. In such cases 1222 get the index from the packet. */ 1223 hlen = ieee80211_hdrlen(hdr->frame_control); 1224 if (ieee80211_has_protected(hdr->frame_control) && 1225 !(rs->rs_status & AR5K_RXERR_DECRYPT) && 1226 skb->len >= hlen + 4) { 1227 keyix = skb->data[hlen + 3] >> 6; 1228 1229 if (test_bit(keyix, common->keymap)) 1230 return RX_FLAG_DECRYPTED; 1231 } 1232 1233 return 0; 1234 } 1235 1236 1237 static void 1238 ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb, 1239 struct ieee80211_rx_status *rxs) 1240 { 1241 u64 tsf, bc_tstamp; 1242 u32 hw_tu; 1243 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1244 1245 if (le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS) { 1246 /* 1247 * Received an IBSS beacon with the same BSSID. Hardware *must* 1248 * have updated the local TSF. We have to work around various 1249 * hardware bugs, though... 1250 */ 1251 tsf = ath5k_hw_get_tsf64(ah); 1252 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp); 1253 hw_tu = TSF_TO_TU(tsf); 1254 1255 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 1256 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n", 1257 (unsigned long long)bc_tstamp, 1258 (unsigned long long)rxs->mactime, 1259 (unsigned long long)(rxs->mactime - bc_tstamp), 1260 (unsigned long long)tsf); 1261 1262 /* 1263 * Sometimes the HW will give us a wrong tstamp in the rx 1264 * status, causing the timestamp extension to go wrong. 1265 * (This seems to happen especially with beacon frames bigger 1266 * than 78 byte (incl. FCS)) 1267 * But we know that the receive timestamp must be later than the 1268 * timestamp of the beacon since HW must have synced to that. 1269 * 1270 * NOTE: here we assume mactime to be after the frame was 1271 * received, not like mac80211 which defines it at the start. 1272 */ 1273 if (bc_tstamp > rxs->mactime) { 1274 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 1275 "fixing mactime from %llx to %llx\n", 1276 (unsigned long long)rxs->mactime, 1277 (unsigned long long)tsf); 1278 rxs->mactime = tsf; 1279 } 1280 1281 /* 1282 * Local TSF might have moved higher than our beacon timers, 1283 * in that case we have to update them to continue sending 1284 * beacons. This also takes care of synchronizing beacon sending 1285 * times with other stations. 1286 */ 1287 if (hw_tu >= ah->nexttbtt) 1288 ath5k_beacon_update_timers(ah, bc_tstamp); 1289 1290 /* Check if the beacon timers are still correct, because a TSF 1291 * update might have created a window between them - for a 1292 * longer description see the comment of this function: */ 1293 if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) { 1294 ath5k_beacon_update_timers(ah, bc_tstamp); 1295 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 1296 "fixed beacon timers after beacon receive\n"); 1297 } 1298 } 1299 } 1300 1301 /* 1302 * Compute padding position. skb must contain an IEEE 802.11 frame 1303 */ 1304 static int ath5k_common_padpos(struct sk_buff *skb) 1305 { 1306 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1307 __le16 frame_control = hdr->frame_control; 1308 int padpos = 24; 1309 1310 if (ieee80211_has_a4(frame_control)) 1311 padpos += ETH_ALEN; 1312 1313 if (ieee80211_is_data_qos(frame_control)) 1314 padpos += IEEE80211_QOS_CTL_LEN; 1315 1316 return padpos; 1317 } 1318 1319 /* 1320 * This function expects an 802.11 frame and returns the number of 1321 * bytes added, or -1 if we don't have enough header room. 1322 */ 1323 static int ath5k_add_padding(struct sk_buff *skb) 1324 { 1325 int padpos = ath5k_common_padpos(skb); 1326 int padsize = padpos & 3; 1327 1328 if (padsize && skb->len > padpos) { 1329 1330 if (skb_headroom(skb) < padsize) 1331 return -1; 1332 1333 skb_push(skb, padsize); 1334 memmove(skb->data, skb->data + padsize, padpos); 1335 return padsize; 1336 } 1337 1338 return 0; 1339 } 1340 1341 /* 1342 * The MAC header is padded to have 32-bit boundary if the 1343 * packet payload is non-zero. The general calculation for 1344 * padsize would take into account odd header lengths: 1345 * padsize = 4 - (hdrlen & 3); however, since only 1346 * even-length headers are used, padding can only be 0 or 2 1347 * bytes and we can optimize this a bit. We must not try to 1348 * remove padding from short control frames that do not have a 1349 * payload. 1350 * 1351 * This function expects an 802.11 frame and returns the number of 1352 * bytes removed. 1353 */ 1354 static int ath5k_remove_padding(struct sk_buff *skb) 1355 { 1356 int padpos = ath5k_common_padpos(skb); 1357 int padsize = padpos & 3; 1358 1359 if (padsize && skb->len >= padpos + padsize) { 1360 memmove(skb->data + padsize, skb->data, padpos); 1361 skb_pull(skb, padsize); 1362 return padsize; 1363 } 1364 1365 return 0; 1366 } 1367 1368 static void 1369 ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb, 1370 struct ath5k_rx_status *rs) 1371 { 1372 struct ieee80211_rx_status *rxs; 1373 struct ath_common *common = ath5k_hw_common(ah); 1374 1375 ath5k_remove_padding(skb); 1376 1377 rxs = IEEE80211_SKB_RXCB(skb); 1378 1379 rxs->flag = 0; 1380 if (unlikely(rs->rs_status & AR5K_RXERR_MIC)) 1381 rxs->flag |= RX_FLAG_MMIC_ERROR; 1382 1383 /* 1384 * always extend the mac timestamp, since this information is 1385 * also needed for proper IBSS merging. 1386 * 1387 * XXX: it might be too late to do it here, since rs_tstamp is 1388 * 15bit only. that means TSF extension has to be done within 1389 * 32768usec (about 32ms). it might be necessary to move this to 1390 * the interrupt handler, like it is done in madwifi. 1391 */ 1392 rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp); 1393 rxs->flag |= RX_FLAG_MACTIME_END; 1394 1395 rxs->freq = ah->curchan->center_freq; 1396 rxs->band = ah->curchan->band; 1397 1398 rxs->signal = ah->ah_noise_floor + rs->rs_rssi; 1399 1400 rxs->antenna = rs->rs_antenna; 1401 1402 if (rs->rs_antenna > 0 && rs->rs_antenna < 5) 1403 ah->stats.antenna_rx[rs->rs_antenna]++; 1404 else 1405 ah->stats.antenna_rx[0]++; /* invalid */ 1406 1407 rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate); 1408 rxs->flag |= ath5k_rx_decrypted(ah, skb, rs); 1409 switch (ah->ah_bwmode) { 1410 case AR5K_BWMODE_5MHZ: 1411 rxs->flag |= RX_FLAG_5MHZ; 1412 break; 1413 case AR5K_BWMODE_10MHZ: 1414 rxs->flag |= RX_FLAG_10MHZ; 1415 break; 1416 default: 1417 break; 1418 } 1419 1420 if (rxs->rate_idx >= 0 && rs->rs_rate == 1421 ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short) 1422 rxs->flag |= RX_FLAG_SHORTPRE; 1423 1424 trace_ath5k_rx(ah, skb); 1425 1426 if (ath_is_mybeacon(common, (struct ieee80211_hdr *)skb->data)) { 1427 ewma_add(&ah->ah_beacon_rssi_avg, rs->rs_rssi); 1428 1429 /* check beacons in IBSS mode */ 1430 if (ah->opmode == NL80211_IFTYPE_ADHOC) 1431 ath5k_check_ibss_tsf(ah, skb, rxs); 1432 } 1433 1434 ieee80211_rx(ah->hw, skb); 1435 } 1436 1437 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not? 1438 * 1439 * Check if we want to further process this frame or not. Also update 1440 * statistics. Return true if we want this frame, false if not. 1441 */ 1442 static bool 1443 ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs) 1444 { 1445 ah->stats.rx_all_count++; 1446 ah->stats.rx_bytes_count += rs->rs_datalen; 1447 1448 if (unlikely(rs->rs_status)) { 1449 if (rs->rs_status & AR5K_RXERR_CRC) 1450 ah->stats.rxerr_crc++; 1451 if (rs->rs_status & AR5K_RXERR_FIFO) 1452 ah->stats.rxerr_fifo++; 1453 if (rs->rs_status & AR5K_RXERR_PHY) { 1454 ah->stats.rxerr_phy++; 1455 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32) 1456 ah->stats.rxerr_phy_code[rs->rs_phyerr]++; 1457 return false; 1458 } 1459 if (rs->rs_status & AR5K_RXERR_DECRYPT) { 1460 /* 1461 * Decrypt error. If the error occurred 1462 * because there was no hardware key, then 1463 * let the frame through so the upper layers 1464 * can process it. This is necessary for 5210 1465 * parts which have no way to setup a ``clear'' 1466 * key cache entry. 1467 * 1468 * XXX do key cache faulting 1469 */ 1470 ah->stats.rxerr_decrypt++; 1471 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID && 1472 !(rs->rs_status & AR5K_RXERR_CRC)) 1473 return true; 1474 } 1475 if (rs->rs_status & AR5K_RXERR_MIC) { 1476 ah->stats.rxerr_mic++; 1477 return true; 1478 } 1479 1480 /* reject any frames with non-crypto errors */ 1481 if (rs->rs_status & ~(AR5K_RXERR_DECRYPT)) 1482 return false; 1483 } 1484 1485 if (unlikely(rs->rs_more)) { 1486 ah->stats.rxerr_jumbo++; 1487 return false; 1488 } 1489 return true; 1490 } 1491 1492 static void 1493 ath5k_set_current_imask(struct ath5k_hw *ah) 1494 { 1495 enum ath5k_int imask; 1496 unsigned long flags; 1497 1498 spin_lock_irqsave(&ah->irqlock, flags); 1499 imask = ah->imask; 1500 if (ah->rx_pending) 1501 imask &= ~AR5K_INT_RX_ALL; 1502 if (ah->tx_pending) 1503 imask &= ~AR5K_INT_TX_ALL; 1504 ath5k_hw_set_imr(ah, imask); 1505 spin_unlock_irqrestore(&ah->irqlock, flags); 1506 } 1507 1508 static void 1509 ath5k_tasklet_rx(unsigned long data) 1510 { 1511 struct ath5k_rx_status rs = {}; 1512 struct sk_buff *skb, *next_skb; 1513 dma_addr_t next_skb_addr; 1514 struct ath5k_hw *ah = (void *)data; 1515 struct ath_common *common = ath5k_hw_common(ah); 1516 struct ath5k_buf *bf; 1517 struct ath5k_desc *ds; 1518 int ret; 1519 1520 spin_lock(&ah->rxbuflock); 1521 if (list_empty(&ah->rxbuf)) { 1522 ATH5K_WARN(ah, "empty rx buf pool\n"); 1523 goto unlock; 1524 } 1525 do { 1526 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list); 1527 BUG_ON(bf->skb == NULL); 1528 skb = bf->skb; 1529 ds = bf->desc; 1530 1531 /* bail if HW is still using self-linked descriptor */ 1532 if (ath5k_hw_get_rxdp(ah) == bf->daddr) 1533 break; 1534 1535 ret = ah->ah_proc_rx_desc(ah, ds, &rs); 1536 if (unlikely(ret == -EINPROGRESS)) 1537 break; 1538 else if (unlikely(ret)) { 1539 ATH5K_ERR(ah, "error in processing rx descriptor\n"); 1540 ah->stats.rxerr_proc++; 1541 break; 1542 } 1543 1544 if (ath5k_receive_frame_ok(ah, &rs)) { 1545 next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr); 1546 1547 /* 1548 * If we can't replace bf->skb with a new skb under 1549 * memory pressure, just skip this packet 1550 */ 1551 if (!next_skb) 1552 goto next; 1553 1554 dma_unmap_single(ah->dev, bf->skbaddr, 1555 common->rx_bufsize, 1556 DMA_FROM_DEVICE); 1557 1558 skb_put(skb, rs.rs_datalen); 1559 1560 ath5k_receive_frame(ah, skb, &rs); 1561 1562 bf->skb = next_skb; 1563 bf->skbaddr = next_skb_addr; 1564 } 1565 next: 1566 list_move_tail(&bf->list, &ah->rxbuf); 1567 } while (ath5k_rxbuf_setup(ah, bf) == 0); 1568 unlock: 1569 spin_unlock(&ah->rxbuflock); 1570 ah->rx_pending = false; 1571 ath5k_set_current_imask(ah); 1572 } 1573 1574 1575 /*************\ 1576 * TX Handling * 1577 \*************/ 1578 1579 void 1580 ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb, 1581 struct ath5k_txq *txq, struct ieee80211_tx_control *control) 1582 { 1583 struct ath5k_hw *ah = hw->priv; 1584 struct ath5k_buf *bf; 1585 unsigned long flags; 1586 int padsize; 1587 1588 trace_ath5k_tx(ah, skb, txq); 1589 1590 /* 1591 * The hardware expects the header padded to 4 byte boundaries. 1592 * If this is not the case, we add the padding after the header. 1593 */ 1594 padsize = ath5k_add_padding(skb); 1595 if (padsize < 0) { 1596 ATH5K_ERR(ah, "tx hdrlen not %%4: not enough" 1597 " headroom to pad"); 1598 goto drop_packet; 1599 } 1600 1601 if (txq->txq_len >= txq->txq_max && 1602 txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX) 1603 ieee80211_stop_queue(hw, txq->qnum); 1604 1605 spin_lock_irqsave(&ah->txbuflock, flags); 1606 if (list_empty(&ah->txbuf)) { 1607 ATH5K_ERR(ah, "no further txbuf available, dropping packet\n"); 1608 spin_unlock_irqrestore(&ah->txbuflock, flags); 1609 ieee80211_stop_queues(hw); 1610 goto drop_packet; 1611 } 1612 bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list); 1613 list_del(&bf->list); 1614 ah->txbuf_len--; 1615 if (list_empty(&ah->txbuf)) 1616 ieee80211_stop_queues(hw); 1617 spin_unlock_irqrestore(&ah->txbuflock, flags); 1618 1619 bf->skb = skb; 1620 1621 if (ath5k_txbuf_setup(ah, bf, txq, padsize, control)) { 1622 bf->skb = NULL; 1623 spin_lock_irqsave(&ah->txbuflock, flags); 1624 list_add_tail(&bf->list, &ah->txbuf); 1625 ah->txbuf_len++; 1626 spin_unlock_irqrestore(&ah->txbuflock, flags); 1627 goto drop_packet; 1628 } 1629 return; 1630 1631 drop_packet: 1632 ieee80211_free_txskb(hw, skb); 1633 } 1634 1635 static void 1636 ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb, 1637 struct ath5k_txq *txq, struct ath5k_tx_status *ts, 1638 struct ath5k_buf *bf) 1639 { 1640 struct ieee80211_tx_info *info; 1641 u8 tries[3]; 1642 int i; 1643 int size = 0; 1644 1645 ah->stats.tx_all_count++; 1646 ah->stats.tx_bytes_count += skb->len; 1647 info = IEEE80211_SKB_CB(skb); 1648 1649 size = min_t(int, sizeof(info->status.rates), sizeof(bf->rates)); 1650 memcpy(info->status.rates, bf->rates, size); 1651 1652 tries[0] = info->status.rates[0].count; 1653 tries[1] = info->status.rates[1].count; 1654 tries[2] = info->status.rates[2].count; 1655 1656 ieee80211_tx_info_clear_status(info); 1657 1658 for (i = 0; i < ts->ts_final_idx; i++) { 1659 struct ieee80211_tx_rate *r = 1660 &info->status.rates[i]; 1661 1662 r->count = tries[i]; 1663 } 1664 1665 info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry; 1666 info->status.rates[ts->ts_final_idx + 1].idx = -1; 1667 1668 if (unlikely(ts->ts_status)) { 1669 ah->stats.ack_fail++; 1670 if (ts->ts_status & AR5K_TXERR_FILT) { 1671 info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 1672 ah->stats.txerr_filt++; 1673 } 1674 if (ts->ts_status & AR5K_TXERR_XRETRY) 1675 ah->stats.txerr_retry++; 1676 if (ts->ts_status & AR5K_TXERR_FIFO) 1677 ah->stats.txerr_fifo++; 1678 } else { 1679 info->flags |= IEEE80211_TX_STAT_ACK; 1680 info->status.ack_signal = ts->ts_rssi; 1681 1682 /* count the successful attempt as well */ 1683 info->status.rates[ts->ts_final_idx].count++; 1684 } 1685 1686 /* 1687 * Remove MAC header padding before giving the frame 1688 * back to mac80211. 1689 */ 1690 ath5k_remove_padding(skb); 1691 1692 if (ts->ts_antenna > 0 && ts->ts_antenna < 5) 1693 ah->stats.antenna_tx[ts->ts_antenna]++; 1694 else 1695 ah->stats.antenna_tx[0]++; /* invalid */ 1696 1697 trace_ath5k_tx_complete(ah, skb, txq, ts); 1698 ieee80211_tx_status(ah->hw, skb); 1699 } 1700 1701 static void 1702 ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq) 1703 { 1704 struct ath5k_tx_status ts = {}; 1705 struct ath5k_buf *bf, *bf0; 1706 struct ath5k_desc *ds; 1707 struct sk_buff *skb; 1708 int ret; 1709 1710 spin_lock(&txq->lock); 1711 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 1712 1713 txq->txq_poll_mark = false; 1714 1715 /* skb might already have been processed last time. */ 1716 if (bf->skb != NULL) { 1717 ds = bf->desc; 1718 1719 ret = ah->ah_proc_tx_desc(ah, ds, &ts); 1720 if (unlikely(ret == -EINPROGRESS)) 1721 break; 1722 else if (unlikely(ret)) { 1723 ATH5K_ERR(ah, 1724 "error %d while processing " 1725 "queue %u\n", ret, txq->qnum); 1726 break; 1727 } 1728 1729 skb = bf->skb; 1730 bf->skb = NULL; 1731 1732 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, 1733 DMA_TO_DEVICE); 1734 ath5k_tx_frame_completed(ah, skb, txq, &ts, bf); 1735 } 1736 1737 /* 1738 * It's possible that the hardware can say the buffer is 1739 * completed when it hasn't yet loaded the ds_link from 1740 * host memory and moved on. 1741 * Always keep the last descriptor to avoid HW races... 1742 */ 1743 if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) { 1744 spin_lock(&ah->txbuflock); 1745 list_move_tail(&bf->list, &ah->txbuf); 1746 ah->txbuf_len++; 1747 txq->txq_len--; 1748 spin_unlock(&ah->txbuflock); 1749 } 1750 } 1751 spin_unlock(&txq->lock); 1752 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4) 1753 ieee80211_wake_queue(ah->hw, txq->qnum); 1754 } 1755 1756 static void 1757 ath5k_tasklet_tx(unsigned long data) 1758 { 1759 int i; 1760 struct ath5k_hw *ah = (void *)data; 1761 1762 for (i = 0; i < AR5K_NUM_TX_QUEUES; i++) 1763 if (ah->txqs[i].setup && (ah->ah_txq_isr_txok_all & BIT(i))) 1764 ath5k_tx_processq(ah, &ah->txqs[i]); 1765 1766 ah->tx_pending = false; 1767 ath5k_set_current_imask(ah); 1768 } 1769 1770 1771 /*****************\ 1772 * Beacon handling * 1773 \*****************/ 1774 1775 /* 1776 * Setup the beacon frame for transmit. 1777 */ 1778 static int 1779 ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf) 1780 { 1781 struct sk_buff *skb = bf->skb; 1782 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1783 struct ath5k_desc *ds; 1784 int ret = 0; 1785 u8 antenna; 1786 u32 flags; 1787 const int padsize = 0; 1788 1789 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len, 1790 DMA_TO_DEVICE); 1791 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] " 1792 "skbaddr %llx\n", skb, skb->data, skb->len, 1793 (unsigned long long)bf->skbaddr); 1794 1795 if (dma_mapping_error(ah->dev, bf->skbaddr)) { 1796 ATH5K_ERR(ah, "beacon DMA mapping failed\n"); 1797 dev_kfree_skb_any(skb); 1798 bf->skb = NULL; 1799 return -EIO; 1800 } 1801 1802 ds = bf->desc; 1803 antenna = ah->ah_tx_ant; 1804 1805 flags = AR5K_TXDESC_NOACK; 1806 if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) { 1807 ds->ds_link = bf->daddr; /* self-linked */ 1808 flags |= AR5K_TXDESC_VEOL; 1809 } else 1810 ds->ds_link = 0; 1811 1812 /* 1813 * If we use multiple antennas on AP and use 1814 * the Sectored AP scenario, switch antenna every 1815 * 4 beacons to make sure everybody hears our AP. 1816 * When a client tries to associate, hw will keep 1817 * track of the tx antenna to be used for this client 1818 * automatically, based on ACKed packets. 1819 * 1820 * Note: AP still listens and transmits RTS on the 1821 * default antenna which is supposed to be an omni. 1822 * 1823 * Note2: On sectored scenarios it's possible to have 1824 * multiple antennas (1 omni -- the default -- and 14 1825 * sectors), so if we choose to actually support this 1826 * mode, we need to allow the user to set how many antennas 1827 * we have and tweak the code below to send beacons 1828 * on all of them. 1829 */ 1830 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP) 1831 antenna = ah->bsent & 4 ? 2 : 1; 1832 1833 1834 /* FIXME: If we are in g mode and rate is a CCK rate 1835 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta 1836 * from tx power (value is in dB units already) */ 1837 ds->ds_data = bf->skbaddr; 1838 ret = ah->ah_setup_tx_desc(ah, ds, skb->len, 1839 ieee80211_get_hdrlen_from_skb(skb), padsize, 1840 AR5K_PKT_TYPE_BEACON, 1841 (ah->ah_txpower.txp_requested * 2), 1842 ieee80211_get_tx_rate(ah->hw, info)->hw_value, 1843 1, AR5K_TXKEYIX_INVALID, 1844 antenna, flags, 0, 0); 1845 if (ret) 1846 goto err_unmap; 1847 1848 return 0; 1849 err_unmap: 1850 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); 1851 return ret; 1852 } 1853 1854 /* 1855 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc, 1856 * this is called only once at config_bss time, for AP we do it every 1857 * SWBA interrupt so that the TIM will reflect buffered frames. 1858 * 1859 * Called with the beacon lock. 1860 */ 1861 int 1862 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1863 { 1864 int ret; 1865 struct ath5k_hw *ah = hw->priv; 1866 struct ath5k_vif *avf; 1867 struct sk_buff *skb; 1868 1869 if (WARN_ON(!vif)) { 1870 ret = -EINVAL; 1871 goto out; 1872 } 1873 1874 skb = ieee80211_beacon_get(hw, vif); 1875 1876 if (!skb) { 1877 ret = -ENOMEM; 1878 goto out; 1879 } 1880 1881 avf = (void *)vif->drv_priv; 1882 ath5k_txbuf_free_skb(ah, avf->bbuf); 1883 avf->bbuf->skb = skb; 1884 ret = ath5k_beacon_setup(ah, avf->bbuf); 1885 out: 1886 return ret; 1887 } 1888 1889 /* 1890 * Transmit a beacon frame at SWBA. Dynamic updates to the 1891 * frame contents are done as needed and the slot time is 1892 * also adjusted based on current state. 1893 * 1894 * This is called from software irq context (beacontq tasklets) 1895 * or user context from ath5k_beacon_config. 1896 */ 1897 static void 1898 ath5k_beacon_send(struct ath5k_hw *ah) 1899 { 1900 struct ieee80211_vif *vif; 1901 struct ath5k_vif *avf; 1902 struct ath5k_buf *bf; 1903 struct sk_buff *skb; 1904 int err; 1905 1906 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n"); 1907 1908 /* 1909 * Check if the previous beacon has gone out. If 1910 * not, don't don't try to post another: skip this 1911 * period and wait for the next. Missed beacons 1912 * indicate a problem and should not occur. If we 1913 * miss too many consecutive beacons reset the device. 1914 */ 1915 if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) { 1916 ah->bmisscount++; 1917 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 1918 "missed %u consecutive beacons\n", ah->bmisscount); 1919 if (ah->bmisscount > 10) { /* NB: 10 is a guess */ 1920 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 1921 "stuck beacon time (%u missed)\n", 1922 ah->bmisscount); 1923 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 1924 "stuck beacon, resetting\n"); 1925 ieee80211_queue_work(ah->hw, &ah->reset_work); 1926 } 1927 return; 1928 } 1929 if (unlikely(ah->bmisscount != 0)) { 1930 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 1931 "resume beacon xmit after %u misses\n", 1932 ah->bmisscount); 1933 ah->bmisscount = 0; 1934 } 1935 1936 if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs + 1937 ah->num_mesh_vifs > 1) || 1938 ah->opmode == NL80211_IFTYPE_MESH_POINT) { 1939 u64 tsf = ath5k_hw_get_tsf64(ah); 1940 u32 tsftu = TSF_TO_TU(tsf); 1941 int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval; 1942 vif = ah->bslot[(slot + 1) % ATH_BCBUF]; 1943 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 1944 "tsf %llx tsftu %x intval %u slot %u vif %p\n", 1945 (unsigned long long)tsf, tsftu, ah->bintval, slot, vif); 1946 } else /* only one interface */ 1947 vif = ah->bslot[0]; 1948 1949 if (!vif) 1950 return; 1951 1952 avf = (void *)vif->drv_priv; 1953 bf = avf->bbuf; 1954 1955 /* 1956 * Stop any current dma and put the new frame on the queue. 1957 * This should never fail since we check above that no frames 1958 * are still pending on the queue. 1959 */ 1960 if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) { 1961 ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq); 1962 /* NB: hw still stops DMA, so proceed */ 1963 } 1964 1965 /* refresh the beacon for AP or MESH mode */ 1966 if (ah->opmode == NL80211_IFTYPE_AP || 1967 ah->opmode == NL80211_IFTYPE_MESH_POINT) { 1968 err = ath5k_beacon_update(ah->hw, vif); 1969 if (err) 1970 return; 1971 } 1972 1973 if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION || 1974 ah->opmode == NL80211_IFTYPE_MONITOR)) { 1975 ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf->skb); 1976 return; 1977 } 1978 1979 trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]); 1980 1981 ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr); 1982 ath5k_hw_start_tx_dma(ah, ah->bhalq); 1983 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n", 1984 ah->bhalq, (unsigned long long)bf->daddr, bf->desc); 1985 1986 skb = ieee80211_get_buffered_bc(ah->hw, vif); 1987 while (skb) { 1988 ath5k_tx_queue(ah->hw, skb, ah->cabq, NULL); 1989 1990 if (ah->cabq->txq_len >= ah->cabq->txq_max) 1991 break; 1992 1993 skb = ieee80211_get_buffered_bc(ah->hw, vif); 1994 } 1995 1996 ah->bsent++; 1997 } 1998 1999 /** 2000 * ath5k_beacon_update_timers - update beacon timers 2001 * 2002 * @ah: struct ath5k_hw pointer we are operating on 2003 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a 2004 * beacon timer update based on the current HW TSF. 2005 * 2006 * Calculate the next target beacon transmit time (TBTT) based on the timestamp 2007 * of a received beacon or the current local hardware TSF and write it to the 2008 * beacon timer registers. 2009 * 2010 * This is called in a variety of situations, e.g. when a beacon is received, 2011 * when a TSF update has been detected, but also when an new IBSS is created or 2012 * when we otherwise know we have to update the timers, but we keep it in this 2013 * function to have it all together in one place. 2014 */ 2015 void 2016 ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf) 2017 { 2018 u32 nexttbtt, intval, hw_tu, bc_tu; 2019 u64 hw_tsf; 2020 2021 intval = ah->bintval & AR5K_BEACON_PERIOD; 2022 if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs 2023 + ah->num_mesh_vifs > 1) { 2024 intval /= ATH_BCBUF; /* staggered multi-bss beacons */ 2025 if (intval < 15) 2026 ATH5K_WARN(ah, "intval %u is too low, min 15\n", 2027 intval); 2028 } 2029 if (WARN_ON(!intval)) 2030 return; 2031 2032 /* beacon TSF converted to TU */ 2033 bc_tu = TSF_TO_TU(bc_tsf); 2034 2035 /* current TSF converted to TU */ 2036 hw_tsf = ath5k_hw_get_tsf64(ah); 2037 hw_tu = TSF_TO_TU(hw_tsf); 2038 2039 #define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3) 2040 /* We use FUDGE to make sure the next TBTT is ahead of the current TU. 2041 * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer 2042 * configuration we need to make sure it is bigger than that. */ 2043 2044 if (bc_tsf == -1) { 2045 /* 2046 * no beacons received, called internally. 2047 * just need to refresh timers based on HW TSF. 2048 */ 2049 nexttbtt = roundup(hw_tu + FUDGE, intval); 2050 } else if (bc_tsf == 0) { 2051 /* 2052 * no beacon received, probably called by ath5k_reset_tsf(). 2053 * reset TSF to start with 0. 2054 */ 2055 nexttbtt = intval; 2056 intval |= AR5K_BEACON_RESET_TSF; 2057 } else if (bc_tsf > hw_tsf) { 2058 /* 2059 * beacon received, SW merge happened but HW TSF not yet updated. 2060 * not possible to reconfigure timers yet, but next time we 2061 * receive a beacon with the same BSSID, the hardware will 2062 * automatically update the TSF and then we need to reconfigure 2063 * the timers. 2064 */ 2065 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2066 "need to wait for HW TSF sync\n"); 2067 return; 2068 } else { 2069 /* 2070 * most important case for beacon synchronization between STA. 2071 * 2072 * beacon received and HW TSF has been already updated by HW. 2073 * update next TBTT based on the TSF of the beacon, but make 2074 * sure it is ahead of our local TSF timer. 2075 */ 2076 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval); 2077 } 2078 #undef FUDGE 2079 2080 ah->nexttbtt = nexttbtt; 2081 2082 intval |= AR5K_BEACON_ENA; 2083 ath5k_hw_init_beacon_timers(ah, nexttbtt, intval); 2084 2085 /* 2086 * debugging output last in order to preserve the time critical aspect 2087 * of this function 2088 */ 2089 if (bc_tsf == -1) 2090 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2091 "reconfigured timers based on HW TSF\n"); 2092 else if (bc_tsf == 0) 2093 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2094 "reset HW TSF and timers\n"); 2095 else 2096 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2097 "updated timers based on beacon TSF\n"); 2098 2099 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2100 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n", 2101 (unsigned long long) bc_tsf, 2102 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt); 2103 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n", 2104 intval & AR5K_BEACON_PERIOD, 2105 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "", 2106 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : ""); 2107 } 2108 2109 /** 2110 * ath5k_beacon_config - Configure the beacon queues and interrupts 2111 * 2112 * @ah: struct ath5k_hw pointer we are operating on 2113 * 2114 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA 2115 * interrupts to detect TSF updates only. 2116 */ 2117 void 2118 ath5k_beacon_config(struct ath5k_hw *ah) 2119 { 2120 spin_lock_bh(&ah->block); 2121 ah->bmisscount = 0; 2122 ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA); 2123 2124 if (ah->enable_beacon) { 2125 /* 2126 * In IBSS mode we use a self-linked tx descriptor and let the 2127 * hardware send the beacons automatically. We have to load it 2128 * only once here. 2129 * We use the SWBA interrupt only to keep track of the beacon 2130 * timers in order to detect automatic TSF updates. 2131 */ 2132 ath5k_beaconq_config(ah); 2133 2134 ah->imask |= AR5K_INT_SWBA; 2135 2136 if (ah->opmode == NL80211_IFTYPE_ADHOC) { 2137 if (ath5k_hw_hasveol(ah)) 2138 ath5k_beacon_send(ah); 2139 } else 2140 ath5k_beacon_update_timers(ah, -1); 2141 } else { 2142 ath5k_hw_stop_beacon_queue(ah, ah->bhalq); 2143 } 2144 2145 ath5k_hw_set_imr(ah, ah->imask); 2146 mmiowb(); 2147 spin_unlock_bh(&ah->block); 2148 } 2149 2150 static void ath5k_tasklet_beacon(unsigned long data) 2151 { 2152 struct ath5k_hw *ah = (struct ath5k_hw *) data; 2153 2154 /* 2155 * Software beacon alert--time to send a beacon. 2156 * 2157 * In IBSS mode we use this interrupt just to 2158 * keep track of the next TBTT (target beacon 2159 * transmission time) in order to detect whether 2160 * automatic TSF updates happened. 2161 */ 2162 if (ah->opmode == NL80211_IFTYPE_ADHOC) { 2163 /* XXX: only if VEOL supported */ 2164 u64 tsf = ath5k_hw_get_tsf64(ah); 2165 ah->nexttbtt += ah->bintval; 2166 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 2167 "SWBA nexttbtt: %x hw_tu: %x " 2168 "TSF: %llx\n", 2169 ah->nexttbtt, 2170 TSF_TO_TU(tsf), 2171 (unsigned long long) tsf); 2172 } else { 2173 spin_lock(&ah->block); 2174 ath5k_beacon_send(ah); 2175 spin_unlock(&ah->block); 2176 } 2177 } 2178 2179 2180 /********************\ 2181 * Interrupt handling * 2182 \********************/ 2183 2184 static void 2185 ath5k_intr_calibration_poll(struct ath5k_hw *ah) 2186 { 2187 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) && 2188 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) && 2189 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) { 2190 2191 /* Run ANI only when calibration is not active */ 2192 2193 ah->ah_cal_next_ani = jiffies + 2194 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI); 2195 tasklet_schedule(&ah->ani_tasklet); 2196 2197 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_short) && 2198 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) && 2199 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) { 2200 2201 /* Run calibration only when another calibration 2202 * is not running. 2203 * 2204 * Note: This is for both full/short calibration, 2205 * if it's time for a full one, ath5k_calibrate_work will deal 2206 * with it. */ 2207 2208 ah->ah_cal_next_short = jiffies + 2209 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT); 2210 ieee80211_queue_work(ah->hw, &ah->calib_work); 2211 } 2212 /* we could use SWI to generate enough interrupts to meet our 2213 * calibration interval requirements, if necessary: 2214 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */ 2215 } 2216 2217 static void 2218 ath5k_schedule_rx(struct ath5k_hw *ah) 2219 { 2220 ah->rx_pending = true; 2221 tasklet_schedule(&ah->rxtq); 2222 } 2223 2224 static void 2225 ath5k_schedule_tx(struct ath5k_hw *ah) 2226 { 2227 ah->tx_pending = true; 2228 tasklet_schedule(&ah->txtq); 2229 } 2230 2231 static irqreturn_t 2232 ath5k_intr(int irq, void *dev_id) 2233 { 2234 struct ath5k_hw *ah = dev_id; 2235 enum ath5k_int status; 2236 unsigned int counter = 1000; 2237 2238 2239 /* 2240 * If hw is not ready (or detached) and we get an 2241 * interrupt, or if we have no interrupts pending 2242 * (that means it's not for us) skip it. 2243 * 2244 * NOTE: Group 0/1 PCI interface registers are not 2245 * supported on WiSOCs, so we can't check for pending 2246 * interrupts (ISR belongs to another register group 2247 * so we are ok). 2248 */ 2249 if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) || 2250 ((ath5k_get_bus_type(ah) != ATH_AHB) && 2251 !ath5k_hw_is_intr_pending(ah)))) 2252 return IRQ_NONE; 2253 2254 /** Main loop **/ 2255 do { 2256 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ 2257 2258 ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n", 2259 status, ah->imask); 2260 2261 /* 2262 * Fatal hw error -> Log and reset 2263 * 2264 * Fatal errors are unrecoverable so we have to 2265 * reset the card. These errors include bus and 2266 * dma errors. 2267 */ 2268 if (unlikely(status & AR5K_INT_FATAL)) { 2269 2270 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2271 "fatal int, resetting\n"); 2272 ieee80211_queue_work(ah->hw, &ah->reset_work); 2273 2274 /* 2275 * RX Overrun -> Count and reset if needed 2276 * 2277 * Receive buffers are full. Either the bus is busy or 2278 * the CPU is not fast enough to process all received 2279 * frames. 2280 */ 2281 } else if (unlikely(status & AR5K_INT_RXORN)) { 2282 2283 /* 2284 * Older chipsets need a reset to come out of this 2285 * condition, but we treat it as RX for newer chips. 2286 * We don't know exactly which versions need a reset 2287 * this guess is copied from the HAL. 2288 */ 2289 ah->stats.rxorn_intr++; 2290 2291 if (ah->ah_mac_srev < AR5K_SREV_AR5212) { 2292 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2293 "rx overrun, resetting\n"); 2294 ieee80211_queue_work(ah->hw, &ah->reset_work); 2295 } else 2296 ath5k_schedule_rx(ah); 2297 2298 } else { 2299 2300 /* Software Beacon Alert -> Schedule beacon tasklet */ 2301 if (status & AR5K_INT_SWBA) 2302 tasklet_hi_schedule(&ah->beacontq); 2303 2304 /* 2305 * No more RX descriptors -> Just count 2306 * 2307 * NB: the hardware should re-read the link when 2308 * RXE bit is written, but it doesn't work at 2309 * least on older hardware revs. 2310 */ 2311 if (status & AR5K_INT_RXEOL) 2312 ah->stats.rxeol_intr++; 2313 2314 2315 /* TX Underrun -> Bump tx trigger level */ 2316 if (status & AR5K_INT_TXURN) 2317 ath5k_hw_update_tx_triglevel(ah, true); 2318 2319 /* RX -> Schedule rx tasklet */ 2320 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR)) 2321 ath5k_schedule_rx(ah); 2322 2323 /* TX -> Schedule tx tasklet */ 2324 if (status & (AR5K_INT_TXOK 2325 | AR5K_INT_TXDESC 2326 | AR5K_INT_TXERR 2327 | AR5K_INT_TXEOL)) 2328 ath5k_schedule_tx(ah); 2329 2330 /* Missed beacon -> TODO 2331 if (status & AR5K_INT_BMISS) 2332 */ 2333 2334 /* MIB event -> Update counters and notify ANI */ 2335 if (status & AR5K_INT_MIB) { 2336 ah->stats.mib_intr++; 2337 ath5k_hw_update_mib_counters(ah); 2338 ath5k_ani_mib_intr(ah); 2339 } 2340 2341 /* GPIO -> Notify RFKill layer */ 2342 if (status & AR5K_INT_GPIO) 2343 tasklet_schedule(&ah->rf_kill.toggleq); 2344 2345 } 2346 2347 if (ath5k_get_bus_type(ah) == ATH_AHB) 2348 break; 2349 2350 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0); 2351 2352 /* 2353 * Until we handle rx/tx interrupts mask them on IMR 2354 * 2355 * NOTE: ah->(rx/tx)_pending are set when scheduling the tasklets 2356 * and unset after we 've handled the interrupts. 2357 */ 2358 if (ah->rx_pending || ah->tx_pending) 2359 ath5k_set_current_imask(ah); 2360 2361 if (unlikely(!counter)) 2362 ATH5K_WARN(ah, "too many interrupts, giving up for now\n"); 2363 2364 /* Fire up calibration poll */ 2365 ath5k_intr_calibration_poll(ah); 2366 2367 return IRQ_HANDLED; 2368 } 2369 2370 /* 2371 * Periodically recalibrate the PHY to account 2372 * for temperature/environment changes. 2373 */ 2374 static void 2375 ath5k_calibrate_work(struct work_struct *work) 2376 { 2377 struct ath5k_hw *ah = container_of(work, struct ath5k_hw, 2378 calib_work); 2379 2380 /* Should we run a full calibration ? */ 2381 if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) { 2382 2383 ah->ah_cal_next_full = jiffies + 2384 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL); 2385 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL; 2386 2387 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, 2388 "running full calibration\n"); 2389 2390 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) { 2391 /* 2392 * Rfgain is out of bounds, reset the chip 2393 * to load new gain values. 2394 */ 2395 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2396 "got new rfgain, resetting\n"); 2397 ieee80211_queue_work(ah->hw, &ah->reset_work); 2398 } 2399 } else 2400 ah->ah_cal_mask |= AR5K_CALIBRATION_SHORT; 2401 2402 2403 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n", 2404 ieee80211_frequency_to_channel(ah->curchan->center_freq), 2405 ah->curchan->hw_value); 2406 2407 if (ath5k_hw_phy_calibrate(ah, ah->curchan)) 2408 ATH5K_ERR(ah, "calibration of channel %u failed\n", 2409 ieee80211_frequency_to_channel( 2410 ah->curchan->center_freq)); 2411 2412 /* Clear calibration flags */ 2413 if (ah->ah_cal_mask & AR5K_CALIBRATION_FULL) 2414 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL; 2415 else if (ah->ah_cal_mask & AR5K_CALIBRATION_SHORT) 2416 ah->ah_cal_mask &= ~AR5K_CALIBRATION_SHORT; 2417 } 2418 2419 2420 static void 2421 ath5k_tasklet_ani(unsigned long data) 2422 { 2423 struct ath5k_hw *ah = (void *)data; 2424 2425 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI; 2426 ath5k_ani_calibration(ah); 2427 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI; 2428 } 2429 2430 2431 static void 2432 ath5k_tx_complete_poll_work(struct work_struct *work) 2433 { 2434 struct ath5k_hw *ah = container_of(work, struct ath5k_hw, 2435 tx_complete_work.work); 2436 struct ath5k_txq *txq; 2437 int i; 2438 bool needreset = false; 2439 2440 if (!test_bit(ATH_STAT_STARTED, ah->status)) 2441 return; 2442 2443 mutex_lock(&ah->lock); 2444 2445 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) { 2446 if (ah->txqs[i].setup) { 2447 txq = &ah->txqs[i]; 2448 spin_lock_bh(&txq->lock); 2449 if (txq->txq_len > 1) { 2450 if (txq->txq_poll_mark) { 2451 ATH5K_DBG(ah, ATH5K_DEBUG_XMIT, 2452 "TX queue stuck %d\n", 2453 txq->qnum); 2454 needreset = true; 2455 txq->txq_stuck++; 2456 spin_unlock_bh(&txq->lock); 2457 break; 2458 } else { 2459 txq->txq_poll_mark = true; 2460 } 2461 } 2462 spin_unlock_bh(&txq->lock); 2463 } 2464 } 2465 2466 if (needreset) { 2467 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2468 "TX queues stuck, resetting\n"); 2469 ath5k_reset(ah, NULL, true); 2470 } 2471 2472 mutex_unlock(&ah->lock); 2473 2474 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work, 2475 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); 2476 } 2477 2478 2479 /*************************\ 2480 * Initialization routines * 2481 \*************************/ 2482 2483 static const struct ieee80211_iface_limit if_limits[] = { 2484 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) }, 2485 { .max = 4, .types = 2486 #ifdef CONFIG_MAC80211_MESH 2487 BIT(NL80211_IFTYPE_MESH_POINT) | 2488 #endif 2489 BIT(NL80211_IFTYPE_AP) }, 2490 }; 2491 2492 static const struct ieee80211_iface_combination if_comb = { 2493 .limits = if_limits, 2494 .n_limits = ARRAY_SIZE(if_limits), 2495 .max_interfaces = 2048, 2496 .num_different_channels = 1, 2497 }; 2498 2499 int 2500 ath5k_init_ah(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops) 2501 { 2502 struct ieee80211_hw *hw = ah->hw; 2503 struct ath_common *common; 2504 int ret; 2505 int csz; 2506 2507 /* Initialize driver private data */ 2508 SET_IEEE80211_DEV(hw, ah->dev); 2509 hw->flags = IEEE80211_HW_RX_INCLUDES_FCS | 2510 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING | 2511 IEEE80211_HW_SIGNAL_DBM | 2512 IEEE80211_HW_MFP_CAPABLE | 2513 IEEE80211_HW_REPORTS_TX_ACK_STATUS | 2514 IEEE80211_HW_SUPPORTS_RC_TABLE; 2515 2516 hw->wiphy->interface_modes = 2517 BIT(NL80211_IFTYPE_AP) | 2518 BIT(NL80211_IFTYPE_STATION) | 2519 BIT(NL80211_IFTYPE_ADHOC) | 2520 BIT(NL80211_IFTYPE_MESH_POINT); 2521 2522 hw->wiphy->iface_combinations = &if_comb; 2523 hw->wiphy->n_iface_combinations = 1; 2524 2525 /* SW support for IBSS_RSN is provided by mac80211 */ 2526 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; 2527 2528 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ; 2529 2530 /* both antennas can be configured as RX or TX */ 2531 hw->wiphy->available_antennas_tx = 0x3; 2532 hw->wiphy->available_antennas_rx = 0x3; 2533 2534 hw->extra_tx_headroom = 2; 2535 2536 /* 2537 * Mark the device as detached to avoid processing 2538 * interrupts until setup is complete. 2539 */ 2540 __set_bit(ATH_STAT_INVALID, ah->status); 2541 2542 ah->opmode = NL80211_IFTYPE_STATION; 2543 ah->bintval = 1000; 2544 mutex_init(&ah->lock); 2545 spin_lock_init(&ah->rxbuflock); 2546 spin_lock_init(&ah->txbuflock); 2547 spin_lock_init(&ah->block); 2548 spin_lock_init(&ah->irqlock); 2549 2550 /* Setup interrupt handler */ 2551 ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah); 2552 if (ret) { 2553 ATH5K_ERR(ah, "request_irq failed\n"); 2554 goto err; 2555 } 2556 2557 common = ath5k_hw_common(ah); 2558 common->ops = &ath5k_common_ops; 2559 common->bus_ops = bus_ops; 2560 common->ah = ah; 2561 common->hw = hw; 2562 common->priv = ah; 2563 common->clockrate = 40; 2564 2565 /* 2566 * Cache line size is used to size and align various 2567 * structures used to communicate with the hardware. 2568 */ 2569 ath5k_read_cachesize(common, &csz); 2570 common->cachelsz = csz << 2; /* convert to bytes */ 2571 2572 spin_lock_init(&common->cc_lock); 2573 2574 /* Initialize device */ 2575 ret = ath5k_hw_init(ah); 2576 if (ret) 2577 goto err_irq; 2578 2579 /* Set up multi-rate retry capabilities */ 2580 if (ah->ah_capabilities.cap_has_mrr_support) { 2581 hw->max_rates = 4; 2582 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT, 2583 AR5K_INIT_RETRY_LONG); 2584 } 2585 2586 hw->vif_data_size = sizeof(struct ath5k_vif); 2587 2588 /* Finish private driver data initialization */ 2589 ret = ath5k_init(hw); 2590 if (ret) 2591 goto err_ah; 2592 2593 ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n", 2594 ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev), 2595 ah->ah_mac_srev, 2596 ah->ah_phy_revision); 2597 2598 if (!ah->ah_single_chip) { 2599 /* Single chip radio (!RF5111) */ 2600 if (ah->ah_radio_5ghz_revision && 2601 !ah->ah_radio_2ghz_revision) { 2602 /* No 5GHz support -> report 2GHz radio */ 2603 if (!test_bit(AR5K_MODE_11A, 2604 ah->ah_capabilities.cap_mode)) { 2605 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n", 2606 ath5k_chip_name(AR5K_VERSION_RAD, 2607 ah->ah_radio_5ghz_revision), 2608 ah->ah_radio_5ghz_revision); 2609 /* No 2GHz support (5110 and some 2610 * 5GHz only cards) -> report 5GHz radio */ 2611 } else if (!test_bit(AR5K_MODE_11B, 2612 ah->ah_capabilities.cap_mode)) { 2613 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n", 2614 ath5k_chip_name(AR5K_VERSION_RAD, 2615 ah->ah_radio_5ghz_revision), 2616 ah->ah_radio_5ghz_revision); 2617 /* Multiband radio */ 2618 } else { 2619 ATH5K_INFO(ah, "RF%s multiband radio found" 2620 " (0x%x)\n", 2621 ath5k_chip_name(AR5K_VERSION_RAD, 2622 ah->ah_radio_5ghz_revision), 2623 ah->ah_radio_5ghz_revision); 2624 } 2625 } 2626 /* Multi chip radio (RF5111 - RF2111) -> 2627 * report both 2GHz/5GHz radios */ 2628 else if (ah->ah_radio_5ghz_revision && 2629 ah->ah_radio_2ghz_revision) { 2630 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n", 2631 ath5k_chip_name(AR5K_VERSION_RAD, 2632 ah->ah_radio_5ghz_revision), 2633 ah->ah_radio_5ghz_revision); 2634 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n", 2635 ath5k_chip_name(AR5K_VERSION_RAD, 2636 ah->ah_radio_2ghz_revision), 2637 ah->ah_radio_2ghz_revision); 2638 } 2639 } 2640 2641 ath5k_debug_init_device(ah); 2642 2643 /* ready to process interrupts */ 2644 __clear_bit(ATH_STAT_INVALID, ah->status); 2645 2646 return 0; 2647 err_ah: 2648 ath5k_hw_deinit(ah); 2649 err_irq: 2650 free_irq(ah->irq, ah); 2651 err: 2652 return ret; 2653 } 2654 2655 static int 2656 ath5k_stop_locked(struct ath5k_hw *ah) 2657 { 2658 2659 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n", 2660 test_bit(ATH_STAT_INVALID, ah->status)); 2661 2662 /* 2663 * Shutdown the hardware and driver: 2664 * stop output from above 2665 * disable interrupts 2666 * turn off timers 2667 * turn off the radio 2668 * clear transmit machinery 2669 * clear receive machinery 2670 * drain and release tx queues 2671 * reclaim beacon resources 2672 * power down hardware 2673 * 2674 * Note that some of this work is not possible if the 2675 * hardware is gone (invalid). 2676 */ 2677 ieee80211_stop_queues(ah->hw); 2678 2679 if (!test_bit(ATH_STAT_INVALID, ah->status)) { 2680 ath5k_led_off(ah); 2681 ath5k_hw_set_imr(ah, 0); 2682 synchronize_irq(ah->irq); 2683 ath5k_rx_stop(ah); 2684 ath5k_hw_dma_stop(ah); 2685 ath5k_drain_tx_buffs(ah); 2686 ath5k_hw_phy_disable(ah); 2687 } 2688 2689 return 0; 2690 } 2691 2692 int ath5k_start(struct ieee80211_hw *hw) 2693 { 2694 struct ath5k_hw *ah = hw->priv; 2695 struct ath_common *common = ath5k_hw_common(ah); 2696 int ret, i; 2697 2698 mutex_lock(&ah->lock); 2699 2700 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode); 2701 2702 /* 2703 * Stop anything previously setup. This is safe 2704 * no matter this is the first time through or not. 2705 */ 2706 ath5k_stop_locked(ah); 2707 2708 /* 2709 * The basic interface to setting the hardware in a good 2710 * state is ``reset''. On return the hardware is known to 2711 * be powered up and with interrupts disabled. This must 2712 * be followed by initialization of the appropriate bits 2713 * and then setup of the interrupt mask. 2714 */ 2715 ah->curchan = ah->hw->conf.chandef.chan; 2716 ah->imask = AR5K_INT_RXOK 2717 | AR5K_INT_RXERR 2718 | AR5K_INT_RXEOL 2719 | AR5K_INT_RXORN 2720 | AR5K_INT_TXDESC 2721 | AR5K_INT_TXEOL 2722 | AR5K_INT_FATAL 2723 | AR5K_INT_GLOBAL 2724 | AR5K_INT_MIB; 2725 2726 ret = ath5k_reset(ah, NULL, false); 2727 if (ret) 2728 goto done; 2729 2730 if (!ath5k_modparam_no_hw_rfkill_switch) 2731 ath5k_rfkill_hw_start(ah); 2732 2733 /* 2734 * Reset the key cache since some parts do not reset the 2735 * contents on initial power up or resume from suspend. 2736 */ 2737 for (i = 0; i < common->keymax; i++) 2738 ath_hw_keyreset(common, (u16) i); 2739 2740 /* Use higher rates for acks instead of base 2741 * rate */ 2742 ah->ah_ack_bitrate_high = true; 2743 2744 for (i = 0; i < ARRAY_SIZE(ah->bslot); i++) 2745 ah->bslot[i] = NULL; 2746 2747 ret = 0; 2748 done: 2749 mmiowb(); 2750 mutex_unlock(&ah->lock); 2751 2752 set_bit(ATH_STAT_STARTED, ah->status); 2753 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work, 2754 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); 2755 2756 return ret; 2757 } 2758 2759 static void ath5k_stop_tasklets(struct ath5k_hw *ah) 2760 { 2761 ah->rx_pending = false; 2762 ah->tx_pending = false; 2763 tasklet_kill(&ah->rxtq); 2764 tasklet_kill(&ah->txtq); 2765 tasklet_kill(&ah->beacontq); 2766 tasklet_kill(&ah->ani_tasklet); 2767 } 2768 2769 /* 2770 * Stop the device, grabbing the top-level lock to protect 2771 * against concurrent entry through ath5k_init (which can happen 2772 * if another thread does a system call and the thread doing the 2773 * stop is preempted). 2774 */ 2775 void ath5k_stop(struct ieee80211_hw *hw) 2776 { 2777 struct ath5k_hw *ah = hw->priv; 2778 int ret; 2779 2780 mutex_lock(&ah->lock); 2781 ret = ath5k_stop_locked(ah); 2782 if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) { 2783 /* 2784 * Don't set the card in full sleep mode! 2785 * 2786 * a) When the device is in this state it must be carefully 2787 * woken up or references to registers in the PCI clock 2788 * domain may freeze the bus (and system). This varies 2789 * by chip and is mostly an issue with newer parts 2790 * (madwifi sources mentioned srev >= 0x78) that go to 2791 * sleep more quickly. 2792 * 2793 * b) On older chips full sleep results a weird behaviour 2794 * during wakeup. I tested various cards with srev < 0x78 2795 * and they don't wake up after module reload, a second 2796 * module reload is needed to bring the card up again. 2797 * 2798 * Until we figure out what's going on don't enable 2799 * full chip reset on any chip (this is what Legacy HAL 2800 * and Sam's HAL do anyway). Instead Perform a full reset 2801 * on the device (same as initial state after attach) and 2802 * leave it idle (keep MAC/BB on warm reset) */ 2803 ret = ath5k_hw_on_hold(ah); 2804 2805 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2806 "putting device to sleep\n"); 2807 } 2808 2809 mmiowb(); 2810 mutex_unlock(&ah->lock); 2811 2812 ath5k_stop_tasklets(ah); 2813 2814 clear_bit(ATH_STAT_STARTED, ah->status); 2815 cancel_delayed_work_sync(&ah->tx_complete_work); 2816 2817 if (!ath5k_modparam_no_hw_rfkill_switch) 2818 ath5k_rfkill_hw_stop(ah); 2819 } 2820 2821 /* 2822 * Reset the hardware. If chan is not NULL, then also pause rx/tx 2823 * and change to the given channel. 2824 * 2825 * This should be called with ah->lock. 2826 */ 2827 static int 2828 ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan, 2829 bool skip_pcu) 2830 { 2831 struct ath_common *common = ath5k_hw_common(ah); 2832 int ret, ani_mode; 2833 bool fast; 2834 2835 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n"); 2836 2837 ath5k_hw_set_imr(ah, 0); 2838 synchronize_irq(ah->irq); 2839 ath5k_stop_tasklets(ah); 2840 2841 /* Save ani mode and disable ANI during 2842 * reset. If we don't we might get false 2843 * PHY error interrupts. */ 2844 ani_mode = ah->ani_state.ani_mode; 2845 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF); 2846 2847 /* We are going to empty hw queues 2848 * so we should also free any remaining 2849 * tx buffers */ 2850 ath5k_drain_tx_buffs(ah); 2851 if (chan) 2852 ah->curchan = chan; 2853 2854 fast = ((chan != NULL) && modparam_fastchanswitch) ? 1 : 0; 2855 2856 ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu); 2857 if (ret) { 2858 ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret); 2859 goto err; 2860 } 2861 2862 ret = ath5k_rx_start(ah); 2863 if (ret) { 2864 ATH5K_ERR(ah, "can't start recv logic\n"); 2865 goto err; 2866 } 2867 2868 ath5k_ani_init(ah, ani_mode); 2869 2870 /* 2871 * Set calibration intervals 2872 * 2873 * Note: We don't need to run calibration imediately 2874 * since some initial calibration is done on reset 2875 * even for fast channel switching. Also on scanning 2876 * this will get set again and again and it won't get 2877 * executed unless we connect somewhere and spend some 2878 * time on the channel (that's what calibration needs 2879 * anyway to be accurate). 2880 */ 2881 ah->ah_cal_next_full = jiffies + 2882 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL); 2883 ah->ah_cal_next_ani = jiffies + 2884 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI); 2885 ah->ah_cal_next_short = jiffies + 2886 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT); 2887 2888 ewma_init(&ah->ah_beacon_rssi_avg, 1024, 8); 2889 2890 /* clear survey data and cycle counters */ 2891 memset(&ah->survey, 0, sizeof(ah->survey)); 2892 spin_lock_bh(&common->cc_lock); 2893 ath_hw_cycle_counters_update(common); 2894 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 2895 memset(&common->cc_ani, 0, sizeof(common->cc_ani)); 2896 spin_unlock_bh(&common->cc_lock); 2897 2898 /* 2899 * Change channels and update the h/w rate map if we're switching; 2900 * e.g. 11a to 11b/g. 2901 * 2902 * We may be doing a reset in response to an ioctl that changes the 2903 * channel so update any state that might change as a result. 2904 * 2905 * XXX needed? 2906 */ 2907 /* ath5k_chan_change(ah, c); */ 2908 2909 ath5k_beacon_config(ah); 2910 /* intrs are enabled by ath5k_beacon_config */ 2911 2912 ieee80211_wake_queues(ah->hw); 2913 2914 return 0; 2915 err: 2916 return ret; 2917 } 2918 2919 static void ath5k_reset_work(struct work_struct *work) 2920 { 2921 struct ath5k_hw *ah = container_of(work, struct ath5k_hw, 2922 reset_work); 2923 2924 mutex_lock(&ah->lock); 2925 ath5k_reset(ah, NULL, true); 2926 mutex_unlock(&ah->lock); 2927 } 2928 2929 static int 2930 ath5k_init(struct ieee80211_hw *hw) 2931 { 2932 2933 struct ath5k_hw *ah = hw->priv; 2934 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 2935 struct ath5k_txq *txq; 2936 u8 mac[ETH_ALEN] = {}; 2937 int ret; 2938 2939 2940 /* 2941 * Collect the channel list. The 802.11 layer 2942 * is responsible for filtering this list based 2943 * on settings like the phy mode and regulatory 2944 * domain restrictions. 2945 */ 2946 ret = ath5k_setup_bands(hw); 2947 if (ret) { 2948 ATH5K_ERR(ah, "can't get channels\n"); 2949 goto err; 2950 } 2951 2952 /* 2953 * Allocate tx+rx descriptors and populate the lists. 2954 */ 2955 ret = ath5k_desc_alloc(ah); 2956 if (ret) { 2957 ATH5K_ERR(ah, "can't allocate descriptors\n"); 2958 goto err; 2959 } 2960 2961 /* 2962 * Allocate hardware transmit queues: one queue for 2963 * beacon frames and one data queue for each QoS 2964 * priority. Note that hw functions handle resetting 2965 * these queues at the needed time. 2966 */ 2967 ret = ath5k_beaconq_setup(ah); 2968 if (ret < 0) { 2969 ATH5K_ERR(ah, "can't setup a beacon xmit queue\n"); 2970 goto err_desc; 2971 } 2972 ah->bhalq = ret; 2973 ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0); 2974 if (IS_ERR(ah->cabq)) { 2975 ATH5K_ERR(ah, "can't setup cab queue\n"); 2976 ret = PTR_ERR(ah->cabq); 2977 goto err_bhal; 2978 } 2979 2980 /* 5211 and 5212 usually support 10 queues but we better rely on the 2981 * capability information */ 2982 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) { 2983 /* This order matches mac80211's queue priority, so we can 2984 * directly use the mac80211 queue number without any mapping */ 2985 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO); 2986 if (IS_ERR(txq)) { 2987 ATH5K_ERR(ah, "can't setup xmit queue\n"); 2988 ret = PTR_ERR(txq); 2989 goto err_queues; 2990 } 2991 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI); 2992 if (IS_ERR(txq)) { 2993 ATH5K_ERR(ah, "can't setup xmit queue\n"); 2994 ret = PTR_ERR(txq); 2995 goto err_queues; 2996 } 2997 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); 2998 if (IS_ERR(txq)) { 2999 ATH5K_ERR(ah, "can't setup xmit queue\n"); 3000 ret = PTR_ERR(txq); 3001 goto err_queues; 3002 } 3003 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); 3004 if (IS_ERR(txq)) { 3005 ATH5K_ERR(ah, "can't setup xmit queue\n"); 3006 ret = PTR_ERR(txq); 3007 goto err_queues; 3008 } 3009 hw->queues = 4; 3010 } else { 3011 /* older hardware (5210) can only support one data queue */ 3012 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); 3013 if (IS_ERR(txq)) { 3014 ATH5K_ERR(ah, "can't setup xmit queue\n"); 3015 ret = PTR_ERR(txq); 3016 goto err_queues; 3017 } 3018 hw->queues = 1; 3019 } 3020 3021 tasklet_init(&ah->rxtq, ath5k_tasklet_rx, (unsigned long)ah); 3022 tasklet_init(&ah->txtq, ath5k_tasklet_tx, (unsigned long)ah); 3023 tasklet_init(&ah->beacontq, ath5k_tasklet_beacon, (unsigned long)ah); 3024 tasklet_init(&ah->ani_tasklet, ath5k_tasklet_ani, (unsigned long)ah); 3025 3026 INIT_WORK(&ah->reset_work, ath5k_reset_work); 3027 INIT_WORK(&ah->calib_work, ath5k_calibrate_work); 3028 INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work); 3029 3030 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac); 3031 if (ret) { 3032 ATH5K_ERR(ah, "unable to read address from EEPROM\n"); 3033 goto err_queues; 3034 } 3035 3036 SET_IEEE80211_PERM_ADDR(hw, mac); 3037 /* All MAC address bits matter for ACKs */ 3038 ath5k_update_bssid_mask_and_opmode(ah, NULL); 3039 3040 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain; 3041 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier); 3042 if (ret) { 3043 ATH5K_ERR(ah, "can't initialize regulatory system\n"); 3044 goto err_queues; 3045 } 3046 3047 ret = ieee80211_register_hw(hw); 3048 if (ret) { 3049 ATH5K_ERR(ah, "can't register ieee80211 hw\n"); 3050 goto err_queues; 3051 } 3052 3053 if (!ath_is_world_regd(regulatory)) 3054 regulatory_hint(hw->wiphy, regulatory->alpha2); 3055 3056 ath5k_init_leds(ah); 3057 3058 ath5k_sysfs_register(ah); 3059 3060 return 0; 3061 err_queues: 3062 ath5k_txq_release(ah); 3063 err_bhal: 3064 ath5k_hw_release_tx_queue(ah, ah->bhalq); 3065 err_desc: 3066 ath5k_desc_free(ah); 3067 err: 3068 return ret; 3069 } 3070 3071 void 3072 ath5k_deinit_ah(struct ath5k_hw *ah) 3073 { 3074 struct ieee80211_hw *hw = ah->hw; 3075 3076 /* 3077 * NB: the order of these is important: 3078 * o call the 802.11 layer before detaching ath5k_hw to 3079 * ensure callbacks into the driver to delete global 3080 * key cache entries can be handled 3081 * o reclaim the tx queue data structures after calling 3082 * the 802.11 layer as we'll get called back to reclaim 3083 * node state and potentially want to use them 3084 * o to cleanup the tx queues the hal is called, so detach 3085 * it last 3086 * XXX: ??? detach ath5k_hw ??? 3087 * Other than that, it's straightforward... 3088 */ 3089 ieee80211_unregister_hw(hw); 3090 ath5k_desc_free(ah); 3091 ath5k_txq_release(ah); 3092 ath5k_hw_release_tx_queue(ah, ah->bhalq); 3093 ath5k_unregister_leds(ah); 3094 3095 ath5k_sysfs_unregister(ah); 3096 /* 3097 * NB: can't reclaim these until after ieee80211_ifdetach 3098 * returns because we'll get called back to reclaim node 3099 * state and potentially want to use them. 3100 */ 3101 ath5k_hw_deinit(ah); 3102 free_irq(ah->irq, ah); 3103 } 3104 3105 bool 3106 ath5k_any_vif_assoc(struct ath5k_hw *ah) 3107 { 3108 struct ath5k_vif_iter_data iter_data; 3109 iter_data.hw_macaddr = NULL; 3110 iter_data.any_assoc = false; 3111 iter_data.need_set_hw_addr = false; 3112 iter_data.found_active = true; 3113 3114 ieee80211_iterate_active_interfaces_atomic( 3115 ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 3116 ath5k_vif_iter, &iter_data); 3117 return iter_data.any_assoc; 3118 } 3119 3120 void 3121 ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable) 3122 { 3123 struct ath5k_hw *ah = hw->priv; 3124 u32 rfilt; 3125 rfilt = ath5k_hw_get_rx_filter(ah); 3126 if (enable) 3127 rfilt |= AR5K_RX_FILTER_BEACON; 3128 else 3129 rfilt &= ~AR5K_RX_FILTER_BEACON; 3130 ath5k_hw_set_rx_filter(ah, rfilt); 3131 ah->filter_flags = rfilt; 3132 } 3133 3134 void _ath5k_printk(const struct ath5k_hw *ah, const char *level, 3135 const char *fmt, ...) 3136 { 3137 struct va_format vaf; 3138 va_list args; 3139 3140 va_start(args, fmt); 3141 3142 vaf.fmt = fmt; 3143 vaf.va = &args; 3144 3145 if (ah && ah->hw) 3146 printk("%s" pr_fmt("%s: %pV"), 3147 level, wiphy_name(ah->hw->wiphy), &vaf); 3148 else 3149 printk("%s" pr_fmt("%pV"), level, &vaf); 3150 3151 va_end(args); 3152 } 3153