1 /*- 2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 3 * Copyright (c) 2004-2005 Atheros Communications, Inc. 4 * Copyright (c) 2006 Devicescape Software, Inc. 5 * Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com> 6 * Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu> 7 * 8 * All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer, 15 * without modification. 16 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 17 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 18 * redistribution must be conditioned upon including a substantially 19 * similar Disclaimer requirement for further binary redistribution. 20 * 3. Neither the names of the above-listed copyright holders nor the names 21 * of any contributors may be used to endorse or promote products derived 22 * from this software without specific prior written permission. 23 * 24 * Alternatively, this software may be distributed under the terms of the 25 * GNU General Public License ("GPL") version 2 as published by the Free 26 * Software Foundation. 27 * 28 * NO WARRANTY 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 32 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 33 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 34 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 35 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 36 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 37 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 38 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 39 * THE POSSIBILITY OF SUCH DAMAGES. 40 * 41 */ 42 43 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 44 45 #include <linux/module.h> 46 #include <linux/delay.h> 47 #include <linux/dma-mapping.h> 48 #include <linux/hardirq.h> 49 #include <linux/if.h> 50 #include <linux/io.h> 51 #include <linux/netdevice.h> 52 #include <linux/cache.h> 53 #include <linux/ethtool.h> 54 #include <linux/uaccess.h> 55 #include <linux/slab.h> 56 #include <linux/etherdevice.h> 57 #include <linux/nl80211.h> 58 59 #include <net/cfg80211.h> 60 #include <net/ieee80211_radiotap.h> 61 62 #include <asm/unaligned.h> 63 64 #include <net/mac80211.h> 65 #include "base.h" 66 #include "reg.h" 67 #include "debug.h" 68 #include "ani.h" 69 #include "ath5k.h" 70 #include "../regd.h" 71 72 #define CREATE_TRACE_POINTS 73 #include "trace.h" 74 75 bool ath5k_modparam_nohwcrypt; 76 module_param_named(nohwcrypt, ath5k_modparam_nohwcrypt, bool, 0444); 77 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption."); 78 79 static bool modparam_fastchanswitch; 80 module_param_named(fastchanswitch, modparam_fastchanswitch, bool, 0444); 81 MODULE_PARM_DESC(fastchanswitch, "Enable fast channel switching for AR2413/AR5413 radios."); 82 83 static bool ath5k_modparam_no_hw_rfkill_switch; 84 module_param_named(no_hw_rfkill_switch, ath5k_modparam_no_hw_rfkill_switch, 85 bool, 0444); 86 MODULE_PARM_DESC(no_hw_rfkill_switch, "Ignore the GPIO RFKill switch state"); 87 88 89 /* Module info */ 90 MODULE_AUTHOR("Jiri Slaby"); 91 MODULE_AUTHOR("Nick Kossifidis"); 92 MODULE_DESCRIPTION("Support for 5xxx series of Atheros 802.11 wireless LAN cards."); 93 MODULE_LICENSE("Dual BSD/GPL"); 94 95 static int ath5k_init(struct ieee80211_hw *hw); 96 static int ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan, 97 bool skip_pcu); 98 99 /* Known SREVs */ 100 static const struct ath5k_srev_name srev_names[] = { 101 #ifdef CONFIG_ATH5K_AHB 102 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R2 }, 103 { "5312", AR5K_VERSION_MAC, AR5K_SREV_AR5312_R7 }, 104 { "2313", AR5K_VERSION_MAC, AR5K_SREV_AR2313_R8 }, 105 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R6 }, 106 { "2315", AR5K_VERSION_MAC, AR5K_SREV_AR2315_R7 }, 107 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R1 }, 108 { "2317", AR5K_VERSION_MAC, AR5K_SREV_AR2317_R2 }, 109 #else 110 { "5210", AR5K_VERSION_MAC, AR5K_SREV_AR5210 }, 111 { "5311", AR5K_VERSION_MAC, AR5K_SREV_AR5311 }, 112 { "5311A", AR5K_VERSION_MAC, AR5K_SREV_AR5311A }, 113 { "5311B", AR5K_VERSION_MAC, AR5K_SREV_AR5311B }, 114 { "5211", AR5K_VERSION_MAC, AR5K_SREV_AR5211 }, 115 { "5212", AR5K_VERSION_MAC, AR5K_SREV_AR5212 }, 116 { "5213", AR5K_VERSION_MAC, AR5K_SREV_AR5213 }, 117 { "5213A", AR5K_VERSION_MAC, AR5K_SREV_AR5213A }, 118 { "2413", AR5K_VERSION_MAC, AR5K_SREV_AR2413 }, 119 { "2414", AR5K_VERSION_MAC, AR5K_SREV_AR2414 }, 120 { "5424", AR5K_VERSION_MAC, AR5K_SREV_AR5424 }, 121 { "5413", AR5K_VERSION_MAC, AR5K_SREV_AR5413 }, 122 { "5414", AR5K_VERSION_MAC, AR5K_SREV_AR5414 }, 123 { "2415", AR5K_VERSION_MAC, AR5K_SREV_AR2415 }, 124 { "5416", AR5K_VERSION_MAC, AR5K_SREV_AR5416 }, 125 { "5418", AR5K_VERSION_MAC, AR5K_SREV_AR5418 }, 126 { "2425", AR5K_VERSION_MAC, AR5K_SREV_AR2425 }, 127 { "2417", AR5K_VERSION_MAC, AR5K_SREV_AR2417 }, 128 #endif 129 { "xxxxx", AR5K_VERSION_MAC, AR5K_SREV_UNKNOWN }, 130 { "5110", AR5K_VERSION_RAD, AR5K_SREV_RAD_5110 }, 131 { "5111", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111 }, 132 { "5111A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5111A }, 133 { "2111", AR5K_VERSION_RAD, AR5K_SREV_RAD_2111 }, 134 { "5112", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112 }, 135 { "5112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112A }, 136 { "5112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_5112B }, 137 { "2112", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112 }, 138 { "2112A", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112A }, 139 { "2112B", AR5K_VERSION_RAD, AR5K_SREV_RAD_2112B }, 140 { "2413", AR5K_VERSION_RAD, AR5K_SREV_RAD_2413 }, 141 { "5413", AR5K_VERSION_RAD, AR5K_SREV_RAD_5413 }, 142 { "5424", AR5K_VERSION_RAD, AR5K_SREV_RAD_5424 }, 143 { "5133", AR5K_VERSION_RAD, AR5K_SREV_RAD_5133 }, 144 #ifdef CONFIG_ATH5K_AHB 145 { "2316", AR5K_VERSION_RAD, AR5K_SREV_RAD_2316 }, 146 { "2317", AR5K_VERSION_RAD, AR5K_SREV_RAD_2317 }, 147 #endif 148 { "xxxxx", AR5K_VERSION_RAD, AR5K_SREV_UNKNOWN }, 149 }; 150 151 static const struct ieee80211_rate ath5k_rates[] = { 152 { .bitrate = 10, 153 .hw_value = ATH5K_RATE_CODE_1M, }, 154 { .bitrate = 20, 155 .hw_value = ATH5K_RATE_CODE_2M, 156 .hw_value_short = ATH5K_RATE_CODE_2M | AR5K_SET_SHORT_PREAMBLE, 157 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 158 { .bitrate = 55, 159 .hw_value = ATH5K_RATE_CODE_5_5M, 160 .hw_value_short = ATH5K_RATE_CODE_5_5M | AR5K_SET_SHORT_PREAMBLE, 161 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 162 { .bitrate = 110, 163 .hw_value = ATH5K_RATE_CODE_11M, 164 .hw_value_short = ATH5K_RATE_CODE_11M | AR5K_SET_SHORT_PREAMBLE, 165 .flags = IEEE80211_RATE_SHORT_PREAMBLE }, 166 { .bitrate = 60, 167 .hw_value = ATH5K_RATE_CODE_6M, 168 .flags = IEEE80211_RATE_SUPPORTS_5MHZ | 169 IEEE80211_RATE_SUPPORTS_10MHZ }, 170 { .bitrate = 90, 171 .hw_value = ATH5K_RATE_CODE_9M, 172 .flags = IEEE80211_RATE_SUPPORTS_5MHZ | 173 IEEE80211_RATE_SUPPORTS_10MHZ }, 174 { .bitrate = 120, 175 .hw_value = ATH5K_RATE_CODE_12M, 176 .flags = IEEE80211_RATE_SUPPORTS_5MHZ | 177 IEEE80211_RATE_SUPPORTS_10MHZ }, 178 { .bitrate = 180, 179 .hw_value = ATH5K_RATE_CODE_18M, 180 .flags = IEEE80211_RATE_SUPPORTS_5MHZ | 181 IEEE80211_RATE_SUPPORTS_10MHZ }, 182 { .bitrate = 240, 183 .hw_value = ATH5K_RATE_CODE_24M, 184 .flags = IEEE80211_RATE_SUPPORTS_5MHZ | 185 IEEE80211_RATE_SUPPORTS_10MHZ }, 186 { .bitrate = 360, 187 .hw_value = ATH5K_RATE_CODE_36M, 188 .flags = IEEE80211_RATE_SUPPORTS_5MHZ | 189 IEEE80211_RATE_SUPPORTS_10MHZ }, 190 { .bitrate = 480, 191 .hw_value = ATH5K_RATE_CODE_48M, 192 .flags = IEEE80211_RATE_SUPPORTS_5MHZ | 193 IEEE80211_RATE_SUPPORTS_10MHZ }, 194 { .bitrate = 540, 195 .hw_value = ATH5K_RATE_CODE_54M, 196 .flags = IEEE80211_RATE_SUPPORTS_5MHZ | 197 IEEE80211_RATE_SUPPORTS_10MHZ }, 198 }; 199 200 static inline u64 ath5k_extend_tsf(struct ath5k_hw *ah, u32 rstamp) 201 { 202 u64 tsf = ath5k_hw_get_tsf64(ah); 203 204 if ((tsf & 0x7fff) < rstamp) 205 tsf -= 0x8000; 206 207 return (tsf & ~0x7fff) | rstamp; 208 } 209 210 const char * 211 ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val) 212 { 213 const char *name = "xxxxx"; 214 unsigned int i; 215 216 for (i = 0; i < ARRAY_SIZE(srev_names); i++) { 217 if (srev_names[i].sr_type != type) 218 continue; 219 220 if ((val & 0xf0) == srev_names[i].sr_val) 221 name = srev_names[i].sr_name; 222 223 if ((val & 0xff) == srev_names[i].sr_val) { 224 name = srev_names[i].sr_name; 225 break; 226 } 227 } 228 229 return name; 230 } 231 static unsigned int ath5k_ioread32(void *hw_priv, u32 reg_offset) 232 { 233 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; 234 return ath5k_hw_reg_read(ah, reg_offset); 235 } 236 237 static void ath5k_iowrite32(void *hw_priv, u32 val, u32 reg_offset) 238 { 239 struct ath5k_hw *ah = (struct ath5k_hw *) hw_priv; 240 ath5k_hw_reg_write(ah, val, reg_offset); 241 } 242 243 static const struct ath_ops ath5k_common_ops = { 244 .read = ath5k_ioread32, 245 .write = ath5k_iowrite32, 246 }; 247 248 /***********************\ 249 * Driver Initialization * 250 \***********************/ 251 252 static void ath5k_reg_notifier(struct wiphy *wiphy, 253 struct regulatory_request *request) 254 { 255 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 256 struct ath5k_hw *ah = hw->priv; 257 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 258 259 ath_reg_notifier_apply(wiphy, request, regulatory); 260 } 261 262 /********************\ 263 * Channel/mode setup * 264 \********************/ 265 266 /* 267 * Returns true for the channel numbers used. 268 */ 269 #ifdef CONFIG_ATH5K_TEST_CHANNELS 270 static bool ath5k_is_standard_channel(short chan, enum nl80211_band band) 271 { 272 return true; 273 } 274 275 #else 276 static bool ath5k_is_standard_channel(short chan, enum nl80211_band band) 277 { 278 if (band == NL80211_BAND_2GHZ && chan <= 14) 279 return true; 280 281 return /* UNII 1,2 */ 282 (((chan & 3) == 0 && chan >= 36 && chan <= 64) || 283 /* midband */ 284 ((chan & 3) == 0 && chan >= 100 && chan <= 140) || 285 /* UNII-3 */ 286 ((chan & 3) == 1 && chan >= 149 && chan <= 165) || 287 /* 802.11j 5.030-5.080 GHz (20MHz) */ 288 (chan == 8 || chan == 12 || chan == 16) || 289 /* 802.11j 4.9GHz (20MHz) */ 290 (chan == 184 || chan == 188 || chan == 192 || chan == 196)); 291 } 292 #endif 293 294 static unsigned int 295 ath5k_setup_channels(struct ath5k_hw *ah, struct ieee80211_channel *channels, 296 unsigned int mode, unsigned int max) 297 { 298 unsigned int count, size, freq, ch; 299 enum nl80211_band band; 300 301 switch (mode) { 302 case AR5K_MODE_11A: 303 /* 1..220, but 2GHz frequencies are filtered by check_channel */ 304 size = 220; 305 band = NL80211_BAND_5GHZ; 306 break; 307 case AR5K_MODE_11B: 308 case AR5K_MODE_11G: 309 size = 26; 310 band = NL80211_BAND_2GHZ; 311 break; 312 default: 313 ATH5K_WARN(ah, "bad mode, not copying channels\n"); 314 return 0; 315 } 316 317 count = 0; 318 for (ch = 1; ch <= size && count < max; ch++) { 319 freq = ieee80211_channel_to_frequency(ch, band); 320 321 if (freq == 0) /* mapping failed - not a standard channel */ 322 continue; 323 324 /* Write channel info, needed for ath5k_channel_ok() */ 325 channels[count].center_freq = freq; 326 channels[count].band = band; 327 channels[count].hw_value = mode; 328 329 /* Check if channel is supported by the chipset */ 330 if (!ath5k_channel_ok(ah, &channels[count])) 331 continue; 332 333 if (!ath5k_is_standard_channel(ch, band)) 334 continue; 335 336 count++; 337 } 338 339 return count; 340 } 341 342 static void 343 ath5k_setup_rate_idx(struct ath5k_hw *ah, struct ieee80211_supported_band *b) 344 { 345 u8 i; 346 347 for (i = 0; i < AR5K_MAX_RATES; i++) 348 ah->rate_idx[b->band][i] = -1; 349 350 for (i = 0; i < b->n_bitrates; i++) { 351 ah->rate_idx[b->band][b->bitrates[i].hw_value] = i; 352 if (b->bitrates[i].hw_value_short) 353 ah->rate_idx[b->band][b->bitrates[i].hw_value_short] = i; 354 } 355 } 356 357 static int 358 ath5k_setup_bands(struct ieee80211_hw *hw) 359 { 360 struct ath5k_hw *ah = hw->priv; 361 struct ieee80211_supported_band *sband; 362 int max_c, count_c = 0; 363 int i; 364 365 BUILD_BUG_ON(ARRAY_SIZE(ah->sbands) < NUM_NL80211_BANDS); 366 max_c = ARRAY_SIZE(ah->channels); 367 368 /* 2GHz band */ 369 sband = &ah->sbands[NL80211_BAND_2GHZ]; 370 sband->band = NL80211_BAND_2GHZ; 371 sband->bitrates = &ah->rates[NL80211_BAND_2GHZ][0]; 372 373 if (test_bit(AR5K_MODE_11G, ah->ah_capabilities.cap_mode)) { 374 /* G mode */ 375 memcpy(sband->bitrates, &ath5k_rates[0], 376 sizeof(struct ieee80211_rate) * 12); 377 sband->n_bitrates = 12; 378 379 sband->channels = ah->channels; 380 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 381 AR5K_MODE_11G, max_c); 382 383 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 384 count_c = sband->n_channels; 385 max_c -= count_c; 386 } else if (test_bit(AR5K_MODE_11B, ah->ah_capabilities.cap_mode)) { 387 /* B mode */ 388 memcpy(sband->bitrates, &ath5k_rates[0], 389 sizeof(struct ieee80211_rate) * 4); 390 sband->n_bitrates = 4; 391 392 /* 5211 only supports B rates and uses 4bit rate codes 393 * (e.g normally we have 0x1B for 1M, but on 5211 we have 0x0B) 394 * fix them up here: 395 */ 396 if (ah->ah_version == AR5K_AR5211) { 397 for (i = 0; i < 4; i++) { 398 sband->bitrates[i].hw_value = 399 sband->bitrates[i].hw_value & 0xF; 400 sband->bitrates[i].hw_value_short = 401 sband->bitrates[i].hw_value_short & 0xF; 402 } 403 } 404 405 sband->channels = ah->channels; 406 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 407 AR5K_MODE_11B, max_c); 408 409 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; 410 count_c = sband->n_channels; 411 max_c -= count_c; 412 } 413 ath5k_setup_rate_idx(ah, sband); 414 415 /* 5GHz band, A mode */ 416 if (test_bit(AR5K_MODE_11A, ah->ah_capabilities.cap_mode)) { 417 sband = &ah->sbands[NL80211_BAND_5GHZ]; 418 sband->band = NL80211_BAND_5GHZ; 419 sband->bitrates = &ah->rates[NL80211_BAND_5GHZ][0]; 420 421 memcpy(sband->bitrates, &ath5k_rates[4], 422 sizeof(struct ieee80211_rate) * 8); 423 sband->n_bitrates = 8; 424 425 sband->channels = &ah->channels[count_c]; 426 sband->n_channels = ath5k_setup_channels(ah, sband->channels, 427 AR5K_MODE_11A, max_c); 428 429 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband; 430 } 431 ath5k_setup_rate_idx(ah, sband); 432 433 ath5k_debug_dump_bands(ah); 434 435 return 0; 436 } 437 438 /* 439 * Set/change channels. We always reset the chip. 440 * To accomplish this we must first cleanup any pending DMA, 441 * then restart stuff after a la ath5k_init. 442 * 443 * Called with ah->lock. 444 */ 445 int 446 ath5k_chan_set(struct ath5k_hw *ah, struct cfg80211_chan_def *chandef) 447 { 448 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 449 "channel set, resetting (%u -> %u MHz)\n", 450 ah->curchan->center_freq, chandef->chan->center_freq); 451 452 switch (chandef->width) { 453 case NL80211_CHAN_WIDTH_20: 454 case NL80211_CHAN_WIDTH_20_NOHT: 455 ah->ah_bwmode = AR5K_BWMODE_DEFAULT; 456 break; 457 case NL80211_CHAN_WIDTH_5: 458 ah->ah_bwmode = AR5K_BWMODE_5MHZ; 459 break; 460 case NL80211_CHAN_WIDTH_10: 461 ah->ah_bwmode = AR5K_BWMODE_10MHZ; 462 break; 463 default: 464 WARN_ON(1); 465 return -EINVAL; 466 } 467 468 /* 469 * To switch channels clear any pending DMA operations; 470 * wait long enough for the RX fifo to drain, reset the 471 * hardware at the new frequency, and then re-enable 472 * the relevant bits of the h/w. 473 */ 474 return ath5k_reset(ah, chandef->chan, true); 475 } 476 477 void ath5k_vif_iter(void *data, u8 *mac, struct ieee80211_vif *vif) 478 { 479 struct ath5k_vif_iter_data *iter_data = data; 480 int i; 481 struct ath5k_vif *avf = (void *)vif->drv_priv; 482 483 if (iter_data->hw_macaddr) 484 for (i = 0; i < ETH_ALEN; i++) 485 iter_data->mask[i] &= 486 ~(iter_data->hw_macaddr[i] ^ mac[i]); 487 488 if (!iter_data->found_active) { 489 iter_data->found_active = true; 490 memcpy(iter_data->active_mac, mac, ETH_ALEN); 491 } 492 493 if (iter_data->need_set_hw_addr && iter_data->hw_macaddr) 494 if (ether_addr_equal(iter_data->hw_macaddr, mac)) 495 iter_data->need_set_hw_addr = false; 496 497 if (!iter_data->any_assoc) { 498 if (avf->assoc) 499 iter_data->any_assoc = true; 500 } 501 502 /* Calculate combined mode - when APs are active, operate in AP mode. 503 * Otherwise use the mode of the new interface. This can currently 504 * only deal with combinations of APs and STAs. Only one ad-hoc 505 * interfaces is allowed. 506 */ 507 if (avf->opmode == NL80211_IFTYPE_AP) 508 iter_data->opmode = NL80211_IFTYPE_AP; 509 else { 510 if (avf->opmode == NL80211_IFTYPE_STATION) 511 iter_data->n_stas++; 512 if (iter_data->opmode == NL80211_IFTYPE_UNSPECIFIED) 513 iter_data->opmode = avf->opmode; 514 } 515 } 516 517 void 518 ath5k_update_bssid_mask_and_opmode(struct ath5k_hw *ah, 519 struct ieee80211_vif *vif) 520 { 521 struct ath_common *common = ath5k_hw_common(ah); 522 struct ath5k_vif_iter_data iter_data; 523 u32 rfilt; 524 525 /* 526 * Use the hardware MAC address as reference, the hardware uses it 527 * together with the BSSID mask when matching addresses. 528 */ 529 iter_data.hw_macaddr = common->macaddr; 530 eth_broadcast_addr(iter_data.mask); 531 iter_data.found_active = false; 532 iter_data.need_set_hw_addr = true; 533 iter_data.opmode = NL80211_IFTYPE_UNSPECIFIED; 534 iter_data.n_stas = 0; 535 536 if (vif) 537 ath5k_vif_iter(&iter_data, vif->addr, vif); 538 539 /* Get list of all active MAC addresses */ 540 ieee80211_iterate_active_interfaces_atomic( 541 ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 542 ath5k_vif_iter, &iter_data); 543 memcpy(ah->bssidmask, iter_data.mask, ETH_ALEN); 544 545 ah->opmode = iter_data.opmode; 546 if (ah->opmode == NL80211_IFTYPE_UNSPECIFIED) 547 /* Nothing active, default to station mode */ 548 ah->opmode = NL80211_IFTYPE_STATION; 549 550 ath5k_hw_set_opmode(ah, ah->opmode); 551 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "mode setup opmode %d (%s)\n", 552 ah->opmode, ath_opmode_to_string(ah->opmode)); 553 554 if (iter_data.need_set_hw_addr && iter_data.found_active) 555 ath5k_hw_set_lladdr(ah, iter_data.active_mac); 556 557 if (ath5k_hw_hasbssidmask(ah)) 558 ath5k_hw_set_bssid_mask(ah, ah->bssidmask); 559 560 /* Set up RX Filter */ 561 if (iter_data.n_stas > 1) { 562 /* If you have multiple STA interfaces connected to 563 * different APs, ARPs are not received (most of the time?) 564 * Enabling PROMISC appears to fix that problem. 565 */ 566 ah->filter_flags |= AR5K_RX_FILTER_PROM; 567 } 568 569 rfilt = ah->filter_flags; 570 ath5k_hw_set_rx_filter(ah, rfilt); 571 ATH5K_DBG(ah, ATH5K_DEBUG_MODE, "RX filter 0x%x\n", rfilt); 572 } 573 574 static inline int 575 ath5k_hw_to_driver_rix(struct ath5k_hw *ah, int hw_rix) 576 { 577 int rix; 578 579 /* return base rate on errors */ 580 if (WARN(hw_rix < 0 || hw_rix >= AR5K_MAX_RATES, 581 "hw_rix out of bounds: %x\n", hw_rix)) 582 return 0; 583 584 rix = ah->rate_idx[ah->curchan->band][hw_rix]; 585 if (WARN(rix < 0, "invalid hw_rix: %x\n", hw_rix)) 586 rix = 0; 587 588 return rix; 589 } 590 591 /***************\ 592 * Buffers setup * 593 \***************/ 594 595 static 596 struct sk_buff *ath5k_rx_skb_alloc(struct ath5k_hw *ah, dma_addr_t *skb_addr) 597 { 598 struct ath_common *common = ath5k_hw_common(ah); 599 struct sk_buff *skb; 600 601 /* 602 * Allocate buffer with headroom_needed space for the 603 * fake physical layer header at the start. 604 */ 605 skb = ath_rxbuf_alloc(common, 606 common->rx_bufsize, 607 GFP_ATOMIC); 608 609 if (!skb) { 610 ATH5K_ERR(ah, "can't alloc skbuff of size %u\n", 611 common->rx_bufsize); 612 return NULL; 613 } 614 615 *skb_addr = dma_map_single(ah->dev, 616 skb->data, common->rx_bufsize, 617 DMA_FROM_DEVICE); 618 619 if (unlikely(dma_mapping_error(ah->dev, *skb_addr))) { 620 ATH5K_ERR(ah, "%s: DMA mapping failed\n", __func__); 621 dev_kfree_skb(skb); 622 return NULL; 623 } 624 return skb; 625 } 626 627 static int 628 ath5k_rxbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf) 629 { 630 struct sk_buff *skb = bf->skb; 631 struct ath5k_desc *ds; 632 int ret; 633 634 if (!skb) { 635 skb = ath5k_rx_skb_alloc(ah, &bf->skbaddr); 636 if (!skb) 637 return -ENOMEM; 638 bf->skb = skb; 639 } 640 641 /* 642 * Setup descriptors. For receive we always terminate 643 * the descriptor list with a self-linked entry so we'll 644 * not get overrun under high load (as can happen with a 645 * 5212 when ANI processing enables PHY error frames). 646 * 647 * To ensure the last descriptor is self-linked we create 648 * each descriptor as self-linked and add it to the end. As 649 * each additional descriptor is added the previous self-linked 650 * entry is "fixed" naturally. This should be safe even 651 * if DMA is happening. When processing RX interrupts we 652 * never remove/process the last, self-linked, entry on the 653 * descriptor list. This ensures the hardware always has 654 * someplace to write a new frame. 655 */ 656 ds = bf->desc; 657 ds->ds_link = bf->daddr; /* link to self */ 658 ds->ds_data = bf->skbaddr; 659 ret = ath5k_hw_setup_rx_desc(ah, ds, ah->common.rx_bufsize, 0); 660 if (ret) { 661 ATH5K_ERR(ah, "%s: could not setup RX desc\n", __func__); 662 return ret; 663 } 664 665 if (ah->rxlink != NULL) 666 *ah->rxlink = bf->daddr; 667 ah->rxlink = &ds->ds_link; 668 return 0; 669 } 670 671 static enum ath5k_pkt_type get_hw_packet_type(struct sk_buff *skb) 672 { 673 struct ieee80211_hdr *hdr; 674 enum ath5k_pkt_type htype; 675 __le16 fc; 676 677 hdr = (struct ieee80211_hdr *)skb->data; 678 fc = hdr->frame_control; 679 680 if (ieee80211_is_beacon(fc)) 681 htype = AR5K_PKT_TYPE_BEACON; 682 else if (ieee80211_is_probe_resp(fc)) 683 htype = AR5K_PKT_TYPE_PROBE_RESP; 684 else if (ieee80211_is_atim(fc)) 685 htype = AR5K_PKT_TYPE_ATIM; 686 else if (ieee80211_is_pspoll(fc)) 687 htype = AR5K_PKT_TYPE_PSPOLL; 688 else 689 htype = AR5K_PKT_TYPE_NORMAL; 690 691 return htype; 692 } 693 694 static struct ieee80211_rate * 695 ath5k_get_rate(const struct ieee80211_hw *hw, 696 const struct ieee80211_tx_info *info, 697 struct ath5k_buf *bf, int idx) 698 { 699 /* 700 * convert a ieee80211_tx_rate RC-table entry to 701 * the respective ieee80211_rate struct 702 */ 703 if (bf->rates[idx].idx < 0) { 704 return NULL; 705 } 706 707 return &hw->wiphy->bands[info->band]->bitrates[ bf->rates[idx].idx ]; 708 } 709 710 static u16 711 ath5k_get_rate_hw_value(const struct ieee80211_hw *hw, 712 const struct ieee80211_tx_info *info, 713 struct ath5k_buf *bf, int idx) 714 { 715 struct ieee80211_rate *rate; 716 u16 hw_rate; 717 u8 rc_flags; 718 719 rate = ath5k_get_rate(hw, info, bf, idx); 720 if (!rate) 721 return 0; 722 723 rc_flags = bf->rates[idx].flags; 724 hw_rate = (rc_flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE) ? 725 rate->hw_value_short : rate->hw_value; 726 727 return hw_rate; 728 } 729 730 static bool ath5k_merge_ratetbl(struct ieee80211_sta *sta, 731 struct ath5k_buf *bf, 732 struct ieee80211_tx_info *tx_info) 733 { 734 struct ieee80211_sta_rates *ratetbl; 735 u8 i; 736 737 if (!sta) 738 return false; 739 740 ratetbl = rcu_dereference(sta->rates); 741 if (!ratetbl) 742 return false; 743 744 if (tx_info->control.rates[0].idx < 0 || 745 tx_info->control.rates[0].count == 0) 746 { 747 i = 0; 748 } else { 749 bf->rates[0] = tx_info->control.rates[0]; 750 i = 1; 751 } 752 753 for ( ; i < IEEE80211_TX_MAX_RATES; i++) { 754 bf->rates[i].idx = ratetbl->rate[i].idx; 755 bf->rates[i].flags = ratetbl->rate[i].flags; 756 if (tx_info->control.use_rts) 757 bf->rates[i].count = ratetbl->rate[i].count_rts; 758 else if (tx_info->control.use_cts_prot) 759 bf->rates[i].count = ratetbl->rate[i].count_cts; 760 else 761 bf->rates[i].count = ratetbl->rate[i].count; 762 } 763 764 return true; 765 } 766 767 static int 768 ath5k_txbuf_setup(struct ath5k_hw *ah, struct ath5k_buf *bf, 769 struct ath5k_txq *txq, int padsize, 770 struct ieee80211_tx_control *control) 771 { 772 struct ath5k_desc *ds = bf->desc; 773 struct sk_buff *skb = bf->skb; 774 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 775 unsigned int pktlen, flags, keyidx = AR5K_TXKEYIX_INVALID; 776 struct ieee80211_rate *rate; 777 struct ieee80211_sta *sta; 778 unsigned int mrr_rate[3], mrr_tries[3]; 779 int i, ret; 780 u16 hw_rate; 781 u16 cts_rate = 0; 782 u16 duration = 0; 783 u8 rc_flags; 784 785 flags = AR5K_TXDESC_INTREQ | AR5K_TXDESC_CLRDMASK; 786 787 /* XXX endianness */ 788 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len, 789 DMA_TO_DEVICE); 790 791 if (dma_mapping_error(ah->dev, bf->skbaddr)) 792 return -ENOSPC; 793 794 if (control) 795 sta = control->sta; 796 else 797 sta = NULL; 798 799 if (!ath5k_merge_ratetbl(sta, bf, info)) { 800 ieee80211_get_tx_rates(info->control.vif, 801 sta, skb, bf->rates, 802 ARRAY_SIZE(bf->rates)); 803 } 804 805 rate = ath5k_get_rate(ah->hw, info, bf, 0); 806 807 if (!rate) { 808 ret = -EINVAL; 809 goto err_unmap; 810 } 811 812 if (info->flags & IEEE80211_TX_CTL_NO_ACK) 813 flags |= AR5K_TXDESC_NOACK; 814 815 rc_flags = bf->rates[0].flags; 816 817 hw_rate = ath5k_get_rate_hw_value(ah->hw, info, bf, 0); 818 819 pktlen = skb->len; 820 821 /* FIXME: If we are in g mode and rate is a CCK rate 822 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta 823 * from tx power (value is in dB units already) */ 824 if (info->control.hw_key) { 825 keyidx = info->control.hw_key->hw_key_idx; 826 pktlen += info->control.hw_key->icv_len; 827 } 828 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) { 829 flags |= AR5K_TXDESC_RTSENA; 830 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value; 831 duration = le16_to_cpu(ieee80211_rts_duration(ah->hw, 832 info->control.vif, pktlen, info)); 833 } 834 if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) { 835 flags |= AR5K_TXDESC_CTSENA; 836 cts_rate = ieee80211_get_rts_cts_rate(ah->hw, info)->hw_value; 837 duration = le16_to_cpu(ieee80211_ctstoself_duration(ah->hw, 838 info->control.vif, pktlen, info)); 839 } 840 841 ret = ah->ah_setup_tx_desc(ah, ds, pktlen, 842 ieee80211_get_hdrlen_from_skb(skb), padsize, 843 get_hw_packet_type(skb), 844 (ah->ah_txpower.txp_requested * 2), 845 hw_rate, 846 bf->rates[0].count, keyidx, ah->ah_tx_ant, flags, 847 cts_rate, duration); 848 if (ret) 849 goto err_unmap; 850 851 /* Set up MRR descriptor */ 852 if (ah->ah_capabilities.cap_has_mrr_support) { 853 memset(mrr_rate, 0, sizeof(mrr_rate)); 854 memset(mrr_tries, 0, sizeof(mrr_tries)); 855 856 for (i = 0; i < 3; i++) { 857 858 rate = ath5k_get_rate(ah->hw, info, bf, i); 859 if (!rate) 860 break; 861 862 mrr_rate[i] = ath5k_get_rate_hw_value(ah->hw, info, bf, i); 863 mrr_tries[i] = bf->rates[i].count; 864 } 865 866 ath5k_hw_setup_mrr_tx_desc(ah, ds, 867 mrr_rate[0], mrr_tries[0], 868 mrr_rate[1], mrr_tries[1], 869 mrr_rate[2], mrr_tries[2]); 870 } 871 872 ds->ds_link = 0; 873 ds->ds_data = bf->skbaddr; 874 875 spin_lock_bh(&txq->lock); 876 list_add_tail(&bf->list, &txq->q); 877 txq->txq_len++; 878 if (txq->link == NULL) /* is this first packet? */ 879 ath5k_hw_set_txdp(ah, txq->qnum, bf->daddr); 880 else /* no, so only link it */ 881 *txq->link = bf->daddr; 882 883 txq->link = &ds->ds_link; 884 ath5k_hw_start_tx_dma(ah, txq->qnum); 885 spin_unlock_bh(&txq->lock); 886 887 return 0; 888 err_unmap: 889 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); 890 return ret; 891 } 892 893 /*******************\ 894 * Descriptors setup * 895 \*******************/ 896 897 static int 898 ath5k_desc_alloc(struct ath5k_hw *ah) 899 { 900 struct ath5k_desc *ds; 901 struct ath5k_buf *bf; 902 dma_addr_t da; 903 unsigned int i; 904 int ret; 905 906 /* allocate descriptors */ 907 ah->desc_len = sizeof(struct ath5k_desc) * 908 (ATH_TXBUF + ATH_RXBUF + ATH_BCBUF + 1); 909 910 ah->desc = dma_alloc_coherent(ah->dev, ah->desc_len, 911 &ah->desc_daddr, GFP_KERNEL); 912 if (ah->desc == NULL) { 913 ATH5K_ERR(ah, "can't allocate descriptors\n"); 914 ret = -ENOMEM; 915 goto err; 916 } 917 ds = ah->desc; 918 da = ah->desc_daddr; 919 ATH5K_DBG(ah, ATH5K_DEBUG_ANY, "DMA map: %p (%zu) -> %llx\n", 920 ds, ah->desc_len, (unsigned long long)ah->desc_daddr); 921 922 bf = kcalloc(1 + ATH_TXBUF + ATH_RXBUF + ATH_BCBUF, 923 sizeof(struct ath5k_buf), GFP_KERNEL); 924 if (bf == NULL) { 925 ATH5K_ERR(ah, "can't allocate bufptr\n"); 926 ret = -ENOMEM; 927 goto err_free; 928 } 929 ah->bufptr = bf; 930 931 INIT_LIST_HEAD(&ah->rxbuf); 932 for (i = 0; i < ATH_RXBUF; i++, bf++, ds++, da += sizeof(*ds)) { 933 bf->desc = ds; 934 bf->daddr = da; 935 list_add_tail(&bf->list, &ah->rxbuf); 936 } 937 938 INIT_LIST_HEAD(&ah->txbuf); 939 ah->txbuf_len = ATH_TXBUF; 940 for (i = 0; i < ATH_TXBUF; i++, bf++, ds++, da += sizeof(*ds)) { 941 bf->desc = ds; 942 bf->daddr = da; 943 list_add_tail(&bf->list, &ah->txbuf); 944 } 945 946 /* beacon buffers */ 947 INIT_LIST_HEAD(&ah->bcbuf); 948 for (i = 0; i < ATH_BCBUF; i++, bf++, ds++, da += sizeof(*ds)) { 949 bf->desc = ds; 950 bf->daddr = da; 951 list_add_tail(&bf->list, &ah->bcbuf); 952 } 953 954 return 0; 955 err_free: 956 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr); 957 err: 958 ah->desc = NULL; 959 return ret; 960 } 961 962 void 963 ath5k_txbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf) 964 { 965 BUG_ON(!bf); 966 if (!bf->skb) 967 return; 968 dma_unmap_single(ah->dev, bf->skbaddr, bf->skb->len, 969 DMA_TO_DEVICE); 970 ieee80211_free_txskb(ah->hw, bf->skb); 971 bf->skb = NULL; 972 bf->skbaddr = 0; 973 bf->desc->ds_data = 0; 974 } 975 976 void 977 ath5k_rxbuf_free_skb(struct ath5k_hw *ah, struct ath5k_buf *bf) 978 { 979 struct ath_common *common = ath5k_hw_common(ah); 980 981 BUG_ON(!bf); 982 if (!bf->skb) 983 return; 984 dma_unmap_single(ah->dev, bf->skbaddr, common->rx_bufsize, 985 DMA_FROM_DEVICE); 986 dev_kfree_skb_any(bf->skb); 987 bf->skb = NULL; 988 bf->skbaddr = 0; 989 bf->desc->ds_data = 0; 990 } 991 992 static void 993 ath5k_desc_free(struct ath5k_hw *ah) 994 { 995 struct ath5k_buf *bf; 996 997 list_for_each_entry(bf, &ah->txbuf, list) 998 ath5k_txbuf_free_skb(ah, bf); 999 list_for_each_entry(bf, &ah->rxbuf, list) 1000 ath5k_rxbuf_free_skb(ah, bf); 1001 list_for_each_entry(bf, &ah->bcbuf, list) 1002 ath5k_txbuf_free_skb(ah, bf); 1003 1004 /* Free memory associated with all descriptors */ 1005 dma_free_coherent(ah->dev, ah->desc_len, ah->desc, ah->desc_daddr); 1006 ah->desc = NULL; 1007 ah->desc_daddr = 0; 1008 1009 kfree(ah->bufptr); 1010 ah->bufptr = NULL; 1011 } 1012 1013 1014 /**************\ 1015 * Queues setup * 1016 \**************/ 1017 1018 static struct ath5k_txq * 1019 ath5k_txq_setup(struct ath5k_hw *ah, 1020 int qtype, int subtype) 1021 { 1022 struct ath5k_txq *txq; 1023 struct ath5k_txq_info qi = { 1024 .tqi_subtype = subtype, 1025 /* XXX: default values not correct for B and XR channels, 1026 * but who cares? */ 1027 .tqi_aifs = AR5K_TUNE_AIFS, 1028 .tqi_cw_min = AR5K_TUNE_CWMIN, 1029 .tqi_cw_max = AR5K_TUNE_CWMAX 1030 }; 1031 int qnum; 1032 1033 /* 1034 * Enable interrupts only for EOL and DESC conditions. 1035 * We mark tx descriptors to receive a DESC interrupt 1036 * when a tx queue gets deep; otherwise we wait for the 1037 * EOL to reap descriptors. Note that this is done to 1038 * reduce interrupt load and this only defers reaping 1039 * descriptors, never transmitting frames. Aside from 1040 * reducing interrupts this also permits more concurrency. 1041 * The only potential downside is if the tx queue backs 1042 * up in which case the top half of the kernel may backup 1043 * due to a lack of tx descriptors. 1044 */ 1045 qi.tqi_flags = AR5K_TXQ_FLAG_TXEOLINT_ENABLE | 1046 AR5K_TXQ_FLAG_TXDESCINT_ENABLE; 1047 qnum = ath5k_hw_setup_tx_queue(ah, qtype, &qi); 1048 if (qnum < 0) { 1049 /* 1050 * NB: don't print a message, this happens 1051 * normally on parts with too few tx queues 1052 */ 1053 return ERR_PTR(qnum); 1054 } 1055 txq = &ah->txqs[qnum]; 1056 if (!txq->setup) { 1057 txq->qnum = qnum; 1058 txq->link = NULL; 1059 INIT_LIST_HEAD(&txq->q); 1060 spin_lock_init(&txq->lock); 1061 txq->setup = true; 1062 txq->txq_len = 0; 1063 txq->txq_max = ATH5K_TXQ_LEN_MAX; 1064 txq->txq_poll_mark = false; 1065 txq->txq_stuck = 0; 1066 } 1067 return &ah->txqs[qnum]; 1068 } 1069 1070 static int 1071 ath5k_beaconq_setup(struct ath5k_hw *ah) 1072 { 1073 struct ath5k_txq_info qi = { 1074 /* XXX: default values not correct for B and XR channels, 1075 * but who cares? */ 1076 .tqi_aifs = AR5K_TUNE_AIFS, 1077 .tqi_cw_min = AR5K_TUNE_CWMIN, 1078 .tqi_cw_max = AR5K_TUNE_CWMAX, 1079 /* NB: for dynamic turbo, don't enable any other interrupts */ 1080 .tqi_flags = AR5K_TXQ_FLAG_TXDESCINT_ENABLE 1081 }; 1082 1083 return ath5k_hw_setup_tx_queue(ah, AR5K_TX_QUEUE_BEACON, &qi); 1084 } 1085 1086 static int 1087 ath5k_beaconq_config(struct ath5k_hw *ah) 1088 { 1089 struct ath5k_txq_info qi; 1090 int ret; 1091 1092 ret = ath5k_hw_get_tx_queueprops(ah, ah->bhalq, &qi); 1093 if (ret) 1094 goto err; 1095 1096 if (ah->opmode == NL80211_IFTYPE_AP || 1097 ah->opmode == NL80211_IFTYPE_MESH_POINT) { 1098 /* 1099 * Always burst out beacon and CAB traffic 1100 * (aifs = cwmin = cwmax = 0) 1101 */ 1102 qi.tqi_aifs = 0; 1103 qi.tqi_cw_min = 0; 1104 qi.tqi_cw_max = 0; 1105 } else if (ah->opmode == NL80211_IFTYPE_ADHOC) { 1106 /* 1107 * Adhoc mode; backoff between 0 and (2 * cw_min). 1108 */ 1109 qi.tqi_aifs = 0; 1110 qi.tqi_cw_min = 0; 1111 qi.tqi_cw_max = 2 * AR5K_TUNE_CWMIN; 1112 } 1113 1114 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 1115 "beacon queueprops tqi_aifs:%d tqi_cw_min:%d tqi_cw_max:%d\n", 1116 qi.tqi_aifs, qi.tqi_cw_min, qi.tqi_cw_max); 1117 1118 ret = ath5k_hw_set_tx_queueprops(ah, ah->bhalq, &qi); 1119 if (ret) { 1120 ATH5K_ERR(ah, "%s: unable to update parameters for beacon " 1121 "hardware queue!\n", __func__); 1122 goto err; 1123 } 1124 ret = ath5k_hw_reset_tx_queue(ah, ah->bhalq); /* push to h/w */ 1125 if (ret) 1126 goto err; 1127 1128 /* reconfigure cabq with ready time to 80% of beacon_interval */ 1129 ret = ath5k_hw_get_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); 1130 if (ret) 1131 goto err; 1132 1133 qi.tqi_ready_time = (ah->bintval * 80) / 100; 1134 ret = ath5k_hw_set_tx_queueprops(ah, AR5K_TX_QUEUE_ID_CAB, &qi); 1135 if (ret) 1136 goto err; 1137 1138 ret = ath5k_hw_reset_tx_queue(ah, AR5K_TX_QUEUE_ID_CAB); 1139 err: 1140 return ret; 1141 } 1142 1143 /** 1144 * ath5k_drain_tx_buffs - Empty tx buffers 1145 * 1146 * @ah: The &struct ath5k_hw 1147 * 1148 * Empty tx buffers from all queues in preparation 1149 * of a reset or during shutdown. 1150 * 1151 * NB: this assumes output has been stopped and 1152 * we do not need to block ath5k_tx_tasklet 1153 */ 1154 static void 1155 ath5k_drain_tx_buffs(struct ath5k_hw *ah) 1156 { 1157 struct ath5k_txq *txq; 1158 struct ath5k_buf *bf, *bf0; 1159 int i; 1160 1161 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) { 1162 if (ah->txqs[i].setup) { 1163 txq = &ah->txqs[i]; 1164 spin_lock_bh(&txq->lock); 1165 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 1166 ath5k_debug_printtxbuf(ah, bf); 1167 1168 ath5k_txbuf_free_skb(ah, bf); 1169 1170 spin_lock(&ah->txbuflock); 1171 list_move_tail(&bf->list, &ah->txbuf); 1172 ah->txbuf_len++; 1173 txq->txq_len--; 1174 spin_unlock(&ah->txbuflock); 1175 } 1176 txq->link = NULL; 1177 txq->txq_poll_mark = false; 1178 spin_unlock_bh(&txq->lock); 1179 } 1180 } 1181 } 1182 1183 static void 1184 ath5k_txq_release(struct ath5k_hw *ah) 1185 { 1186 struct ath5k_txq *txq = ah->txqs; 1187 unsigned int i; 1188 1189 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++, txq++) 1190 if (txq->setup) { 1191 ath5k_hw_release_tx_queue(ah, txq->qnum); 1192 txq->setup = false; 1193 } 1194 } 1195 1196 1197 /*************\ 1198 * RX Handling * 1199 \*************/ 1200 1201 /* 1202 * Enable the receive h/w following a reset. 1203 */ 1204 static int 1205 ath5k_rx_start(struct ath5k_hw *ah) 1206 { 1207 struct ath_common *common = ath5k_hw_common(ah); 1208 struct ath5k_buf *bf; 1209 int ret; 1210 1211 common->rx_bufsize = roundup(IEEE80211_MAX_FRAME_LEN, common->cachelsz); 1212 1213 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "cachelsz %u rx_bufsize %u\n", 1214 common->cachelsz, common->rx_bufsize); 1215 1216 spin_lock_bh(&ah->rxbuflock); 1217 ah->rxlink = NULL; 1218 list_for_each_entry(bf, &ah->rxbuf, list) { 1219 ret = ath5k_rxbuf_setup(ah, bf); 1220 if (ret != 0) { 1221 spin_unlock_bh(&ah->rxbuflock); 1222 goto err; 1223 } 1224 } 1225 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list); 1226 ath5k_hw_set_rxdp(ah, bf->daddr); 1227 spin_unlock_bh(&ah->rxbuflock); 1228 1229 ath5k_hw_start_rx_dma(ah); /* enable recv descriptors */ 1230 ath5k_update_bssid_mask_and_opmode(ah, NULL); /* set filters, etc. */ 1231 ath5k_hw_start_rx_pcu(ah); /* re-enable PCU/DMA engine */ 1232 1233 return 0; 1234 err: 1235 return ret; 1236 } 1237 1238 /* 1239 * Disable the receive logic on PCU (DRU) 1240 * In preparation for a shutdown. 1241 * 1242 * Note: Doesn't stop rx DMA, ath5k_hw_dma_stop 1243 * does. 1244 */ 1245 static void 1246 ath5k_rx_stop(struct ath5k_hw *ah) 1247 { 1248 1249 ath5k_hw_set_rx_filter(ah, 0); /* clear recv filter */ 1250 ath5k_hw_stop_rx_pcu(ah); /* disable PCU */ 1251 1252 ath5k_debug_printrxbuffs(ah); 1253 } 1254 1255 static unsigned int 1256 ath5k_rx_decrypted(struct ath5k_hw *ah, struct sk_buff *skb, 1257 struct ath5k_rx_status *rs) 1258 { 1259 struct ath_common *common = ath5k_hw_common(ah); 1260 struct ieee80211_hdr *hdr = (void *)skb->data; 1261 unsigned int keyix, hlen; 1262 1263 if (!(rs->rs_status & AR5K_RXERR_DECRYPT) && 1264 rs->rs_keyix != AR5K_RXKEYIX_INVALID) 1265 return RX_FLAG_DECRYPTED; 1266 1267 /* Apparently when a default key is used to decrypt the packet 1268 the hw does not set the index used to decrypt. In such cases 1269 get the index from the packet. */ 1270 hlen = ieee80211_hdrlen(hdr->frame_control); 1271 if (ieee80211_has_protected(hdr->frame_control) && 1272 !(rs->rs_status & AR5K_RXERR_DECRYPT) && 1273 skb->len >= hlen + 4) { 1274 keyix = skb->data[hlen + 3] >> 6; 1275 1276 if (test_bit(keyix, common->keymap)) 1277 return RX_FLAG_DECRYPTED; 1278 } 1279 1280 return 0; 1281 } 1282 1283 1284 static void 1285 ath5k_check_ibss_tsf(struct ath5k_hw *ah, struct sk_buff *skb, 1286 struct ieee80211_rx_status *rxs) 1287 { 1288 u64 tsf, bc_tstamp; 1289 u32 hw_tu; 1290 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data; 1291 1292 if (le16_to_cpu(mgmt->u.beacon.capab_info) & WLAN_CAPABILITY_IBSS) { 1293 /* 1294 * Received an IBSS beacon with the same BSSID. Hardware *must* 1295 * have updated the local TSF. We have to work around various 1296 * hardware bugs, though... 1297 */ 1298 tsf = ath5k_hw_get_tsf64(ah); 1299 bc_tstamp = le64_to_cpu(mgmt->u.beacon.timestamp); 1300 hw_tu = TSF_TO_TU(tsf); 1301 1302 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 1303 "beacon %llx mactime %llx (diff %lld) tsf now %llx\n", 1304 (unsigned long long)bc_tstamp, 1305 (unsigned long long)rxs->mactime, 1306 (unsigned long long)(rxs->mactime - bc_tstamp), 1307 (unsigned long long)tsf); 1308 1309 /* 1310 * Sometimes the HW will give us a wrong tstamp in the rx 1311 * status, causing the timestamp extension to go wrong. 1312 * (This seems to happen especially with beacon frames bigger 1313 * than 78 byte (incl. FCS)) 1314 * But we know that the receive timestamp must be later than the 1315 * timestamp of the beacon since HW must have synced to that. 1316 * 1317 * NOTE: here we assume mactime to be after the frame was 1318 * received, not like mac80211 which defines it at the start. 1319 */ 1320 if (bc_tstamp > rxs->mactime) { 1321 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 1322 "fixing mactime from %llx to %llx\n", 1323 (unsigned long long)rxs->mactime, 1324 (unsigned long long)tsf); 1325 rxs->mactime = tsf; 1326 } 1327 1328 /* 1329 * Local TSF might have moved higher than our beacon timers, 1330 * in that case we have to update them to continue sending 1331 * beacons. This also takes care of synchronizing beacon sending 1332 * times with other stations. 1333 */ 1334 if (hw_tu >= ah->nexttbtt) 1335 ath5k_beacon_update_timers(ah, bc_tstamp); 1336 1337 /* Check if the beacon timers are still correct, because a TSF 1338 * update might have created a window between them - for a 1339 * longer description see the comment of this function: */ 1340 if (!ath5k_hw_check_beacon_timers(ah, ah->bintval)) { 1341 ath5k_beacon_update_timers(ah, bc_tstamp); 1342 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 1343 "fixed beacon timers after beacon receive\n"); 1344 } 1345 } 1346 } 1347 1348 /* 1349 * Compute padding position. skb must contain an IEEE 802.11 frame 1350 */ 1351 static int ath5k_common_padpos(struct sk_buff *skb) 1352 { 1353 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1354 __le16 frame_control = hdr->frame_control; 1355 int padpos = 24; 1356 1357 if (ieee80211_has_a4(frame_control)) 1358 padpos += ETH_ALEN; 1359 1360 if (ieee80211_is_data_qos(frame_control)) 1361 padpos += IEEE80211_QOS_CTL_LEN; 1362 1363 return padpos; 1364 } 1365 1366 /* 1367 * This function expects an 802.11 frame and returns the number of 1368 * bytes added, or -1 if we don't have enough header room. 1369 */ 1370 static int ath5k_add_padding(struct sk_buff *skb) 1371 { 1372 int padpos = ath5k_common_padpos(skb); 1373 int padsize = padpos & 3; 1374 1375 if (padsize && skb->len > padpos) { 1376 1377 if (skb_headroom(skb) < padsize) 1378 return -1; 1379 1380 skb_push(skb, padsize); 1381 memmove(skb->data, skb->data + padsize, padpos); 1382 return padsize; 1383 } 1384 1385 return 0; 1386 } 1387 1388 /* 1389 * The MAC header is padded to have 32-bit boundary if the 1390 * packet payload is non-zero. The general calculation for 1391 * padsize would take into account odd header lengths: 1392 * padsize = 4 - (hdrlen & 3); however, since only 1393 * even-length headers are used, padding can only be 0 or 2 1394 * bytes and we can optimize this a bit. We must not try to 1395 * remove padding from short control frames that do not have a 1396 * payload. 1397 * 1398 * This function expects an 802.11 frame and returns the number of 1399 * bytes removed. 1400 */ 1401 static int ath5k_remove_padding(struct sk_buff *skb) 1402 { 1403 int padpos = ath5k_common_padpos(skb); 1404 int padsize = padpos & 3; 1405 1406 if (padsize && skb->len >= padpos + padsize) { 1407 memmove(skb->data + padsize, skb->data, padpos); 1408 skb_pull(skb, padsize); 1409 return padsize; 1410 } 1411 1412 return 0; 1413 } 1414 1415 static void 1416 ath5k_receive_frame(struct ath5k_hw *ah, struct sk_buff *skb, 1417 struct ath5k_rx_status *rs) 1418 { 1419 struct ieee80211_rx_status *rxs; 1420 struct ath_common *common = ath5k_hw_common(ah); 1421 1422 ath5k_remove_padding(skb); 1423 1424 rxs = IEEE80211_SKB_RXCB(skb); 1425 1426 rxs->flag = 0; 1427 if (unlikely(rs->rs_status & AR5K_RXERR_MIC)) 1428 rxs->flag |= RX_FLAG_MMIC_ERROR; 1429 if (unlikely(rs->rs_status & AR5K_RXERR_CRC)) 1430 rxs->flag |= RX_FLAG_FAILED_FCS_CRC; 1431 1432 1433 /* 1434 * always extend the mac timestamp, since this information is 1435 * also needed for proper IBSS merging. 1436 * 1437 * XXX: it might be too late to do it here, since rs_tstamp is 1438 * 15bit only. that means TSF extension has to be done within 1439 * 32768usec (about 32ms). it might be necessary to move this to 1440 * the interrupt handler, like it is done in madwifi. 1441 */ 1442 rxs->mactime = ath5k_extend_tsf(ah, rs->rs_tstamp); 1443 rxs->flag |= RX_FLAG_MACTIME_END; 1444 1445 rxs->freq = ah->curchan->center_freq; 1446 rxs->band = ah->curchan->band; 1447 1448 rxs->signal = ah->ah_noise_floor + rs->rs_rssi; 1449 1450 rxs->antenna = rs->rs_antenna; 1451 1452 if (rs->rs_antenna > 0 && rs->rs_antenna < 5) 1453 ah->stats.antenna_rx[rs->rs_antenna]++; 1454 else 1455 ah->stats.antenna_rx[0]++; /* invalid */ 1456 1457 rxs->rate_idx = ath5k_hw_to_driver_rix(ah, rs->rs_rate); 1458 rxs->flag |= ath5k_rx_decrypted(ah, skb, rs); 1459 switch (ah->ah_bwmode) { 1460 case AR5K_BWMODE_5MHZ: 1461 rxs->bw = RATE_INFO_BW_5; 1462 break; 1463 case AR5K_BWMODE_10MHZ: 1464 rxs->bw = RATE_INFO_BW_10; 1465 break; 1466 default: 1467 break; 1468 } 1469 1470 if (rs->rs_rate == 1471 ah->sbands[ah->curchan->band].bitrates[rxs->rate_idx].hw_value_short) 1472 rxs->enc_flags |= RX_ENC_FLAG_SHORTPRE; 1473 1474 trace_ath5k_rx(ah, skb); 1475 1476 if (ath_is_mybeacon(common, (struct ieee80211_hdr *)skb->data)) { 1477 ewma_beacon_rssi_add(&ah->ah_beacon_rssi_avg, rs->rs_rssi); 1478 1479 /* check beacons in IBSS mode */ 1480 if (ah->opmode == NL80211_IFTYPE_ADHOC) 1481 ath5k_check_ibss_tsf(ah, skb, rxs); 1482 } 1483 1484 ieee80211_rx(ah->hw, skb); 1485 } 1486 1487 /** ath5k_frame_receive_ok() - Do we want to receive this frame or not? 1488 * 1489 * Check if we want to further process this frame or not. Also update 1490 * statistics. Return true if we want this frame, false if not. 1491 */ 1492 static bool 1493 ath5k_receive_frame_ok(struct ath5k_hw *ah, struct ath5k_rx_status *rs) 1494 { 1495 ah->stats.rx_all_count++; 1496 ah->stats.rx_bytes_count += rs->rs_datalen; 1497 1498 if (unlikely(rs->rs_status)) { 1499 unsigned int filters; 1500 1501 if (rs->rs_status & AR5K_RXERR_CRC) 1502 ah->stats.rxerr_crc++; 1503 if (rs->rs_status & AR5K_RXERR_FIFO) 1504 ah->stats.rxerr_fifo++; 1505 if (rs->rs_status & AR5K_RXERR_PHY) { 1506 ah->stats.rxerr_phy++; 1507 if (rs->rs_phyerr > 0 && rs->rs_phyerr < 32) 1508 ah->stats.rxerr_phy_code[rs->rs_phyerr]++; 1509 1510 /* 1511 * Treat packets that underwent a CCK or OFDM reset as having a bad CRC. 1512 * These restarts happen when the radio resynchronizes to a stronger frame 1513 * while receiving a weaker frame. Here we receive the prefix of the weak 1514 * frame. Since these are incomplete packets, mark their CRC as invalid. 1515 */ 1516 if (rs->rs_phyerr == AR5K_RX_PHY_ERROR_OFDM_RESTART || 1517 rs->rs_phyerr == AR5K_RX_PHY_ERROR_CCK_RESTART) { 1518 rs->rs_status |= AR5K_RXERR_CRC; 1519 rs->rs_status &= ~AR5K_RXERR_PHY; 1520 } else { 1521 return false; 1522 } 1523 } 1524 if (rs->rs_status & AR5K_RXERR_DECRYPT) { 1525 /* 1526 * Decrypt error. If the error occurred 1527 * because there was no hardware key, then 1528 * let the frame through so the upper layers 1529 * can process it. This is necessary for 5210 1530 * parts which have no way to setup a ``clear'' 1531 * key cache entry. 1532 * 1533 * XXX do key cache faulting 1534 */ 1535 ah->stats.rxerr_decrypt++; 1536 if (rs->rs_keyix == AR5K_RXKEYIX_INVALID && 1537 !(rs->rs_status & AR5K_RXERR_CRC)) 1538 return true; 1539 } 1540 if (rs->rs_status & AR5K_RXERR_MIC) { 1541 ah->stats.rxerr_mic++; 1542 return true; 1543 } 1544 1545 /* 1546 * Reject any frames with non-crypto errors, and take into account the 1547 * current FIF_* filters. 1548 */ 1549 filters = AR5K_RXERR_DECRYPT; 1550 if (ah->fif_filter_flags & FIF_FCSFAIL) 1551 filters |= AR5K_RXERR_CRC; 1552 1553 if (rs->rs_status & ~filters) 1554 return false; 1555 } 1556 1557 if (unlikely(rs->rs_more)) { 1558 ah->stats.rxerr_jumbo++; 1559 return false; 1560 } 1561 return true; 1562 } 1563 1564 static void 1565 ath5k_set_current_imask(struct ath5k_hw *ah) 1566 { 1567 enum ath5k_int imask; 1568 unsigned long flags; 1569 1570 if (test_bit(ATH_STAT_RESET, ah->status)) 1571 return; 1572 1573 spin_lock_irqsave(&ah->irqlock, flags); 1574 imask = ah->imask; 1575 if (ah->rx_pending) 1576 imask &= ~AR5K_INT_RX_ALL; 1577 if (ah->tx_pending) 1578 imask &= ~AR5K_INT_TX_ALL; 1579 ath5k_hw_set_imr(ah, imask); 1580 spin_unlock_irqrestore(&ah->irqlock, flags); 1581 } 1582 1583 static void 1584 ath5k_tasklet_rx(struct tasklet_struct *t) 1585 { 1586 struct ath5k_rx_status rs = {}; 1587 struct sk_buff *skb, *next_skb; 1588 dma_addr_t next_skb_addr; 1589 struct ath5k_hw *ah = from_tasklet(ah, t, rxtq); 1590 struct ath_common *common = ath5k_hw_common(ah); 1591 struct ath5k_buf *bf; 1592 struct ath5k_desc *ds; 1593 int ret; 1594 1595 spin_lock(&ah->rxbuflock); 1596 if (list_empty(&ah->rxbuf)) { 1597 ATH5K_WARN(ah, "empty rx buf pool\n"); 1598 goto unlock; 1599 } 1600 do { 1601 bf = list_first_entry(&ah->rxbuf, struct ath5k_buf, list); 1602 BUG_ON(bf->skb == NULL); 1603 skb = bf->skb; 1604 ds = bf->desc; 1605 1606 /* bail if HW is still using self-linked descriptor */ 1607 if (ath5k_hw_get_rxdp(ah) == bf->daddr) 1608 break; 1609 1610 ret = ah->ah_proc_rx_desc(ah, ds, &rs); 1611 if (unlikely(ret == -EINPROGRESS)) 1612 break; 1613 else if (unlikely(ret)) { 1614 ATH5K_ERR(ah, "error in processing rx descriptor\n"); 1615 ah->stats.rxerr_proc++; 1616 break; 1617 } 1618 1619 if (ath5k_receive_frame_ok(ah, &rs)) { 1620 next_skb = ath5k_rx_skb_alloc(ah, &next_skb_addr); 1621 1622 /* 1623 * If we can't replace bf->skb with a new skb under 1624 * memory pressure, just skip this packet 1625 */ 1626 if (!next_skb) 1627 goto next; 1628 1629 dma_unmap_single(ah->dev, bf->skbaddr, 1630 common->rx_bufsize, 1631 DMA_FROM_DEVICE); 1632 1633 skb_put(skb, rs.rs_datalen); 1634 1635 ath5k_receive_frame(ah, skb, &rs); 1636 1637 bf->skb = next_skb; 1638 bf->skbaddr = next_skb_addr; 1639 } 1640 next: 1641 list_move_tail(&bf->list, &ah->rxbuf); 1642 } while (ath5k_rxbuf_setup(ah, bf) == 0); 1643 unlock: 1644 spin_unlock(&ah->rxbuflock); 1645 ah->rx_pending = false; 1646 ath5k_set_current_imask(ah); 1647 } 1648 1649 1650 /*************\ 1651 * TX Handling * 1652 \*************/ 1653 1654 void 1655 ath5k_tx_queue(struct ieee80211_hw *hw, struct sk_buff *skb, 1656 struct ath5k_txq *txq, struct ieee80211_tx_control *control) 1657 { 1658 struct ath5k_hw *ah = hw->priv; 1659 struct ath5k_buf *bf; 1660 unsigned long flags; 1661 int padsize; 1662 1663 trace_ath5k_tx(ah, skb, txq); 1664 1665 /* 1666 * The hardware expects the header padded to 4 byte boundaries. 1667 * If this is not the case, we add the padding after the header. 1668 */ 1669 padsize = ath5k_add_padding(skb); 1670 if (padsize < 0) { 1671 ATH5K_ERR(ah, "tx hdrlen not %%4: not enough" 1672 " headroom to pad"); 1673 goto drop_packet; 1674 } 1675 1676 if (txq->txq_len >= txq->txq_max && 1677 txq->qnum <= AR5K_TX_QUEUE_ID_DATA_MAX) 1678 ieee80211_stop_queue(hw, txq->qnum); 1679 1680 spin_lock_irqsave(&ah->txbuflock, flags); 1681 if (list_empty(&ah->txbuf)) { 1682 ATH5K_ERR(ah, "no further txbuf available, dropping packet\n"); 1683 spin_unlock_irqrestore(&ah->txbuflock, flags); 1684 ieee80211_stop_queues(hw); 1685 goto drop_packet; 1686 } 1687 bf = list_first_entry(&ah->txbuf, struct ath5k_buf, list); 1688 list_del(&bf->list); 1689 ah->txbuf_len--; 1690 if (list_empty(&ah->txbuf)) 1691 ieee80211_stop_queues(hw); 1692 spin_unlock_irqrestore(&ah->txbuflock, flags); 1693 1694 bf->skb = skb; 1695 1696 if (ath5k_txbuf_setup(ah, bf, txq, padsize, control)) { 1697 bf->skb = NULL; 1698 spin_lock_irqsave(&ah->txbuflock, flags); 1699 list_add_tail(&bf->list, &ah->txbuf); 1700 ah->txbuf_len++; 1701 spin_unlock_irqrestore(&ah->txbuflock, flags); 1702 goto drop_packet; 1703 } 1704 return; 1705 1706 drop_packet: 1707 ieee80211_free_txskb(hw, skb); 1708 } 1709 1710 static void 1711 ath5k_tx_frame_completed(struct ath5k_hw *ah, struct sk_buff *skb, 1712 struct ath5k_txq *txq, struct ath5k_tx_status *ts, 1713 struct ath5k_buf *bf) 1714 { 1715 struct ieee80211_tx_info *info; 1716 u8 tries[3]; 1717 int i; 1718 int size = 0; 1719 1720 ah->stats.tx_all_count++; 1721 ah->stats.tx_bytes_count += skb->len; 1722 info = IEEE80211_SKB_CB(skb); 1723 1724 size = min_t(int, sizeof(info->status.rates), sizeof(bf->rates)); 1725 memcpy(info->status.rates, bf->rates, size); 1726 1727 tries[0] = info->status.rates[0].count; 1728 tries[1] = info->status.rates[1].count; 1729 tries[2] = info->status.rates[2].count; 1730 1731 ieee80211_tx_info_clear_status(info); 1732 1733 for (i = 0; i < ts->ts_final_idx; i++) { 1734 struct ieee80211_tx_rate *r = 1735 &info->status.rates[i]; 1736 1737 r->count = tries[i]; 1738 } 1739 1740 info->status.rates[ts->ts_final_idx].count = ts->ts_final_retry; 1741 info->status.rates[ts->ts_final_idx + 1].idx = -1; 1742 1743 if (unlikely(ts->ts_status)) { 1744 ah->stats.ack_fail++; 1745 if (ts->ts_status & AR5K_TXERR_FILT) { 1746 info->flags |= IEEE80211_TX_STAT_TX_FILTERED; 1747 ah->stats.txerr_filt++; 1748 } 1749 if (ts->ts_status & AR5K_TXERR_XRETRY) 1750 ah->stats.txerr_retry++; 1751 if (ts->ts_status & AR5K_TXERR_FIFO) 1752 ah->stats.txerr_fifo++; 1753 } else { 1754 info->flags |= IEEE80211_TX_STAT_ACK; 1755 info->status.ack_signal = ts->ts_rssi; 1756 1757 /* count the successful attempt as well */ 1758 info->status.rates[ts->ts_final_idx].count++; 1759 } 1760 1761 /* 1762 * Remove MAC header padding before giving the frame 1763 * back to mac80211. 1764 */ 1765 ath5k_remove_padding(skb); 1766 1767 if (ts->ts_antenna > 0 && ts->ts_antenna < 5) 1768 ah->stats.antenna_tx[ts->ts_antenna]++; 1769 else 1770 ah->stats.antenna_tx[0]++; /* invalid */ 1771 1772 trace_ath5k_tx_complete(ah, skb, txq, ts); 1773 ieee80211_tx_status(ah->hw, skb); 1774 } 1775 1776 static void 1777 ath5k_tx_processq(struct ath5k_hw *ah, struct ath5k_txq *txq) 1778 { 1779 struct ath5k_tx_status ts = {}; 1780 struct ath5k_buf *bf, *bf0; 1781 struct ath5k_desc *ds; 1782 struct sk_buff *skb; 1783 int ret; 1784 1785 spin_lock(&txq->lock); 1786 list_for_each_entry_safe(bf, bf0, &txq->q, list) { 1787 1788 txq->txq_poll_mark = false; 1789 1790 /* skb might already have been processed last time. */ 1791 if (bf->skb != NULL) { 1792 ds = bf->desc; 1793 1794 ret = ah->ah_proc_tx_desc(ah, ds, &ts); 1795 if (unlikely(ret == -EINPROGRESS)) 1796 break; 1797 else if (unlikely(ret)) { 1798 ATH5K_ERR(ah, 1799 "error %d while processing " 1800 "queue %u\n", ret, txq->qnum); 1801 break; 1802 } 1803 1804 skb = bf->skb; 1805 bf->skb = NULL; 1806 1807 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, 1808 DMA_TO_DEVICE); 1809 ath5k_tx_frame_completed(ah, skb, txq, &ts, bf); 1810 } 1811 1812 /* 1813 * It's possible that the hardware can say the buffer is 1814 * completed when it hasn't yet loaded the ds_link from 1815 * host memory and moved on. 1816 * Always keep the last descriptor to avoid HW races... 1817 */ 1818 if (ath5k_hw_get_txdp(ah, txq->qnum) != bf->daddr) { 1819 spin_lock(&ah->txbuflock); 1820 list_move_tail(&bf->list, &ah->txbuf); 1821 ah->txbuf_len++; 1822 txq->txq_len--; 1823 spin_unlock(&ah->txbuflock); 1824 } 1825 } 1826 spin_unlock(&txq->lock); 1827 if (txq->txq_len < ATH5K_TXQ_LEN_LOW && txq->qnum < 4) 1828 ieee80211_wake_queue(ah->hw, txq->qnum); 1829 } 1830 1831 static void 1832 ath5k_tasklet_tx(struct tasklet_struct *t) 1833 { 1834 int i; 1835 struct ath5k_hw *ah = from_tasklet(ah, t, txtq); 1836 1837 for (i = 0; i < AR5K_NUM_TX_QUEUES; i++) 1838 if (ah->txqs[i].setup && (ah->ah_txq_isr_txok_all & BIT(i))) 1839 ath5k_tx_processq(ah, &ah->txqs[i]); 1840 1841 ah->tx_pending = false; 1842 ath5k_set_current_imask(ah); 1843 } 1844 1845 1846 /*****************\ 1847 * Beacon handling * 1848 \*****************/ 1849 1850 /* 1851 * Setup the beacon frame for transmit. 1852 */ 1853 static int 1854 ath5k_beacon_setup(struct ath5k_hw *ah, struct ath5k_buf *bf) 1855 { 1856 struct sk_buff *skb = bf->skb; 1857 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1858 struct ath5k_desc *ds; 1859 int ret = 0; 1860 u8 antenna; 1861 u32 flags; 1862 const int padsize = 0; 1863 1864 bf->skbaddr = dma_map_single(ah->dev, skb->data, skb->len, 1865 DMA_TO_DEVICE); 1866 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "skb %p [data %p len %u] " 1867 "skbaddr %llx\n", skb, skb->data, skb->len, 1868 (unsigned long long)bf->skbaddr); 1869 1870 if (dma_mapping_error(ah->dev, bf->skbaddr)) { 1871 ATH5K_ERR(ah, "beacon DMA mapping failed\n"); 1872 dev_kfree_skb_any(skb); 1873 bf->skb = NULL; 1874 return -EIO; 1875 } 1876 1877 ds = bf->desc; 1878 antenna = ah->ah_tx_ant; 1879 1880 flags = AR5K_TXDESC_NOACK; 1881 if (ah->opmode == NL80211_IFTYPE_ADHOC && ath5k_hw_hasveol(ah)) { 1882 ds->ds_link = bf->daddr; /* self-linked */ 1883 flags |= AR5K_TXDESC_VEOL; 1884 } else 1885 ds->ds_link = 0; 1886 1887 /* 1888 * If we use multiple antennas on AP and use 1889 * the Sectored AP scenario, switch antenna every 1890 * 4 beacons to make sure everybody hears our AP. 1891 * When a client tries to associate, hw will keep 1892 * track of the tx antenna to be used for this client 1893 * automatically, based on ACKed packets. 1894 * 1895 * Note: AP still listens and transmits RTS on the 1896 * default antenna which is supposed to be an omni. 1897 * 1898 * Note2: On sectored scenarios it's possible to have 1899 * multiple antennas (1 omni -- the default -- and 14 1900 * sectors), so if we choose to actually support this 1901 * mode, we need to allow the user to set how many antennas 1902 * we have and tweak the code below to send beacons 1903 * on all of them. 1904 */ 1905 if (ah->ah_ant_mode == AR5K_ANTMODE_SECTOR_AP) 1906 antenna = ah->bsent & 4 ? 2 : 1; 1907 1908 1909 /* FIXME: If we are in g mode and rate is a CCK rate 1910 * subtract ah->ah_txpower.txp_cck_ofdm_pwr_delta 1911 * from tx power (value is in dB units already) */ 1912 ds->ds_data = bf->skbaddr; 1913 ret = ah->ah_setup_tx_desc(ah, ds, skb->len, 1914 ieee80211_get_hdrlen_from_skb(skb), padsize, 1915 AR5K_PKT_TYPE_BEACON, 1916 (ah->ah_txpower.txp_requested * 2), 1917 ieee80211_get_tx_rate(ah->hw, info)->hw_value, 1918 1, AR5K_TXKEYIX_INVALID, 1919 antenna, flags, 0, 0); 1920 if (ret) 1921 goto err_unmap; 1922 1923 return 0; 1924 err_unmap: 1925 dma_unmap_single(ah->dev, bf->skbaddr, skb->len, DMA_TO_DEVICE); 1926 return ret; 1927 } 1928 1929 /* 1930 * Updates the beacon that is sent by ath5k_beacon_send. For adhoc, 1931 * this is called only once at config_bss time, for AP we do it every 1932 * SWBA interrupt so that the TIM will reflect buffered frames. 1933 * 1934 * Called with the beacon lock. 1935 */ 1936 int 1937 ath5k_beacon_update(struct ieee80211_hw *hw, struct ieee80211_vif *vif) 1938 { 1939 int ret; 1940 struct ath5k_hw *ah = hw->priv; 1941 struct ath5k_vif *avf; 1942 struct sk_buff *skb; 1943 1944 if (WARN_ON(!vif)) { 1945 ret = -EINVAL; 1946 goto out; 1947 } 1948 1949 skb = ieee80211_beacon_get(hw, vif); 1950 1951 if (!skb) { 1952 ret = -ENOMEM; 1953 goto out; 1954 } 1955 1956 avf = (void *)vif->drv_priv; 1957 ath5k_txbuf_free_skb(ah, avf->bbuf); 1958 avf->bbuf->skb = skb; 1959 ret = ath5k_beacon_setup(ah, avf->bbuf); 1960 out: 1961 return ret; 1962 } 1963 1964 /* 1965 * Transmit a beacon frame at SWBA. Dynamic updates to the 1966 * frame contents are done as needed and the slot time is 1967 * also adjusted based on current state. 1968 * 1969 * This is called from software irq context (beacontq tasklets) 1970 * or user context from ath5k_beacon_config. 1971 */ 1972 static void 1973 ath5k_beacon_send(struct ath5k_hw *ah) 1974 { 1975 struct ieee80211_vif *vif; 1976 struct ath5k_vif *avf; 1977 struct ath5k_buf *bf; 1978 struct sk_buff *skb; 1979 int err; 1980 1981 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "in beacon_send\n"); 1982 1983 /* 1984 * Check if the previous beacon has gone out. If 1985 * not, don't don't try to post another: skip this 1986 * period and wait for the next. Missed beacons 1987 * indicate a problem and should not occur. If we 1988 * miss too many consecutive beacons reset the device. 1989 */ 1990 if (unlikely(ath5k_hw_num_tx_pending(ah, ah->bhalq) != 0)) { 1991 ah->bmisscount++; 1992 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 1993 "missed %u consecutive beacons\n", ah->bmisscount); 1994 if (ah->bmisscount > 10) { /* NB: 10 is a guess */ 1995 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 1996 "stuck beacon time (%u missed)\n", 1997 ah->bmisscount); 1998 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 1999 "stuck beacon, resetting\n"); 2000 ieee80211_queue_work(ah->hw, &ah->reset_work); 2001 } 2002 return; 2003 } 2004 if (unlikely(ah->bmisscount != 0)) { 2005 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 2006 "resume beacon xmit after %u misses\n", 2007 ah->bmisscount); 2008 ah->bmisscount = 0; 2009 } 2010 2011 if ((ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs + 2012 ah->num_mesh_vifs > 1) || 2013 ah->opmode == NL80211_IFTYPE_MESH_POINT) { 2014 u64 tsf = ath5k_hw_get_tsf64(ah); 2015 u32 tsftu = TSF_TO_TU(tsf); 2016 int slot = ((tsftu % ah->bintval) * ATH_BCBUF) / ah->bintval; 2017 vif = ah->bslot[(slot + 1) % ATH_BCBUF]; 2018 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 2019 "tsf %llx tsftu %x intval %u slot %u vif %p\n", 2020 (unsigned long long)tsf, tsftu, ah->bintval, slot, vif); 2021 } else /* only one interface */ 2022 vif = ah->bslot[0]; 2023 2024 if (!vif) 2025 return; 2026 2027 avf = (void *)vif->drv_priv; 2028 bf = avf->bbuf; 2029 2030 /* 2031 * Stop any current dma and put the new frame on the queue. 2032 * This should never fail since we check above that no frames 2033 * are still pending on the queue. 2034 */ 2035 if (unlikely(ath5k_hw_stop_beacon_queue(ah, ah->bhalq))) { 2036 ATH5K_WARN(ah, "beacon queue %u didn't start/stop ?\n", ah->bhalq); 2037 /* NB: hw still stops DMA, so proceed */ 2038 } 2039 2040 /* refresh the beacon for AP or MESH mode */ 2041 if (ah->opmode == NL80211_IFTYPE_AP || 2042 ah->opmode == NL80211_IFTYPE_MESH_POINT) { 2043 err = ath5k_beacon_update(ah->hw, vif); 2044 if (err) 2045 return; 2046 } 2047 2048 if (unlikely(bf->skb == NULL || ah->opmode == NL80211_IFTYPE_STATION || 2049 ah->opmode == NL80211_IFTYPE_MONITOR)) { 2050 ATH5K_WARN(ah, "bf=%p bf_skb=%p\n", bf, bf->skb); 2051 return; 2052 } 2053 2054 trace_ath5k_tx(ah, bf->skb, &ah->txqs[ah->bhalq]); 2055 2056 ath5k_hw_set_txdp(ah, ah->bhalq, bf->daddr); 2057 ath5k_hw_start_tx_dma(ah, ah->bhalq); 2058 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, "TXDP[%u] = %llx (%p)\n", 2059 ah->bhalq, (unsigned long long)bf->daddr, bf->desc); 2060 2061 skb = ieee80211_get_buffered_bc(ah->hw, vif); 2062 while (skb) { 2063 ath5k_tx_queue(ah->hw, skb, ah->cabq, NULL); 2064 2065 if (ah->cabq->txq_len >= ah->cabq->txq_max) 2066 break; 2067 2068 skb = ieee80211_get_buffered_bc(ah->hw, vif); 2069 } 2070 2071 ah->bsent++; 2072 } 2073 2074 /** 2075 * ath5k_beacon_update_timers - update beacon timers 2076 * 2077 * @ah: struct ath5k_hw pointer we are operating on 2078 * @bc_tsf: the timestamp of the beacon. 0 to reset the TSF. -1 to perform a 2079 * beacon timer update based on the current HW TSF. 2080 * 2081 * Calculate the next target beacon transmit time (TBTT) based on the timestamp 2082 * of a received beacon or the current local hardware TSF and write it to the 2083 * beacon timer registers. 2084 * 2085 * This is called in a variety of situations, e.g. when a beacon is received, 2086 * when a TSF update has been detected, but also when an new IBSS is created or 2087 * when we otherwise know we have to update the timers, but we keep it in this 2088 * function to have it all together in one place. 2089 */ 2090 void 2091 ath5k_beacon_update_timers(struct ath5k_hw *ah, u64 bc_tsf) 2092 { 2093 u32 nexttbtt, intval, hw_tu, bc_tu; 2094 u64 hw_tsf; 2095 2096 intval = ah->bintval & AR5K_BEACON_PERIOD; 2097 if (ah->opmode == NL80211_IFTYPE_AP && ah->num_ap_vifs 2098 + ah->num_mesh_vifs > 1) { 2099 intval /= ATH_BCBUF; /* staggered multi-bss beacons */ 2100 if (intval < 15) 2101 ATH5K_WARN(ah, "intval %u is too low, min 15\n", 2102 intval); 2103 } 2104 if (WARN_ON(!intval)) 2105 return; 2106 2107 /* beacon TSF converted to TU */ 2108 bc_tu = TSF_TO_TU(bc_tsf); 2109 2110 /* current TSF converted to TU */ 2111 hw_tsf = ath5k_hw_get_tsf64(ah); 2112 hw_tu = TSF_TO_TU(hw_tsf); 2113 2114 #define FUDGE (AR5K_TUNE_SW_BEACON_RESP + 3) 2115 /* We use FUDGE to make sure the next TBTT is ahead of the current TU. 2116 * Since we later subtract AR5K_TUNE_SW_BEACON_RESP (10) in the timer 2117 * configuration we need to make sure it is bigger than that. */ 2118 2119 if (bc_tsf == -1) { 2120 /* 2121 * no beacons received, called internally. 2122 * just need to refresh timers based on HW TSF. 2123 */ 2124 nexttbtt = roundup(hw_tu + FUDGE, intval); 2125 } else if (bc_tsf == 0) { 2126 /* 2127 * no beacon received, probably called by ath5k_reset_tsf(). 2128 * reset TSF to start with 0. 2129 */ 2130 nexttbtt = intval; 2131 intval |= AR5K_BEACON_RESET_TSF; 2132 } else if (bc_tsf > hw_tsf) { 2133 /* 2134 * beacon received, SW merge happened but HW TSF not yet updated. 2135 * not possible to reconfigure timers yet, but next time we 2136 * receive a beacon with the same BSSID, the hardware will 2137 * automatically update the TSF and then we need to reconfigure 2138 * the timers. 2139 */ 2140 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2141 "need to wait for HW TSF sync\n"); 2142 return; 2143 } else { 2144 /* 2145 * most important case for beacon synchronization between STA. 2146 * 2147 * beacon received and HW TSF has been already updated by HW. 2148 * update next TBTT based on the TSF of the beacon, but make 2149 * sure it is ahead of our local TSF timer. 2150 */ 2151 nexttbtt = bc_tu + roundup(hw_tu + FUDGE - bc_tu, intval); 2152 } 2153 #undef FUDGE 2154 2155 ah->nexttbtt = nexttbtt; 2156 2157 intval |= AR5K_BEACON_ENA; 2158 ath5k_hw_init_beacon_timers(ah, nexttbtt, intval); 2159 2160 /* 2161 * debugging output last in order to preserve the time critical aspect 2162 * of this function 2163 */ 2164 if (bc_tsf == -1) 2165 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2166 "reconfigured timers based on HW TSF\n"); 2167 else if (bc_tsf == 0) 2168 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2169 "reset HW TSF and timers\n"); 2170 else 2171 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2172 "updated timers based on beacon TSF\n"); 2173 2174 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, 2175 "bc_tsf %llx hw_tsf %llx bc_tu %u hw_tu %u nexttbtt %u\n", 2176 (unsigned long long) bc_tsf, 2177 (unsigned long long) hw_tsf, bc_tu, hw_tu, nexttbtt); 2178 ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_BEACON, "intval %u %s %s\n", 2179 intval & AR5K_BEACON_PERIOD, 2180 intval & AR5K_BEACON_ENA ? "AR5K_BEACON_ENA" : "", 2181 intval & AR5K_BEACON_RESET_TSF ? "AR5K_BEACON_RESET_TSF" : ""); 2182 } 2183 2184 /** 2185 * ath5k_beacon_config - Configure the beacon queues and interrupts 2186 * 2187 * @ah: struct ath5k_hw pointer we are operating on 2188 * 2189 * In IBSS mode we use a self-linked tx descriptor if possible. We enable SWBA 2190 * interrupts to detect TSF updates only. 2191 */ 2192 void 2193 ath5k_beacon_config(struct ath5k_hw *ah) 2194 { 2195 spin_lock_bh(&ah->block); 2196 ah->bmisscount = 0; 2197 ah->imask &= ~(AR5K_INT_BMISS | AR5K_INT_SWBA); 2198 2199 if (ah->enable_beacon) { 2200 /* 2201 * In IBSS mode we use a self-linked tx descriptor and let the 2202 * hardware send the beacons automatically. We have to load it 2203 * only once here. 2204 * We use the SWBA interrupt only to keep track of the beacon 2205 * timers in order to detect automatic TSF updates. 2206 */ 2207 ath5k_beaconq_config(ah); 2208 2209 ah->imask |= AR5K_INT_SWBA; 2210 2211 if (ah->opmode == NL80211_IFTYPE_ADHOC) { 2212 if (ath5k_hw_hasveol(ah)) 2213 ath5k_beacon_send(ah); 2214 } else 2215 ath5k_beacon_update_timers(ah, -1); 2216 } else { 2217 ath5k_hw_stop_beacon_queue(ah, ah->bhalq); 2218 } 2219 2220 ath5k_hw_set_imr(ah, ah->imask); 2221 spin_unlock_bh(&ah->block); 2222 } 2223 2224 static void ath5k_tasklet_beacon(struct tasklet_struct *t) 2225 { 2226 struct ath5k_hw *ah = from_tasklet(ah, t, beacontq); 2227 2228 /* 2229 * Software beacon alert--time to send a beacon. 2230 * 2231 * In IBSS mode we use this interrupt just to 2232 * keep track of the next TBTT (target beacon 2233 * transmission time) in order to detect whether 2234 * automatic TSF updates happened. 2235 */ 2236 if (ah->opmode == NL80211_IFTYPE_ADHOC) { 2237 /* XXX: only if VEOL supported */ 2238 u64 tsf = ath5k_hw_get_tsf64(ah); 2239 ah->nexttbtt += ah->bintval; 2240 ATH5K_DBG(ah, ATH5K_DEBUG_BEACON, 2241 "SWBA nexttbtt: %x hw_tu: %x " 2242 "TSF: %llx\n", 2243 ah->nexttbtt, 2244 TSF_TO_TU(tsf), 2245 (unsigned long long) tsf); 2246 } else { 2247 spin_lock(&ah->block); 2248 ath5k_beacon_send(ah); 2249 spin_unlock(&ah->block); 2250 } 2251 } 2252 2253 2254 /********************\ 2255 * Interrupt handling * 2256 \********************/ 2257 2258 static void 2259 ath5k_intr_calibration_poll(struct ath5k_hw *ah) 2260 { 2261 if (time_is_before_eq_jiffies(ah->ah_cal_next_ani) && 2262 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) && 2263 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) { 2264 2265 /* Run ANI only when calibration is not active */ 2266 2267 ah->ah_cal_next_ani = jiffies + 2268 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI); 2269 tasklet_schedule(&ah->ani_tasklet); 2270 2271 } else if (time_is_before_eq_jiffies(ah->ah_cal_next_short) && 2272 !(ah->ah_cal_mask & AR5K_CALIBRATION_FULL) && 2273 !(ah->ah_cal_mask & AR5K_CALIBRATION_SHORT)) { 2274 2275 /* Run calibration only when another calibration 2276 * is not running. 2277 * 2278 * Note: This is for both full/short calibration, 2279 * if it's time for a full one, ath5k_calibrate_work will deal 2280 * with it. */ 2281 2282 ah->ah_cal_next_short = jiffies + 2283 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT); 2284 ieee80211_queue_work(ah->hw, &ah->calib_work); 2285 } 2286 /* we could use SWI to generate enough interrupts to meet our 2287 * calibration interval requirements, if necessary: 2288 * AR5K_REG_ENABLE_BITS(ah, AR5K_CR, AR5K_CR_SWI); */ 2289 } 2290 2291 static void 2292 ath5k_schedule_rx(struct ath5k_hw *ah) 2293 { 2294 ah->rx_pending = true; 2295 tasklet_schedule(&ah->rxtq); 2296 } 2297 2298 static void 2299 ath5k_schedule_tx(struct ath5k_hw *ah) 2300 { 2301 ah->tx_pending = true; 2302 tasklet_schedule(&ah->txtq); 2303 } 2304 2305 static irqreturn_t 2306 ath5k_intr(int irq, void *dev_id) 2307 { 2308 struct ath5k_hw *ah = dev_id; 2309 enum ath5k_int status; 2310 unsigned int counter = 1000; 2311 2312 2313 /* 2314 * If hw is not ready (or detached) and we get an 2315 * interrupt, or if we have no interrupts pending 2316 * (that means it's not for us) skip it. 2317 * 2318 * NOTE: Group 0/1 PCI interface registers are not 2319 * supported on WiSOCs, so we can't check for pending 2320 * interrupts (ISR belongs to another register group 2321 * so we are ok). 2322 */ 2323 if (unlikely(test_bit(ATH_STAT_INVALID, ah->status) || 2324 ((ath5k_get_bus_type(ah) != ATH_AHB) && 2325 !ath5k_hw_is_intr_pending(ah)))) 2326 return IRQ_NONE; 2327 2328 /** Main loop **/ 2329 do { 2330 ath5k_hw_get_isr(ah, &status); /* NB: clears IRQ too */ 2331 2332 ATH5K_DBG(ah, ATH5K_DEBUG_INTR, "status 0x%x/0x%x\n", 2333 status, ah->imask); 2334 2335 /* 2336 * Fatal hw error -> Log and reset 2337 * 2338 * Fatal errors are unrecoverable so we have to 2339 * reset the card. These errors include bus and 2340 * dma errors. 2341 */ 2342 if (unlikely(status & AR5K_INT_FATAL)) { 2343 2344 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2345 "fatal int, resetting\n"); 2346 ieee80211_queue_work(ah->hw, &ah->reset_work); 2347 2348 /* 2349 * RX Overrun -> Count and reset if needed 2350 * 2351 * Receive buffers are full. Either the bus is busy or 2352 * the CPU is not fast enough to process all received 2353 * frames. 2354 */ 2355 } else if (unlikely(status & AR5K_INT_RXORN)) { 2356 2357 /* 2358 * Older chipsets need a reset to come out of this 2359 * condition, but we treat it as RX for newer chips. 2360 * We don't know exactly which versions need a reset 2361 * this guess is copied from the HAL. 2362 */ 2363 ah->stats.rxorn_intr++; 2364 2365 if (ah->ah_mac_srev < AR5K_SREV_AR5212) { 2366 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2367 "rx overrun, resetting\n"); 2368 ieee80211_queue_work(ah->hw, &ah->reset_work); 2369 } else 2370 ath5k_schedule_rx(ah); 2371 2372 } else { 2373 2374 /* Software Beacon Alert -> Schedule beacon tasklet */ 2375 if (status & AR5K_INT_SWBA) 2376 tasklet_hi_schedule(&ah->beacontq); 2377 2378 /* 2379 * No more RX descriptors -> Just count 2380 * 2381 * NB: the hardware should re-read the link when 2382 * RXE bit is written, but it doesn't work at 2383 * least on older hardware revs. 2384 */ 2385 if (status & AR5K_INT_RXEOL) 2386 ah->stats.rxeol_intr++; 2387 2388 2389 /* TX Underrun -> Bump tx trigger level */ 2390 if (status & AR5K_INT_TXURN) 2391 ath5k_hw_update_tx_triglevel(ah, true); 2392 2393 /* RX -> Schedule rx tasklet */ 2394 if (status & (AR5K_INT_RXOK | AR5K_INT_RXERR)) 2395 ath5k_schedule_rx(ah); 2396 2397 /* TX -> Schedule tx tasklet */ 2398 if (status & (AR5K_INT_TXOK 2399 | AR5K_INT_TXDESC 2400 | AR5K_INT_TXERR 2401 | AR5K_INT_TXEOL)) 2402 ath5k_schedule_tx(ah); 2403 2404 /* Missed beacon -> TODO 2405 if (status & AR5K_INT_BMISS) 2406 */ 2407 2408 /* MIB event -> Update counters and notify ANI */ 2409 if (status & AR5K_INT_MIB) { 2410 ah->stats.mib_intr++; 2411 ath5k_hw_update_mib_counters(ah); 2412 ath5k_ani_mib_intr(ah); 2413 } 2414 2415 /* GPIO -> Notify RFKill layer */ 2416 if (status & AR5K_INT_GPIO) 2417 tasklet_schedule(&ah->rf_kill.toggleq); 2418 2419 } 2420 2421 if (ath5k_get_bus_type(ah) == ATH_AHB) 2422 break; 2423 2424 } while (ath5k_hw_is_intr_pending(ah) && --counter > 0); 2425 2426 /* 2427 * Until we handle rx/tx interrupts mask them on IMR 2428 * 2429 * NOTE: ah->(rx/tx)_pending are set when scheduling the tasklets 2430 * and unset after we 've handled the interrupts. 2431 */ 2432 if (ah->rx_pending || ah->tx_pending) 2433 ath5k_set_current_imask(ah); 2434 2435 if (unlikely(!counter)) 2436 ATH5K_WARN(ah, "too many interrupts, giving up for now\n"); 2437 2438 /* Fire up calibration poll */ 2439 ath5k_intr_calibration_poll(ah); 2440 2441 return IRQ_HANDLED; 2442 } 2443 2444 /* 2445 * Periodically recalibrate the PHY to account 2446 * for temperature/environment changes. 2447 */ 2448 static void 2449 ath5k_calibrate_work(struct work_struct *work) 2450 { 2451 struct ath5k_hw *ah = container_of(work, struct ath5k_hw, 2452 calib_work); 2453 2454 /* Should we run a full calibration ? */ 2455 if (time_is_before_eq_jiffies(ah->ah_cal_next_full)) { 2456 2457 ah->ah_cal_next_full = jiffies + 2458 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL); 2459 ah->ah_cal_mask |= AR5K_CALIBRATION_FULL; 2460 2461 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, 2462 "running full calibration\n"); 2463 2464 if (ath5k_hw_gainf_calibrate(ah) == AR5K_RFGAIN_NEED_CHANGE) { 2465 /* 2466 * Rfgain is out of bounds, reset the chip 2467 * to load new gain values. 2468 */ 2469 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2470 "got new rfgain, resetting\n"); 2471 ieee80211_queue_work(ah->hw, &ah->reset_work); 2472 } 2473 } else 2474 ah->ah_cal_mask |= AR5K_CALIBRATION_SHORT; 2475 2476 2477 ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE, "channel %u/%x\n", 2478 ieee80211_frequency_to_channel(ah->curchan->center_freq), 2479 ah->curchan->hw_value); 2480 2481 if (ath5k_hw_phy_calibrate(ah, ah->curchan)) 2482 ATH5K_ERR(ah, "calibration of channel %u failed\n", 2483 ieee80211_frequency_to_channel( 2484 ah->curchan->center_freq)); 2485 2486 /* Clear calibration flags */ 2487 if (ah->ah_cal_mask & AR5K_CALIBRATION_FULL) 2488 ah->ah_cal_mask &= ~AR5K_CALIBRATION_FULL; 2489 else if (ah->ah_cal_mask & AR5K_CALIBRATION_SHORT) 2490 ah->ah_cal_mask &= ~AR5K_CALIBRATION_SHORT; 2491 } 2492 2493 2494 static void 2495 ath5k_tasklet_ani(struct tasklet_struct *t) 2496 { 2497 struct ath5k_hw *ah = from_tasklet(ah, t, ani_tasklet); 2498 2499 ah->ah_cal_mask |= AR5K_CALIBRATION_ANI; 2500 ath5k_ani_calibration(ah); 2501 ah->ah_cal_mask &= ~AR5K_CALIBRATION_ANI; 2502 } 2503 2504 2505 static void 2506 ath5k_tx_complete_poll_work(struct work_struct *work) 2507 { 2508 struct ath5k_hw *ah = container_of(work, struct ath5k_hw, 2509 tx_complete_work.work); 2510 struct ath5k_txq *txq; 2511 int i; 2512 bool needreset = false; 2513 2514 if (!test_bit(ATH_STAT_STARTED, ah->status)) 2515 return; 2516 2517 mutex_lock(&ah->lock); 2518 2519 for (i = 0; i < ARRAY_SIZE(ah->txqs); i++) { 2520 if (ah->txqs[i].setup) { 2521 txq = &ah->txqs[i]; 2522 spin_lock_bh(&txq->lock); 2523 if (txq->txq_len > 1) { 2524 if (txq->txq_poll_mark) { 2525 ATH5K_DBG(ah, ATH5K_DEBUG_XMIT, 2526 "TX queue stuck %d\n", 2527 txq->qnum); 2528 needreset = true; 2529 txq->txq_stuck++; 2530 spin_unlock_bh(&txq->lock); 2531 break; 2532 } else { 2533 txq->txq_poll_mark = true; 2534 } 2535 } 2536 spin_unlock_bh(&txq->lock); 2537 } 2538 } 2539 2540 if (needreset) { 2541 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2542 "TX queues stuck, resetting\n"); 2543 ath5k_reset(ah, NULL, true); 2544 } 2545 2546 mutex_unlock(&ah->lock); 2547 2548 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work, 2549 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); 2550 } 2551 2552 2553 /*************************\ 2554 * Initialization routines * 2555 \*************************/ 2556 2557 static const struct ieee80211_iface_limit if_limits[] = { 2558 { .max = 2048, .types = BIT(NL80211_IFTYPE_STATION) }, 2559 { .max = 4, .types = 2560 #ifdef CONFIG_MAC80211_MESH 2561 BIT(NL80211_IFTYPE_MESH_POINT) | 2562 #endif 2563 BIT(NL80211_IFTYPE_AP) }, 2564 }; 2565 2566 static const struct ieee80211_iface_combination if_comb = { 2567 .limits = if_limits, 2568 .n_limits = ARRAY_SIZE(if_limits), 2569 .max_interfaces = 2048, 2570 .num_different_channels = 1, 2571 }; 2572 2573 int 2574 ath5k_init_ah(struct ath5k_hw *ah, const struct ath_bus_ops *bus_ops) 2575 { 2576 struct ieee80211_hw *hw = ah->hw; 2577 struct ath_common *common; 2578 int ret; 2579 int csz; 2580 2581 /* Initialize driver private data */ 2582 SET_IEEE80211_DEV(hw, ah->dev); 2583 ieee80211_hw_set(hw, SUPPORTS_RC_TABLE); 2584 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 2585 ieee80211_hw_set(hw, MFP_CAPABLE); 2586 ieee80211_hw_set(hw, SIGNAL_DBM); 2587 ieee80211_hw_set(hw, RX_INCLUDES_FCS); 2588 ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING); 2589 2590 hw->wiphy->interface_modes = 2591 BIT(NL80211_IFTYPE_AP) | 2592 BIT(NL80211_IFTYPE_STATION) | 2593 BIT(NL80211_IFTYPE_ADHOC) | 2594 BIT(NL80211_IFTYPE_MESH_POINT); 2595 2596 hw->wiphy->iface_combinations = &if_comb; 2597 hw->wiphy->n_iface_combinations = 1; 2598 2599 /* SW support for IBSS_RSN is provided by mac80211 */ 2600 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; 2601 2602 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ; 2603 2604 /* both antennas can be configured as RX or TX */ 2605 hw->wiphy->available_antennas_tx = 0x3; 2606 hw->wiphy->available_antennas_rx = 0x3; 2607 2608 hw->extra_tx_headroom = 2; 2609 2610 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST); 2611 2612 /* 2613 * Mark the device as detached to avoid processing 2614 * interrupts until setup is complete. 2615 */ 2616 __set_bit(ATH_STAT_INVALID, ah->status); 2617 2618 ah->opmode = NL80211_IFTYPE_STATION; 2619 ah->bintval = 1000; 2620 mutex_init(&ah->lock); 2621 spin_lock_init(&ah->rxbuflock); 2622 spin_lock_init(&ah->txbuflock); 2623 spin_lock_init(&ah->block); 2624 spin_lock_init(&ah->irqlock); 2625 2626 /* Setup interrupt handler */ 2627 ret = request_irq(ah->irq, ath5k_intr, IRQF_SHARED, "ath", ah); 2628 if (ret) { 2629 ATH5K_ERR(ah, "request_irq failed\n"); 2630 goto err; 2631 } 2632 2633 common = ath5k_hw_common(ah); 2634 common->ops = &ath5k_common_ops; 2635 common->bus_ops = bus_ops; 2636 common->ah = ah; 2637 common->hw = hw; 2638 common->priv = ah; 2639 common->clockrate = 40; 2640 2641 /* 2642 * Cache line size is used to size and align various 2643 * structures used to communicate with the hardware. 2644 */ 2645 ath5k_read_cachesize(common, &csz); 2646 common->cachelsz = csz << 2; /* convert to bytes */ 2647 2648 spin_lock_init(&common->cc_lock); 2649 2650 /* Initialize device */ 2651 ret = ath5k_hw_init(ah); 2652 if (ret) 2653 goto err_irq; 2654 2655 /* Set up multi-rate retry capabilities */ 2656 if (ah->ah_capabilities.cap_has_mrr_support) { 2657 hw->max_rates = 4; 2658 hw->max_rate_tries = max(AR5K_INIT_RETRY_SHORT, 2659 AR5K_INIT_RETRY_LONG); 2660 } 2661 2662 hw->vif_data_size = sizeof(struct ath5k_vif); 2663 2664 /* Finish private driver data initialization */ 2665 ret = ath5k_init(hw); 2666 if (ret) 2667 goto err_ah; 2668 2669 ATH5K_INFO(ah, "Atheros AR%s chip found (MAC: 0x%x, PHY: 0x%x)\n", 2670 ath5k_chip_name(AR5K_VERSION_MAC, ah->ah_mac_srev), 2671 ah->ah_mac_srev, 2672 ah->ah_phy_revision); 2673 2674 if (!ah->ah_single_chip) { 2675 /* Single chip radio (!RF5111) */ 2676 if (ah->ah_radio_5ghz_revision && 2677 !ah->ah_radio_2ghz_revision) { 2678 /* No 5GHz support -> report 2GHz radio */ 2679 if (!test_bit(AR5K_MODE_11A, 2680 ah->ah_capabilities.cap_mode)) { 2681 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n", 2682 ath5k_chip_name(AR5K_VERSION_RAD, 2683 ah->ah_radio_5ghz_revision), 2684 ah->ah_radio_5ghz_revision); 2685 /* No 2GHz support (5110 and some 2686 * 5GHz only cards) -> report 5GHz radio */ 2687 } else if (!test_bit(AR5K_MODE_11B, 2688 ah->ah_capabilities.cap_mode)) { 2689 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n", 2690 ath5k_chip_name(AR5K_VERSION_RAD, 2691 ah->ah_radio_5ghz_revision), 2692 ah->ah_radio_5ghz_revision); 2693 /* Multiband radio */ 2694 } else { 2695 ATH5K_INFO(ah, "RF%s multiband radio found" 2696 " (0x%x)\n", 2697 ath5k_chip_name(AR5K_VERSION_RAD, 2698 ah->ah_radio_5ghz_revision), 2699 ah->ah_radio_5ghz_revision); 2700 } 2701 } 2702 /* Multi chip radio (RF5111 - RF2111) -> 2703 * report both 2GHz/5GHz radios */ 2704 else if (ah->ah_radio_5ghz_revision && 2705 ah->ah_radio_2ghz_revision) { 2706 ATH5K_INFO(ah, "RF%s 5GHz radio found (0x%x)\n", 2707 ath5k_chip_name(AR5K_VERSION_RAD, 2708 ah->ah_radio_5ghz_revision), 2709 ah->ah_radio_5ghz_revision); 2710 ATH5K_INFO(ah, "RF%s 2GHz radio found (0x%x)\n", 2711 ath5k_chip_name(AR5K_VERSION_RAD, 2712 ah->ah_radio_2ghz_revision), 2713 ah->ah_radio_2ghz_revision); 2714 } 2715 } 2716 2717 ath5k_debug_init_device(ah); 2718 2719 /* ready to process interrupts */ 2720 __clear_bit(ATH_STAT_INVALID, ah->status); 2721 2722 return 0; 2723 err_ah: 2724 ath5k_hw_deinit(ah); 2725 err_irq: 2726 free_irq(ah->irq, ah); 2727 err: 2728 return ret; 2729 } 2730 2731 static int 2732 ath5k_stop_locked(struct ath5k_hw *ah) 2733 { 2734 2735 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "invalid %u\n", 2736 test_bit(ATH_STAT_INVALID, ah->status)); 2737 2738 /* 2739 * Shutdown the hardware and driver: 2740 * stop output from above 2741 * disable interrupts 2742 * turn off timers 2743 * turn off the radio 2744 * clear transmit machinery 2745 * clear receive machinery 2746 * drain and release tx queues 2747 * reclaim beacon resources 2748 * power down hardware 2749 * 2750 * Note that some of this work is not possible if the 2751 * hardware is gone (invalid). 2752 */ 2753 ieee80211_stop_queues(ah->hw); 2754 2755 if (!test_bit(ATH_STAT_INVALID, ah->status)) { 2756 ath5k_led_off(ah); 2757 ath5k_hw_set_imr(ah, 0); 2758 synchronize_irq(ah->irq); 2759 ath5k_rx_stop(ah); 2760 ath5k_hw_dma_stop(ah); 2761 ath5k_drain_tx_buffs(ah); 2762 ath5k_hw_phy_disable(ah); 2763 } 2764 2765 return 0; 2766 } 2767 2768 int ath5k_start(struct ieee80211_hw *hw) 2769 { 2770 struct ath5k_hw *ah = hw->priv; 2771 struct ath_common *common = ath5k_hw_common(ah); 2772 int ret, i; 2773 2774 mutex_lock(&ah->lock); 2775 2776 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "mode %d\n", ah->opmode); 2777 2778 /* 2779 * Stop anything previously setup. This is safe 2780 * no matter this is the first time through or not. 2781 */ 2782 ath5k_stop_locked(ah); 2783 2784 /* 2785 * The basic interface to setting the hardware in a good 2786 * state is ``reset''. On return the hardware is known to 2787 * be powered up and with interrupts disabled. This must 2788 * be followed by initialization of the appropriate bits 2789 * and then setup of the interrupt mask. 2790 */ 2791 ah->curchan = ah->hw->conf.chandef.chan; 2792 ah->imask = AR5K_INT_RXOK 2793 | AR5K_INT_RXERR 2794 | AR5K_INT_RXEOL 2795 | AR5K_INT_RXORN 2796 | AR5K_INT_TXDESC 2797 | AR5K_INT_TXEOL 2798 | AR5K_INT_FATAL 2799 | AR5K_INT_GLOBAL 2800 | AR5K_INT_MIB; 2801 2802 ret = ath5k_reset(ah, NULL, false); 2803 if (ret) 2804 goto done; 2805 2806 if (!ath5k_modparam_no_hw_rfkill_switch) 2807 ath5k_rfkill_hw_start(ah); 2808 2809 /* 2810 * Reset the key cache since some parts do not reset the 2811 * contents on initial power up or resume from suspend. 2812 */ 2813 for (i = 0; i < common->keymax; i++) 2814 ath_hw_keyreset(common, (u16) i); 2815 2816 /* Use higher rates for acks instead of base 2817 * rate */ 2818 ah->ah_ack_bitrate_high = true; 2819 2820 for (i = 0; i < ARRAY_SIZE(ah->bslot); i++) 2821 ah->bslot[i] = NULL; 2822 2823 ret = 0; 2824 done: 2825 mutex_unlock(&ah->lock); 2826 2827 set_bit(ATH_STAT_STARTED, ah->status); 2828 ieee80211_queue_delayed_work(ah->hw, &ah->tx_complete_work, 2829 msecs_to_jiffies(ATH5K_TX_COMPLETE_POLL_INT)); 2830 2831 return ret; 2832 } 2833 2834 static void ath5k_stop_tasklets(struct ath5k_hw *ah) 2835 { 2836 ah->rx_pending = false; 2837 ah->tx_pending = false; 2838 tasklet_kill(&ah->rxtq); 2839 tasklet_kill(&ah->txtq); 2840 tasklet_kill(&ah->beacontq); 2841 tasklet_kill(&ah->ani_tasklet); 2842 } 2843 2844 /* 2845 * Stop the device, grabbing the top-level lock to protect 2846 * against concurrent entry through ath5k_init (which can happen 2847 * if another thread does a system call and the thread doing the 2848 * stop is preempted). 2849 */ 2850 void ath5k_stop(struct ieee80211_hw *hw) 2851 { 2852 struct ath5k_hw *ah = hw->priv; 2853 int ret; 2854 2855 mutex_lock(&ah->lock); 2856 ret = ath5k_stop_locked(ah); 2857 if (ret == 0 && !test_bit(ATH_STAT_INVALID, ah->status)) { 2858 /* 2859 * Don't set the card in full sleep mode! 2860 * 2861 * a) When the device is in this state it must be carefully 2862 * woken up or references to registers in the PCI clock 2863 * domain may freeze the bus (and system). This varies 2864 * by chip and is mostly an issue with newer parts 2865 * (madwifi sources mentioned srev >= 0x78) that go to 2866 * sleep more quickly. 2867 * 2868 * b) On older chips full sleep results a weird behaviour 2869 * during wakeup. I tested various cards with srev < 0x78 2870 * and they don't wake up after module reload, a second 2871 * module reload is needed to bring the card up again. 2872 * 2873 * Until we figure out what's going on don't enable 2874 * full chip reset on any chip (this is what Legacy HAL 2875 * and Sam's HAL do anyway). Instead Perform a full reset 2876 * on the device (same as initial state after attach) and 2877 * leave it idle (keep MAC/BB on warm reset) */ 2878 ret = ath5k_hw_on_hold(ah); 2879 2880 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2881 "putting device to sleep\n"); 2882 } 2883 2884 mutex_unlock(&ah->lock); 2885 2886 ath5k_stop_tasklets(ah); 2887 2888 clear_bit(ATH_STAT_STARTED, ah->status); 2889 cancel_delayed_work_sync(&ah->tx_complete_work); 2890 2891 if (!ath5k_modparam_no_hw_rfkill_switch) 2892 ath5k_rfkill_hw_stop(ah); 2893 } 2894 2895 /* 2896 * Reset the hardware. If chan is not NULL, then also pause rx/tx 2897 * and change to the given channel. 2898 * 2899 * This should be called with ah->lock. 2900 */ 2901 static int 2902 ath5k_reset(struct ath5k_hw *ah, struct ieee80211_channel *chan, 2903 bool skip_pcu) 2904 { 2905 struct ath_common *common = ath5k_hw_common(ah); 2906 int ret, ani_mode; 2907 bool fast = chan && modparam_fastchanswitch ? 1 : 0; 2908 2909 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, "resetting\n"); 2910 2911 __set_bit(ATH_STAT_RESET, ah->status); 2912 2913 ath5k_hw_set_imr(ah, 0); 2914 synchronize_irq(ah->irq); 2915 ath5k_stop_tasklets(ah); 2916 2917 /* Save ani mode and disable ANI during 2918 * reset. If we don't we might get false 2919 * PHY error interrupts. */ 2920 ani_mode = ah->ani_state.ani_mode; 2921 ath5k_ani_init(ah, ATH5K_ANI_MODE_OFF); 2922 2923 /* We are going to empty hw queues 2924 * so we should also free any remaining 2925 * tx buffers */ 2926 ath5k_drain_tx_buffs(ah); 2927 2928 /* Stop PCU */ 2929 ath5k_hw_stop_rx_pcu(ah); 2930 2931 /* Stop DMA 2932 * 2933 * Note: If DMA didn't stop continue 2934 * since only a reset will fix it. 2935 */ 2936 ret = ath5k_hw_dma_stop(ah); 2937 2938 /* RF Bus grant won't work if we have pending 2939 * frames 2940 */ 2941 if (ret && fast) { 2942 ATH5K_DBG(ah, ATH5K_DEBUG_RESET, 2943 "DMA didn't stop, falling back to normal reset\n"); 2944 fast = false; 2945 } 2946 2947 if (chan) 2948 ah->curchan = chan; 2949 2950 ret = ath5k_hw_reset(ah, ah->opmode, ah->curchan, fast, skip_pcu); 2951 if (ret) { 2952 ATH5K_ERR(ah, "can't reset hardware (%d)\n", ret); 2953 goto err; 2954 } 2955 2956 ret = ath5k_rx_start(ah); 2957 if (ret) { 2958 ATH5K_ERR(ah, "can't start recv logic\n"); 2959 goto err; 2960 } 2961 2962 ath5k_ani_init(ah, ani_mode); 2963 2964 /* 2965 * Set calibration intervals 2966 * 2967 * Note: We don't need to run calibration imediately 2968 * since some initial calibration is done on reset 2969 * even for fast channel switching. Also on scanning 2970 * this will get set again and again and it won't get 2971 * executed unless we connect somewhere and spend some 2972 * time on the channel (that's what calibration needs 2973 * anyway to be accurate). 2974 */ 2975 ah->ah_cal_next_full = jiffies + 2976 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_FULL); 2977 ah->ah_cal_next_ani = jiffies + 2978 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_ANI); 2979 ah->ah_cal_next_short = jiffies + 2980 msecs_to_jiffies(ATH5K_TUNE_CALIBRATION_INTERVAL_SHORT); 2981 2982 ewma_beacon_rssi_init(&ah->ah_beacon_rssi_avg); 2983 2984 /* clear survey data and cycle counters */ 2985 memset(&ah->survey, 0, sizeof(ah->survey)); 2986 spin_lock_bh(&common->cc_lock); 2987 ath_hw_cycle_counters_update(common); 2988 memset(&common->cc_survey, 0, sizeof(common->cc_survey)); 2989 memset(&common->cc_ani, 0, sizeof(common->cc_ani)); 2990 spin_unlock_bh(&common->cc_lock); 2991 2992 /* 2993 * Change channels and update the h/w rate map if we're switching; 2994 * e.g. 11a to 11b/g. 2995 * 2996 * We may be doing a reset in response to an ioctl that changes the 2997 * channel so update any state that might change as a result. 2998 * 2999 * XXX needed? 3000 */ 3001 /* ath5k_chan_change(ah, c); */ 3002 3003 __clear_bit(ATH_STAT_RESET, ah->status); 3004 3005 ath5k_beacon_config(ah); 3006 /* intrs are enabled by ath5k_beacon_config */ 3007 3008 ieee80211_wake_queues(ah->hw); 3009 3010 return 0; 3011 err: 3012 return ret; 3013 } 3014 3015 static void ath5k_reset_work(struct work_struct *work) 3016 { 3017 struct ath5k_hw *ah = container_of(work, struct ath5k_hw, 3018 reset_work); 3019 3020 mutex_lock(&ah->lock); 3021 ath5k_reset(ah, NULL, true); 3022 mutex_unlock(&ah->lock); 3023 } 3024 3025 static int 3026 ath5k_init(struct ieee80211_hw *hw) 3027 { 3028 3029 struct ath5k_hw *ah = hw->priv; 3030 struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah); 3031 struct ath5k_txq *txq; 3032 u8 mac[ETH_ALEN] = {}; 3033 int ret; 3034 3035 3036 /* 3037 * Collect the channel list. The 802.11 layer 3038 * is responsible for filtering this list based 3039 * on settings like the phy mode and regulatory 3040 * domain restrictions. 3041 */ 3042 ret = ath5k_setup_bands(hw); 3043 if (ret) { 3044 ATH5K_ERR(ah, "can't get channels\n"); 3045 goto err; 3046 } 3047 3048 /* 3049 * Allocate tx+rx descriptors and populate the lists. 3050 */ 3051 ret = ath5k_desc_alloc(ah); 3052 if (ret) { 3053 ATH5K_ERR(ah, "can't allocate descriptors\n"); 3054 goto err; 3055 } 3056 3057 /* 3058 * Allocate hardware transmit queues: one queue for 3059 * beacon frames and one data queue for each QoS 3060 * priority. Note that hw functions handle resetting 3061 * these queues at the needed time. 3062 */ 3063 ret = ath5k_beaconq_setup(ah); 3064 if (ret < 0) { 3065 ATH5K_ERR(ah, "can't setup a beacon xmit queue\n"); 3066 goto err_desc; 3067 } 3068 ah->bhalq = ret; 3069 ah->cabq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_CAB, 0); 3070 if (IS_ERR(ah->cabq)) { 3071 ATH5K_ERR(ah, "can't setup cab queue\n"); 3072 ret = PTR_ERR(ah->cabq); 3073 goto err_bhal; 3074 } 3075 3076 /* 5211 and 5212 usually support 10 queues but we better rely on the 3077 * capability information */ 3078 if (ah->ah_capabilities.cap_queues.q_tx_num >= 6) { 3079 /* This order matches mac80211's queue priority, so we can 3080 * directly use the mac80211 queue number without any mapping */ 3081 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VO); 3082 if (IS_ERR(txq)) { 3083 ATH5K_ERR(ah, "can't setup xmit queue\n"); 3084 ret = PTR_ERR(txq); 3085 goto err_queues; 3086 } 3087 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_VI); 3088 if (IS_ERR(txq)) { 3089 ATH5K_ERR(ah, "can't setup xmit queue\n"); 3090 ret = PTR_ERR(txq); 3091 goto err_queues; 3092 } 3093 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); 3094 if (IS_ERR(txq)) { 3095 ATH5K_ERR(ah, "can't setup xmit queue\n"); 3096 ret = PTR_ERR(txq); 3097 goto err_queues; 3098 } 3099 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BK); 3100 if (IS_ERR(txq)) { 3101 ATH5K_ERR(ah, "can't setup xmit queue\n"); 3102 ret = PTR_ERR(txq); 3103 goto err_queues; 3104 } 3105 hw->queues = 4; 3106 } else { 3107 /* older hardware (5210) can only support one data queue */ 3108 txq = ath5k_txq_setup(ah, AR5K_TX_QUEUE_DATA, AR5K_WME_AC_BE); 3109 if (IS_ERR(txq)) { 3110 ATH5K_ERR(ah, "can't setup xmit queue\n"); 3111 ret = PTR_ERR(txq); 3112 goto err_queues; 3113 } 3114 hw->queues = 1; 3115 } 3116 3117 tasklet_setup(&ah->rxtq, ath5k_tasklet_rx); 3118 tasklet_setup(&ah->txtq, ath5k_tasklet_tx); 3119 tasklet_setup(&ah->beacontq, ath5k_tasklet_beacon); 3120 tasklet_setup(&ah->ani_tasklet, ath5k_tasklet_ani); 3121 3122 INIT_WORK(&ah->reset_work, ath5k_reset_work); 3123 INIT_WORK(&ah->calib_work, ath5k_calibrate_work); 3124 INIT_DELAYED_WORK(&ah->tx_complete_work, ath5k_tx_complete_poll_work); 3125 3126 ret = ath5k_hw_common(ah)->bus_ops->eeprom_read_mac(ah, mac); 3127 if (ret) { 3128 ATH5K_ERR(ah, "unable to read address from EEPROM\n"); 3129 goto err_queues; 3130 } 3131 3132 SET_IEEE80211_PERM_ADDR(hw, mac); 3133 /* All MAC address bits matter for ACKs */ 3134 ath5k_update_bssid_mask_and_opmode(ah, NULL); 3135 3136 regulatory->current_rd = ah->ah_capabilities.cap_eeprom.ee_regdomain; 3137 ret = ath_regd_init(regulatory, hw->wiphy, ath5k_reg_notifier); 3138 if (ret) { 3139 ATH5K_ERR(ah, "can't initialize regulatory system\n"); 3140 goto err_queues; 3141 } 3142 3143 ret = ieee80211_register_hw(hw); 3144 if (ret) { 3145 ATH5K_ERR(ah, "can't register ieee80211 hw\n"); 3146 goto err_queues; 3147 } 3148 3149 if (!ath_is_world_regd(regulatory)) 3150 regulatory_hint(hw->wiphy, regulatory->alpha2); 3151 3152 ath5k_init_leds(ah); 3153 3154 ath5k_sysfs_register(ah); 3155 3156 return 0; 3157 err_queues: 3158 ath5k_txq_release(ah); 3159 err_bhal: 3160 ath5k_hw_release_tx_queue(ah, ah->bhalq); 3161 err_desc: 3162 ath5k_desc_free(ah); 3163 err: 3164 return ret; 3165 } 3166 3167 void 3168 ath5k_deinit_ah(struct ath5k_hw *ah) 3169 { 3170 struct ieee80211_hw *hw = ah->hw; 3171 3172 /* 3173 * NB: the order of these is important: 3174 * o call the 802.11 layer before detaching ath5k_hw to 3175 * ensure callbacks into the driver to delete global 3176 * key cache entries can be handled 3177 * o reclaim the tx queue data structures after calling 3178 * the 802.11 layer as we'll get called back to reclaim 3179 * node state and potentially want to use them 3180 * o to cleanup the tx queues the hal is called, so detach 3181 * it last 3182 * XXX: ??? detach ath5k_hw ??? 3183 * Other than that, it's straightforward... 3184 */ 3185 ieee80211_unregister_hw(hw); 3186 ath5k_desc_free(ah); 3187 ath5k_txq_release(ah); 3188 ath5k_hw_release_tx_queue(ah, ah->bhalq); 3189 ath5k_unregister_leds(ah); 3190 3191 ath5k_sysfs_unregister(ah); 3192 /* 3193 * NB: can't reclaim these until after ieee80211_ifdetach 3194 * returns because we'll get called back to reclaim node 3195 * state and potentially want to use them. 3196 */ 3197 ath5k_hw_deinit(ah); 3198 free_irq(ah->irq, ah); 3199 } 3200 3201 bool 3202 ath5k_any_vif_assoc(struct ath5k_hw *ah) 3203 { 3204 struct ath5k_vif_iter_data iter_data; 3205 iter_data.hw_macaddr = NULL; 3206 iter_data.any_assoc = false; 3207 iter_data.need_set_hw_addr = false; 3208 iter_data.found_active = true; 3209 3210 ieee80211_iterate_active_interfaces_atomic( 3211 ah->hw, IEEE80211_IFACE_ITER_RESUME_ALL, 3212 ath5k_vif_iter, &iter_data); 3213 return iter_data.any_assoc; 3214 } 3215 3216 void 3217 ath5k_set_beacon_filter(struct ieee80211_hw *hw, bool enable) 3218 { 3219 struct ath5k_hw *ah = hw->priv; 3220 u32 rfilt; 3221 rfilt = ath5k_hw_get_rx_filter(ah); 3222 if (enable) 3223 rfilt |= AR5K_RX_FILTER_BEACON; 3224 else 3225 rfilt &= ~AR5K_RX_FILTER_BEACON; 3226 ath5k_hw_set_rx_filter(ah, rfilt); 3227 ah->filter_flags = rfilt; 3228 } 3229 3230 void _ath5k_printk(const struct ath5k_hw *ah, const char *level, 3231 const char *fmt, ...) 3232 { 3233 struct va_format vaf; 3234 va_list args; 3235 3236 va_start(args, fmt); 3237 3238 vaf.fmt = fmt; 3239 vaf.va = &args; 3240 3241 if (ah && ah->hw) 3242 printk("%s" pr_fmt("%s: %pV"), 3243 level, wiphy_name(ah->hw->wiphy), &vaf); 3244 else 3245 printk("%s" pr_fmt("%pV"), level, &vaf); 3246 3247 va_end(args); 3248 } 3249