1 /* 2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org> 3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com> 4 * 5 * Permission to use, copy, modify, and distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _ATH5K_H 19 #define _ATH5K_H 20 21 /* TODO: Clean up channel debuging -doesn't work anyway- and start 22 * working on reg. control code using all available eeprom information 23 * -rev. engineering needed- */ 24 #define CHAN_DEBUG 0 25 26 #include <linux/io.h> 27 #include <linux/types.h> 28 #include <linux/average.h> 29 #include <net/mac80211.h> 30 31 /* RX/TX descriptor hw structs 32 * TODO: Driver part should only see sw structs */ 33 #include "desc.h" 34 35 /* EEPROM structs/offsets 36 * TODO: Make a more generic struct (eg. add more stuff to ath5k_capabilities) 37 * and clean up common bits, then introduce set/get functions in eeprom.c */ 38 #include "eeprom.h" 39 #include "../ath.h" 40 41 /* PCI IDs */ 42 #define PCI_DEVICE_ID_ATHEROS_AR5210 0x0007 /* AR5210 */ 43 #define PCI_DEVICE_ID_ATHEROS_AR5311 0x0011 /* AR5311 */ 44 #define PCI_DEVICE_ID_ATHEROS_AR5211 0x0012 /* AR5211 */ 45 #define PCI_DEVICE_ID_ATHEROS_AR5212 0x0013 /* AR5212 */ 46 #define PCI_DEVICE_ID_3COM_3CRDAG675 0x0013 /* 3CRDAG675 (Atheros AR5212) */ 47 #define PCI_DEVICE_ID_3COM_2_3CRPAG175 0x0013 /* 3CRPAG175 (Atheros AR5212) */ 48 #define PCI_DEVICE_ID_ATHEROS_AR5210_AP 0x0207 /* AR5210 (Early) */ 49 #define PCI_DEVICE_ID_ATHEROS_AR5212_IBM 0x1014 /* AR5212 (IBM MiniPCI) */ 50 #define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT 0x1107 /* AR5210 (no eeprom) */ 51 #define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT 0x1113 /* AR5212 (no eeprom) */ 52 #define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT 0x1112 /* AR5211 (no eeprom) */ 53 #define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA 0xf013 /* AR5212 (emulation board) */ 54 #define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY 0xff12 /* AR5211 (emulation board) */ 55 #define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B 0xf11b /* AR5211 (emulation board) */ 56 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */ 57 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */ 58 #define PCI_DEVICE_ID_ATHEROS_AR5312_REV8 0x0058 /* AR5312 WMAC (AP43-030) */ 59 #define PCI_DEVICE_ID_ATHEROS_AR5212_0014 0x0014 /* AR5212 compatible */ 60 #define PCI_DEVICE_ID_ATHEROS_AR5212_0015 0x0015 /* AR5212 compatible */ 61 #define PCI_DEVICE_ID_ATHEROS_AR5212_0016 0x0016 /* AR5212 compatible */ 62 #define PCI_DEVICE_ID_ATHEROS_AR5212_0017 0x0017 /* AR5212 compatible */ 63 #define PCI_DEVICE_ID_ATHEROS_AR5212_0018 0x0018 /* AR5212 compatible */ 64 #define PCI_DEVICE_ID_ATHEROS_AR5212_0019 0x0019 /* AR5212 compatible */ 65 #define PCI_DEVICE_ID_ATHEROS_AR2413 0x001a /* AR2413 (Griffin-lite) */ 66 #define PCI_DEVICE_ID_ATHEROS_AR5413 0x001b /* AR5413 (Eagle) */ 67 #define PCI_DEVICE_ID_ATHEROS_AR5424 0x001c /* AR5424 (Condor PCI-E) */ 68 #define PCI_DEVICE_ID_ATHEROS_AR5416 0x0023 /* AR5416 */ 69 #define PCI_DEVICE_ID_ATHEROS_AR5418 0x0024 /* AR5418 */ 70 71 /****************************\ 72 GENERIC DRIVER DEFINITIONS 73 \****************************/ 74 75 #define ATH5K_PRINTF(fmt, ...) printk("%s: " fmt, __func__, ##__VA_ARGS__) 76 77 #define ATH5K_PRINTK(_sc, _level, _fmt, ...) \ 78 printk(_level "ath5k %s: " _fmt, \ 79 ((_sc) && (_sc)->hw) ? wiphy_name((_sc)->hw->wiphy) : "", \ 80 ##__VA_ARGS__) 81 82 #define ATH5K_PRINTK_LIMIT(_sc, _level, _fmt, ...) do { \ 83 if (net_ratelimit()) \ 84 ATH5K_PRINTK(_sc, _level, _fmt, ##__VA_ARGS__); \ 85 } while (0) 86 87 #define ATH5K_INFO(_sc, _fmt, ...) \ 88 ATH5K_PRINTK(_sc, KERN_INFO, _fmt, ##__VA_ARGS__) 89 90 #define ATH5K_WARN(_sc, _fmt, ...) \ 91 ATH5K_PRINTK_LIMIT(_sc, KERN_WARNING, _fmt, ##__VA_ARGS__) 92 93 #define ATH5K_ERR(_sc, _fmt, ...) \ 94 ATH5K_PRINTK_LIMIT(_sc, KERN_ERR, _fmt, ##__VA_ARGS__) 95 96 /* 97 * AR5K REGISTER ACCESS 98 */ 99 100 /* Some macros to read/write fields */ 101 102 /* First shift, then mask */ 103 #define AR5K_REG_SM(_val, _flags) \ 104 (((_val) << _flags##_S) & (_flags)) 105 106 /* First mask, then shift */ 107 #define AR5K_REG_MS(_val, _flags) \ 108 (((_val) & (_flags)) >> _flags##_S) 109 110 /* Some registers can hold multiple values of interest. For this 111 * reason when we want to write to these registers we must first 112 * retrieve the values which we do not want to clear (lets call this 113 * old_data) and then set the register with this and our new_value: 114 * ( old_data | new_value) */ 115 #define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \ 116 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \ 117 (((_val) << _flags##_S) & (_flags)), _reg) 118 119 #define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \ 120 ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \ 121 (_mask)) | (_flags), _reg) 122 123 #define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \ 124 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg) 125 126 #define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \ 127 ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg) 128 129 /* Access to PHY registers */ 130 #define AR5K_PHY_READ(ah, _reg) \ 131 ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2)) 132 133 #define AR5K_PHY_WRITE(ah, _reg, _val) \ 134 ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2)) 135 136 /* Access QCU registers per queue */ 137 #define AR5K_REG_READ_Q(ah, _reg, _queue) \ 138 (ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \ 139 140 #define AR5K_REG_WRITE_Q(ah, _reg, _queue) \ 141 ath5k_hw_reg_write(ah, (1 << _queue), _reg) 142 143 #define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \ 144 _reg |= 1 << _queue; \ 145 } while (0) 146 147 #define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \ 148 _reg &= ~(1 << _queue); \ 149 } while (0) 150 151 /* Used while writing initvals */ 152 #define AR5K_REG_WAIT(_i) do { \ 153 if (_i % 64) \ 154 udelay(1); \ 155 } while (0) 156 157 /* 158 * Some tuneable values (these should be changeable by the user) 159 * TODO: Make use of them and add more options OR use debug/configfs 160 */ 161 #define AR5K_TUNE_DMA_BEACON_RESP 2 162 #define AR5K_TUNE_SW_BEACON_RESP 10 163 #define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF 0 164 #define AR5K_TUNE_RADAR_ALERT false 165 #define AR5K_TUNE_MIN_TX_FIFO_THRES 1 166 #define AR5K_TUNE_MAX_TX_FIFO_THRES ((IEEE80211_MAX_FRAME_LEN / 64) + 1) 167 #define AR5K_TUNE_REGISTER_TIMEOUT 20000 168 /* Register for RSSI threshold has a mask of 0xff, so 255 seems to 169 * be the max value. */ 170 #define AR5K_TUNE_RSSI_THRES 129 171 /* This must be set when setting the RSSI threshold otherwise it can 172 * prevent a reset. If AR5K_RSSI_THR is read after writing to it 173 * the BMISS_THRES will be seen as 0, seems harware doesn't keep 174 * track of it. Max value depends on harware. For AR5210 this is just 7. 175 * For AR5211+ this seems to be up to 255. */ 176 #define AR5K_TUNE_BMISS_THRES 7 177 #define AR5K_TUNE_REGISTER_DWELL_TIME 20000 178 #define AR5K_TUNE_BEACON_INTERVAL 100 179 #define AR5K_TUNE_AIFS 2 180 #define AR5K_TUNE_AIFS_11B 2 181 #define AR5K_TUNE_AIFS_XR 0 182 #define AR5K_TUNE_CWMIN 15 183 #define AR5K_TUNE_CWMIN_11B 31 184 #define AR5K_TUNE_CWMIN_XR 3 185 #define AR5K_TUNE_CWMAX 1023 186 #define AR5K_TUNE_CWMAX_11B 1023 187 #define AR5K_TUNE_CWMAX_XR 7 188 #define AR5K_TUNE_NOISE_FLOOR -72 189 #define AR5K_TUNE_CCA_MAX_GOOD_VALUE -95 190 #define AR5K_TUNE_MAX_TXPOWER 63 191 #define AR5K_TUNE_DEFAULT_TXPOWER 25 192 #define AR5K_TUNE_TPC_TXPOWER false 193 #define ATH5K_TUNE_CALIBRATION_INTERVAL_FULL 10000 /* 10 sec */ 194 #define ATH5K_TUNE_CALIBRATION_INTERVAL_ANI 1000 /* 1 sec */ 195 #define ATH5K_TUNE_CALIBRATION_INTERVAL_NF 60000 /* 60 sec */ 196 197 #define ATH5K_TX_COMPLETE_POLL_INT 3000 /* 3 sec */ 198 199 #define AR5K_INIT_CARR_SENSE_EN 1 200 201 /*Swap RX/TX Descriptor for big endian archs*/ 202 #if defined(__BIG_ENDIAN) 203 #define AR5K_INIT_CFG ( \ 204 AR5K_CFG_SWTD | AR5K_CFG_SWRD \ 205 ) 206 #else 207 #define AR5K_INIT_CFG 0x00000000 208 #endif 209 210 /* Initial values */ 211 #define AR5K_INIT_CYCRSSI_THR1 2 212 213 /* Tx retry limits */ 214 #define AR5K_INIT_SH_RETRY 10 215 #define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY 216 /* For station mode */ 217 #define AR5K_INIT_SSH_RETRY 32 218 #define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY 219 #define AR5K_INIT_TX_RETRY 10 220 221 222 /* Slot time */ 223 #define AR5K_INIT_SLOT_TIME_TURBO 6 224 #define AR5K_INIT_SLOT_TIME_DEFAULT 9 225 #define AR5K_INIT_SLOT_TIME_HALF_RATE 13 226 #define AR5K_INIT_SLOT_TIME_QUARTER_RATE 21 227 #define AR5K_INIT_SLOT_TIME_B 20 228 #define AR5K_SLOT_TIME_MAX 0xffff 229 230 /* SIFS */ 231 #define AR5K_INIT_SIFS_TURBO 6 232 /* XXX: 8 from initvals 10 from standard */ 233 #define AR5K_INIT_SIFS_DEFAULT_BG 8 234 #define AR5K_INIT_SIFS_DEFAULT_A 16 235 #define AR5K_INIT_SIFS_HALF_RATE 32 236 #define AR5K_INIT_SIFS_QUARTER_RATE 64 237 238 /* Used to calculate tx time for non 5/10/40MHz 239 * operation */ 240 /* It's preamble time + signal time (16 + 4) */ 241 #define AR5K_INIT_OFDM_PREAMPLE_TIME 20 242 /* Preamble time for 40MHz (turbo) operation (min ?) */ 243 #define AR5K_INIT_OFDM_PREAMBLE_TIME_MIN 14 244 #define AR5K_INIT_OFDM_SYMBOL_TIME 4 245 #define AR5K_INIT_OFDM_PLCP_BITS 22 246 247 /* Rx latency for 5 and 10MHz operation (max ?) */ 248 #define AR5K_INIT_RX_LAT_MAX 63 249 /* Tx latencies from initvals (5212 only but no problem 250 * because we only tweak them on 5212) */ 251 #define AR5K_INIT_TX_LAT_A 54 252 #define AR5K_INIT_TX_LAT_BG 384 253 /* Tx latency for 40MHz (turbo) operation (min ?) */ 254 #define AR5K_INIT_TX_LAT_MIN 32 255 /* Default Tx/Rx latencies (same for 5211)*/ 256 #define AR5K_INIT_TX_LATENCY_5210 54 257 #define AR5K_INIT_RX_LATENCY_5210 29 258 259 /* Tx frame to Tx data start delay */ 260 #define AR5K_INIT_TXF2TXD_START_DEFAULT 14 261 #define AR5K_INIT_TXF2TXD_START_DELAY_10MHZ 12 262 #define AR5K_INIT_TXF2TXD_START_DELAY_5MHZ 13 263 264 /* We need to increase PHY switch and agc settling time 265 * on turbo mode */ 266 #define AR5K_SWITCH_SETTLING 5760 267 #define AR5K_SWITCH_SETTLING_TURBO 7168 268 269 #define AR5K_AGC_SETTLING 28 270 /* 38 on 5210 but shouldn't matter */ 271 #define AR5K_AGC_SETTLING_TURBO 37 272 273 274 /* GENERIC CHIPSET DEFINITIONS */ 275 276 /* MAC Chips */ 277 enum ath5k_version { 278 AR5K_AR5210 = 0, 279 AR5K_AR5211 = 1, 280 AR5K_AR5212 = 2, 281 }; 282 283 /* PHY Chips */ 284 enum ath5k_radio { 285 AR5K_RF5110 = 0, 286 AR5K_RF5111 = 1, 287 AR5K_RF5112 = 2, 288 AR5K_RF2413 = 3, 289 AR5K_RF5413 = 4, 290 AR5K_RF2316 = 5, 291 AR5K_RF2317 = 6, 292 AR5K_RF2425 = 7, 293 }; 294 295 /* 296 * Common silicon revision/version values 297 */ 298 299 enum ath5k_srev_type { 300 AR5K_VERSION_MAC, 301 AR5K_VERSION_RAD, 302 }; 303 304 struct ath5k_srev_name { 305 const char *sr_name; 306 enum ath5k_srev_type sr_type; 307 u_int sr_val; 308 }; 309 310 #define AR5K_SREV_UNKNOWN 0xffff 311 312 #define AR5K_SREV_AR5210 0x00 /* Crete */ 313 #define AR5K_SREV_AR5311 0x10 /* Maui 1 */ 314 #define AR5K_SREV_AR5311A 0x20 /* Maui 2 */ 315 #define AR5K_SREV_AR5311B 0x30 /* Spirit */ 316 #define AR5K_SREV_AR5211 0x40 /* Oahu */ 317 #define AR5K_SREV_AR5212 0x50 /* Venice */ 318 #define AR5K_SREV_AR5312_R2 0x52 /* AP31 */ 319 #define AR5K_SREV_AR5212_V4 0x54 /* ??? */ 320 #define AR5K_SREV_AR5213 0x55 /* ??? */ 321 #define AR5K_SREV_AR5312_R7 0x57 /* AP30 */ 322 #define AR5K_SREV_AR2313_R8 0x58 /* AP43 */ 323 #define AR5K_SREV_AR5213A 0x59 /* Hainan */ 324 #define AR5K_SREV_AR2413 0x78 /* Griffin lite */ 325 #define AR5K_SREV_AR2414 0x70 /* Griffin */ 326 #define AR5K_SREV_AR2315_R6 0x86 /* AP51-Light */ 327 #define AR5K_SREV_AR2315_R7 0x87 /* AP51-Full */ 328 #define AR5K_SREV_AR5424 0x90 /* Condor */ 329 #define AR5K_SREV_AR2317_R1 0x90 /* AP61-Light */ 330 #define AR5K_SREV_AR2317_R2 0x91 /* AP61-Full */ 331 #define AR5K_SREV_AR5413 0xa4 /* Eagle lite */ 332 #define AR5K_SREV_AR5414 0xa0 /* Eagle */ 333 #define AR5K_SREV_AR2415 0xb0 /* Talon */ 334 #define AR5K_SREV_AR5416 0xc0 /* PCI-E */ 335 #define AR5K_SREV_AR5418 0xca /* PCI-E */ 336 #define AR5K_SREV_AR2425 0xe0 /* Swan */ 337 #define AR5K_SREV_AR2417 0xf0 /* Nala */ 338 339 #define AR5K_SREV_RAD_5110 0x00 340 #define AR5K_SREV_RAD_5111 0x10 341 #define AR5K_SREV_RAD_5111A 0x15 342 #define AR5K_SREV_RAD_2111 0x20 343 #define AR5K_SREV_RAD_5112 0x30 344 #define AR5K_SREV_RAD_5112A 0x35 345 #define AR5K_SREV_RAD_5112B 0x36 346 #define AR5K_SREV_RAD_2112 0x40 347 #define AR5K_SREV_RAD_2112A 0x45 348 #define AR5K_SREV_RAD_2112B 0x46 349 #define AR5K_SREV_RAD_2413 0x50 350 #define AR5K_SREV_RAD_5413 0x60 351 #define AR5K_SREV_RAD_2316 0x70 /* Cobra SoC */ 352 #define AR5K_SREV_RAD_2317 0x80 353 #define AR5K_SREV_RAD_5424 0xa0 /* Mostly same as 5413 */ 354 #define AR5K_SREV_RAD_2425 0xa2 355 #define AR5K_SREV_RAD_5133 0xc0 356 357 #define AR5K_SREV_PHY_5211 0x30 358 #define AR5K_SREV_PHY_5212 0x41 359 #define AR5K_SREV_PHY_5212A 0x42 360 #define AR5K_SREV_PHY_5212B 0x43 361 #define AR5K_SREV_PHY_2413 0x45 362 #define AR5K_SREV_PHY_5413 0x61 363 #define AR5K_SREV_PHY_2425 0x70 364 365 /* TODO add support to mac80211 for vendor-specific rates and modes */ 366 367 /* 368 * Some of this information is based on Documentation from: 369 * 370 * http://madwifi-project.org/wiki/ChipsetFeatures/SuperAG 371 * 372 * Modulation for Atheros' eXtended Range - range enhancing extension that is 373 * supposed to double the distance an Atheros client device can keep a 374 * connection with an Atheros access point. This is achieved by increasing 375 * the receiver sensitivity up to, -105dBm, which is about 20dB above what 376 * the 802.11 specifications demand. In addition, new (proprietary) data rates 377 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s. 378 * 379 * Please note that can you either use XR or TURBO but you cannot use both, 380 * they are exclusive. 381 * 382 */ 383 #define MODULATION_XR 0x00000200 384 /* 385 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a 386 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s 387 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g 388 * channels. To use this feature your Access Point must also suport it. 389 * There is also a distinction between "static" and "dynamic" turbo modes: 390 * 391 * - Static: is the dumb version: devices set to this mode stick to it until 392 * the mode is turned off. 393 * - Dynamic: is the intelligent version, the network decides itself if it 394 * is ok to use turbo. As soon as traffic is detected on adjacent channels 395 * (which would get used in turbo mode), or when a non-turbo station joins 396 * the network, turbo mode won't be used until the situation changes again. 397 * Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which 398 * monitors the used radio band in order to decide whether turbo mode may 399 * be used or not. 400 * 401 * This article claims Super G sticks to bonding of channels 5 and 6 for 402 * USA: 403 * 404 * http://www.pcworld.com/article/id,113428-page,1/article.html 405 * 406 * The channel bonding seems to be driver specific though. In addition to 407 * deciding what channels will be used, these "Turbo" modes are accomplished 408 * by also enabling the following features: 409 * 410 * - Bursting: allows multiple frames to be sent at once, rather than pausing 411 * after each frame. Bursting is a standards-compliant feature that can be 412 * used with any Access Point. 413 * - Fast frames: increases the amount of information that can be sent per 414 * frame, also resulting in a reduction of transmission overhead. It is a 415 * proprietary feature that needs to be supported by the Access Point. 416 * - Compression: data frames are compressed in real time using a Lempel Ziv 417 * algorithm. This is done transparently. Once this feature is enabled, 418 * compression and decompression takes place inside the chipset, without 419 * putting additional load on the host CPU. 420 * 421 */ 422 #define MODULATION_TURBO 0x00000080 423 424 enum ath5k_driver_mode { 425 AR5K_MODE_11A = 0, 426 AR5K_MODE_11B = 1, 427 AR5K_MODE_11G = 2, 428 AR5K_MODE_XR = 0, 429 AR5K_MODE_MAX = 3 430 }; 431 432 enum ath5k_ant_mode { 433 AR5K_ANTMODE_DEFAULT = 0, /* default antenna setup */ 434 AR5K_ANTMODE_FIXED_A = 1, /* only antenna A is present */ 435 AR5K_ANTMODE_FIXED_B = 2, /* only antenna B is present */ 436 AR5K_ANTMODE_SINGLE_AP = 3, /* sta locked on a single ap */ 437 AR5K_ANTMODE_SECTOR_AP = 4, /* AP with tx antenna set on tx desc */ 438 AR5K_ANTMODE_SECTOR_STA = 5, /* STA with tx antenna set on tx desc */ 439 AR5K_ANTMODE_DEBUG = 6, /* Debug mode -A -> Rx, B-> Tx- */ 440 AR5K_ANTMODE_MAX, 441 }; 442 443 enum ath5k_bw_mode { 444 AR5K_BWMODE_DEFAULT = 0, /* 20MHz, default operation */ 445 AR5K_BWMODE_5MHZ = 1, /* Quarter rate */ 446 AR5K_BWMODE_10MHZ = 2, /* Half rate */ 447 AR5K_BWMODE_40MHZ = 3 /* Turbo */ 448 }; 449 450 /****************\ 451 TX DEFINITIONS 452 \****************/ 453 454 /* 455 * TX Status descriptor 456 */ 457 struct ath5k_tx_status { 458 u16 ts_seqnum; 459 u16 ts_tstamp; 460 u8 ts_status; 461 u8 ts_rate[4]; 462 u8 ts_retry[4]; 463 u8 ts_final_idx; 464 s8 ts_rssi; 465 u8 ts_shortretry; 466 u8 ts_longretry; 467 u8 ts_virtcol; 468 u8 ts_antenna; 469 }; 470 471 #define AR5K_TXSTAT_ALTRATE 0x80 472 #define AR5K_TXERR_XRETRY 0x01 473 #define AR5K_TXERR_FILT 0x02 474 #define AR5K_TXERR_FIFO 0x04 475 476 /** 477 * enum ath5k_tx_queue - Queue types used to classify tx queues. 478 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue 479 * @AR5K_TX_QUEUE_DATA: A normal data queue 480 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue 481 * @AR5K_TX_QUEUE_BEACON: The beacon queue 482 * @AR5K_TX_QUEUE_CAB: The after-beacon queue 483 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue 484 */ 485 enum ath5k_tx_queue { 486 AR5K_TX_QUEUE_INACTIVE = 0, 487 AR5K_TX_QUEUE_DATA, 488 AR5K_TX_QUEUE_XR_DATA, 489 AR5K_TX_QUEUE_BEACON, 490 AR5K_TX_QUEUE_CAB, 491 AR5K_TX_QUEUE_UAPSD, 492 }; 493 494 #define AR5K_NUM_TX_QUEUES 10 495 #define AR5K_NUM_TX_QUEUES_NOQCU 2 496 497 /* 498 * Queue syb-types to classify normal data queues. 499 * These are the 4 Access Categories as defined in 500 * WME spec. 0 is the lowest priority and 4 is the 501 * highest. Normal data that hasn't been classified 502 * goes to the Best Effort AC. 503 */ 504 enum ath5k_tx_queue_subtype { 505 AR5K_WME_AC_BK = 0, /*Background traffic*/ 506 AR5K_WME_AC_BE, /*Best-effort (normal) traffic)*/ 507 AR5K_WME_AC_VI, /*Video traffic*/ 508 AR5K_WME_AC_VO, /*Voice traffic*/ 509 }; 510 511 /* 512 * Queue ID numbers as returned by the hw functions, each number 513 * represents a hw queue. If hw does not support hw queues 514 * (eg 5210) all data goes in one queue. These match 515 * d80211 definitions (net80211/MadWiFi don't use them). 516 */ 517 enum ath5k_tx_queue_id { 518 AR5K_TX_QUEUE_ID_NOQCU_DATA = 0, 519 AR5K_TX_QUEUE_ID_NOQCU_BEACON = 1, 520 AR5K_TX_QUEUE_ID_DATA_MIN = 0, /*IEEE80211_TX_QUEUE_DATA0*/ 521 AR5K_TX_QUEUE_ID_DATA_MAX = 4, /*IEEE80211_TX_QUEUE_DATA4*/ 522 AR5K_TX_QUEUE_ID_DATA_SVP = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/ 523 AR5K_TX_QUEUE_ID_CAB = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/ 524 AR5K_TX_QUEUE_ID_BEACON = 7, /*IEEE80211_TX_QUEUE_BEACON*/ 525 AR5K_TX_QUEUE_ID_UAPSD = 8, 526 AR5K_TX_QUEUE_ID_XR_DATA = 9, 527 }; 528 529 /* 530 * Flags to set hw queue's parameters... 531 */ 532 #define AR5K_TXQ_FLAG_TXOKINT_ENABLE 0x0001 /* Enable TXOK interrupt */ 533 #define AR5K_TXQ_FLAG_TXERRINT_ENABLE 0x0002 /* Enable TXERR interrupt */ 534 #define AR5K_TXQ_FLAG_TXEOLINT_ENABLE 0x0004 /* Enable TXEOL interrupt -not used- */ 535 #define AR5K_TXQ_FLAG_TXDESCINT_ENABLE 0x0008 /* Enable TXDESC interrupt -not used- */ 536 #define AR5K_TXQ_FLAG_TXURNINT_ENABLE 0x0010 /* Enable TXURN interrupt */ 537 #define AR5K_TXQ_FLAG_CBRORNINT_ENABLE 0x0020 /* Enable CBRORN interrupt */ 538 #define AR5K_TXQ_FLAG_CBRURNINT_ENABLE 0x0040 /* Enable CBRURN interrupt */ 539 #define AR5K_TXQ_FLAG_QTRIGINT_ENABLE 0x0080 /* Enable QTRIG interrupt */ 540 #define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE 0x0100 /* Enable TXNOFRM interrupt */ 541 #define AR5K_TXQ_FLAG_BACKOFF_DISABLE 0x0200 /* Disable random post-backoff */ 542 #define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300 /* Enable ready time expiry policy (?)*/ 543 #define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800 /* Enable backoff while bursting */ 544 #define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS 0x1000 /* Disable backoff while bursting */ 545 #define AR5K_TXQ_FLAG_COMPRESSION_ENABLE 0x2000 /* Enable hw compression -not implemented-*/ 546 547 /* 548 * A struct to hold tx queue's parameters 549 */ 550 struct ath5k_txq_info { 551 enum ath5k_tx_queue tqi_type; 552 enum ath5k_tx_queue_subtype tqi_subtype; 553 u16 tqi_flags; /* Tx queue flags (see above) */ 554 u8 tqi_aifs; /* Arbitrated Interframe Space */ 555 u16 tqi_cw_min; /* Minimum Contention Window */ 556 u16 tqi_cw_max; /* Maximum Contention Window */ 557 u32 tqi_cbr_period; /* Constant bit rate period */ 558 u32 tqi_cbr_overflow_limit; 559 u32 tqi_burst_time; 560 u32 tqi_ready_time; /* Time queue waits after an event */ 561 }; 562 563 /* 564 * Transmit packet types. 565 * used on tx control descriptor 566 */ 567 enum ath5k_pkt_type { 568 AR5K_PKT_TYPE_NORMAL = 0, 569 AR5K_PKT_TYPE_ATIM = 1, 570 AR5K_PKT_TYPE_PSPOLL = 2, 571 AR5K_PKT_TYPE_BEACON = 3, 572 AR5K_PKT_TYPE_PROBE_RESP = 4, 573 AR5K_PKT_TYPE_PIFS = 5, 574 }; 575 576 /* 577 * TX power and TPC settings 578 */ 579 #define AR5K_TXPOWER_OFDM(_r, _v) ( \ 580 ((0 & 1) << ((_v) + 6)) | \ 581 (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \ 582 ) 583 584 #define AR5K_TXPOWER_CCK(_r, _v) ( \ 585 (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v) \ 586 ) 587 588 /* 589 * DMA size definitions (2^(n+2)) 590 */ 591 enum ath5k_dmasize { 592 AR5K_DMASIZE_4B = 0, 593 AR5K_DMASIZE_8B, 594 AR5K_DMASIZE_16B, 595 AR5K_DMASIZE_32B, 596 AR5K_DMASIZE_64B, 597 AR5K_DMASIZE_128B, 598 AR5K_DMASIZE_256B, 599 AR5K_DMASIZE_512B 600 }; 601 602 603 /****************\ 604 RX DEFINITIONS 605 \****************/ 606 607 /* 608 * RX Status descriptor 609 */ 610 struct ath5k_rx_status { 611 u16 rs_datalen; 612 u16 rs_tstamp; 613 u8 rs_status; 614 u8 rs_phyerr; 615 s8 rs_rssi; 616 u8 rs_keyix; 617 u8 rs_rate; 618 u8 rs_antenna; 619 u8 rs_more; 620 }; 621 622 #define AR5K_RXERR_CRC 0x01 623 #define AR5K_RXERR_PHY 0x02 624 #define AR5K_RXERR_FIFO 0x04 625 #define AR5K_RXERR_DECRYPT 0x08 626 #define AR5K_RXERR_MIC 0x10 627 #define AR5K_RXKEYIX_INVALID ((u8) - 1) 628 #define AR5K_TXKEYIX_INVALID ((u32) - 1) 629 630 631 /**************************\ 632 BEACON TIMERS DEFINITIONS 633 \**************************/ 634 635 #define AR5K_BEACON_PERIOD 0x0000ffff 636 #define AR5K_BEACON_ENA 0x00800000 /*enable beacon xmit*/ 637 #define AR5K_BEACON_RESET_TSF 0x01000000 /*force a TSF reset*/ 638 639 640 /* 641 * TSF to TU conversion: 642 * 643 * TSF is a 64bit value in usec (microseconds). 644 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of 645 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024). 646 */ 647 #define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10) 648 649 650 /*******************************\ 651 GAIN OPTIMIZATION DEFINITIONS 652 \*******************************/ 653 654 enum ath5k_rfgain { 655 AR5K_RFGAIN_INACTIVE = 0, 656 AR5K_RFGAIN_ACTIVE, 657 AR5K_RFGAIN_READ_REQUESTED, 658 AR5K_RFGAIN_NEED_CHANGE, 659 }; 660 661 struct ath5k_gain { 662 u8 g_step_idx; 663 u8 g_current; 664 u8 g_target; 665 u8 g_low; 666 u8 g_high; 667 u8 g_f_corr; 668 u8 g_state; 669 }; 670 671 /********************\ 672 COMMON DEFINITIONS 673 \********************/ 674 675 #define AR5K_SLOT_TIME_9 396 676 #define AR5K_SLOT_TIME_20 880 677 #define AR5K_SLOT_TIME_MAX 0xffff 678 679 /* channel_flags */ 680 #define CHANNEL_CW_INT 0x0008 /* Contention Window interference detected */ 681 #define CHANNEL_CCK 0x0020 /* CCK channel */ 682 #define CHANNEL_OFDM 0x0040 /* OFDM channel */ 683 #define CHANNEL_2GHZ 0x0080 /* 2GHz channel. */ 684 #define CHANNEL_5GHZ 0x0100 /* 5GHz channel */ 685 #define CHANNEL_PASSIVE 0x0200 /* Only passive scan allowed */ 686 #define CHANNEL_DYN 0x0400 /* Dynamic CCK-OFDM channel (for g operation) */ 687 #define CHANNEL_XR 0x0800 /* XR channel */ 688 689 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM) 690 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK) 691 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM) 692 #define CHANNEL_X (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR) 693 694 #define CHANNEL_ALL (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ) 695 696 #define CHANNEL_MODES CHANNEL_ALL 697 698 /* 699 * Used internaly for reset_tx_queue). 700 * Also see struct struct ieee80211_channel. 701 */ 702 #define IS_CHAN_XR(_c) ((_c->hw_value & CHANNEL_XR) != 0) 703 #define IS_CHAN_B(_c) ((_c->hw_value & CHANNEL_B) != 0) 704 705 /* 706 * The following structure is used to map 2GHz channels to 707 * 5GHz Atheros channels. 708 * TODO: Clean up 709 */ 710 struct ath5k_athchan_2ghz { 711 u32 a2_flags; 712 u16 a2_athchan; 713 }; 714 715 716 /******************\ 717 RATE DEFINITIONS 718 \******************/ 719 720 /** 721 * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32. 722 * 723 * The rate code is used to get the RX rate or set the TX rate on the 724 * hardware descriptors. It is also used for internal modulation control 725 * and settings. 726 * 727 * This is the hardware rate map we are aware of: 728 * 729 * rate_code 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 730 * rate_kbps 3000 1000 ? ? ? 2000 500 48000 731 * 732 * rate_code 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 733 * rate_kbps 24000 12000 6000 54000 36000 18000 9000 ? 734 * 735 * rate_code 17 18 19 20 21 22 23 24 736 * rate_kbps ? ? ? ? ? ? ? 11000 737 * 738 * rate_code 25 26 27 28 29 30 31 32 739 * rate_kbps 5500 2000 1000 11000S 5500S 2000S ? ? 740 * 741 * "S" indicates CCK rates with short preamble. 742 * 743 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the 744 * lowest 4 bits, so they are the same as below with a 0xF mask. 745 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M). 746 * We handle this in ath5k_setup_bands(). 747 */ 748 #define AR5K_MAX_RATES 32 749 750 /* B */ 751 #define ATH5K_RATE_CODE_1M 0x1B 752 #define ATH5K_RATE_CODE_2M 0x1A 753 #define ATH5K_RATE_CODE_5_5M 0x19 754 #define ATH5K_RATE_CODE_11M 0x18 755 /* A and G */ 756 #define ATH5K_RATE_CODE_6M 0x0B 757 #define ATH5K_RATE_CODE_9M 0x0F 758 #define ATH5K_RATE_CODE_12M 0x0A 759 #define ATH5K_RATE_CODE_18M 0x0E 760 #define ATH5K_RATE_CODE_24M 0x09 761 #define ATH5K_RATE_CODE_36M 0x0D 762 #define ATH5K_RATE_CODE_48M 0x08 763 #define ATH5K_RATE_CODE_54M 0x0C 764 /* XR */ 765 #define ATH5K_RATE_CODE_XR_500K 0x07 766 #define ATH5K_RATE_CODE_XR_1M 0x02 767 #define ATH5K_RATE_CODE_XR_2M 0x06 768 #define ATH5K_RATE_CODE_XR_3M 0x01 769 770 /* adding this flag to rate_code enables short preamble */ 771 #define AR5K_SET_SHORT_PREAMBLE 0x04 772 773 /* 774 * Crypto definitions 775 */ 776 777 #define AR5K_KEYCACHE_SIZE 8 778 779 /***********************\ 780 HW RELATED DEFINITIONS 781 \***********************/ 782 783 /* 784 * Misc definitions 785 */ 786 #define AR5K_RSSI_EP_MULTIPLIER (1<<7) 787 788 #define AR5K_ASSERT_ENTRY(_e, _s) do { \ 789 if (_e >= _s) \ 790 return (false); \ 791 } while (0) 792 793 /* 794 * Hardware interrupt abstraction 795 */ 796 797 /** 798 * enum ath5k_int - Hardware interrupt masks helpers 799 * 800 * @AR5K_INT_RX: mask to identify received frame interrupts, of type 801 * AR5K_ISR_RXOK or AR5K_ISR_RXERR 802 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?) 803 * @AR5K_INT_RXNOFRM: No frame received (?) 804 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The 805 * Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's 806 * LinkPtr is NULL. For more details, refer to: 807 * http://www.freepatentsonline.com/20030225739.html 808 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors). 809 * Note that Rx overrun is not always fatal, on some chips we can continue 810 * operation without reseting the card, that's why int_fatal is not 811 * common for all chips. 812 * @AR5K_INT_TX: mask to identify received frame interrupts, of type 813 * AR5K_ISR_TXOK or AR5K_ISR_TXERR 814 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?) 815 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold 816 * We currently do increments on interrupt by 817 * (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2 818 * @AR5K_INT_MIB: Indicates the either Management Information Base counters or 819 * one of the PHY error counters reached the maximum value and should be 820 * read and cleared. 821 * @AR5K_INT_RXPHY: RX PHY Error 822 * @AR5K_INT_RXKCM: RX Key cache miss 823 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a 824 * beacon that must be handled in software. The alternative is if you 825 * have VEOL support, in that case you let the hardware deal with things. 826 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing 827 * beacons from the AP have associated with, we should probably try to 828 * reassociate. When in IBSS mode this might mean we have not received 829 * any beacons from any local stations. Note that every station in an 830 * IBSS schedules to send beacons at the Target Beacon Transmission Time 831 * (TBTT) with a random backoff. 832 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ?? 833 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now 834 * until properly handled 835 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA 836 * errors. These types of errors we can enable seem to be of type 837 * AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR. 838 * @AR5K_INT_GLOBAL: Used to clear and set the IER 839 * @AR5K_INT_NOCARD: signals the card has been removed 840 * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same 841 * bit value 842 * 843 * These are mapped to take advantage of some common bits 844 * between the MACs, to be able to set intr properties 845 * easier. Some of them are not used yet inside hw.c. Most map 846 * to the respective hw interrupt value as they are common amogst different 847 * MACs. 848 */ 849 enum ath5k_int { 850 AR5K_INT_RXOK = 0x00000001, 851 AR5K_INT_RXDESC = 0x00000002, 852 AR5K_INT_RXERR = 0x00000004, 853 AR5K_INT_RXNOFRM = 0x00000008, 854 AR5K_INT_RXEOL = 0x00000010, 855 AR5K_INT_RXORN = 0x00000020, 856 AR5K_INT_TXOK = 0x00000040, 857 AR5K_INT_TXDESC = 0x00000080, 858 AR5K_INT_TXERR = 0x00000100, 859 AR5K_INT_TXNOFRM = 0x00000200, 860 AR5K_INT_TXEOL = 0x00000400, 861 AR5K_INT_TXURN = 0x00000800, 862 AR5K_INT_MIB = 0x00001000, 863 AR5K_INT_SWI = 0x00002000, 864 AR5K_INT_RXPHY = 0x00004000, 865 AR5K_INT_RXKCM = 0x00008000, 866 AR5K_INT_SWBA = 0x00010000, 867 AR5K_INT_BRSSI = 0x00020000, 868 AR5K_INT_BMISS = 0x00040000, 869 AR5K_INT_FATAL = 0x00080000, /* Non common */ 870 AR5K_INT_BNR = 0x00100000, /* Non common */ 871 AR5K_INT_TIM = 0x00200000, /* Non common */ 872 AR5K_INT_DTIM = 0x00400000, /* Non common */ 873 AR5K_INT_DTIM_SYNC = 0x00800000, /* Non common */ 874 AR5K_INT_GPIO = 0x01000000, 875 AR5K_INT_BCN_TIMEOUT = 0x02000000, /* Non common */ 876 AR5K_INT_CAB_TIMEOUT = 0x04000000, /* Non common */ 877 AR5K_INT_RX_DOPPLER = 0x08000000, /* Non common */ 878 AR5K_INT_QCBRORN = 0x10000000, /* Non common */ 879 AR5K_INT_QCBRURN = 0x20000000, /* Non common */ 880 AR5K_INT_QTRIG = 0x40000000, /* Non common */ 881 AR5K_INT_GLOBAL = 0x80000000, 882 883 AR5K_INT_COMMON = AR5K_INT_RXOK 884 | AR5K_INT_RXDESC 885 | AR5K_INT_RXERR 886 | AR5K_INT_RXNOFRM 887 | AR5K_INT_RXEOL 888 | AR5K_INT_RXORN 889 | AR5K_INT_TXOK 890 | AR5K_INT_TXDESC 891 | AR5K_INT_TXERR 892 | AR5K_INT_TXNOFRM 893 | AR5K_INT_TXEOL 894 | AR5K_INT_TXURN 895 | AR5K_INT_MIB 896 | AR5K_INT_SWI 897 | AR5K_INT_RXPHY 898 | AR5K_INT_RXKCM 899 | AR5K_INT_SWBA 900 | AR5K_INT_BRSSI 901 | AR5K_INT_BMISS 902 | AR5K_INT_GPIO 903 | AR5K_INT_GLOBAL, 904 905 AR5K_INT_NOCARD = 0xffffffff 906 }; 907 908 /* mask which calibration is active at the moment */ 909 enum ath5k_calibration_mask { 910 AR5K_CALIBRATION_FULL = 0x01, 911 AR5K_CALIBRATION_SHORT = 0x02, 912 AR5K_CALIBRATION_ANI = 0x04, 913 }; 914 915 /* 916 * Power management 917 */ 918 enum ath5k_power_mode { 919 AR5K_PM_UNDEFINED = 0, 920 AR5K_PM_AUTO, 921 AR5K_PM_AWAKE, 922 AR5K_PM_FULL_SLEEP, 923 AR5K_PM_NETWORK_SLEEP, 924 }; 925 926 /* 927 * These match net80211 definitions (not used in 928 * mac80211). 929 * TODO: Clean this up 930 */ 931 #define AR5K_LED_INIT 0 /*IEEE80211_S_INIT*/ 932 #define AR5K_LED_SCAN 1 /*IEEE80211_S_SCAN*/ 933 #define AR5K_LED_AUTH 2 /*IEEE80211_S_AUTH*/ 934 #define AR5K_LED_ASSOC 3 /*IEEE80211_S_ASSOC*/ 935 #define AR5K_LED_RUN 4 /*IEEE80211_S_RUN*/ 936 937 /* GPIO-controlled software LED */ 938 #define AR5K_SOFTLED_PIN 0 939 #define AR5K_SOFTLED_ON 0 940 #define AR5K_SOFTLED_OFF 1 941 942 /* 943 * Chipset capabilities -see ath5k_hw_get_capability- 944 * get_capability function is not yet fully implemented 945 * in ath5k so most of these don't work yet... 946 * TODO: Implement these & merge with _TUNE_ stuff above 947 */ 948 enum ath5k_capability_type { 949 AR5K_CAP_REG_DMN = 0, /* Used to get current reg. domain id */ 950 AR5K_CAP_TKIP_MIC = 2, /* Can handle TKIP MIC in hardware */ 951 AR5K_CAP_TKIP_SPLIT = 3, /* TKIP uses split keys */ 952 AR5K_CAP_PHYCOUNTERS = 4, /* PHY error counters */ 953 AR5K_CAP_DIVERSITY = 5, /* Supports fast diversity */ 954 AR5K_CAP_NUM_TXQUEUES = 6, /* Used to get max number of hw txqueues */ 955 AR5K_CAP_VEOL = 7, /* Supports virtual EOL */ 956 AR5K_CAP_COMPRESSION = 8, /* Supports compression */ 957 AR5K_CAP_BURST = 9, /* Supports packet bursting */ 958 AR5K_CAP_FASTFRAME = 10, /* Supports fast frames */ 959 AR5K_CAP_TXPOW = 11, /* Used to get global tx power limit */ 960 AR5K_CAP_TPC = 12, /* Can do per-packet tx power control (needed for 802.11a) */ 961 AR5K_CAP_BSSIDMASK = 13, /* Supports bssid mask */ 962 AR5K_CAP_MCAST_KEYSRCH = 14, /* Supports multicast key search */ 963 AR5K_CAP_TSF_ADJUST = 15, /* Supports beacon tsf adjust */ 964 AR5K_CAP_XR = 16, /* Supports XR mode */ 965 AR5K_CAP_WME_TKIPMIC = 17, /* Supports TKIP MIC when using WMM */ 966 AR5K_CAP_CHAN_HALFRATE = 18, /* Supports half rate channels */ 967 AR5K_CAP_CHAN_QUARTERRATE = 19, /* Supports quarter rate channels */ 968 AR5K_CAP_RFSILENT = 20, /* Supports RFsilent */ 969 }; 970 971 972 /* XXX: we *may* move cap_range stuff to struct wiphy */ 973 struct ath5k_capabilities { 974 /* 975 * Supported PHY modes 976 * (ie. CHANNEL_A, CHANNEL_B, ...) 977 */ 978 DECLARE_BITMAP(cap_mode, AR5K_MODE_MAX); 979 980 /* 981 * Frequency range (without regulation restrictions) 982 */ 983 struct { 984 u16 range_2ghz_min; 985 u16 range_2ghz_max; 986 u16 range_5ghz_min; 987 u16 range_5ghz_max; 988 } cap_range; 989 990 /* 991 * Values stored in the EEPROM (some of them...) 992 */ 993 struct ath5k_eeprom_info cap_eeprom; 994 995 /* 996 * Queue information 997 */ 998 struct { 999 u8 q_tx_num; 1000 } cap_queues; 1001 1002 bool cap_has_phyerr_counters; 1003 }; 1004 1005 /* size of noise floor history (keep it a power of two) */ 1006 #define ATH5K_NF_CAL_HIST_MAX 8 1007 struct ath5k_nfcal_hist 1008 { 1009 s16 index; /* current index into nfval */ 1010 s16 nfval[ATH5K_NF_CAL_HIST_MAX]; /* last few noise floors */ 1011 }; 1012 1013 /** 1014 * struct avg_val - Helper structure for average calculation 1015 * @avg: contains the actual average value 1016 * @avg_weight: is used internally during calculation to prevent rounding errors 1017 */ 1018 struct ath5k_avg_val { 1019 int avg; 1020 int avg_weight; 1021 }; 1022 1023 /***************************************\ 1024 HARDWARE ABSTRACTION LAYER STRUCTURE 1025 \***************************************/ 1026 1027 /* 1028 * Misc defines 1029 */ 1030 1031 #define AR5K_MAX_GPIO 10 1032 #define AR5K_MAX_RF_BANKS 8 1033 1034 /* TODO: Clean up and merge with ath5k_softc */ 1035 struct ath5k_hw { 1036 struct ath_common common; 1037 1038 struct ath5k_softc *ah_sc; 1039 void __iomem *ah_iobase; 1040 1041 enum ath5k_int ah_imr; 1042 1043 struct ieee80211_channel *ah_current_channel; 1044 bool ah_calibration; 1045 bool ah_single_chip; 1046 1047 enum ath5k_version ah_version; 1048 enum ath5k_radio ah_radio; 1049 u32 ah_phy; 1050 u32 ah_mac_srev; 1051 u16 ah_mac_version; 1052 u16 ah_mac_revision; 1053 u16 ah_phy_revision; 1054 u16 ah_radio_5ghz_revision; 1055 u16 ah_radio_2ghz_revision; 1056 1057 #define ah_modes ah_capabilities.cap_mode 1058 #define ah_ee_version ah_capabilities.cap_eeprom.ee_version 1059 1060 u32 ah_limit_tx_retries; 1061 u8 ah_coverage_class; 1062 bool ah_ack_bitrate_high; 1063 u8 ah_bwmode; 1064 1065 /* Antenna Control */ 1066 u32 ah_ant_ctl[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX]; 1067 u8 ah_ant_mode; 1068 u8 ah_tx_ant; 1069 u8 ah_def_ant; 1070 bool ah_software_retry; 1071 1072 struct ath5k_capabilities ah_capabilities; 1073 1074 struct ath5k_txq_info ah_txq[AR5K_NUM_TX_QUEUES]; 1075 u32 ah_txq_status; 1076 u32 ah_txq_imr_txok; 1077 u32 ah_txq_imr_txerr; 1078 u32 ah_txq_imr_txurn; 1079 u32 ah_txq_imr_txdesc; 1080 u32 ah_txq_imr_txeol; 1081 u32 ah_txq_imr_cbrorn; 1082 u32 ah_txq_imr_cbrurn; 1083 u32 ah_txq_imr_qtrig; 1084 u32 ah_txq_imr_nofrm; 1085 u32 ah_txq_isr; 1086 u32 *ah_rf_banks; 1087 size_t ah_rf_banks_size; 1088 size_t ah_rf_regs_count; 1089 struct ath5k_gain ah_gain; 1090 u8 ah_offset[AR5K_MAX_RF_BANKS]; 1091 1092 1093 struct { 1094 /* Temporary tables used for interpolation */ 1095 u8 tmpL[AR5K_EEPROM_N_PD_GAINS] 1096 [AR5K_EEPROM_POWER_TABLE_SIZE]; 1097 u8 tmpR[AR5K_EEPROM_N_PD_GAINS] 1098 [AR5K_EEPROM_POWER_TABLE_SIZE]; 1099 u8 txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2]; 1100 u16 txp_rates_power_table[AR5K_MAX_RATES]; 1101 u8 txp_min_idx; 1102 bool txp_tpc; 1103 /* Values in 0.25dB units */ 1104 s16 txp_min_pwr; 1105 s16 txp_max_pwr; 1106 s16 txp_cur_pwr; 1107 /* Values in 0.5dB units */ 1108 s16 txp_offset; 1109 s16 txp_ofdm; 1110 s16 txp_cck_ofdm_gainf_delta; 1111 /* Value in dB units */ 1112 s16 txp_cck_ofdm_pwr_delta; 1113 bool txp_setup; 1114 } ah_txpower; 1115 1116 struct { 1117 bool r_enabled; 1118 int r_last_alert; 1119 struct ieee80211_channel r_last_channel; 1120 } ah_radar; 1121 1122 struct ath5k_nfcal_hist ah_nfcal_hist; 1123 1124 /* average beacon RSSI in our BSS (used by ANI) */ 1125 struct ewma ah_beacon_rssi_avg; 1126 1127 /* noise floor from last periodic calibration */ 1128 s32 ah_noise_floor; 1129 1130 /* Calibration timestamp */ 1131 unsigned long ah_cal_next_full; 1132 unsigned long ah_cal_next_ani; 1133 unsigned long ah_cal_next_nf; 1134 1135 /* Calibration mask */ 1136 u8 ah_cal_mask; 1137 1138 /* 1139 * Function pointers 1140 */ 1141 int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1142 unsigned int, unsigned int, int, enum ath5k_pkt_type, 1143 unsigned int, unsigned int, unsigned int, unsigned int, 1144 unsigned int, unsigned int, unsigned int, unsigned int); 1145 int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1146 struct ath5k_tx_status *); 1147 int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *, 1148 struct ath5k_rx_status *); 1149 }; 1150 1151 /* 1152 * Prototypes 1153 */ 1154 extern const struct ieee80211_ops ath5k_hw_ops; 1155 1156 /* Initialization and detach functions */ 1157 int ath5k_init_softc(struct ath5k_softc *sc, const struct ath_bus_ops *bus_ops); 1158 void ath5k_deinit_softc(struct ath5k_softc *sc); 1159 int ath5k_hw_init(struct ath5k_softc *sc); 1160 void ath5k_hw_deinit(struct ath5k_hw *ah); 1161 1162 int ath5k_sysfs_register(struct ath5k_softc *sc); 1163 void ath5k_sysfs_unregister(struct ath5k_softc *sc); 1164 1165 /*Chip id helper functions */ 1166 const char *ath5k_chip_name(enum ath5k_srev_type type, u_int16_t val); 1167 int ath5k_hw_read_srev(struct ath5k_hw *ah); 1168 1169 /* LED functions */ 1170 int ath5k_init_leds(struct ath5k_softc *sc); 1171 void ath5k_led_enable(struct ath5k_softc *sc); 1172 void ath5k_led_off(struct ath5k_softc *sc); 1173 void ath5k_unregister_leds(struct ath5k_softc *sc); 1174 1175 1176 /* Reset Functions */ 1177 int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, bool initial); 1178 int ath5k_hw_on_hold(struct ath5k_hw *ah); 1179 int ath5k_hw_reset(struct ath5k_hw *ah, enum nl80211_iftype op_mode, 1180 struct ieee80211_channel *channel, bool fast, bool skip_pcu); 1181 int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag, u32 val, 1182 bool is_set); 1183 /* Power management functions */ 1184 1185 1186 /* Clock rate related functions */ 1187 unsigned int ath5k_hw_htoclock(struct ath5k_hw *ah, unsigned int usec); 1188 unsigned int ath5k_hw_clocktoh(struct ath5k_hw *ah, unsigned int clock); 1189 void ath5k_hw_set_clockrate(struct ath5k_hw *ah); 1190 1191 1192 /* DMA Related Functions */ 1193 void ath5k_hw_start_rx_dma(struct ath5k_hw *ah); 1194 u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah); 1195 int ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr); 1196 int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue); 1197 int ath5k_hw_stop_beacon_queue(struct ath5k_hw *ah, unsigned int queue); 1198 u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue); 1199 int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue, 1200 u32 phys_addr); 1201 int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, bool increase); 1202 /* Interrupt handling */ 1203 bool ath5k_hw_is_intr_pending(struct ath5k_hw *ah); 1204 int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask); 1205 enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask); 1206 void ath5k_hw_update_mib_counters(struct ath5k_hw *ah); 1207 /* Init/Stop functions */ 1208 void ath5k_hw_dma_init(struct ath5k_hw *ah); 1209 int ath5k_hw_dma_stop(struct ath5k_hw *ah); 1210 1211 /* EEPROM access functions */ 1212 int ath5k_eeprom_init(struct ath5k_hw *ah); 1213 void ath5k_eeprom_detach(struct ath5k_hw *ah); 1214 int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac); 1215 1216 1217 /* Protocol Control Unit Functions */ 1218 /* Helpers */ 1219 int ath5k_hw_get_frame_duration(struct ath5k_hw *ah, 1220 int len, struct ieee80211_rate *rate); 1221 unsigned int ath5k_hw_get_default_slottime(struct ath5k_hw *ah); 1222 unsigned int ath5k_hw_get_default_sifs(struct ath5k_hw *ah); 1223 extern int ath5k_hw_set_opmode(struct ath5k_hw *ah, enum nl80211_iftype opmode); 1224 void ath5k_hw_set_coverage_class(struct ath5k_hw *ah, u8 coverage_class); 1225 /* RX filter control*/ 1226 int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac); 1227 void ath5k_hw_set_bssid(struct ath5k_hw *ah); 1228 void ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask); 1229 void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1); 1230 u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah); 1231 void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter); 1232 /* Receive (DRU) start/stop functions */ 1233 void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah); 1234 void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah); 1235 /* Beacon control functions */ 1236 u64 ath5k_hw_get_tsf64(struct ath5k_hw *ah); 1237 void ath5k_hw_set_tsf64(struct ath5k_hw *ah, u64 tsf64); 1238 void ath5k_hw_reset_tsf(struct ath5k_hw *ah); 1239 void ath5k_hw_init_beacon(struct ath5k_hw *ah, u32 next_beacon, u32 interval); 1240 bool ath5k_hw_check_beacon_timers(struct ath5k_hw *ah, int intval); 1241 /* Init function */ 1242 void ath5k_hw_pcu_init(struct ath5k_hw *ah, enum nl80211_iftype op_mode, 1243 u8 mode); 1244 1245 /* Queue Control Unit, DFS Control Unit Functions */ 1246 int ath5k_hw_get_tx_queueprops(struct ath5k_hw *ah, int queue, 1247 struct ath5k_txq_info *queue_info); 1248 int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, int queue, 1249 const struct ath5k_txq_info *queue_info); 1250 int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah, 1251 enum ath5k_tx_queue queue_type, 1252 struct ath5k_txq_info *queue_info); 1253 u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah, unsigned int queue); 1254 void ath5k_hw_release_tx_queue(struct ath5k_hw *ah, unsigned int queue); 1255 int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah, unsigned int queue); 1256 int ath5k_hw_set_ifs_intervals(struct ath5k_hw *ah, unsigned int slot_time); 1257 /* Init function */ 1258 int ath5k_hw_init_queues(struct ath5k_hw *ah); 1259 1260 /* Hardware Descriptor Functions */ 1261 int ath5k_hw_init_desc_functions(struct ath5k_hw *ah); 1262 int ath5k_hw_setup_rx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, 1263 u32 size, unsigned int flags); 1264 int ath5k_hw_setup_mrr_tx_desc(struct ath5k_hw *ah, struct ath5k_desc *desc, 1265 unsigned int tx_rate1, u_int tx_tries1, u_int tx_rate2, 1266 u_int tx_tries2, unsigned int tx_rate3, u_int tx_tries3); 1267 1268 1269 /* GPIO Functions */ 1270 void ath5k_hw_set_ledstate(struct ath5k_hw *ah, unsigned int state); 1271 int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio); 1272 int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio); 1273 u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio); 1274 int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val); 1275 void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, 1276 u32 interrupt_level); 1277 1278 1279 /* RFkill Functions */ 1280 void ath5k_rfkill_hw_start(struct ath5k_hw *ah); 1281 void ath5k_rfkill_hw_stop(struct ath5k_hw *ah); 1282 1283 1284 /* Misc functions TODO: Cleanup */ 1285 int ath5k_hw_set_capabilities(struct ath5k_hw *ah); 1286 int ath5k_hw_get_capability(struct ath5k_hw *ah, 1287 enum ath5k_capability_type cap_type, u32 capability, 1288 u32 *result); 1289 int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id); 1290 int ath5k_hw_disable_pspoll(struct ath5k_hw *ah); 1291 1292 1293 /* Initial register settings functions */ 1294 int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, bool change_channel); 1295 1296 1297 /* PHY functions */ 1298 /* Misc PHY functions */ 1299 u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan); 1300 int ath5k_hw_phy_disable(struct ath5k_hw *ah); 1301 /* Gain_F optimization */ 1302 enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah); 1303 int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah); 1304 /* PHY/RF channel functions */ 1305 bool ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags); 1306 /* PHY calibration */ 1307 void ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah); 1308 int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, 1309 struct ieee80211_channel *channel); 1310 void ath5k_hw_update_noise_floor(struct ath5k_hw *ah); 1311 /* Spur mitigation */ 1312 bool ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah, 1313 struct ieee80211_channel *channel); 1314 /* Antenna control */ 1315 void ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode); 1316 void ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode); 1317 /* TX power setup */ 1318 int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower); 1319 /* Init function */ 1320 int ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel, 1321 u8 mode, bool fast); 1322 1323 /* 1324 * Functions used internaly 1325 */ 1326 1327 static inline struct ath_common *ath5k_hw_common(struct ath5k_hw *ah) 1328 { 1329 return &ah->common; 1330 } 1331 1332 static inline struct ath_regulatory *ath5k_hw_regulatory(struct ath5k_hw *ah) 1333 { 1334 return &(ath5k_hw_common(ah)->regulatory); 1335 } 1336 1337 #ifdef CONFIG_ATHEROS_AR231X 1338 #define AR5K_AR2315_PCI_BASE ((void __iomem *)0xb0100000) 1339 1340 static inline void __iomem *ath5k_ahb_reg(struct ath5k_hw *ah, u16 reg) 1341 { 1342 /* On AR2315 and AR2317 the PCI clock domain registers 1343 * are outside of the WMAC register space */ 1344 if (unlikely((reg >= 0x4000) && (reg < 0x5000) && 1345 (ah->ah_mac_srev >= AR5K_SREV_AR2315_R6))) 1346 return AR5K_AR2315_PCI_BASE + reg; 1347 1348 return ah->ah_iobase + reg; 1349 } 1350 1351 static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg) 1352 { 1353 return __raw_readl(ath5k_ahb_reg(ah, reg)); 1354 } 1355 1356 static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg) 1357 { 1358 __raw_writel(val, ath5k_ahb_reg(ah, reg)); 1359 } 1360 1361 #else 1362 1363 static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg) 1364 { 1365 return ioread32(ah->ah_iobase + reg); 1366 } 1367 1368 static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg) 1369 { 1370 iowrite32(val, ah->ah_iobase + reg); 1371 } 1372 1373 #endif 1374 1375 static inline enum ath_bus_type ath5k_get_bus_type(struct ath5k_hw *ah) 1376 { 1377 return ath5k_hw_common(ah)->bus_ops->ath_bus_type; 1378 } 1379 1380 static inline void ath5k_read_cachesize(struct ath_common *common, int *csz) 1381 { 1382 common->bus_ops->read_cachesize(common, csz); 1383 } 1384 1385 static inline bool ath5k_hw_nvram_read(struct ath5k_hw *ah, u32 off, u16 *data) 1386 { 1387 struct ath_common *common = ath5k_hw_common(ah); 1388 return common->bus_ops->eeprom_read(common, off, data); 1389 } 1390 1391 static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits) 1392 { 1393 u32 retval = 0, bit, i; 1394 1395 for (i = 0; i < bits; i++) { 1396 bit = (val >> i) & 1; 1397 retval = (retval << 1) | bit; 1398 } 1399 1400 return retval; 1401 } 1402 1403 #endif 1404