1 /* 2 * Copyright (C) 2010 Bruno Randolf <br1@einfach.org> 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17 #include "ath5k.h" 18 #include "base.h" 19 #include "reg.h" 20 #include "debug.h" 21 #include "ani.h" 22 23 /** 24 * DOC: Basic ANI Operation 25 * 26 * Adaptive Noise Immunity (ANI) controls five noise immunity parameters 27 * depending on the amount of interference in the environment, increasing 28 * or reducing sensitivity as necessary. 29 * 30 * The parameters are: 31 * - "noise immunity" 32 * - "spur immunity" 33 * - "firstep level" 34 * - "OFDM weak signal detection" 35 * - "CCK weak signal detection" 36 * 37 * Basically we look at the amount of ODFM and CCK timing errors we get and then 38 * raise or lower immunity accordingly by setting one or more of these 39 * parameters. 40 * Newer chipsets have PHY error counters in hardware which will generate a MIB 41 * interrupt when they overflow. Older hardware has too enable PHY error frames 42 * by setting a RX flag and then count every single PHY error. When a specified 43 * threshold of errors has been reached we will raise immunity. 44 * Also we regularly check the amount of errors and lower or raise immunity as 45 * necessary. 46 */ 47 48 49 /*** ANI parameter control ***/ 50 51 /** 52 * ath5k_ani_set_noise_immunity_level() - Set noise immunity level 53 * 54 * @level: level between 0 and @ATH5K_ANI_MAX_NOISE_IMM_LVL 55 */ 56 void 57 ath5k_ani_set_noise_immunity_level(struct ath5k_hw *ah, int level) 58 { 59 /* TODO: 60 * ANI documents suggest the following five levels to use, but the HAL 61 * and ath9k use only the last two levels, making this 62 * essentially an on/off option. There *may* be a reason for this (???), 63 * so i stick with the HAL version for now... 64 */ 65 #if 0 66 static const s8 lo[] = { -52, -56, -60, -64, -70 }; 67 static const s8 hi[] = { -18, -18, -16, -14, -12 }; 68 static const s8 sz[] = { -34, -41, -48, -55, -62 }; 69 static const s8 fr[] = { -70, -72, -75, -78, -80 }; 70 #else 71 static const s8 lo[] = { -64, -70 }; 72 static const s8 hi[] = { -14, -12 }; 73 static const s8 sz[] = { -55, -62 }; 74 static const s8 fr[] = { -78, -80 }; 75 #endif 76 if (level < 0 || level >= ARRAY_SIZE(sz)) { 77 ATH5K_ERR(ah->ah_sc, "noise immunity level %d out of range", 78 level); 79 return; 80 } 81 82 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_DESIRED_SIZE, 83 AR5K_PHY_DESIRED_SIZE_TOT, sz[level]); 84 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_AGCCOARSE, 85 AR5K_PHY_AGCCOARSE_LO, lo[level]); 86 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_AGCCOARSE, 87 AR5K_PHY_AGCCOARSE_HI, hi[level]); 88 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SIG, 89 AR5K_PHY_SIG_FIRPWR, fr[level]); 90 91 ah->ah_sc->ani_state.noise_imm_level = level; 92 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "new level %d", level); 93 } 94 95 96 /** 97 * ath5k_ani_set_spur_immunity_level() - Set spur immunity level 98 * 99 * @level: level between 0 and @max_spur_level (the maximum level is dependent 100 * on the chip revision). 101 */ 102 void 103 ath5k_ani_set_spur_immunity_level(struct ath5k_hw *ah, int level) 104 { 105 static const int val[] = { 2, 4, 6, 8, 10, 12, 14, 16 }; 106 107 if (level < 0 || level >= ARRAY_SIZE(val) || 108 level > ah->ah_sc->ani_state.max_spur_level) { 109 ATH5K_ERR(ah->ah_sc, "spur immunity level %d out of range", 110 level); 111 return; 112 } 113 114 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_OFDM_SELFCORR, 115 AR5K_PHY_OFDM_SELFCORR_CYPWR_THR1, val[level]); 116 117 ah->ah_sc->ani_state.spur_level = level; 118 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "new level %d", level); 119 } 120 121 122 /** 123 * ath5k_ani_set_firstep_level() - Set "firstep" level 124 * 125 * @level: level between 0 and @ATH5K_ANI_MAX_FIRSTEP_LVL 126 */ 127 void 128 ath5k_ani_set_firstep_level(struct ath5k_hw *ah, int level) 129 { 130 static const int val[] = { 0, 4, 8 }; 131 132 if (level < 0 || level >= ARRAY_SIZE(val)) { 133 ATH5K_ERR(ah->ah_sc, "firstep level %d out of range", level); 134 return; 135 } 136 137 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_SIG, 138 AR5K_PHY_SIG_FIRSTEP, val[level]); 139 140 ah->ah_sc->ani_state.firstep_level = level; 141 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "new level %d", level); 142 } 143 144 145 /** 146 * ath5k_ani_set_ofdm_weak_signal_detection() - Control OFDM weak signal 147 * detection 148 * 149 * @on: turn on or off 150 */ 151 void 152 ath5k_ani_set_ofdm_weak_signal_detection(struct ath5k_hw *ah, bool on) 153 { 154 static const int m1l[] = { 127, 50 }; 155 static const int m2l[] = { 127, 40 }; 156 static const int m1[] = { 127, 0x4d }; 157 static const int m2[] = { 127, 0x40 }; 158 static const int m2cnt[] = { 31, 16 }; 159 static const int m2lcnt[] = { 63, 48 }; 160 161 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR, 162 AR5K_PHY_WEAK_OFDM_LOW_THR_M1, m1l[on]); 163 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR, 164 AR5K_PHY_WEAK_OFDM_LOW_THR_M2, m2l[on]); 165 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_HIGH_THR, 166 AR5K_PHY_WEAK_OFDM_HIGH_THR_M1, m1[on]); 167 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_HIGH_THR, 168 AR5K_PHY_WEAK_OFDM_HIGH_THR_M2, m2[on]); 169 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_HIGH_THR, 170 AR5K_PHY_WEAK_OFDM_HIGH_THR_M2_COUNT, m2cnt[on]); 171 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR, 172 AR5K_PHY_WEAK_OFDM_LOW_THR_M2_COUNT, m2lcnt[on]); 173 174 if (on) 175 AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR, 176 AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN); 177 else 178 AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_WEAK_OFDM_LOW_THR, 179 AR5K_PHY_WEAK_OFDM_LOW_THR_SELFCOR_EN); 180 181 ah->ah_sc->ani_state.ofdm_weak_sig = on; 182 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "turned %s", 183 on ? "on" : "off"); 184 } 185 186 187 /** 188 * ath5k_ani_set_cck_weak_signal_detection() - control CCK weak signal detection 189 * 190 * @on: turn on or off 191 */ 192 void 193 ath5k_ani_set_cck_weak_signal_detection(struct ath5k_hw *ah, bool on) 194 { 195 static const int val[] = { 8, 6 }; 196 AR5K_REG_WRITE_BITS(ah, AR5K_PHY_CCK_CROSSCORR, 197 AR5K_PHY_CCK_CROSSCORR_WEAK_SIG_THR, val[on]); 198 ah->ah_sc->ani_state.cck_weak_sig = on; 199 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "turned %s", 200 on ? "on" : "off"); 201 } 202 203 204 /*** ANI algorithm ***/ 205 206 /** 207 * ath5k_ani_raise_immunity() - Increase noise immunity 208 * 209 * @ofdm_trigger: If this is true we are called because of too many OFDM errors, 210 * the algorithm will tune more parameters then. 211 * 212 * Try to raise noise immunity (=decrease sensitivity) in several steps 213 * depending on the average RSSI of the beacons we received. 214 */ 215 static void 216 ath5k_ani_raise_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as, 217 bool ofdm_trigger) 218 { 219 int rssi = ewma_read(&ah->ah_beacon_rssi_avg); 220 221 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "raise immunity (%s)", 222 ofdm_trigger ? "ODFM" : "CCK"); 223 224 /* first: raise noise immunity */ 225 if (as->noise_imm_level < ATH5K_ANI_MAX_NOISE_IMM_LVL) { 226 ath5k_ani_set_noise_immunity_level(ah, as->noise_imm_level + 1); 227 return; 228 } 229 230 /* only OFDM: raise spur immunity level */ 231 if (ofdm_trigger && 232 as->spur_level < ah->ah_sc->ani_state.max_spur_level) { 233 ath5k_ani_set_spur_immunity_level(ah, as->spur_level + 1); 234 return; 235 } 236 237 /* AP mode */ 238 if (ah->ah_sc->opmode == NL80211_IFTYPE_AP) { 239 if (as->firstep_level < ATH5K_ANI_MAX_FIRSTEP_LVL) 240 ath5k_ani_set_firstep_level(ah, as->firstep_level + 1); 241 return; 242 } 243 244 /* STA and IBSS mode */ 245 246 /* TODO: for IBSS mode it would be better to keep a beacon RSSI average 247 * per each neighbour node and use the minimum of these, to make sure we 248 * don't shut out a remote node by raising immunity too high. */ 249 250 if (rssi > ATH5K_ANI_RSSI_THR_HIGH) { 251 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, 252 "beacon RSSI high"); 253 /* only OFDM: beacon RSSI is high, we can disable ODFM weak 254 * signal detection */ 255 if (ofdm_trigger && as->ofdm_weak_sig == true) { 256 ath5k_ani_set_ofdm_weak_signal_detection(ah, false); 257 ath5k_ani_set_spur_immunity_level(ah, 0); 258 return; 259 } 260 /* as a last resort or CCK: raise firstep level */ 261 if (as->firstep_level < ATH5K_ANI_MAX_FIRSTEP_LVL) { 262 ath5k_ani_set_firstep_level(ah, as->firstep_level + 1); 263 return; 264 } 265 } else if (rssi > ATH5K_ANI_RSSI_THR_LOW) { 266 /* beacon RSSI in mid range, we need OFDM weak signal detect, 267 * but can raise firstep level */ 268 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, 269 "beacon RSSI mid"); 270 if (ofdm_trigger && as->ofdm_weak_sig == false) 271 ath5k_ani_set_ofdm_weak_signal_detection(ah, true); 272 if (as->firstep_level < ATH5K_ANI_MAX_FIRSTEP_LVL) 273 ath5k_ani_set_firstep_level(ah, as->firstep_level + 1); 274 return; 275 } else if (ah->ah_current_channel->band == IEEE80211_BAND_2GHZ) { 276 /* beacon RSSI is low. in B/G mode turn of OFDM weak signal 277 * detect and zero firstep level to maximize CCK sensitivity */ 278 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, 279 "beacon RSSI low, 2GHz"); 280 if (ofdm_trigger && as->ofdm_weak_sig == true) 281 ath5k_ani_set_ofdm_weak_signal_detection(ah, false); 282 if (as->firstep_level > 0) 283 ath5k_ani_set_firstep_level(ah, 0); 284 return; 285 } 286 287 /* TODO: why not?: 288 if (as->cck_weak_sig == true) { 289 ath5k_ani_set_cck_weak_signal_detection(ah, false); 290 } 291 */ 292 } 293 294 295 /** 296 * ath5k_ani_lower_immunity() - Decrease noise immunity 297 * 298 * Try to lower noise immunity (=increase sensitivity) in several steps 299 * depending on the average RSSI of the beacons we received. 300 */ 301 static void 302 ath5k_ani_lower_immunity(struct ath5k_hw *ah, struct ath5k_ani_state *as) 303 { 304 int rssi = ewma_read(&ah->ah_beacon_rssi_avg); 305 306 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "lower immunity"); 307 308 if (ah->ah_sc->opmode == NL80211_IFTYPE_AP) { 309 /* AP mode */ 310 if (as->firstep_level > 0) { 311 ath5k_ani_set_firstep_level(ah, as->firstep_level - 1); 312 return; 313 } 314 } else { 315 /* STA and IBSS mode (see TODO above) */ 316 if (rssi > ATH5K_ANI_RSSI_THR_HIGH) { 317 /* beacon signal is high, leave OFDM weak signal 318 * detection off or it may oscillate 319 * TODO: who said it's off??? */ 320 } else if (rssi > ATH5K_ANI_RSSI_THR_LOW) { 321 /* beacon RSSI is mid-range: turn on ODFM weak signal 322 * detection and next, lower firstep level */ 323 if (as->ofdm_weak_sig == false) { 324 ath5k_ani_set_ofdm_weak_signal_detection(ah, 325 true); 326 return; 327 } 328 if (as->firstep_level > 0) { 329 ath5k_ani_set_firstep_level(ah, 330 as->firstep_level - 1); 331 return; 332 } 333 } else { 334 /* beacon signal is low: only reduce firstep level */ 335 if (as->firstep_level > 0) { 336 ath5k_ani_set_firstep_level(ah, 337 as->firstep_level - 1); 338 return; 339 } 340 } 341 } 342 343 /* all modes */ 344 if (as->spur_level > 0) { 345 ath5k_ani_set_spur_immunity_level(ah, as->spur_level - 1); 346 return; 347 } 348 349 /* finally, reduce noise immunity */ 350 if (as->noise_imm_level > 0) { 351 ath5k_ani_set_noise_immunity_level(ah, as->noise_imm_level - 1); 352 return; 353 } 354 } 355 356 357 /** 358 * ath5k_hw_ani_get_listen_time() - Update counters and return listening time 359 * 360 * Return an approximation of the time spent "listening" in milliseconds (ms) 361 * since the last call of this function. 362 * Save a snapshot of the counter values for debugging/statistics. 363 */ 364 static int 365 ath5k_hw_ani_get_listen_time(struct ath5k_hw *ah, struct ath5k_ani_state *as) 366 { 367 struct ath_common *common = ath5k_hw_common(ah); 368 int listen; 369 370 spin_lock_bh(&common->cc_lock); 371 372 ath_hw_cycle_counters_update(common); 373 memcpy(&as->last_cc, &common->cc_ani, sizeof(as->last_cc)); 374 375 /* clears common->cc_ani */ 376 listen = ath_hw_get_listen_time(common); 377 378 spin_unlock_bh(&common->cc_lock); 379 380 return listen; 381 } 382 383 384 /** 385 * ath5k_ani_save_and_clear_phy_errors() - Clear and save PHY error counters 386 * 387 * Clear the PHY error counters as soon as possible, since this might be called 388 * from a MIB interrupt and we want to make sure we don't get interrupted again. 389 * Add the count of CCK and OFDM errors to our internal state, so it can be used 390 * by the algorithm later. 391 * 392 * Will be called from interrupt and tasklet context. 393 * Returns 0 if both counters are zero. 394 */ 395 static int 396 ath5k_ani_save_and_clear_phy_errors(struct ath5k_hw *ah, 397 struct ath5k_ani_state *as) 398 { 399 unsigned int ofdm_err, cck_err; 400 401 if (!ah->ah_capabilities.cap_has_phyerr_counters) 402 return 0; 403 404 ofdm_err = ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT1); 405 cck_err = ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT2); 406 407 /* reset counters first, we might be in a hurry (interrupt) */ 408 ath5k_hw_reg_write(ah, ATH5K_PHYERR_CNT_MAX - ATH5K_ANI_OFDM_TRIG_HIGH, 409 AR5K_PHYERR_CNT1); 410 ath5k_hw_reg_write(ah, ATH5K_PHYERR_CNT_MAX - ATH5K_ANI_CCK_TRIG_HIGH, 411 AR5K_PHYERR_CNT2); 412 413 ofdm_err = ATH5K_ANI_OFDM_TRIG_HIGH - (ATH5K_PHYERR_CNT_MAX - ofdm_err); 414 cck_err = ATH5K_ANI_CCK_TRIG_HIGH - (ATH5K_PHYERR_CNT_MAX - cck_err); 415 416 /* sometimes both can be zero, especially when there is a superfluous 417 * second interrupt. detect that here and return an error. */ 418 if (ofdm_err <= 0 && cck_err <= 0) 419 return 0; 420 421 /* avoid negative values should one of the registers overflow */ 422 if (ofdm_err > 0) { 423 as->ofdm_errors += ofdm_err; 424 as->sum_ofdm_errors += ofdm_err; 425 } 426 if (cck_err > 0) { 427 as->cck_errors += cck_err; 428 as->sum_cck_errors += cck_err; 429 } 430 return 1; 431 } 432 433 434 /** 435 * ath5k_ani_period_restart() - Restart ANI period 436 * 437 * Just reset counters, so they are clear for the next "ani period". 438 */ 439 static void 440 ath5k_ani_period_restart(struct ath5k_hw *ah, struct ath5k_ani_state *as) 441 { 442 /* keep last values for debugging */ 443 as->last_ofdm_errors = as->ofdm_errors; 444 as->last_cck_errors = as->cck_errors; 445 as->last_listen = as->listen_time; 446 447 as->ofdm_errors = 0; 448 as->cck_errors = 0; 449 as->listen_time = 0; 450 } 451 452 453 /** 454 * ath5k_ani_calibration() - The main ANI calibration function 455 * 456 * We count OFDM and CCK errors relative to the time where we did not send or 457 * receive ("listen" time) and raise or lower immunity accordingly. 458 * This is called regularly (every second) from the calibration timer, but also 459 * when an error threshold has been reached. 460 * 461 * In order to synchronize access from different contexts, this should be 462 * called only indirectly by scheduling the ANI tasklet! 463 */ 464 void 465 ath5k_ani_calibration(struct ath5k_hw *ah) 466 { 467 struct ath5k_ani_state *as = &ah->ah_sc->ani_state; 468 int listen, ofdm_high, ofdm_low, cck_high, cck_low; 469 470 /* get listen time since last call and add it to the counter because we 471 * might not have restarted the "ani period" last time. 472 * always do this to calculate the busy time also in manual mode */ 473 listen = ath5k_hw_ani_get_listen_time(ah, as); 474 as->listen_time += listen; 475 476 if (as->ani_mode != ATH5K_ANI_MODE_AUTO) 477 return; 478 479 ath5k_ani_save_and_clear_phy_errors(ah, as); 480 481 ofdm_high = as->listen_time * ATH5K_ANI_OFDM_TRIG_HIGH / 1000; 482 cck_high = as->listen_time * ATH5K_ANI_CCK_TRIG_HIGH / 1000; 483 ofdm_low = as->listen_time * ATH5K_ANI_OFDM_TRIG_LOW / 1000; 484 cck_low = as->listen_time * ATH5K_ANI_CCK_TRIG_LOW / 1000; 485 486 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, 487 "listen %d (now %d)", as->listen_time, listen); 488 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, 489 "check high ofdm %d/%d cck %d/%d", 490 as->ofdm_errors, ofdm_high, as->cck_errors, cck_high); 491 492 if (as->ofdm_errors > ofdm_high || as->cck_errors > cck_high) { 493 /* too many PHY errors - we have to raise immunity */ 494 bool ofdm_flag = as->ofdm_errors > ofdm_high ? true : false; 495 ath5k_ani_raise_immunity(ah, as, ofdm_flag); 496 ath5k_ani_period_restart(ah, as); 497 498 } else if (as->listen_time > 5 * ATH5K_ANI_LISTEN_PERIOD) { 499 /* If more than 5 (TODO: why 5?) periods have passed and we got 500 * relatively little errors we can try to lower immunity */ 501 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, 502 "check low ofdm %d/%d cck %d/%d", 503 as->ofdm_errors, ofdm_low, as->cck_errors, cck_low); 504 505 if (as->ofdm_errors <= ofdm_low && as->cck_errors <= cck_low) 506 ath5k_ani_lower_immunity(ah, as); 507 508 ath5k_ani_period_restart(ah, as); 509 } 510 } 511 512 513 /*** INTERRUPT HANDLER ***/ 514 515 /** 516 * ath5k_ani_mib_intr() - Interrupt handler for ANI MIB counters 517 * 518 * Just read & reset the registers quickly, so they don't generate more 519 * interrupts, save the counters and schedule the tasklet to decide whether 520 * to raise immunity or not. 521 * 522 * We just need to handle PHY error counters, ath5k_hw_update_mib_counters() 523 * should take care of all "normal" MIB interrupts. 524 */ 525 void 526 ath5k_ani_mib_intr(struct ath5k_hw *ah) 527 { 528 struct ath5k_ani_state *as = &ah->ah_sc->ani_state; 529 530 /* nothing to do here if HW does not have PHY error counters - they 531 * can't be the reason for the MIB interrupt then */ 532 if (!ah->ah_capabilities.cap_has_phyerr_counters) 533 return; 534 535 /* not in use but clear anyways */ 536 ath5k_hw_reg_write(ah, 0, AR5K_OFDM_FIL_CNT); 537 ath5k_hw_reg_write(ah, 0, AR5K_CCK_FIL_CNT); 538 539 if (ah->ah_sc->ani_state.ani_mode != ATH5K_ANI_MODE_AUTO) 540 return; 541 542 /* If one of the errors triggered, we can get a superfluous second 543 * interrupt, even though we have already reset the register. The 544 * function detects that so we can return early. */ 545 if (ath5k_ani_save_and_clear_phy_errors(ah, as) == 0) 546 return; 547 548 if (as->ofdm_errors > ATH5K_ANI_OFDM_TRIG_HIGH || 549 as->cck_errors > ATH5K_ANI_CCK_TRIG_HIGH) 550 tasklet_schedule(&ah->ah_sc->ani_tasklet); 551 } 552 553 554 /** 555 * ath5k_ani_phy_error_report() - Used by older HW to report PHY errors 556 * 557 * This is used by hardware without PHY error counters to report PHY errors 558 * on a frame-by-frame basis, instead of the interrupt. 559 */ 560 void 561 ath5k_ani_phy_error_report(struct ath5k_hw *ah, 562 enum ath5k_phy_error_code phyerr) 563 { 564 struct ath5k_ani_state *as = &ah->ah_sc->ani_state; 565 566 if (phyerr == AR5K_RX_PHY_ERROR_OFDM_TIMING) { 567 as->ofdm_errors++; 568 if (as->ofdm_errors > ATH5K_ANI_OFDM_TRIG_HIGH) 569 tasklet_schedule(&ah->ah_sc->ani_tasklet); 570 } else if (phyerr == AR5K_RX_PHY_ERROR_CCK_TIMING) { 571 as->cck_errors++; 572 if (as->cck_errors > ATH5K_ANI_CCK_TRIG_HIGH) 573 tasklet_schedule(&ah->ah_sc->ani_tasklet); 574 } 575 } 576 577 578 /*** INIT ***/ 579 580 /** 581 * ath5k_enable_phy_err_counters() - Enable PHY error counters 582 * 583 * Enable PHY error counters for OFDM and CCK timing errors. 584 */ 585 static void 586 ath5k_enable_phy_err_counters(struct ath5k_hw *ah) 587 { 588 ath5k_hw_reg_write(ah, ATH5K_PHYERR_CNT_MAX - ATH5K_ANI_OFDM_TRIG_HIGH, 589 AR5K_PHYERR_CNT1); 590 ath5k_hw_reg_write(ah, ATH5K_PHYERR_CNT_MAX - ATH5K_ANI_CCK_TRIG_HIGH, 591 AR5K_PHYERR_CNT2); 592 ath5k_hw_reg_write(ah, AR5K_PHY_ERR_FIL_OFDM, AR5K_PHYERR_CNT1_MASK); 593 ath5k_hw_reg_write(ah, AR5K_PHY_ERR_FIL_CCK, AR5K_PHYERR_CNT2_MASK); 594 595 /* not in use */ 596 ath5k_hw_reg_write(ah, 0, AR5K_OFDM_FIL_CNT); 597 ath5k_hw_reg_write(ah, 0, AR5K_CCK_FIL_CNT); 598 } 599 600 601 /** 602 * ath5k_disable_phy_err_counters() - Disable PHY error counters 603 * 604 * Disable PHY error counters for OFDM and CCK timing errors. 605 */ 606 static void 607 ath5k_disable_phy_err_counters(struct ath5k_hw *ah) 608 { 609 ath5k_hw_reg_write(ah, 0, AR5K_PHYERR_CNT1); 610 ath5k_hw_reg_write(ah, 0, AR5K_PHYERR_CNT2); 611 ath5k_hw_reg_write(ah, 0, AR5K_PHYERR_CNT1_MASK); 612 ath5k_hw_reg_write(ah, 0, AR5K_PHYERR_CNT2_MASK); 613 614 /* not in use */ 615 ath5k_hw_reg_write(ah, 0, AR5K_OFDM_FIL_CNT); 616 ath5k_hw_reg_write(ah, 0, AR5K_CCK_FIL_CNT); 617 } 618 619 620 /** 621 * ath5k_ani_init() - Initialize ANI 622 * @mode: Which mode to use (auto, manual high, manual low, off) 623 * 624 * Initialize ANI according to mode. 625 */ 626 void 627 ath5k_ani_init(struct ath5k_hw *ah, enum ath5k_ani_mode mode) 628 { 629 /* ANI is only possible on 5212 and newer */ 630 if (ah->ah_version < AR5K_AR5212) 631 return; 632 633 if (mode < ATH5K_ANI_MODE_OFF || mode > ATH5K_ANI_MODE_AUTO) { 634 ATH5K_ERR(ah->ah_sc, "ANI mode %d out of range", mode); 635 return; 636 } 637 638 /* clear old state information */ 639 memset(&ah->ah_sc->ani_state, 0, sizeof(ah->ah_sc->ani_state)); 640 641 /* older hardware has more spur levels than newer */ 642 if (ah->ah_mac_srev < AR5K_SREV_AR2414) 643 ah->ah_sc->ani_state.max_spur_level = 7; 644 else 645 ah->ah_sc->ani_state.max_spur_level = 2; 646 647 /* initial values for our ani parameters */ 648 if (mode == ATH5K_ANI_MODE_OFF) { 649 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "ANI off\n"); 650 } else if (mode == ATH5K_ANI_MODE_MANUAL_LOW) { 651 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, 652 "ANI manual low -> high sensitivity\n"); 653 ath5k_ani_set_noise_immunity_level(ah, 0); 654 ath5k_ani_set_spur_immunity_level(ah, 0); 655 ath5k_ani_set_firstep_level(ah, 0); 656 ath5k_ani_set_ofdm_weak_signal_detection(ah, true); 657 ath5k_ani_set_cck_weak_signal_detection(ah, true); 658 } else if (mode == ATH5K_ANI_MODE_MANUAL_HIGH) { 659 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, 660 "ANI manual high -> low sensitivity\n"); 661 ath5k_ani_set_noise_immunity_level(ah, 662 ATH5K_ANI_MAX_NOISE_IMM_LVL); 663 ath5k_ani_set_spur_immunity_level(ah, 664 ah->ah_sc->ani_state.max_spur_level); 665 ath5k_ani_set_firstep_level(ah, ATH5K_ANI_MAX_FIRSTEP_LVL); 666 ath5k_ani_set_ofdm_weak_signal_detection(ah, false); 667 ath5k_ani_set_cck_weak_signal_detection(ah, false); 668 } else if (mode == ATH5K_ANI_MODE_AUTO) { 669 ATH5K_DBG_UNLIMIT(ah->ah_sc, ATH5K_DEBUG_ANI, "ANI auto\n"); 670 ath5k_ani_set_noise_immunity_level(ah, 0); 671 ath5k_ani_set_spur_immunity_level(ah, 0); 672 ath5k_ani_set_firstep_level(ah, 0); 673 ath5k_ani_set_ofdm_weak_signal_detection(ah, true); 674 ath5k_ani_set_cck_weak_signal_detection(ah, false); 675 } 676 677 /* newer hardware has PHY error counter registers which we can use to 678 * get OFDM and CCK error counts. older hardware has to set rxfilter and 679 * report every single PHY error by calling ath5k_ani_phy_error_report() 680 */ 681 if (mode == ATH5K_ANI_MODE_AUTO) { 682 if (ah->ah_capabilities.cap_has_phyerr_counters) 683 ath5k_enable_phy_err_counters(ah); 684 else 685 ath5k_hw_set_rx_filter(ah, ath5k_hw_get_rx_filter(ah) | 686 AR5K_RX_FILTER_PHYERR); 687 } else { 688 if (ah->ah_capabilities.cap_has_phyerr_counters) 689 ath5k_disable_phy_err_counters(ah); 690 else 691 ath5k_hw_set_rx_filter(ah, ath5k_hw_get_rx_filter(ah) & 692 ~AR5K_RX_FILTER_PHYERR); 693 } 694 695 ah->ah_sc->ani_state.ani_mode = mode; 696 } 697 698 699 /*** DEBUG ***/ 700 701 #ifdef CONFIG_ATH5K_DEBUG 702 703 void 704 ath5k_ani_print_counters(struct ath5k_hw *ah) 705 { 706 /* clears too */ 707 printk(KERN_NOTICE "ACK fail\t%d\n", 708 ath5k_hw_reg_read(ah, AR5K_ACK_FAIL)); 709 printk(KERN_NOTICE "RTS fail\t%d\n", 710 ath5k_hw_reg_read(ah, AR5K_RTS_FAIL)); 711 printk(KERN_NOTICE "RTS success\t%d\n", 712 ath5k_hw_reg_read(ah, AR5K_RTS_OK)); 713 printk(KERN_NOTICE "FCS error\t%d\n", 714 ath5k_hw_reg_read(ah, AR5K_FCS_FAIL)); 715 716 /* no clear */ 717 printk(KERN_NOTICE "tx\t%d\n", 718 ath5k_hw_reg_read(ah, AR5K_PROFCNT_TX)); 719 printk(KERN_NOTICE "rx\t%d\n", 720 ath5k_hw_reg_read(ah, AR5K_PROFCNT_RX)); 721 printk(KERN_NOTICE "busy\t%d\n", 722 ath5k_hw_reg_read(ah, AR5K_PROFCNT_RXCLR)); 723 printk(KERN_NOTICE "cycles\t%d\n", 724 ath5k_hw_reg_read(ah, AR5K_PROFCNT_CYCLE)); 725 726 printk(KERN_NOTICE "AR5K_PHYERR_CNT1\t%d\n", 727 ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT1)); 728 printk(KERN_NOTICE "AR5K_PHYERR_CNT2\t%d\n", 729 ath5k_hw_reg_read(ah, AR5K_PHYERR_CNT2)); 730 printk(KERN_NOTICE "AR5K_OFDM_FIL_CNT\t%d\n", 731 ath5k_hw_reg_read(ah, AR5K_OFDM_FIL_CNT)); 732 printk(KERN_NOTICE "AR5K_CCK_FIL_CNT\t%d\n", 733 ath5k_hw_reg_read(ah, AR5K_CCK_FIL_CNT)); 734 } 735 736 #endif 737