1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/module.h> 8 #include <linux/msi.h> 9 #include <linux/pci.h> 10 11 #include "pci.h" 12 #include "core.h" 13 #include "hif.h" 14 #include "mhi.h" 15 #include "debug.h" 16 17 #define ATH12K_PCI_BAR_NUM 0 18 #define ATH12K_PCI_DMA_MASK 32 19 20 #define ATH12K_PCI_IRQ_CE0_OFFSET 3 21 22 #define WINDOW_ENABLE_BIT 0x40000000 23 #define WINDOW_REG_ADDRESS 0x310c 24 #define WINDOW_VALUE_MASK GENMASK(24, 19) 25 #define WINDOW_START 0x80000 26 #define WINDOW_RANGE_MASK GENMASK(18, 0) 27 #define WINDOW_STATIC_MASK GENMASK(31, 6) 28 29 #define TCSR_SOC_HW_VERSION 0x1B00000 30 #define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8) 31 #define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 4) 32 33 /* BAR0 + 4k is always accessible, and no 34 * need to force wakeup. 35 * 4K - 32 = 0xFE0 36 */ 37 #define ACCESS_ALWAYS_OFF 0xFE0 38 39 #define QCN9274_DEVICE_ID 0x1109 40 #define WCN7850_DEVICE_ID 0x1107 41 42 static const struct pci_device_id ath12k_pci_id_table[] = { 43 { PCI_VDEVICE(QCOM, QCN9274_DEVICE_ID) }, 44 { PCI_VDEVICE(QCOM, WCN7850_DEVICE_ID) }, 45 {0} 46 }; 47 48 MODULE_DEVICE_TABLE(pci, ath12k_pci_id_table); 49 50 /* TODO: revisit IRQ mapping for new SRNG's */ 51 static const struct ath12k_msi_config ath12k_msi_config[] = { 52 { 53 .total_vectors = 16, 54 .total_users = 3, 55 .users = (struct ath12k_msi_user[]) { 56 { .name = "MHI", .num_vectors = 3, .base_vector = 0 }, 57 { .name = "CE", .num_vectors = 5, .base_vector = 3 }, 58 { .name = "DP", .num_vectors = 8, .base_vector = 8 }, 59 }, 60 }, 61 }; 62 63 static const char *irq_name[ATH12K_IRQ_NUM_MAX] = { 64 "bhi", 65 "mhi-er0", 66 "mhi-er1", 67 "ce0", 68 "ce1", 69 "ce2", 70 "ce3", 71 "ce4", 72 "ce5", 73 "ce6", 74 "ce7", 75 "ce8", 76 "ce9", 77 "ce10", 78 "ce11", 79 "ce12", 80 "ce13", 81 "ce14", 82 "ce15", 83 "host2wbm-desc-feed", 84 "host2reo-re-injection", 85 "host2reo-command", 86 "host2rxdma-monitor-ring3", 87 "host2rxdma-monitor-ring2", 88 "host2rxdma-monitor-ring1", 89 "reo2ost-exception", 90 "wbm2host-rx-release", 91 "reo2host-status", 92 "reo2host-destination-ring4", 93 "reo2host-destination-ring3", 94 "reo2host-destination-ring2", 95 "reo2host-destination-ring1", 96 "rxdma2host-monitor-destination-mac3", 97 "rxdma2host-monitor-destination-mac2", 98 "rxdma2host-monitor-destination-mac1", 99 "ppdu-end-interrupts-mac3", 100 "ppdu-end-interrupts-mac2", 101 "ppdu-end-interrupts-mac1", 102 "rxdma2host-monitor-status-ring-mac3", 103 "rxdma2host-monitor-status-ring-mac2", 104 "rxdma2host-monitor-status-ring-mac1", 105 "host2rxdma-host-buf-ring-mac3", 106 "host2rxdma-host-buf-ring-mac2", 107 "host2rxdma-host-buf-ring-mac1", 108 "rxdma2host-destination-ring-mac3", 109 "rxdma2host-destination-ring-mac2", 110 "rxdma2host-destination-ring-mac1", 111 "host2tcl-input-ring4", 112 "host2tcl-input-ring3", 113 "host2tcl-input-ring2", 114 "host2tcl-input-ring1", 115 "wbm2host-tx-completions-ring4", 116 "wbm2host-tx-completions-ring3", 117 "wbm2host-tx-completions-ring2", 118 "wbm2host-tx-completions-ring1", 119 "tcl2host-status-ring", 120 }; 121 122 static int ath12k_pci_bus_wake_up(struct ath12k_base *ab) 123 { 124 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 125 126 return mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev); 127 } 128 129 static void ath12k_pci_bus_release(struct ath12k_base *ab) 130 { 131 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 132 133 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev); 134 } 135 136 static const struct ath12k_pci_ops ath12k_pci_ops_qcn9274 = { 137 .wakeup = NULL, 138 .release = NULL, 139 }; 140 141 static const struct ath12k_pci_ops ath12k_pci_ops_wcn7850 = { 142 .wakeup = ath12k_pci_bus_wake_up, 143 .release = ath12k_pci_bus_release, 144 }; 145 146 static void ath12k_pci_select_window(struct ath12k_pci *ab_pci, u32 offset) 147 { 148 struct ath12k_base *ab = ab_pci->ab; 149 150 u32 window = u32_get_bits(offset, WINDOW_VALUE_MASK); 151 u32 static_window; 152 153 lockdep_assert_held(&ab_pci->window_lock); 154 155 /* Preserve the static window configuration and reset only dynamic window */ 156 static_window = ab_pci->register_window & WINDOW_STATIC_MASK; 157 window |= static_window; 158 159 if (window != ab_pci->register_window) { 160 iowrite32(WINDOW_ENABLE_BIT | window, 161 ab->mem + WINDOW_REG_ADDRESS); 162 ioread32(ab->mem + WINDOW_REG_ADDRESS); 163 ab_pci->register_window = window; 164 } 165 } 166 167 static void ath12k_pci_select_static_window(struct ath12k_pci *ab_pci) 168 { 169 u32 umac_window = u32_get_bits(HAL_SEQ_WCSS_UMAC_OFFSET, WINDOW_VALUE_MASK); 170 u32 ce_window = u32_get_bits(HAL_CE_WFSS_CE_REG_BASE, WINDOW_VALUE_MASK); 171 u32 window; 172 173 window = (umac_window << 12) | (ce_window << 6); 174 175 spin_lock_bh(&ab_pci->window_lock); 176 ab_pci->register_window = window; 177 spin_unlock_bh(&ab_pci->window_lock); 178 179 iowrite32(WINDOW_ENABLE_BIT | window, ab_pci->ab->mem + WINDOW_REG_ADDRESS); 180 } 181 182 static u32 ath12k_pci_get_window_start(struct ath12k_base *ab, 183 u32 offset) 184 { 185 u32 window_start; 186 187 /* If offset lies within DP register range, use 3rd window */ 188 if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < WINDOW_RANGE_MASK) 189 window_start = 3 * WINDOW_START; 190 /* If offset lies within CE register range, use 2nd window */ 191 else if ((offset ^ HAL_CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) 192 window_start = 2 * WINDOW_START; 193 /* If offset lies within PCI_BAR_WINDOW0_BASE and within PCI_SOC_PCI_REG_BASE 194 * use 0th window 195 */ 196 else if (((offset ^ PCI_BAR_WINDOW0_BASE) < WINDOW_RANGE_MASK) && 197 !((offset ^ PCI_SOC_PCI_REG_BASE) < PCI_SOC_RANGE_MASK)) 198 window_start = 0; 199 else 200 window_start = WINDOW_START; 201 202 return window_start; 203 } 204 205 static void ath12k_pci_soc_global_reset(struct ath12k_base *ab) 206 { 207 u32 val, delay; 208 209 val = ath12k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET); 210 211 val |= PCIE_SOC_GLOBAL_RESET_V; 212 213 ath12k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 214 215 /* TODO: exact time to sleep is uncertain */ 216 delay = 10; 217 mdelay(delay); 218 219 /* Need to toggle V bit back otherwise stuck in reset status */ 220 val &= ~PCIE_SOC_GLOBAL_RESET_V; 221 222 ath12k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 223 224 mdelay(delay); 225 226 val = ath12k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET); 227 if (val == 0xffffffff) 228 ath12k_warn(ab, "link down error during global reset\n"); 229 } 230 231 static void ath12k_pci_clear_dbg_registers(struct ath12k_base *ab) 232 { 233 u32 val; 234 235 /* read cookie */ 236 val = ath12k_pci_read32(ab, PCIE_Q6_COOKIE_ADDR); 237 ath12k_dbg(ab, ATH12K_DBG_PCI, "cookie:0x%x\n", val); 238 239 val = ath12k_pci_read32(ab, WLAON_WARM_SW_ENTRY); 240 ath12k_dbg(ab, ATH12K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val); 241 242 /* TODO: exact time to sleep is uncertain */ 243 mdelay(10); 244 245 /* write 0 to WLAON_WARM_SW_ENTRY to prevent Q6 from 246 * continuing warm path and entering dead loop. 247 */ 248 ath12k_pci_write32(ab, WLAON_WARM_SW_ENTRY, 0); 249 mdelay(10); 250 251 val = ath12k_pci_read32(ab, WLAON_WARM_SW_ENTRY); 252 ath12k_dbg(ab, ATH12K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val); 253 254 /* A read clear register. clear the register to prevent 255 * Q6 from entering wrong code path. 256 */ 257 val = ath12k_pci_read32(ab, WLAON_SOC_RESET_CAUSE_REG); 258 ath12k_dbg(ab, ATH12K_DBG_PCI, "soc reset cause:%d\n", val); 259 } 260 261 static void ath12k_pci_enable_ltssm(struct ath12k_base *ab) 262 { 263 u32 val; 264 int i; 265 266 val = ath12k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM); 267 268 /* PCIE link seems very unstable after the Hot Reset*/ 269 for (i = 0; val != PARM_LTSSM_VALUE && i < 5; i++) { 270 if (val == 0xffffffff) 271 mdelay(5); 272 273 ath12k_pci_write32(ab, PCIE_PCIE_PARF_LTSSM, PARM_LTSSM_VALUE); 274 val = ath12k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM); 275 } 276 277 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci ltssm 0x%x\n", val); 278 279 val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST); 280 val |= GCC_GCC_PCIE_HOT_RST_VAL; 281 ath12k_pci_write32(ab, GCC_GCC_PCIE_HOT_RST, val); 282 val = ath12k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST); 283 284 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci pcie_hot_rst 0x%x\n", val); 285 286 mdelay(5); 287 } 288 289 static void ath12k_pci_clear_all_intrs(struct ath12k_base *ab) 290 { 291 /* This is a WAR for PCIE Hotreset. 292 * When target receive Hotreset, but will set the interrupt. 293 * So when download SBL again, SBL will open Interrupt and 294 * receive it, and crash immediately. 295 */ 296 ath12k_pci_write32(ab, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL); 297 } 298 299 static void ath12k_pci_set_wlaon_pwr_ctrl(struct ath12k_base *ab) 300 { 301 u32 val; 302 303 val = ath12k_pci_read32(ab, WLAON_QFPROM_PWR_CTRL_REG); 304 val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK; 305 ath12k_pci_write32(ab, WLAON_QFPROM_PWR_CTRL_REG, val); 306 } 307 308 static void ath12k_pci_force_wake(struct ath12k_base *ab) 309 { 310 ath12k_pci_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1); 311 mdelay(5); 312 } 313 314 static void ath12k_pci_sw_reset(struct ath12k_base *ab, bool power_on) 315 { 316 if (power_on) { 317 ath12k_pci_enable_ltssm(ab); 318 ath12k_pci_clear_all_intrs(ab); 319 ath12k_pci_set_wlaon_pwr_ctrl(ab); 320 } 321 322 ath12k_mhi_clear_vector(ab); 323 ath12k_pci_clear_dbg_registers(ab); 324 ath12k_pci_soc_global_reset(ab); 325 ath12k_mhi_set_mhictrl_reset(ab); 326 } 327 328 static void ath12k_pci_free_ext_irq(struct ath12k_base *ab) 329 { 330 int i, j; 331 332 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { 333 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 334 335 for (j = 0; j < irq_grp->num_irq; j++) 336 free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp); 337 338 netif_napi_del(&irq_grp->napi); 339 } 340 } 341 342 static void ath12k_pci_free_irq(struct ath12k_base *ab) 343 { 344 int i, irq_idx; 345 346 for (i = 0; i < ab->hw_params->ce_count; i++) { 347 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 348 continue; 349 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i; 350 free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]); 351 } 352 353 ath12k_pci_free_ext_irq(ab); 354 } 355 356 static void ath12k_pci_ce_irq_enable(struct ath12k_base *ab, u16 ce_id) 357 { 358 u32 irq_idx; 359 360 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_id; 361 enable_irq(ab->irq_num[irq_idx]); 362 } 363 364 static void ath12k_pci_ce_irq_disable(struct ath12k_base *ab, u16 ce_id) 365 { 366 u32 irq_idx; 367 368 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + ce_id; 369 disable_irq_nosync(ab->irq_num[irq_idx]); 370 } 371 372 static void ath12k_pci_ce_irqs_disable(struct ath12k_base *ab) 373 { 374 int i; 375 376 for (i = 0; i < ab->hw_params->ce_count; i++) { 377 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 378 continue; 379 ath12k_pci_ce_irq_disable(ab, i); 380 } 381 } 382 383 static void ath12k_pci_sync_ce_irqs(struct ath12k_base *ab) 384 { 385 int i; 386 int irq_idx; 387 388 for (i = 0; i < ab->hw_params->ce_count; i++) { 389 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 390 continue; 391 392 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i; 393 synchronize_irq(ab->irq_num[irq_idx]); 394 } 395 } 396 397 static void ath12k_pci_ce_tasklet(struct tasklet_struct *t) 398 { 399 struct ath12k_ce_pipe *ce_pipe = from_tasklet(ce_pipe, t, intr_tq); 400 401 ath12k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num); 402 403 ath12k_pci_ce_irq_enable(ce_pipe->ab, ce_pipe->pipe_num); 404 } 405 406 static irqreturn_t ath12k_pci_ce_interrupt_handler(int irq, void *arg) 407 { 408 struct ath12k_ce_pipe *ce_pipe = arg; 409 410 /* last interrupt received for this CE */ 411 ce_pipe->timestamp = jiffies; 412 413 ath12k_pci_ce_irq_disable(ce_pipe->ab, ce_pipe->pipe_num); 414 tasklet_schedule(&ce_pipe->intr_tq); 415 416 return IRQ_HANDLED; 417 } 418 419 static void ath12k_pci_ext_grp_disable(struct ath12k_ext_irq_grp *irq_grp) 420 { 421 int i; 422 423 for (i = 0; i < irq_grp->num_irq; i++) 424 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 425 } 426 427 static void __ath12k_pci_ext_irq_disable(struct ath12k_base *sc) 428 { 429 int i; 430 431 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { 432 struct ath12k_ext_irq_grp *irq_grp = &sc->ext_irq_grp[i]; 433 434 ath12k_pci_ext_grp_disable(irq_grp); 435 436 napi_synchronize(&irq_grp->napi); 437 napi_disable(&irq_grp->napi); 438 } 439 } 440 441 static void ath12k_pci_ext_grp_enable(struct ath12k_ext_irq_grp *irq_grp) 442 { 443 int i; 444 445 for (i = 0; i < irq_grp->num_irq; i++) 446 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 447 } 448 449 static void ath12k_pci_sync_ext_irqs(struct ath12k_base *ab) 450 { 451 int i, j, irq_idx; 452 453 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { 454 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 455 456 for (j = 0; j < irq_grp->num_irq; j++) { 457 irq_idx = irq_grp->irqs[j]; 458 synchronize_irq(ab->irq_num[irq_idx]); 459 } 460 } 461 } 462 463 static int ath12k_pci_ext_grp_napi_poll(struct napi_struct *napi, int budget) 464 { 465 struct ath12k_ext_irq_grp *irq_grp = container_of(napi, 466 struct ath12k_ext_irq_grp, 467 napi); 468 struct ath12k_base *ab = irq_grp->ab; 469 int work_done; 470 471 work_done = ath12k_dp_service_srng(ab, irq_grp, budget); 472 if (work_done < budget) { 473 napi_complete_done(napi, work_done); 474 ath12k_pci_ext_grp_enable(irq_grp); 475 } 476 477 if (work_done > budget) 478 work_done = budget; 479 480 return work_done; 481 } 482 483 static irqreturn_t ath12k_pci_ext_interrupt_handler(int irq, void *arg) 484 { 485 struct ath12k_ext_irq_grp *irq_grp = arg; 486 487 ath12k_dbg(irq_grp->ab, ATH12K_DBG_PCI, "ext irq:%d\n", irq); 488 489 /* last interrupt received for this group */ 490 irq_grp->timestamp = jiffies; 491 492 ath12k_pci_ext_grp_disable(irq_grp); 493 494 napi_schedule(&irq_grp->napi); 495 496 return IRQ_HANDLED; 497 } 498 499 static int ath12k_pci_ext_irq_config(struct ath12k_base *ab) 500 { 501 int i, j, ret, num_vectors = 0; 502 u32 user_base_data = 0, base_vector = 0, base_idx; 503 504 base_idx = ATH12K_PCI_IRQ_CE0_OFFSET + CE_COUNT_MAX; 505 ret = ath12k_pci_get_user_msi_assignment(ab, "DP", 506 &num_vectors, 507 &user_base_data, 508 &base_vector); 509 if (ret < 0) 510 return ret; 511 512 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { 513 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 514 u32 num_irq = 0; 515 516 irq_grp->ab = ab; 517 irq_grp->grp_id = i; 518 init_dummy_netdev(&irq_grp->napi_ndev); 519 netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi, 520 ath12k_pci_ext_grp_napi_poll); 521 522 if (ab->hw_params->ring_mask->tx[i] || 523 ab->hw_params->ring_mask->rx[i] || 524 ab->hw_params->ring_mask->rx_err[i] || 525 ab->hw_params->ring_mask->rx_wbm_rel[i] || 526 ab->hw_params->ring_mask->reo_status[i] || 527 ab->hw_params->ring_mask->host2rxdma[i] || 528 ab->hw_params->ring_mask->rx_mon_dest[i]) { 529 num_irq = 1; 530 } 531 532 irq_grp->num_irq = num_irq; 533 irq_grp->irqs[0] = base_idx + i; 534 535 for (j = 0; j < irq_grp->num_irq; j++) { 536 int irq_idx = irq_grp->irqs[j]; 537 int vector = (i % num_vectors) + base_vector; 538 int irq = ath12k_pci_get_msi_irq(ab->dev, vector); 539 540 ab->irq_num[irq_idx] = irq; 541 542 ath12k_dbg(ab, ATH12K_DBG_PCI, 543 "irq:%d group:%d\n", irq, i); 544 545 irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); 546 ret = request_irq(irq, ath12k_pci_ext_interrupt_handler, 547 IRQF_SHARED, 548 "DP_EXT_IRQ", irq_grp); 549 if (ret) { 550 ath12k_err(ab, "failed request irq %d: %d\n", 551 vector, ret); 552 return ret; 553 } 554 555 disable_irq_nosync(ab->irq_num[irq_idx]); 556 } 557 } 558 559 return 0; 560 } 561 562 static int ath12k_pci_config_irq(struct ath12k_base *ab) 563 { 564 struct ath12k_ce_pipe *ce_pipe; 565 u32 msi_data_start; 566 u32 msi_data_count, msi_data_idx; 567 u32 msi_irq_start; 568 unsigned int msi_data; 569 int irq, i, ret, irq_idx; 570 571 ret = ath12k_pci_get_user_msi_assignment(ab, 572 "CE", &msi_data_count, 573 &msi_data_start, &msi_irq_start); 574 if (ret) 575 return ret; 576 577 /* Configure CE irqs */ 578 579 for (i = 0, msi_data_idx = 0; i < ab->hw_params->ce_count; i++) { 580 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 581 continue; 582 583 msi_data = (msi_data_idx % msi_data_count) + msi_irq_start; 584 irq = ath12k_pci_get_msi_irq(ab->dev, msi_data); 585 ce_pipe = &ab->ce.ce_pipe[i]; 586 587 irq_idx = ATH12K_PCI_IRQ_CE0_OFFSET + i; 588 589 tasklet_setup(&ce_pipe->intr_tq, ath12k_pci_ce_tasklet); 590 591 ret = request_irq(irq, ath12k_pci_ce_interrupt_handler, 592 IRQF_SHARED, irq_name[irq_idx], 593 ce_pipe); 594 if (ret) { 595 ath12k_err(ab, "failed to request irq %d: %d\n", 596 irq_idx, ret); 597 return ret; 598 } 599 600 ab->irq_num[irq_idx] = irq; 601 msi_data_idx++; 602 603 ath12k_pci_ce_irq_disable(ab, i); 604 } 605 606 ret = ath12k_pci_ext_irq_config(ab); 607 if (ret) 608 return ret; 609 610 return 0; 611 } 612 613 static void ath12k_pci_init_qmi_ce_config(struct ath12k_base *ab) 614 { 615 struct ath12k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg; 616 617 cfg->tgt_ce = ab->hw_params->target_ce_config; 618 cfg->tgt_ce_len = ab->hw_params->target_ce_count; 619 620 cfg->svc_to_ce_map = ab->hw_params->svc_to_ce_map; 621 cfg->svc_to_ce_map_len = ab->hw_params->svc_to_ce_map_len; 622 ab->qmi.service_ins_id = ab->hw_params->qmi_service_ins_id; 623 } 624 625 static void ath12k_pci_ce_irqs_enable(struct ath12k_base *ab) 626 { 627 int i; 628 629 for (i = 0; i < ab->hw_params->ce_count; i++) { 630 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 631 continue; 632 ath12k_pci_ce_irq_enable(ab, i); 633 } 634 } 635 636 static void ath12k_pci_msi_config(struct ath12k_pci *ab_pci, bool enable) 637 { 638 struct pci_dev *dev = ab_pci->pdev; 639 u16 control; 640 641 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); 642 643 if (enable) 644 control |= PCI_MSI_FLAGS_ENABLE; 645 else 646 control &= ~PCI_MSI_FLAGS_ENABLE; 647 648 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); 649 } 650 651 static void ath12k_pci_msi_enable(struct ath12k_pci *ab_pci) 652 { 653 ath12k_pci_msi_config(ab_pci, true); 654 } 655 656 static void ath12k_pci_msi_disable(struct ath12k_pci *ab_pci) 657 { 658 ath12k_pci_msi_config(ab_pci, false); 659 } 660 661 static int ath12k_pci_msi_alloc(struct ath12k_pci *ab_pci) 662 { 663 struct ath12k_base *ab = ab_pci->ab; 664 const struct ath12k_msi_config *msi_config = ab_pci->msi_config; 665 struct msi_desc *msi_desc; 666 int num_vectors; 667 int ret; 668 669 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev, 670 msi_config->total_vectors, 671 msi_config->total_vectors, 672 PCI_IRQ_MSI); 673 if (num_vectors != msi_config->total_vectors) { 674 ath12k_err(ab, "failed to get %d MSI vectors, only %d available", 675 msi_config->total_vectors, num_vectors); 676 677 if (num_vectors >= 0) 678 return -EINVAL; 679 else 680 return num_vectors; 681 } 682 683 ath12k_pci_msi_disable(ab_pci); 684 685 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq); 686 if (!msi_desc) { 687 ath12k_err(ab, "msi_desc is NULL!\n"); 688 ret = -EINVAL; 689 goto free_msi_vector; 690 } 691 692 ab_pci->msi_ep_base_data = msi_desc->msg.data; 693 if (msi_desc->pci.msi_attrib.is_64) 694 set_bit(ATH12K_PCI_FLAG_IS_MSI_64, &ab_pci->flags); 695 696 ath12k_dbg(ab, ATH12K_DBG_PCI, "msi base data is %d\n", ab_pci->msi_ep_base_data); 697 698 return 0; 699 700 free_msi_vector: 701 pci_free_irq_vectors(ab_pci->pdev); 702 703 return ret; 704 } 705 706 static void ath12k_pci_msi_free(struct ath12k_pci *ab_pci) 707 { 708 pci_free_irq_vectors(ab_pci->pdev); 709 } 710 711 static int ath12k_pci_claim(struct ath12k_pci *ab_pci, struct pci_dev *pdev) 712 { 713 struct ath12k_base *ab = ab_pci->ab; 714 u16 device_id; 715 int ret = 0; 716 717 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id); 718 if (device_id != ab_pci->dev_id) { 719 ath12k_err(ab, "pci device id mismatch: 0x%x 0x%x\n", 720 device_id, ab_pci->dev_id); 721 ret = -EIO; 722 goto out; 723 } 724 725 ret = pci_assign_resource(pdev, ATH12K_PCI_BAR_NUM); 726 if (ret) { 727 ath12k_err(ab, "failed to assign pci resource: %d\n", ret); 728 goto out; 729 } 730 731 ret = pci_enable_device(pdev); 732 if (ret) { 733 ath12k_err(ab, "failed to enable pci device: %d\n", ret); 734 goto out; 735 } 736 737 ret = pci_request_region(pdev, ATH12K_PCI_BAR_NUM, "ath12k_pci"); 738 if (ret) { 739 ath12k_err(ab, "failed to request pci region: %d\n", ret); 740 goto disable_device; 741 } 742 743 ret = dma_set_mask_and_coherent(&pdev->dev, 744 DMA_BIT_MASK(ATH12K_PCI_DMA_MASK)); 745 if (ret) { 746 ath12k_err(ab, "failed to set pci dma mask to %d: %d\n", 747 ATH12K_PCI_DMA_MASK, ret); 748 goto release_region; 749 } 750 751 pci_set_master(pdev); 752 753 ab->mem_len = pci_resource_len(pdev, ATH12K_PCI_BAR_NUM); 754 ab->mem = pci_iomap(pdev, ATH12K_PCI_BAR_NUM, 0); 755 if (!ab->mem) { 756 ath12k_err(ab, "failed to map pci bar %d\n", ATH12K_PCI_BAR_NUM); 757 ret = -EIO; 758 goto release_region; 759 } 760 761 ath12k_dbg(ab, ATH12K_DBG_BOOT, "boot pci_mem 0x%pK\n", ab->mem); 762 return 0; 763 764 release_region: 765 pci_release_region(pdev, ATH12K_PCI_BAR_NUM); 766 disable_device: 767 pci_disable_device(pdev); 768 out: 769 return ret; 770 } 771 772 static void ath12k_pci_free_region(struct ath12k_pci *ab_pci) 773 { 774 struct ath12k_base *ab = ab_pci->ab; 775 struct pci_dev *pci_dev = ab_pci->pdev; 776 777 pci_iounmap(pci_dev, ab->mem); 778 ab->mem = NULL; 779 pci_release_region(pci_dev, ATH12K_PCI_BAR_NUM); 780 if (pci_is_enabled(pci_dev)) 781 pci_disable_device(pci_dev); 782 } 783 784 static void ath12k_pci_aspm_disable(struct ath12k_pci *ab_pci) 785 { 786 struct ath12k_base *ab = ab_pci->ab; 787 788 pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL, 789 &ab_pci->link_ctl); 790 791 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci link_ctl 0x%04x L0s %d L1 %d\n", 792 ab_pci->link_ctl, 793 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S), 794 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1)); 795 796 /* disable L0s and L1 */ 797 pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL, 798 ab_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC); 799 800 set_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags); 801 } 802 803 static void ath12k_pci_aspm_restore(struct ath12k_pci *ab_pci) 804 { 805 if (test_and_clear_bit(ATH12K_PCI_ASPM_RESTORE, &ab_pci->flags)) 806 pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL, 807 ab_pci->link_ctl); 808 } 809 810 static void ath12k_pci_kill_tasklets(struct ath12k_base *ab) 811 { 812 int i; 813 814 for (i = 0; i < ab->hw_params->ce_count; i++) { 815 struct ath12k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i]; 816 817 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 818 continue; 819 820 tasklet_kill(&ce_pipe->intr_tq); 821 } 822 } 823 824 static void ath12k_pci_ce_irq_disable_sync(struct ath12k_base *ab) 825 { 826 ath12k_pci_ce_irqs_disable(ab); 827 ath12k_pci_sync_ce_irqs(ab); 828 ath12k_pci_kill_tasklets(ab); 829 } 830 831 int ath12k_pci_map_service_to_pipe(struct ath12k_base *ab, u16 service_id, 832 u8 *ul_pipe, u8 *dl_pipe) 833 { 834 const struct service_to_pipe *entry; 835 bool ul_set = false, dl_set = false; 836 int i; 837 838 for (i = 0; i < ab->hw_params->svc_to_ce_map_len; i++) { 839 entry = &ab->hw_params->svc_to_ce_map[i]; 840 841 if (__le32_to_cpu(entry->service_id) != service_id) 842 continue; 843 844 switch (__le32_to_cpu(entry->pipedir)) { 845 case PIPEDIR_NONE: 846 break; 847 case PIPEDIR_IN: 848 WARN_ON(dl_set); 849 *dl_pipe = __le32_to_cpu(entry->pipenum); 850 dl_set = true; 851 break; 852 case PIPEDIR_OUT: 853 WARN_ON(ul_set); 854 *ul_pipe = __le32_to_cpu(entry->pipenum); 855 ul_set = true; 856 break; 857 case PIPEDIR_INOUT: 858 WARN_ON(dl_set); 859 WARN_ON(ul_set); 860 *dl_pipe = __le32_to_cpu(entry->pipenum); 861 *ul_pipe = __le32_to_cpu(entry->pipenum); 862 dl_set = true; 863 ul_set = true; 864 break; 865 } 866 } 867 868 if (WARN_ON(!ul_set || !dl_set)) 869 return -ENOENT; 870 871 return 0; 872 } 873 874 int ath12k_pci_get_msi_irq(struct device *dev, unsigned int vector) 875 { 876 struct pci_dev *pci_dev = to_pci_dev(dev); 877 878 return pci_irq_vector(pci_dev, vector); 879 } 880 881 int ath12k_pci_get_user_msi_assignment(struct ath12k_base *ab, char *user_name, 882 int *num_vectors, u32 *user_base_data, 883 u32 *base_vector) 884 { 885 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 886 const struct ath12k_msi_config *msi_config = ab_pci->msi_config; 887 int idx; 888 889 for (idx = 0; idx < msi_config->total_users; idx++) { 890 if (strcmp(user_name, msi_config->users[idx].name) == 0) { 891 *num_vectors = msi_config->users[idx].num_vectors; 892 *user_base_data = msi_config->users[idx].base_vector 893 + ab_pci->msi_ep_base_data; 894 *base_vector = msi_config->users[idx].base_vector; 895 896 ath12k_dbg(ab, ATH12K_DBG_PCI, "Assign MSI to user: %s, num_vectors: %d, user_base_data: %u, base_vector: %u\n", 897 user_name, *num_vectors, *user_base_data, 898 *base_vector); 899 900 return 0; 901 } 902 } 903 904 ath12k_err(ab, "Failed to find MSI assignment for %s!\n", user_name); 905 906 return -EINVAL; 907 } 908 909 void ath12k_pci_get_msi_address(struct ath12k_base *ab, u32 *msi_addr_lo, 910 u32 *msi_addr_hi) 911 { 912 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 913 struct pci_dev *pci_dev = to_pci_dev(ab->dev); 914 915 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO, 916 msi_addr_lo); 917 918 if (test_bit(ATH12K_PCI_FLAG_IS_MSI_64, &ab_pci->flags)) { 919 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI, 920 msi_addr_hi); 921 } else { 922 *msi_addr_hi = 0; 923 } 924 } 925 926 void ath12k_pci_get_ce_msi_idx(struct ath12k_base *ab, u32 ce_id, 927 u32 *msi_idx) 928 { 929 u32 i, msi_data_idx; 930 931 for (i = 0, msi_data_idx = 0; i < ab->hw_params->ce_count; i++) { 932 if (ath12k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 933 continue; 934 935 if (ce_id == i) 936 break; 937 938 msi_data_idx++; 939 } 940 *msi_idx = msi_data_idx; 941 } 942 943 void ath12k_pci_hif_ce_irq_enable(struct ath12k_base *ab) 944 { 945 ath12k_pci_ce_irqs_enable(ab); 946 } 947 948 void ath12k_pci_hif_ce_irq_disable(struct ath12k_base *ab) 949 { 950 ath12k_pci_ce_irq_disable_sync(ab); 951 } 952 953 void ath12k_pci_ext_irq_enable(struct ath12k_base *ab) 954 { 955 int i; 956 957 for (i = 0; i < ATH12K_EXT_IRQ_GRP_NUM_MAX; i++) { 958 struct ath12k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 959 960 napi_enable(&irq_grp->napi); 961 ath12k_pci_ext_grp_enable(irq_grp); 962 } 963 } 964 965 void ath12k_pci_ext_irq_disable(struct ath12k_base *ab) 966 { 967 __ath12k_pci_ext_irq_disable(ab); 968 ath12k_pci_sync_ext_irqs(ab); 969 } 970 971 int ath12k_pci_hif_suspend(struct ath12k_base *ab) 972 { 973 struct ath12k_pci *ar_pci = ath12k_pci_priv(ab); 974 975 ath12k_mhi_suspend(ar_pci); 976 977 return 0; 978 } 979 980 int ath12k_pci_hif_resume(struct ath12k_base *ab) 981 { 982 struct ath12k_pci *ar_pci = ath12k_pci_priv(ab); 983 984 ath12k_mhi_resume(ar_pci); 985 986 return 0; 987 } 988 989 void ath12k_pci_stop(struct ath12k_base *ab) 990 { 991 ath12k_pci_ce_irq_disable_sync(ab); 992 ath12k_ce_cleanup_pipes(ab); 993 } 994 995 int ath12k_pci_start(struct ath12k_base *ab) 996 { 997 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 998 999 set_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags); 1000 1001 ath12k_pci_aspm_restore(ab_pci); 1002 1003 ath12k_pci_ce_irqs_enable(ab); 1004 ath12k_ce_rx_post_buf(ab); 1005 1006 return 0; 1007 } 1008 1009 u32 ath12k_pci_read32(struct ath12k_base *ab, u32 offset) 1010 { 1011 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1012 u32 val, window_start; 1013 int ret = 0; 1014 1015 /* for offset beyond BAR + 4K - 32, may 1016 * need to wakeup MHI to access. 1017 */ 1018 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 1019 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->wakeup) 1020 ret = ab_pci->pci_ops->wakeup(ab); 1021 1022 if (offset < WINDOW_START) { 1023 val = ioread32(ab->mem + offset); 1024 } else { 1025 if (ab->static_window_map) 1026 window_start = ath12k_pci_get_window_start(ab, offset); 1027 else 1028 window_start = WINDOW_START; 1029 1030 if (window_start == WINDOW_START) { 1031 spin_lock_bh(&ab_pci->window_lock); 1032 ath12k_pci_select_window(ab_pci, offset); 1033 val = ioread32(ab->mem + window_start + 1034 (offset & WINDOW_RANGE_MASK)); 1035 spin_unlock_bh(&ab_pci->window_lock); 1036 } else { 1037 if ((!window_start) && 1038 (offset >= PCI_MHIREGLEN_REG && 1039 offset <= PCI_MHI_REGION_END)) 1040 offset = offset - PCI_MHIREGLEN_REG; 1041 1042 val = ioread32(ab->mem + window_start + 1043 (offset & WINDOW_RANGE_MASK)); 1044 } 1045 } 1046 1047 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 1048 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->release && 1049 !ret) 1050 ab_pci->pci_ops->release(ab); 1051 return val; 1052 } 1053 1054 void ath12k_pci_write32(struct ath12k_base *ab, u32 offset, u32 value) 1055 { 1056 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1057 u32 window_start; 1058 int ret = 0; 1059 1060 /* for offset beyond BAR + 4K - 32, may 1061 * need to wakeup MHI to access. 1062 */ 1063 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 1064 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->wakeup) 1065 ret = ab_pci->pci_ops->wakeup(ab); 1066 1067 if (offset < WINDOW_START) { 1068 iowrite32(value, ab->mem + offset); 1069 } else { 1070 if (ab->static_window_map) 1071 window_start = ath12k_pci_get_window_start(ab, offset); 1072 else 1073 window_start = WINDOW_START; 1074 1075 if (window_start == WINDOW_START) { 1076 spin_lock_bh(&ab_pci->window_lock); 1077 ath12k_pci_select_window(ab_pci, offset); 1078 iowrite32(value, ab->mem + window_start + 1079 (offset & WINDOW_RANGE_MASK)); 1080 spin_unlock_bh(&ab_pci->window_lock); 1081 } else { 1082 if ((!window_start) && 1083 (offset >= PCI_MHIREGLEN_REG && 1084 offset <= PCI_MHI_REGION_END)) 1085 offset = offset - PCI_MHIREGLEN_REG; 1086 1087 iowrite32(value, ab->mem + window_start + 1088 (offset & WINDOW_RANGE_MASK)); 1089 } 1090 } 1091 1092 if (test_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 1093 offset >= ACCESS_ALWAYS_OFF && ab_pci->pci_ops->release && 1094 !ret) 1095 ab_pci->pci_ops->release(ab); 1096 } 1097 1098 int ath12k_pci_power_up(struct ath12k_base *ab) 1099 { 1100 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1101 int ret; 1102 1103 ab_pci->register_window = 0; 1104 clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags); 1105 ath12k_pci_sw_reset(ab_pci->ab, true); 1106 1107 /* Disable ASPM during firmware download due to problems switching 1108 * to AMSS state. 1109 */ 1110 ath12k_pci_aspm_disable(ab_pci); 1111 1112 ath12k_pci_msi_enable(ab_pci); 1113 1114 ret = ath12k_mhi_start(ab_pci); 1115 if (ret) { 1116 ath12k_err(ab, "failed to start mhi: %d\n", ret); 1117 return ret; 1118 } 1119 1120 if (ab->static_window_map) 1121 ath12k_pci_select_static_window(ab_pci); 1122 1123 return 0; 1124 } 1125 1126 void ath12k_pci_power_down(struct ath12k_base *ab) 1127 { 1128 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1129 1130 /* restore aspm in case firmware bootup fails */ 1131 ath12k_pci_aspm_restore(ab_pci); 1132 1133 ath12k_pci_force_wake(ab_pci->ab); 1134 ath12k_pci_msi_disable(ab_pci); 1135 ath12k_mhi_stop(ab_pci); 1136 clear_bit(ATH12K_PCI_FLAG_INIT_DONE, &ab_pci->flags); 1137 ath12k_pci_sw_reset(ab_pci->ab, false); 1138 } 1139 1140 static const struct ath12k_hif_ops ath12k_pci_hif_ops = { 1141 .start = ath12k_pci_start, 1142 .stop = ath12k_pci_stop, 1143 .read32 = ath12k_pci_read32, 1144 .write32 = ath12k_pci_write32, 1145 .power_down = ath12k_pci_power_down, 1146 .power_up = ath12k_pci_power_up, 1147 .suspend = ath12k_pci_hif_suspend, 1148 .resume = ath12k_pci_hif_resume, 1149 .irq_enable = ath12k_pci_ext_irq_enable, 1150 .irq_disable = ath12k_pci_ext_irq_disable, 1151 .get_msi_address = ath12k_pci_get_msi_address, 1152 .get_user_msi_vector = ath12k_pci_get_user_msi_assignment, 1153 .map_service_to_pipe = ath12k_pci_map_service_to_pipe, 1154 .ce_irq_enable = ath12k_pci_hif_ce_irq_enable, 1155 .ce_irq_disable = ath12k_pci_hif_ce_irq_disable, 1156 .get_ce_msi_idx = ath12k_pci_get_ce_msi_idx, 1157 }; 1158 1159 static 1160 void ath12k_pci_read_hw_version(struct ath12k_base *ab, u32 *major, u32 *minor) 1161 { 1162 u32 soc_hw_version; 1163 1164 soc_hw_version = ath12k_pci_read32(ab, TCSR_SOC_HW_VERSION); 1165 *major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK, 1166 soc_hw_version); 1167 *minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK, 1168 soc_hw_version); 1169 1170 ath12k_dbg(ab, ATH12K_DBG_PCI, 1171 "pci tcsr_soc_hw_version major %d minor %d\n", 1172 *major, *minor); 1173 } 1174 1175 static int ath12k_pci_probe(struct pci_dev *pdev, 1176 const struct pci_device_id *pci_dev) 1177 { 1178 struct ath12k_base *ab; 1179 struct ath12k_pci *ab_pci; 1180 u32 soc_hw_version_major, soc_hw_version_minor; 1181 int ret; 1182 1183 ab = ath12k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH12K_BUS_PCI); 1184 if (!ab) { 1185 dev_err(&pdev->dev, "failed to allocate ath12k base\n"); 1186 return -ENOMEM; 1187 } 1188 1189 ab->dev = &pdev->dev; 1190 pci_set_drvdata(pdev, ab); 1191 ab_pci = ath12k_pci_priv(ab); 1192 ab_pci->dev_id = pci_dev->device; 1193 ab_pci->ab = ab; 1194 ab_pci->pdev = pdev; 1195 ab->hif.ops = &ath12k_pci_hif_ops; 1196 pci_set_drvdata(pdev, ab); 1197 spin_lock_init(&ab_pci->window_lock); 1198 1199 ret = ath12k_pci_claim(ab_pci, pdev); 1200 if (ret) { 1201 ath12k_err(ab, "failed to claim device: %d\n", ret); 1202 goto err_free_core; 1203 } 1204 1205 switch (pci_dev->device) { 1206 case QCN9274_DEVICE_ID: 1207 ab_pci->msi_config = &ath12k_msi_config[0]; 1208 ab->static_window_map = true; 1209 ab_pci->pci_ops = &ath12k_pci_ops_qcn9274; 1210 ath12k_pci_read_hw_version(ab, &soc_hw_version_major, 1211 &soc_hw_version_minor); 1212 switch (soc_hw_version_major) { 1213 case ATH12K_PCI_SOC_HW_VERSION_2: 1214 ab->hw_rev = ATH12K_HW_QCN9274_HW20; 1215 break; 1216 case ATH12K_PCI_SOC_HW_VERSION_1: 1217 ab->hw_rev = ATH12K_HW_QCN9274_HW10; 1218 break; 1219 default: 1220 dev_err(&pdev->dev, 1221 "Unknown hardware version found for QCN9274: 0x%x\n", 1222 soc_hw_version_major); 1223 ret = -EOPNOTSUPP; 1224 goto err_pci_free_region; 1225 } 1226 break; 1227 case WCN7850_DEVICE_ID: 1228 ab_pci->msi_config = &ath12k_msi_config[0]; 1229 ab->static_window_map = false; 1230 ab->hw_rev = ATH12K_HW_WCN7850_HW20; 1231 ab_pci->pci_ops = &ath12k_pci_ops_wcn7850; 1232 break; 1233 1234 default: 1235 dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n", 1236 pci_dev->device); 1237 ret = -EOPNOTSUPP; 1238 goto err_pci_free_region; 1239 } 1240 1241 ret = ath12k_pci_msi_alloc(ab_pci); 1242 if (ret) { 1243 ath12k_err(ab, "failed to alloc msi: %d\n", ret); 1244 goto err_pci_free_region; 1245 } 1246 1247 ret = ath12k_core_pre_init(ab); 1248 if (ret) 1249 goto err_pci_msi_free; 1250 1251 ret = ath12k_mhi_register(ab_pci); 1252 if (ret) { 1253 ath12k_err(ab, "failed to register mhi: %d\n", ret); 1254 goto err_pci_msi_free; 1255 } 1256 1257 ret = ath12k_hal_srng_init(ab); 1258 if (ret) 1259 goto err_mhi_unregister; 1260 1261 ret = ath12k_ce_alloc_pipes(ab); 1262 if (ret) { 1263 ath12k_err(ab, "failed to allocate ce pipes: %d\n", ret); 1264 goto err_hal_srng_deinit; 1265 } 1266 1267 ath12k_pci_init_qmi_ce_config(ab); 1268 1269 ret = ath12k_pci_config_irq(ab); 1270 if (ret) { 1271 ath12k_err(ab, "failed to config irq: %d\n", ret); 1272 goto err_ce_free; 1273 } 1274 1275 ret = ath12k_core_init(ab); 1276 if (ret) { 1277 ath12k_err(ab, "failed to init core: %d\n", ret); 1278 goto err_free_irq; 1279 } 1280 return 0; 1281 1282 err_free_irq: 1283 ath12k_pci_free_irq(ab); 1284 1285 err_ce_free: 1286 ath12k_ce_free_pipes(ab); 1287 1288 err_hal_srng_deinit: 1289 ath12k_hal_srng_deinit(ab); 1290 1291 err_mhi_unregister: 1292 ath12k_mhi_unregister(ab_pci); 1293 1294 err_pci_msi_free: 1295 ath12k_pci_msi_free(ab_pci); 1296 1297 err_pci_free_region: 1298 ath12k_pci_free_region(ab_pci); 1299 1300 err_free_core: 1301 ath12k_core_free(ab); 1302 1303 return ret; 1304 } 1305 1306 static void ath12k_pci_remove(struct pci_dev *pdev) 1307 { 1308 struct ath12k_base *ab = pci_get_drvdata(pdev); 1309 struct ath12k_pci *ab_pci = ath12k_pci_priv(ab); 1310 1311 if (test_bit(ATH12K_FLAG_QMI_FAIL, &ab->dev_flags)) { 1312 ath12k_pci_power_down(ab); 1313 ath12k_qmi_deinit_service(ab); 1314 goto qmi_fail; 1315 } 1316 1317 set_bit(ATH12K_FLAG_UNREGISTERING, &ab->dev_flags); 1318 1319 cancel_work_sync(&ab->reset_work); 1320 ath12k_core_deinit(ab); 1321 1322 qmi_fail: 1323 ath12k_mhi_unregister(ab_pci); 1324 1325 ath12k_pci_free_irq(ab); 1326 ath12k_pci_msi_free(ab_pci); 1327 ath12k_pci_free_region(ab_pci); 1328 1329 ath12k_hal_srng_deinit(ab); 1330 ath12k_ce_free_pipes(ab); 1331 ath12k_core_free(ab); 1332 } 1333 1334 static void ath12k_pci_shutdown(struct pci_dev *pdev) 1335 { 1336 struct ath12k_base *ab = pci_get_drvdata(pdev); 1337 1338 ath12k_pci_power_down(ab); 1339 } 1340 1341 static __maybe_unused int ath12k_pci_pm_suspend(struct device *dev) 1342 { 1343 struct ath12k_base *ab = dev_get_drvdata(dev); 1344 int ret; 1345 1346 ret = ath12k_core_suspend(ab); 1347 if (ret) 1348 ath12k_warn(ab, "failed to suspend core: %d\n", ret); 1349 1350 return ret; 1351 } 1352 1353 static __maybe_unused int ath12k_pci_pm_resume(struct device *dev) 1354 { 1355 struct ath12k_base *ab = dev_get_drvdata(dev); 1356 int ret; 1357 1358 ret = ath12k_core_resume(ab); 1359 if (ret) 1360 ath12k_warn(ab, "failed to resume core: %d\n", ret); 1361 1362 return ret; 1363 } 1364 1365 static SIMPLE_DEV_PM_OPS(ath12k_pci_pm_ops, 1366 ath12k_pci_pm_suspend, 1367 ath12k_pci_pm_resume); 1368 1369 static struct pci_driver ath12k_pci_driver = { 1370 .name = "ath12k_pci", 1371 .id_table = ath12k_pci_id_table, 1372 .probe = ath12k_pci_probe, 1373 .remove = ath12k_pci_remove, 1374 .shutdown = ath12k_pci_shutdown, 1375 .driver.pm = &ath12k_pci_pm_ops, 1376 }; 1377 1378 static int ath12k_pci_init(void) 1379 { 1380 int ret; 1381 1382 ret = pci_register_driver(&ath12k_pci_driver); 1383 if (ret) { 1384 pr_err("failed to register ath12k pci driver: %d\n", 1385 ret); 1386 return ret; 1387 } 1388 1389 return 0; 1390 } 1391 module_init(ath12k_pci_init); 1392 1393 static void ath12k_pci_exit(void) 1394 { 1395 pci_unregister_driver(&ath12k_pci_driver); 1396 } 1397 1398 module_exit(ath12k_pci_exit); 1399 1400 MODULE_DESCRIPTION("Driver support for Qualcomm Technologies 802.11be WLAN PCIe devices"); 1401 MODULE_LICENSE("Dual BSD/GPL"); 1402