1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/types.h> 8 #include <linux/bitops.h> 9 #include <linux/bitfield.h> 10 11 #include "debug.h" 12 #include "core.h" 13 #include "ce.h" 14 #include "hw.h" 15 #include "mhi.h" 16 #include "dp_rx.h" 17 18 static u8 ath12k_hw_qcn9274_mac_from_pdev_id(int pdev_idx) 19 { 20 return pdev_idx; 21 } 22 23 static int ath12k_hw_mac_id_to_pdev_id_qcn9274(const struct ath12k_hw_params *hw, 24 int mac_id) 25 { 26 return mac_id; 27 } 28 29 static int ath12k_hw_mac_id_to_srng_id_qcn9274(const struct ath12k_hw_params *hw, 30 int mac_id) 31 { 32 return 0; 33 } 34 35 static u8 ath12k_hw_get_ring_selector_qcn9274(struct sk_buff *skb) 36 { 37 return smp_processor_id(); 38 } 39 40 static bool ath12k_dp_srng_is_comp_ring_qcn9274(int ring_num) 41 { 42 if (ring_num < 3 || ring_num == 4) 43 return true; 44 45 return false; 46 } 47 48 static int ath12k_hw_mac_id_to_pdev_id_wcn7850(const struct ath12k_hw_params *hw, 49 int mac_id) 50 { 51 return 0; 52 } 53 54 static int ath12k_hw_mac_id_to_srng_id_wcn7850(const struct ath12k_hw_params *hw, 55 int mac_id) 56 { 57 return mac_id; 58 } 59 60 static u8 ath12k_hw_get_ring_selector_wcn7850(struct sk_buff *skb) 61 { 62 return skb_get_queue_mapping(skb); 63 } 64 65 static bool ath12k_dp_srng_is_comp_ring_wcn7850(int ring_num) 66 { 67 if (ring_num == 0 || ring_num == 2 || ring_num == 4) 68 return true; 69 70 return false; 71 } 72 73 static const struct ath12k_hw_ops qcn9274_ops = { 74 .get_hw_mac_from_pdev_id = ath12k_hw_qcn9274_mac_from_pdev_id, 75 .mac_id_to_pdev_id = ath12k_hw_mac_id_to_pdev_id_qcn9274, 76 .mac_id_to_srng_id = ath12k_hw_mac_id_to_srng_id_qcn9274, 77 .rxdma_ring_sel_config = ath12k_dp_rxdma_ring_sel_config_qcn9274, 78 .get_ring_selector = ath12k_hw_get_ring_selector_qcn9274, 79 .dp_srng_is_tx_comp_ring = ath12k_dp_srng_is_comp_ring_qcn9274, 80 }; 81 82 static const struct ath12k_hw_ops wcn7850_ops = { 83 .get_hw_mac_from_pdev_id = ath12k_hw_qcn9274_mac_from_pdev_id, 84 .mac_id_to_pdev_id = ath12k_hw_mac_id_to_pdev_id_wcn7850, 85 .mac_id_to_srng_id = ath12k_hw_mac_id_to_srng_id_wcn7850, 86 .rxdma_ring_sel_config = ath12k_dp_rxdma_ring_sel_config_wcn7850, 87 .get_ring_selector = ath12k_hw_get_ring_selector_wcn7850, 88 .dp_srng_is_tx_comp_ring = ath12k_dp_srng_is_comp_ring_wcn7850, 89 }; 90 91 #define ATH12K_TX_RING_MASK_0 0x1 92 #define ATH12K_TX_RING_MASK_1 0x2 93 #define ATH12K_TX_RING_MASK_2 0x4 94 #define ATH12K_TX_RING_MASK_3 0x8 95 #define ATH12K_TX_RING_MASK_4 0x10 96 97 #define ATH12K_RX_RING_MASK_0 0x1 98 #define ATH12K_RX_RING_MASK_1 0x2 99 #define ATH12K_RX_RING_MASK_2 0x4 100 #define ATH12K_RX_RING_MASK_3 0x8 101 102 #define ATH12K_RX_ERR_RING_MASK_0 0x1 103 104 #define ATH12K_RX_WBM_REL_RING_MASK_0 0x1 105 106 #define ATH12K_REO_STATUS_RING_MASK_0 0x1 107 108 #define ATH12K_HOST2RXDMA_RING_MASK_0 0x1 109 110 #define ATH12K_RX_MON_RING_MASK_0 0x1 111 #define ATH12K_RX_MON_RING_MASK_1 0x2 112 #define ATH12K_RX_MON_RING_MASK_2 0x4 113 114 #define ATH12K_TX_MON_RING_MASK_0 0x1 115 #define ATH12K_TX_MON_RING_MASK_1 0x2 116 117 /* Target firmware's Copy Engine configuration. */ 118 static const struct ce_pipe_config ath12k_target_ce_config_wlan_qcn9274[] = { 119 /* CE0: host->target HTC control and raw streams */ 120 { 121 .pipenum = __cpu_to_le32(0), 122 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 123 .nentries = __cpu_to_le32(32), 124 .nbytes_max = __cpu_to_le32(2048), 125 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 126 .reserved = __cpu_to_le32(0), 127 }, 128 129 /* CE1: target->host HTT + HTC control */ 130 { 131 .pipenum = __cpu_to_le32(1), 132 .pipedir = __cpu_to_le32(PIPEDIR_IN), 133 .nentries = __cpu_to_le32(32), 134 .nbytes_max = __cpu_to_le32(2048), 135 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 136 .reserved = __cpu_to_le32(0), 137 }, 138 139 /* CE2: target->host WMI */ 140 { 141 .pipenum = __cpu_to_le32(2), 142 .pipedir = __cpu_to_le32(PIPEDIR_IN), 143 .nentries = __cpu_to_le32(32), 144 .nbytes_max = __cpu_to_le32(2048), 145 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 146 .reserved = __cpu_to_le32(0), 147 }, 148 149 /* CE3: host->target WMI (mac0) */ 150 { 151 .pipenum = __cpu_to_le32(3), 152 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 153 .nentries = __cpu_to_le32(32), 154 .nbytes_max = __cpu_to_le32(2048), 155 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 156 .reserved = __cpu_to_le32(0), 157 }, 158 159 /* CE4: host->target HTT */ 160 { 161 .pipenum = __cpu_to_le32(4), 162 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 163 .nentries = __cpu_to_le32(256), 164 .nbytes_max = __cpu_to_le32(256), 165 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 166 .reserved = __cpu_to_le32(0), 167 }, 168 169 /* CE5: target->host Pktlog */ 170 { 171 .pipenum = __cpu_to_le32(5), 172 .pipedir = __cpu_to_le32(PIPEDIR_IN), 173 .nentries = __cpu_to_le32(32), 174 .nbytes_max = __cpu_to_le32(2048), 175 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 176 .reserved = __cpu_to_le32(0), 177 }, 178 179 /* CE6: Reserved for target autonomous hif_memcpy */ 180 { 181 .pipenum = __cpu_to_le32(6), 182 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 183 .nentries = __cpu_to_le32(32), 184 .nbytes_max = __cpu_to_le32(16384), 185 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 186 .reserved = __cpu_to_le32(0), 187 }, 188 189 /* CE7: host->target WMI (mac1) */ 190 { 191 .pipenum = __cpu_to_le32(7), 192 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 193 .nentries = __cpu_to_le32(32), 194 .nbytes_max = __cpu_to_le32(2048), 195 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 196 .reserved = __cpu_to_le32(0), 197 }, 198 199 /* CE8: Reserved for target autonomous hif_memcpy */ 200 { 201 .pipenum = __cpu_to_le32(8), 202 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 203 .nentries = __cpu_to_le32(32), 204 .nbytes_max = __cpu_to_le32(16384), 205 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 206 .reserved = __cpu_to_le32(0), 207 }, 208 209 /* CE9, 10 and 11: Reserved for MHI */ 210 211 /* CE12: Target CV prefetch */ 212 { 213 .pipenum = __cpu_to_le32(12), 214 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 215 .nentries = __cpu_to_le32(32), 216 .nbytes_max = __cpu_to_le32(2048), 217 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 218 .reserved = __cpu_to_le32(0), 219 }, 220 221 /* CE13: Target CV prefetch */ 222 { 223 .pipenum = __cpu_to_le32(13), 224 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 225 .nentries = __cpu_to_le32(32), 226 .nbytes_max = __cpu_to_le32(2048), 227 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 228 .reserved = __cpu_to_le32(0), 229 }, 230 231 /* CE14: WMI logging/CFR/Spectral/Radar */ 232 { 233 .pipenum = __cpu_to_le32(14), 234 .pipedir = __cpu_to_le32(PIPEDIR_IN), 235 .nentries = __cpu_to_le32(32), 236 .nbytes_max = __cpu_to_le32(2048), 237 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 238 .reserved = __cpu_to_le32(0), 239 }, 240 241 /* CE15: Reserved */ 242 }; 243 244 /* Target firmware's Copy Engine configuration. */ 245 static const struct ce_pipe_config ath12k_target_ce_config_wlan_wcn7850[] = { 246 /* CE0: host->target HTC control and raw streams */ 247 { 248 .pipenum = __cpu_to_le32(0), 249 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 250 .nentries = __cpu_to_le32(32), 251 .nbytes_max = __cpu_to_le32(2048), 252 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 253 .reserved = __cpu_to_le32(0), 254 }, 255 256 /* CE1: target->host HTT + HTC control */ 257 { 258 .pipenum = __cpu_to_le32(1), 259 .pipedir = __cpu_to_le32(PIPEDIR_IN), 260 .nentries = __cpu_to_le32(32), 261 .nbytes_max = __cpu_to_le32(2048), 262 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 263 .reserved = __cpu_to_le32(0), 264 }, 265 266 /* CE2: target->host WMI */ 267 { 268 .pipenum = __cpu_to_le32(2), 269 .pipedir = __cpu_to_le32(PIPEDIR_IN), 270 .nentries = __cpu_to_le32(32), 271 .nbytes_max = __cpu_to_le32(2048), 272 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 273 .reserved = __cpu_to_le32(0), 274 }, 275 276 /* CE3: host->target WMI */ 277 { 278 .pipenum = __cpu_to_le32(3), 279 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 280 .nentries = __cpu_to_le32(32), 281 .nbytes_max = __cpu_to_le32(2048), 282 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 283 .reserved = __cpu_to_le32(0), 284 }, 285 286 /* CE4: host->target HTT */ 287 { 288 .pipenum = __cpu_to_le32(4), 289 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 290 .nentries = __cpu_to_le32(256), 291 .nbytes_max = __cpu_to_le32(256), 292 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 293 .reserved = __cpu_to_le32(0), 294 }, 295 296 /* CE5: target->host Pktlog */ 297 { 298 .pipenum = __cpu_to_le32(5), 299 .pipedir = __cpu_to_le32(PIPEDIR_IN), 300 .nentries = __cpu_to_le32(32), 301 .nbytes_max = __cpu_to_le32(2048), 302 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 303 .reserved = __cpu_to_le32(0), 304 }, 305 306 /* CE6: Reserved for target autonomous hif_memcpy */ 307 { 308 .pipenum = __cpu_to_le32(6), 309 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 310 .nentries = __cpu_to_le32(32), 311 .nbytes_max = __cpu_to_le32(16384), 312 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 313 .reserved = __cpu_to_le32(0), 314 }, 315 316 /* CE7 used only by Host */ 317 { 318 .pipenum = __cpu_to_le32(7), 319 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 320 .nentries = __cpu_to_le32(0), 321 .nbytes_max = __cpu_to_le32(0), 322 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 323 .reserved = __cpu_to_le32(0), 324 }, 325 326 /* CE8 target->host used only by IPA */ 327 { 328 .pipenum = __cpu_to_le32(8), 329 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 330 .nentries = __cpu_to_le32(32), 331 .nbytes_max = __cpu_to_le32(16384), 332 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 333 .reserved = __cpu_to_le32(0), 334 }, 335 /* CE 9, 10, 11 are used by MHI driver */ 336 }; 337 338 /* Map from service/endpoint to Copy Engine. 339 * This table is derived from the CE_PCI TABLE, above. 340 * It is passed to the Target at startup for use by firmware. 341 */ 342 static const struct service_to_pipe ath12k_target_service_to_ce_map_wlan_qcn9274[] = { 343 { 344 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO), 345 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 346 __cpu_to_le32(3), 347 }, 348 { 349 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO), 350 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 351 __cpu_to_le32(2), 352 }, 353 { 354 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK), 355 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 356 __cpu_to_le32(3), 357 }, 358 { 359 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK), 360 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 361 __cpu_to_le32(2), 362 }, 363 { 364 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE), 365 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 366 __cpu_to_le32(3), 367 }, 368 { 369 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE), 370 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 371 __cpu_to_le32(2), 372 }, 373 { 374 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI), 375 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 376 __cpu_to_le32(3), 377 }, 378 { 379 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI), 380 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 381 __cpu_to_le32(2), 382 }, 383 { 384 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL), 385 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 386 __cpu_to_le32(3), 387 }, 388 { 389 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL), 390 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 391 __cpu_to_le32(2), 392 }, 393 { 394 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL), 395 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 396 __cpu_to_le32(0), 397 }, 398 { 399 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL), 400 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 401 __cpu_to_le32(1), 402 }, 403 { 404 __cpu_to_le32(ATH12K_HTC_SVC_ID_TEST_RAW_STREAMS), 405 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 406 __cpu_to_le32(0), 407 }, 408 { 409 __cpu_to_le32(ATH12K_HTC_SVC_ID_TEST_RAW_STREAMS), 410 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 411 __cpu_to_le32(1), 412 }, 413 { 414 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG), 415 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 416 __cpu_to_le32(4), 417 }, 418 { 419 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG), 420 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 421 __cpu_to_le32(1), 422 }, 423 { 424 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL_MAC1), 425 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 426 __cpu_to_le32(7), 427 }, 428 { 429 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL_MAC1), 430 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 431 __cpu_to_le32(2), 432 }, 433 { 434 __cpu_to_le32(ATH12K_HTC_SVC_ID_PKT_LOG), 435 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 436 __cpu_to_le32(5), 437 }, 438 { 439 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL_DIAG), 440 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 441 __cpu_to_le32(14), 442 }, 443 444 /* (Additions here) */ 445 446 { /* must be last */ 447 __cpu_to_le32(0), 448 __cpu_to_le32(0), 449 __cpu_to_le32(0), 450 }, 451 }; 452 453 static const struct service_to_pipe ath12k_target_service_to_ce_map_wlan_wcn7850[] = { 454 { 455 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO), 456 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 457 __cpu_to_le32(3), 458 }, 459 { 460 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO), 461 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 462 __cpu_to_le32(2), 463 }, 464 { 465 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK), 466 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 467 __cpu_to_le32(3), 468 }, 469 { 470 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK), 471 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 472 __cpu_to_le32(2), 473 }, 474 { 475 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE), 476 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 477 __cpu_to_le32(3), 478 }, 479 { 480 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE), 481 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 482 __cpu_to_le32(2), 483 }, 484 { 485 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI), 486 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 487 __cpu_to_le32(3), 488 }, 489 { 490 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI), 491 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 492 __cpu_to_le32(2), 493 }, 494 { 495 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL), 496 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 497 __cpu_to_le32(3), 498 }, 499 { 500 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL), 501 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 502 __cpu_to_le32(2), 503 }, 504 { 505 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL), 506 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 507 __cpu_to_le32(0), 508 }, 509 { 510 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL), 511 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 512 __cpu_to_le32(2), 513 }, 514 { 515 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG), 516 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 517 __cpu_to_le32(4), 518 }, 519 { 520 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG), 521 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 522 __cpu_to_le32(1), 523 }, 524 525 /* (Additions here) */ 526 527 { /* must be last */ 528 __cpu_to_le32(0), 529 __cpu_to_le32(0), 530 __cpu_to_le32(0), 531 }, 532 }; 533 534 static const struct ath12k_hw_ring_mask ath12k_hw_ring_mask_qcn9274 = { 535 .tx = { 536 ATH12K_TX_RING_MASK_0, 537 ATH12K_TX_RING_MASK_1, 538 ATH12K_TX_RING_MASK_2, 539 ATH12K_TX_RING_MASK_3, 540 }, 541 .rx_mon_dest = { 542 0, 0, 0, 543 ATH12K_RX_MON_RING_MASK_0, 544 ATH12K_RX_MON_RING_MASK_1, 545 ATH12K_RX_MON_RING_MASK_2, 546 }, 547 .rx = { 548 0, 0, 0, 0, 549 ATH12K_RX_RING_MASK_0, 550 ATH12K_RX_RING_MASK_1, 551 ATH12K_RX_RING_MASK_2, 552 ATH12K_RX_RING_MASK_3, 553 }, 554 .rx_err = { 555 0, 0, 0, 556 ATH12K_RX_ERR_RING_MASK_0, 557 }, 558 .rx_wbm_rel = { 559 0, 0, 0, 560 ATH12K_RX_WBM_REL_RING_MASK_0, 561 }, 562 .reo_status = { 563 0, 0, 0, 564 ATH12K_REO_STATUS_RING_MASK_0, 565 }, 566 .host2rxdma = { 567 0, 0, 0, 568 ATH12K_HOST2RXDMA_RING_MASK_0, 569 }, 570 .tx_mon_dest = { 571 ATH12K_TX_MON_RING_MASK_0, 572 ATH12K_TX_MON_RING_MASK_1, 573 }, 574 }; 575 576 static const struct ath12k_hw_ring_mask ath12k_hw_ring_mask_wcn7850 = { 577 .tx = { 578 ATH12K_TX_RING_MASK_0, 579 ATH12K_TX_RING_MASK_2, 580 ATH12K_TX_RING_MASK_4, 581 }, 582 .rx_mon_dest = { 583 }, 584 .rx = { 585 0, 0, 0, 586 ATH12K_RX_RING_MASK_0, 587 ATH12K_RX_RING_MASK_1, 588 ATH12K_RX_RING_MASK_2, 589 ATH12K_RX_RING_MASK_3, 590 }, 591 .rx_err = { 592 ATH12K_RX_ERR_RING_MASK_0, 593 }, 594 .rx_wbm_rel = { 595 ATH12K_RX_WBM_REL_RING_MASK_0, 596 }, 597 .reo_status = { 598 ATH12K_REO_STATUS_RING_MASK_0, 599 }, 600 .host2rxdma = { 601 }, 602 .tx_mon_dest = { 603 }, 604 }; 605 606 static const struct ath12k_hw_regs qcn9274_v1_regs = { 607 /* SW2TCL(x) R0 ring configuration address */ 608 .hal_tcl1_ring_id = 0x00000908, 609 .hal_tcl1_ring_misc = 0x00000910, 610 .hal_tcl1_ring_tp_addr_lsb = 0x0000091c, 611 .hal_tcl1_ring_tp_addr_msb = 0x00000920, 612 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000930, 613 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000934, 614 .hal_tcl1_ring_msi1_base_lsb = 0x00000948, 615 .hal_tcl1_ring_msi1_base_msb = 0x0000094c, 616 .hal_tcl1_ring_msi1_data = 0x00000950, 617 .hal_tcl_ring_base_lsb = 0x00000b58, 618 619 /* TCL STATUS ring address */ 620 .hal_tcl_status_ring_base_lsb = 0x00000d38, 621 622 .hal_wbm_idle_ring_base_lsb = 0x00000d0c, 623 .hal_wbm_idle_ring_misc_addr = 0x00000d1c, 624 .hal_wbm_r0_idle_list_cntl_addr = 0x00000210, 625 .hal_wbm_r0_idle_list_size_addr = 0x00000214, 626 .hal_wbm_scattered_ring_base_lsb = 0x00000220, 627 .hal_wbm_scattered_ring_base_msb = 0x00000224, 628 .hal_wbm_scattered_desc_head_info_ix0 = 0x00000230, 629 .hal_wbm_scattered_desc_head_info_ix1 = 0x00000234, 630 .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000240, 631 .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000244, 632 .hal_wbm_scattered_desc_ptr_hp_addr = 0x0000024c, 633 634 .hal_wbm_sw_release_ring_base_lsb = 0x0000034c, 635 .hal_wbm_sw1_release_ring_base_lsb = 0x000003c4, 636 .hal_wbm0_release_ring_base_lsb = 0x00000dd8, 637 .hal_wbm1_release_ring_base_lsb = 0x00000e50, 638 639 /* PCIe base address */ 640 .pcie_qserdes_sysclk_en_sel = 0x01e0c0a8, 641 .pcie_pcs_osc_dtct_config_base = 0x01e0d45c, 642 643 /* PPE release ring address */ 644 .hal_ppe_rel_ring_base = 0x0000043c, 645 646 /* REO DEST ring address */ 647 .hal_reo2_ring_base = 0x0000055c, 648 .hal_reo1_misc_ctrl_addr = 0x00000b7c, 649 .hal_reo1_sw_cookie_cfg0 = 0x00000050, 650 .hal_reo1_sw_cookie_cfg1 = 0x00000054, 651 .hal_reo1_qdesc_lut_base0 = 0x00000058, 652 .hal_reo1_qdesc_lut_base1 = 0x0000005c, 653 .hal_reo1_ring_base_lsb = 0x000004e4, 654 .hal_reo1_ring_base_msb = 0x000004e8, 655 .hal_reo1_ring_id = 0x000004ec, 656 .hal_reo1_ring_misc = 0x000004f4, 657 .hal_reo1_ring_hp_addr_lsb = 0x000004f8, 658 .hal_reo1_ring_hp_addr_msb = 0x000004fc, 659 .hal_reo1_ring_producer_int_setup = 0x00000508, 660 .hal_reo1_ring_msi1_base_lsb = 0x0000052C, 661 .hal_reo1_ring_msi1_base_msb = 0x00000530, 662 .hal_reo1_ring_msi1_data = 0x00000534, 663 .hal_reo1_aging_thres_ix0 = 0x00000b08, 664 .hal_reo1_aging_thres_ix1 = 0x00000b0c, 665 .hal_reo1_aging_thres_ix2 = 0x00000b10, 666 .hal_reo1_aging_thres_ix3 = 0x00000b14, 667 668 /* REO Exception ring address */ 669 .hal_reo2_sw0_ring_base = 0x000008a4, 670 671 /* REO Reinject ring address */ 672 .hal_sw2reo_ring_base = 0x00000304, 673 .hal_sw2reo1_ring_base = 0x0000037c, 674 675 /* REO cmd ring address */ 676 .hal_reo_cmd_ring_base = 0x0000028c, 677 678 /* REO status ring address */ 679 .hal_reo_status_ring_base = 0x00000a84, 680 }; 681 682 static const struct ath12k_hw_regs qcn9274_v2_regs = { 683 /* SW2TCL(x) R0 ring configuration address */ 684 .hal_tcl1_ring_id = 0x00000908, 685 .hal_tcl1_ring_misc = 0x00000910, 686 .hal_tcl1_ring_tp_addr_lsb = 0x0000091c, 687 .hal_tcl1_ring_tp_addr_msb = 0x00000920, 688 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000930, 689 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000934, 690 .hal_tcl1_ring_msi1_base_lsb = 0x00000948, 691 .hal_tcl1_ring_msi1_base_msb = 0x0000094c, 692 .hal_tcl1_ring_msi1_data = 0x00000950, 693 .hal_tcl_ring_base_lsb = 0x00000b58, 694 695 /* TCL STATUS ring address */ 696 .hal_tcl_status_ring_base_lsb = 0x00000d38, 697 698 /* WBM idle link ring address */ 699 .hal_wbm_idle_ring_base_lsb = 0x00000d3c, 700 .hal_wbm_idle_ring_misc_addr = 0x00000d4c, 701 .hal_wbm_r0_idle_list_cntl_addr = 0x00000240, 702 .hal_wbm_r0_idle_list_size_addr = 0x00000244, 703 .hal_wbm_scattered_ring_base_lsb = 0x00000250, 704 .hal_wbm_scattered_ring_base_msb = 0x00000254, 705 .hal_wbm_scattered_desc_head_info_ix0 = 0x00000260, 706 .hal_wbm_scattered_desc_head_info_ix1 = 0x00000264, 707 .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000270, 708 .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000274, 709 .hal_wbm_scattered_desc_ptr_hp_addr = 0x0000027c, 710 711 /* SW2WBM release ring address */ 712 .hal_wbm_sw_release_ring_base_lsb = 0x0000037c, 713 .hal_wbm_sw1_release_ring_base_lsb = 0x000003f4, 714 715 /* WBM2SW release ring address */ 716 .hal_wbm0_release_ring_base_lsb = 0x00000e08, 717 .hal_wbm1_release_ring_base_lsb = 0x00000e80, 718 719 /* PCIe base address */ 720 .pcie_qserdes_sysclk_en_sel = 0x01e0c0a8, 721 .pcie_pcs_osc_dtct_config_base = 0x01e0d45c, 722 723 /* PPE release ring address */ 724 .hal_ppe_rel_ring_base = 0x0000046c, 725 726 /* REO DEST ring address */ 727 .hal_reo2_ring_base = 0x00000578, 728 .hal_reo1_misc_ctrl_addr = 0x00000b9c, 729 .hal_reo1_sw_cookie_cfg0 = 0x0000006c, 730 .hal_reo1_sw_cookie_cfg1 = 0x00000070, 731 .hal_reo1_qdesc_lut_base0 = 0x00000074, 732 .hal_reo1_qdesc_lut_base1 = 0x00000078, 733 .hal_reo1_ring_base_lsb = 0x00000500, 734 .hal_reo1_ring_base_msb = 0x00000504, 735 .hal_reo1_ring_id = 0x00000508, 736 .hal_reo1_ring_misc = 0x00000510, 737 .hal_reo1_ring_hp_addr_lsb = 0x00000514, 738 .hal_reo1_ring_hp_addr_msb = 0x00000518, 739 .hal_reo1_ring_producer_int_setup = 0x00000524, 740 .hal_reo1_ring_msi1_base_lsb = 0x00000548, 741 .hal_reo1_ring_msi1_base_msb = 0x0000054C, 742 .hal_reo1_ring_msi1_data = 0x00000550, 743 .hal_reo1_aging_thres_ix0 = 0x00000B28, 744 .hal_reo1_aging_thres_ix1 = 0x00000B2C, 745 .hal_reo1_aging_thres_ix2 = 0x00000B30, 746 .hal_reo1_aging_thres_ix3 = 0x00000B34, 747 748 /* REO Exception ring address */ 749 .hal_reo2_sw0_ring_base = 0x000008c0, 750 751 /* REO Reinject ring address */ 752 .hal_sw2reo_ring_base = 0x00000320, 753 .hal_sw2reo1_ring_base = 0x00000398, 754 755 /* REO cmd ring address */ 756 .hal_reo_cmd_ring_base = 0x000002A8, 757 758 /* REO status ring address */ 759 .hal_reo_status_ring_base = 0x00000aa0, 760 }; 761 762 static const struct ath12k_hw_regs wcn7850_regs = { 763 /* SW2TCL(x) R0 ring configuration address */ 764 .hal_tcl1_ring_id = 0x00000908, 765 .hal_tcl1_ring_misc = 0x00000910, 766 .hal_tcl1_ring_tp_addr_lsb = 0x0000091c, 767 .hal_tcl1_ring_tp_addr_msb = 0x00000920, 768 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000930, 769 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000934, 770 .hal_tcl1_ring_msi1_base_lsb = 0x00000948, 771 .hal_tcl1_ring_msi1_base_msb = 0x0000094c, 772 .hal_tcl1_ring_msi1_data = 0x00000950, 773 .hal_tcl_ring_base_lsb = 0x00000b58, 774 775 /* TCL STATUS ring address */ 776 .hal_tcl_status_ring_base_lsb = 0x00000d38, 777 778 .hal_wbm_idle_ring_base_lsb = 0x00000d3c, 779 .hal_wbm_idle_ring_misc_addr = 0x00000d4c, 780 .hal_wbm_r0_idle_list_cntl_addr = 0x00000240, 781 .hal_wbm_r0_idle_list_size_addr = 0x00000244, 782 .hal_wbm_scattered_ring_base_lsb = 0x00000250, 783 .hal_wbm_scattered_ring_base_msb = 0x00000254, 784 .hal_wbm_scattered_desc_head_info_ix0 = 0x00000260, 785 .hal_wbm_scattered_desc_head_info_ix1 = 0x00000264, 786 .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000270, 787 .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000274, 788 .hal_wbm_scattered_desc_ptr_hp_addr = 0x00000027c, 789 790 .hal_wbm_sw_release_ring_base_lsb = 0x0000037c, 791 .hal_wbm_sw1_release_ring_base_lsb = 0x00000284, 792 .hal_wbm0_release_ring_base_lsb = 0x00000e08, 793 .hal_wbm1_release_ring_base_lsb = 0x00000e80, 794 795 /* PCIe base address */ 796 .pcie_qserdes_sysclk_en_sel = 0x01e0e0a8, 797 .pcie_pcs_osc_dtct_config_base = 0x01e0f45c, 798 799 /* PPE release ring address */ 800 .hal_ppe_rel_ring_base = 0x0000043c, 801 802 /* REO DEST ring address */ 803 .hal_reo2_ring_base = 0x0000055c, 804 .hal_reo1_misc_ctrl_addr = 0x00000b7c, 805 .hal_reo1_sw_cookie_cfg0 = 0x00000050, 806 .hal_reo1_sw_cookie_cfg1 = 0x00000054, 807 .hal_reo1_qdesc_lut_base0 = 0x00000058, 808 .hal_reo1_qdesc_lut_base1 = 0x0000005c, 809 .hal_reo1_ring_base_lsb = 0x000004e4, 810 .hal_reo1_ring_base_msb = 0x000004e8, 811 .hal_reo1_ring_id = 0x000004ec, 812 .hal_reo1_ring_misc = 0x000004f4, 813 .hal_reo1_ring_hp_addr_lsb = 0x000004f8, 814 .hal_reo1_ring_hp_addr_msb = 0x000004fc, 815 .hal_reo1_ring_producer_int_setup = 0x00000508, 816 .hal_reo1_ring_msi1_base_lsb = 0x0000052C, 817 .hal_reo1_ring_msi1_base_msb = 0x00000530, 818 .hal_reo1_ring_msi1_data = 0x00000534, 819 .hal_reo1_aging_thres_ix0 = 0x00000b08, 820 .hal_reo1_aging_thres_ix1 = 0x00000b0c, 821 .hal_reo1_aging_thres_ix2 = 0x00000b10, 822 .hal_reo1_aging_thres_ix3 = 0x00000b14, 823 824 /* REO Exception ring address */ 825 .hal_reo2_sw0_ring_base = 0x000008a4, 826 827 /* REO Reinject ring address */ 828 .hal_sw2reo_ring_base = 0x00000304, 829 .hal_sw2reo1_ring_base = 0x0000037c, 830 831 /* REO cmd ring address */ 832 .hal_reo_cmd_ring_base = 0x0000028c, 833 834 /* REO status ring address */ 835 .hal_reo_status_ring_base = 0x00000a84, 836 }; 837 838 static const struct ath12k_hw_hal_params ath12k_hw_hal_params_qcn9274 = { 839 .rx_buf_rbm = HAL_RX_BUF_RBM_SW3_BM, 840 .wbm2sw_cc_enable = HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN | 841 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW1_EN | 842 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN | 843 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN | 844 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN, 845 }; 846 847 static const struct ath12k_hw_hal_params ath12k_hw_hal_params_wcn7850 = { 848 .rx_buf_rbm = HAL_RX_BUF_RBM_SW1_BM, 849 .wbm2sw_cc_enable = HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN | 850 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN | 851 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN | 852 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN, 853 }; 854 855 static const struct ath12k_hw_params ath12k_hw_params[] = { 856 { 857 .name = "qcn9274 hw1.0", 858 .hw_rev = ATH12K_HW_QCN9274_HW10, 859 .fw = { 860 .dir = "QCN9274/hw1.0", 861 .board_size = 256 * 1024, 862 .cal_offset = 128 * 1024, 863 }, 864 .max_radios = 1, 865 .single_pdev_only = false, 866 .qmi_service_ins_id = ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274, 867 .internal_sleep_clock = false, 868 869 .hw_ops = &qcn9274_ops, 870 .ring_mask = &ath12k_hw_ring_mask_qcn9274, 871 .regs = &qcn9274_v1_regs, 872 873 .host_ce_config = ath12k_host_ce_config_qcn9274, 874 .ce_count = 16, 875 .target_ce_config = ath12k_target_ce_config_wlan_qcn9274, 876 .target_ce_count = 12, 877 .svc_to_ce_map = ath12k_target_service_to_ce_map_wlan_qcn9274, 878 .svc_to_ce_map_len = 18, 879 880 .hal_params = &ath12k_hw_hal_params_qcn9274, 881 882 .rxdma1_enable = false, 883 .num_rxmda_per_pdev = 1, 884 .num_rxdma_dst_ring = 0, 885 .rx_mac_buf_ring = false, 886 .vdev_start_delay = false, 887 888 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 889 BIT(NL80211_IFTYPE_AP), 890 .supports_monitor = false, 891 892 .idle_ps = false, 893 .download_calib = true, 894 .supports_suspend = false, 895 .tcl_ring_retry = true, 896 .reoq_lut_support = false, 897 .supports_shadow_regs = false, 898 899 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9274), 900 .num_tcl_banks = 48, 901 .max_tx_ring = 4, 902 903 .mhi_config = &ath12k_mhi_config_qcn9274, 904 905 .wmi_init = ath12k_wmi_init_qcn9274, 906 907 .hal_ops = &hal_qcn9274_ops, 908 909 .qmi_cnss_feature_bitmap = BIT(CNSS_QDSS_CFG_MISS_V01), 910 }, 911 { 912 .name = "wcn7850 hw2.0", 913 .hw_rev = ATH12K_HW_WCN7850_HW20, 914 915 .fw = { 916 .dir = "WCN7850/hw2.0", 917 .board_size = 256 * 1024, 918 .cal_offset = 256 * 1024, 919 }, 920 921 .max_radios = 1, 922 .single_pdev_only = true, 923 .qmi_service_ins_id = ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_WCN7850, 924 .internal_sleep_clock = true, 925 926 .hw_ops = &wcn7850_ops, 927 .ring_mask = &ath12k_hw_ring_mask_wcn7850, 928 .regs = &wcn7850_regs, 929 930 .host_ce_config = ath12k_host_ce_config_wcn7850, 931 .ce_count = 9, 932 .target_ce_config = ath12k_target_ce_config_wlan_wcn7850, 933 .target_ce_count = 9, 934 .svc_to_ce_map = ath12k_target_service_to_ce_map_wlan_wcn7850, 935 .svc_to_ce_map_len = 14, 936 937 .hal_params = &ath12k_hw_hal_params_wcn7850, 938 939 .rxdma1_enable = false, 940 .num_rxmda_per_pdev = 2, 941 .num_rxdma_dst_ring = 1, 942 .rx_mac_buf_ring = true, 943 .vdev_start_delay = true, 944 945 .interface_modes = BIT(NL80211_IFTYPE_STATION), 946 .supports_monitor = false, 947 948 .idle_ps = true, 949 .download_calib = false, 950 .supports_suspend = false, 951 .tcl_ring_retry = false, 952 .reoq_lut_support = false, 953 .supports_shadow_regs = true, 954 955 .hal_desc_sz = sizeof(struct hal_rx_desc_wcn7850), 956 .num_tcl_banks = 7, 957 .max_tx_ring = 3, 958 959 .mhi_config = &ath12k_mhi_config_wcn7850, 960 961 .wmi_init = ath12k_wmi_init_wcn7850, 962 963 .hal_ops = &hal_wcn7850_ops, 964 965 .qmi_cnss_feature_bitmap = BIT(CNSS_QDSS_CFG_MISS_V01) | 966 BIT(CNSS_PCIE_PERST_NO_PULL_V01), 967 }, 968 { 969 .name = "qcn9274 hw2.0", 970 .hw_rev = ATH12K_HW_QCN9274_HW20, 971 .fw = { 972 .dir = "QCN9274/hw2.0", 973 .board_size = 256 * 1024, 974 .cal_offset = 128 * 1024, 975 }, 976 .max_radios = 1, 977 .single_pdev_only = false, 978 .qmi_service_ins_id = ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274, 979 .internal_sleep_clock = false, 980 981 .hw_ops = &qcn9274_ops, 982 .ring_mask = &ath12k_hw_ring_mask_qcn9274, 983 .regs = &qcn9274_v2_regs, 984 985 .host_ce_config = ath12k_host_ce_config_qcn9274, 986 .ce_count = 16, 987 .target_ce_config = ath12k_target_ce_config_wlan_qcn9274, 988 .target_ce_count = 12, 989 .svc_to_ce_map = ath12k_target_service_to_ce_map_wlan_qcn9274, 990 .svc_to_ce_map_len = 18, 991 992 .hal_params = &ath12k_hw_hal_params_qcn9274, 993 994 .rxdma1_enable = false, 995 .num_rxmda_per_pdev = 1, 996 .num_rxdma_dst_ring = 0, 997 .rx_mac_buf_ring = false, 998 .vdev_start_delay = false, 999 1000 .interface_modes = BIT(NL80211_IFTYPE_STATION) | 1001 BIT(NL80211_IFTYPE_AP), 1002 .supports_monitor = false, 1003 1004 .idle_ps = false, 1005 .download_calib = true, 1006 .supports_suspend = false, 1007 .tcl_ring_retry = true, 1008 .reoq_lut_support = false, 1009 .supports_shadow_regs = false, 1010 1011 .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9274), 1012 .num_tcl_banks = 48, 1013 .max_tx_ring = 4, 1014 1015 .mhi_config = &ath12k_mhi_config_qcn9274, 1016 1017 .wmi_init = ath12k_wmi_init_qcn9274, 1018 1019 .hal_ops = &hal_qcn9274_ops, 1020 1021 .qmi_cnss_feature_bitmap = BIT(CNSS_QDSS_CFG_MISS_V01), 1022 }, 1023 }; 1024 1025 int ath12k_hw_init(struct ath12k_base *ab) 1026 { 1027 const struct ath12k_hw_params *hw_params = NULL; 1028 int i; 1029 1030 for (i = 0; i < ARRAY_SIZE(ath12k_hw_params); i++) { 1031 hw_params = &ath12k_hw_params[i]; 1032 1033 if (hw_params->hw_rev == ab->hw_rev) 1034 break; 1035 } 1036 1037 if (i == ARRAY_SIZE(ath12k_hw_params)) { 1038 ath12k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev); 1039 return -EINVAL; 1040 } 1041 1042 ab->hw_params = hw_params; 1043 1044 ath12k_info(ab, "Hardware name: %s\n", ab->hw_params->name); 1045 1046 return 0; 1047 } 1048