1*d8899132SKalle Valo // SPDX-License-Identifier: BSD-3-Clause-Clear 2*d8899132SKalle Valo /* 3*d8899132SKalle Valo * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4*d8899132SKalle Valo * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 5*d8899132SKalle Valo */ 6*d8899132SKalle Valo 7*d8899132SKalle Valo #include <linux/types.h> 8*d8899132SKalle Valo #include <linux/bitops.h> 9*d8899132SKalle Valo #include <linux/bitfield.h> 10*d8899132SKalle Valo 11*d8899132SKalle Valo #include "debug.h" 12*d8899132SKalle Valo #include "core.h" 13*d8899132SKalle Valo #include "ce.h" 14*d8899132SKalle Valo #include "hw.h" 15*d8899132SKalle Valo #include "mhi.h" 16*d8899132SKalle Valo #include "dp_rx.h" 17*d8899132SKalle Valo 18*d8899132SKalle Valo static u8 ath12k_hw_qcn9274_mac_from_pdev_id(int pdev_idx) 19*d8899132SKalle Valo { 20*d8899132SKalle Valo return pdev_idx; 21*d8899132SKalle Valo } 22*d8899132SKalle Valo 23*d8899132SKalle Valo static int ath12k_hw_mac_id_to_pdev_id_qcn9274(const struct ath12k_hw_params *hw, 24*d8899132SKalle Valo int mac_id) 25*d8899132SKalle Valo { 26*d8899132SKalle Valo return mac_id; 27*d8899132SKalle Valo } 28*d8899132SKalle Valo 29*d8899132SKalle Valo static int ath12k_hw_mac_id_to_srng_id_qcn9274(const struct ath12k_hw_params *hw, 30*d8899132SKalle Valo int mac_id) 31*d8899132SKalle Valo { 32*d8899132SKalle Valo return 0; 33*d8899132SKalle Valo } 34*d8899132SKalle Valo 35*d8899132SKalle Valo static u8 ath12k_hw_get_ring_selector_qcn9274(struct sk_buff *skb) 36*d8899132SKalle Valo { 37*d8899132SKalle Valo return smp_processor_id(); 38*d8899132SKalle Valo } 39*d8899132SKalle Valo 40*d8899132SKalle Valo static bool ath12k_dp_srng_is_comp_ring_qcn9274(int ring_num) 41*d8899132SKalle Valo { 42*d8899132SKalle Valo if (ring_num < 3 || ring_num == 4) 43*d8899132SKalle Valo return true; 44*d8899132SKalle Valo 45*d8899132SKalle Valo return false; 46*d8899132SKalle Valo } 47*d8899132SKalle Valo 48*d8899132SKalle Valo static int ath12k_hw_mac_id_to_pdev_id_wcn7850(const struct ath12k_hw_params *hw, 49*d8899132SKalle Valo int mac_id) 50*d8899132SKalle Valo { 51*d8899132SKalle Valo return 0; 52*d8899132SKalle Valo } 53*d8899132SKalle Valo 54*d8899132SKalle Valo static int ath12k_hw_mac_id_to_srng_id_wcn7850(const struct ath12k_hw_params *hw, 55*d8899132SKalle Valo int mac_id) 56*d8899132SKalle Valo { 57*d8899132SKalle Valo return mac_id; 58*d8899132SKalle Valo } 59*d8899132SKalle Valo 60*d8899132SKalle Valo static u8 ath12k_hw_get_ring_selector_wcn7850(struct sk_buff *skb) 61*d8899132SKalle Valo { 62*d8899132SKalle Valo return skb_get_queue_mapping(skb); 63*d8899132SKalle Valo } 64*d8899132SKalle Valo 65*d8899132SKalle Valo static bool ath12k_dp_srng_is_comp_ring_wcn7850(int ring_num) 66*d8899132SKalle Valo { 67*d8899132SKalle Valo if (ring_num == 0 || ring_num == 2 || ring_num == 4) 68*d8899132SKalle Valo return true; 69*d8899132SKalle Valo 70*d8899132SKalle Valo return false; 71*d8899132SKalle Valo } 72*d8899132SKalle Valo 73*d8899132SKalle Valo static const struct ath12k_hw_ops qcn9274_ops = { 74*d8899132SKalle Valo .get_hw_mac_from_pdev_id = ath12k_hw_qcn9274_mac_from_pdev_id, 75*d8899132SKalle Valo .mac_id_to_pdev_id = ath12k_hw_mac_id_to_pdev_id_qcn9274, 76*d8899132SKalle Valo .mac_id_to_srng_id = ath12k_hw_mac_id_to_srng_id_qcn9274, 77*d8899132SKalle Valo .rxdma_ring_sel_config = ath12k_dp_rxdma_ring_sel_config_qcn9274, 78*d8899132SKalle Valo .get_ring_selector = ath12k_hw_get_ring_selector_qcn9274, 79*d8899132SKalle Valo .dp_srng_is_tx_comp_ring = ath12k_dp_srng_is_comp_ring_qcn9274, 80*d8899132SKalle Valo }; 81*d8899132SKalle Valo 82*d8899132SKalle Valo static const struct ath12k_hw_ops wcn7850_ops = { 83*d8899132SKalle Valo .get_hw_mac_from_pdev_id = ath12k_hw_qcn9274_mac_from_pdev_id, 84*d8899132SKalle Valo .mac_id_to_pdev_id = ath12k_hw_mac_id_to_pdev_id_wcn7850, 85*d8899132SKalle Valo .mac_id_to_srng_id = ath12k_hw_mac_id_to_srng_id_wcn7850, 86*d8899132SKalle Valo .rxdma_ring_sel_config = ath12k_dp_rxdma_ring_sel_config_wcn7850, 87*d8899132SKalle Valo .get_ring_selector = ath12k_hw_get_ring_selector_wcn7850, 88*d8899132SKalle Valo .dp_srng_is_tx_comp_ring = ath12k_dp_srng_is_comp_ring_wcn7850, 89*d8899132SKalle Valo }; 90*d8899132SKalle Valo 91*d8899132SKalle Valo #define ATH12K_TX_RING_MASK_0 0x1 92*d8899132SKalle Valo #define ATH12K_TX_RING_MASK_1 0x2 93*d8899132SKalle Valo #define ATH12K_TX_RING_MASK_2 0x4 94*d8899132SKalle Valo #define ATH12K_TX_RING_MASK_3 0x8 95*d8899132SKalle Valo #define ATH12K_TX_RING_MASK_4 0x10 96*d8899132SKalle Valo 97*d8899132SKalle Valo #define ATH12K_RX_RING_MASK_0 0x1 98*d8899132SKalle Valo #define ATH12K_RX_RING_MASK_1 0x2 99*d8899132SKalle Valo #define ATH12K_RX_RING_MASK_2 0x4 100*d8899132SKalle Valo #define ATH12K_RX_RING_MASK_3 0x8 101*d8899132SKalle Valo 102*d8899132SKalle Valo #define ATH12K_RX_ERR_RING_MASK_0 0x1 103*d8899132SKalle Valo 104*d8899132SKalle Valo #define ATH12K_RX_WBM_REL_RING_MASK_0 0x1 105*d8899132SKalle Valo 106*d8899132SKalle Valo #define ATH12K_REO_STATUS_RING_MASK_0 0x1 107*d8899132SKalle Valo 108*d8899132SKalle Valo #define ATH12K_HOST2RXDMA_RING_MASK_0 0x1 109*d8899132SKalle Valo 110*d8899132SKalle Valo #define ATH12K_RX_MON_RING_MASK_0 0x1 111*d8899132SKalle Valo #define ATH12K_RX_MON_RING_MASK_1 0x2 112*d8899132SKalle Valo #define ATH12K_RX_MON_RING_MASK_2 0x4 113*d8899132SKalle Valo 114*d8899132SKalle Valo #define ATH12K_TX_MON_RING_MASK_0 0x1 115*d8899132SKalle Valo #define ATH12K_TX_MON_RING_MASK_1 0x2 116*d8899132SKalle Valo 117*d8899132SKalle Valo /* Target firmware's Copy Engine configuration. */ 118*d8899132SKalle Valo static const struct ce_pipe_config ath12k_target_ce_config_wlan_qcn9274[] = { 119*d8899132SKalle Valo /* CE0: host->target HTC control and raw streams */ 120*d8899132SKalle Valo { 121*d8899132SKalle Valo .pipenum = __cpu_to_le32(0), 122*d8899132SKalle Valo .pipedir = __cpu_to_le32(PIPEDIR_OUT), 123*d8899132SKalle Valo .nentries = __cpu_to_le32(32), 124*d8899132SKalle Valo .nbytes_max = __cpu_to_le32(2048), 125*d8899132SKalle Valo .flags = __cpu_to_le32(CE_ATTR_FLAGS), 126*d8899132SKalle Valo .reserved = __cpu_to_le32(0), 127*d8899132SKalle Valo }, 128*d8899132SKalle Valo 129*d8899132SKalle Valo /* CE1: target->host HTT + HTC control */ 130*d8899132SKalle Valo { 131*d8899132SKalle Valo .pipenum = __cpu_to_le32(1), 132*d8899132SKalle Valo .pipedir = __cpu_to_le32(PIPEDIR_IN), 133*d8899132SKalle Valo .nentries = __cpu_to_le32(32), 134*d8899132SKalle Valo .nbytes_max = __cpu_to_le32(2048), 135*d8899132SKalle Valo .flags = __cpu_to_le32(CE_ATTR_FLAGS), 136*d8899132SKalle Valo .reserved = __cpu_to_le32(0), 137*d8899132SKalle Valo }, 138*d8899132SKalle Valo 139*d8899132SKalle Valo /* CE2: target->host WMI */ 140*d8899132SKalle Valo { 141*d8899132SKalle Valo .pipenum = __cpu_to_le32(2), 142*d8899132SKalle Valo .pipedir = __cpu_to_le32(PIPEDIR_IN), 143*d8899132SKalle Valo .nentries = __cpu_to_le32(32), 144*d8899132SKalle Valo .nbytes_max = __cpu_to_le32(2048), 145*d8899132SKalle Valo .flags = __cpu_to_le32(CE_ATTR_FLAGS), 146*d8899132SKalle Valo .reserved = __cpu_to_le32(0), 147*d8899132SKalle Valo }, 148*d8899132SKalle Valo 149*d8899132SKalle Valo /* CE3: host->target WMI (mac0) */ 150*d8899132SKalle Valo { 151*d8899132SKalle Valo .pipenum = __cpu_to_le32(3), 152*d8899132SKalle Valo .pipedir = __cpu_to_le32(PIPEDIR_OUT), 153*d8899132SKalle Valo .nentries = __cpu_to_le32(32), 154*d8899132SKalle Valo .nbytes_max = __cpu_to_le32(2048), 155*d8899132SKalle Valo .flags = __cpu_to_le32(CE_ATTR_FLAGS), 156*d8899132SKalle Valo .reserved = __cpu_to_le32(0), 157*d8899132SKalle Valo }, 158*d8899132SKalle Valo 159*d8899132SKalle Valo /* CE4: host->target HTT */ 160*d8899132SKalle Valo { 161*d8899132SKalle Valo .pipenum = __cpu_to_le32(4), 162*d8899132SKalle Valo .pipedir = __cpu_to_le32(PIPEDIR_OUT), 163*d8899132SKalle Valo .nentries = __cpu_to_le32(256), 164*d8899132SKalle Valo .nbytes_max = __cpu_to_le32(256), 165*d8899132SKalle Valo .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 166*d8899132SKalle Valo .reserved = __cpu_to_le32(0), 167*d8899132SKalle Valo }, 168*d8899132SKalle Valo 169*d8899132SKalle Valo /* CE5: target->host Pktlog */ 170*d8899132SKalle Valo { 171*d8899132SKalle Valo .pipenum = __cpu_to_le32(5), 172*d8899132SKalle Valo .pipedir = __cpu_to_le32(PIPEDIR_IN), 173*d8899132SKalle Valo .nentries = __cpu_to_le32(32), 174*d8899132SKalle Valo .nbytes_max = __cpu_to_le32(2048), 175*d8899132SKalle Valo .flags = __cpu_to_le32(CE_ATTR_FLAGS), 176*d8899132SKalle Valo .reserved = __cpu_to_le32(0), 177*d8899132SKalle Valo }, 178*d8899132SKalle Valo 179*d8899132SKalle Valo /* CE6: Reserved for target autonomous hif_memcpy */ 180*d8899132SKalle Valo { 181*d8899132SKalle Valo .pipenum = __cpu_to_le32(6), 182*d8899132SKalle Valo .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 183*d8899132SKalle Valo .nentries = __cpu_to_le32(32), 184*d8899132SKalle Valo .nbytes_max = __cpu_to_le32(16384), 185*d8899132SKalle Valo .flags = __cpu_to_le32(CE_ATTR_FLAGS), 186*d8899132SKalle Valo .reserved = __cpu_to_le32(0), 187*d8899132SKalle Valo }, 188*d8899132SKalle Valo 189*d8899132SKalle Valo /* CE7: host->target WMI (mac1) */ 190*d8899132SKalle Valo { 191*d8899132SKalle Valo .pipenum = __cpu_to_le32(7), 192*d8899132SKalle Valo .pipedir = __cpu_to_le32(PIPEDIR_OUT), 193*d8899132SKalle Valo .nentries = __cpu_to_le32(32), 194*d8899132SKalle Valo .nbytes_max = __cpu_to_le32(2048), 195*d8899132SKalle Valo .flags = __cpu_to_le32(CE_ATTR_FLAGS), 196*d8899132SKalle Valo .reserved = __cpu_to_le32(0), 197*d8899132SKalle Valo }, 198*d8899132SKalle Valo 199*d8899132SKalle Valo /* CE8: Reserved for target autonomous hif_memcpy */ 200*d8899132SKalle Valo { 201*d8899132SKalle Valo .pipenum = __cpu_to_le32(8), 202*d8899132SKalle Valo .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 203*d8899132SKalle Valo .nentries = __cpu_to_le32(32), 204*d8899132SKalle Valo .nbytes_max = __cpu_to_le32(16384), 205*d8899132SKalle Valo .flags = __cpu_to_le32(CE_ATTR_FLAGS), 206*d8899132SKalle Valo .reserved = __cpu_to_le32(0), 207*d8899132SKalle Valo }, 208*d8899132SKalle Valo 209*d8899132SKalle Valo /* CE9, 10 and 11: Reserved for MHI */ 210*d8899132SKalle Valo 211*d8899132SKalle Valo /* CE12: Target CV prefetch */ 212*d8899132SKalle Valo { 213*d8899132SKalle Valo .pipenum = __cpu_to_le32(12), 214*d8899132SKalle Valo .pipedir = __cpu_to_le32(PIPEDIR_OUT), 215*d8899132SKalle Valo .nentries = __cpu_to_le32(32), 216*d8899132SKalle Valo .nbytes_max = __cpu_to_le32(2048), 217*d8899132SKalle Valo .flags = __cpu_to_le32(CE_ATTR_FLAGS), 218*d8899132SKalle Valo .reserved = __cpu_to_le32(0), 219*d8899132SKalle Valo }, 220*d8899132SKalle Valo 221*d8899132SKalle Valo /* CE13: Target CV prefetch */ 222*d8899132SKalle Valo { 223*d8899132SKalle Valo .pipenum = __cpu_to_le32(13), 224*d8899132SKalle Valo .pipedir = __cpu_to_le32(PIPEDIR_OUT), 225*d8899132SKalle Valo .nentries = __cpu_to_le32(32), 226*d8899132SKalle Valo .nbytes_max = __cpu_to_le32(2048), 227*d8899132SKalle Valo .flags = __cpu_to_le32(CE_ATTR_FLAGS), 228*d8899132SKalle Valo .reserved = __cpu_to_le32(0), 229*d8899132SKalle Valo }, 230*d8899132SKalle Valo 231*d8899132SKalle Valo /* CE14: WMI logging/CFR/Spectral/Radar */ 232*d8899132SKalle Valo { 233*d8899132SKalle Valo .pipenum = __cpu_to_le32(14), 234*d8899132SKalle Valo .pipedir = __cpu_to_le32(PIPEDIR_IN), 235*d8899132SKalle Valo .nentries = __cpu_to_le32(32), 236*d8899132SKalle Valo .nbytes_max = __cpu_to_le32(2048), 237*d8899132SKalle Valo .flags = __cpu_to_le32(CE_ATTR_FLAGS), 238*d8899132SKalle Valo .reserved = __cpu_to_le32(0), 239*d8899132SKalle Valo }, 240*d8899132SKalle Valo 241*d8899132SKalle Valo /* CE15: Reserved */ 242*d8899132SKalle Valo }; 243*d8899132SKalle Valo 244*d8899132SKalle Valo /* Target firmware's Copy Engine configuration. */ 245*d8899132SKalle Valo static const struct ce_pipe_config ath12k_target_ce_config_wlan_wcn7850[] = { 246*d8899132SKalle Valo /* CE0: host->target HTC control and raw streams */ 247*d8899132SKalle Valo { 248*d8899132SKalle Valo .pipenum = __cpu_to_le32(0), 249*d8899132SKalle Valo .pipedir = __cpu_to_le32(PIPEDIR_OUT), 250*d8899132SKalle Valo .nentries = __cpu_to_le32(32), 251*d8899132SKalle Valo .nbytes_max = __cpu_to_le32(2048), 252*d8899132SKalle Valo .flags = __cpu_to_le32(CE_ATTR_FLAGS), 253*d8899132SKalle Valo .reserved = __cpu_to_le32(0), 254*d8899132SKalle Valo }, 255*d8899132SKalle Valo 256*d8899132SKalle Valo /* CE1: target->host HTT + HTC control */ 257*d8899132SKalle Valo { 258*d8899132SKalle Valo .pipenum = __cpu_to_le32(1), 259*d8899132SKalle Valo .pipedir = __cpu_to_le32(PIPEDIR_IN), 260*d8899132SKalle Valo .nentries = __cpu_to_le32(32), 261*d8899132SKalle Valo .nbytes_max = __cpu_to_le32(2048), 262*d8899132SKalle Valo .flags = __cpu_to_le32(CE_ATTR_FLAGS), 263*d8899132SKalle Valo .reserved = __cpu_to_le32(0), 264*d8899132SKalle Valo }, 265*d8899132SKalle Valo 266*d8899132SKalle Valo /* CE2: target->host WMI */ 267*d8899132SKalle Valo { 268*d8899132SKalle Valo .pipenum = __cpu_to_le32(2), 269*d8899132SKalle Valo .pipedir = __cpu_to_le32(PIPEDIR_IN), 270*d8899132SKalle Valo .nentries = __cpu_to_le32(32), 271*d8899132SKalle Valo .nbytes_max = __cpu_to_le32(2048), 272*d8899132SKalle Valo .flags = __cpu_to_le32(CE_ATTR_FLAGS), 273*d8899132SKalle Valo .reserved = __cpu_to_le32(0), 274*d8899132SKalle Valo }, 275*d8899132SKalle Valo 276*d8899132SKalle Valo /* CE3: host->target WMI */ 277*d8899132SKalle Valo { 278*d8899132SKalle Valo .pipenum = __cpu_to_le32(3), 279*d8899132SKalle Valo .pipedir = __cpu_to_le32(PIPEDIR_OUT), 280*d8899132SKalle Valo .nentries = __cpu_to_le32(32), 281*d8899132SKalle Valo .nbytes_max = __cpu_to_le32(2048), 282*d8899132SKalle Valo .flags = __cpu_to_le32(CE_ATTR_FLAGS), 283*d8899132SKalle Valo .reserved = __cpu_to_le32(0), 284*d8899132SKalle Valo }, 285*d8899132SKalle Valo 286*d8899132SKalle Valo /* CE4: host->target HTT */ 287*d8899132SKalle Valo { 288*d8899132SKalle Valo .pipenum = __cpu_to_le32(4), 289*d8899132SKalle Valo .pipedir = __cpu_to_le32(PIPEDIR_OUT), 290*d8899132SKalle Valo .nentries = __cpu_to_le32(256), 291*d8899132SKalle Valo .nbytes_max = __cpu_to_le32(256), 292*d8899132SKalle Valo .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 293*d8899132SKalle Valo .reserved = __cpu_to_le32(0), 294*d8899132SKalle Valo }, 295*d8899132SKalle Valo 296*d8899132SKalle Valo /* CE5: target->host Pktlog */ 297*d8899132SKalle Valo { 298*d8899132SKalle Valo .pipenum = __cpu_to_le32(5), 299*d8899132SKalle Valo .pipedir = __cpu_to_le32(PIPEDIR_IN), 300*d8899132SKalle Valo .nentries = __cpu_to_le32(32), 301*d8899132SKalle Valo .nbytes_max = __cpu_to_le32(2048), 302*d8899132SKalle Valo .flags = __cpu_to_le32(CE_ATTR_FLAGS), 303*d8899132SKalle Valo .reserved = __cpu_to_le32(0), 304*d8899132SKalle Valo }, 305*d8899132SKalle Valo 306*d8899132SKalle Valo /* CE6: Reserved for target autonomous hif_memcpy */ 307*d8899132SKalle Valo { 308*d8899132SKalle Valo .pipenum = __cpu_to_le32(6), 309*d8899132SKalle Valo .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 310*d8899132SKalle Valo .nentries = __cpu_to_le32(32), 311*d8899132SKalle Valo .nbytes_max = __cpu_to_le32(16384), 312*d8899132SKalle Valo .flags = __cpu_to_le32(CE_ATTR_FLAGS), 313*d8899132SKalle Valo .reserved = __cpu_to_le32(0), 314*d8899132SKalle Valo }, 315*d8899132SKalle Valo 316*d8899132SKalle Valo /* CE7 used only by Host */ 317*d8899132SKalle Valo { 318*d8899132SKalle Valo .pipenum = __cpu_to_le32(7), 319*d8899132SKalle Valo .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 320*d8899132SKalle Valo .nentries = __cpu_to_le32(0), 321*d8899132SKalle Valo .nbytes_max = __cpu_to_le32(0), 322*d8899132SKalle Valo .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 323*d8899132SKalle Valo .reserved = __cpu_to_le32(0), 324*d8899132SKalle Valo }, 325*d8899132SKalle Valo 326*d8899132SKalle Valo /* CE8 target->host used only by IPA */ 327*d8899132SKalle Valo { 328*d8899132SKalle Valo .pipenum = __cpu_to_le32(8), 329*d8899132SKalle Valo .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 330*d8899132SKalle Valo .nentries = __cpu_to_le32(32), 331*d8899132SKalle Valo .nbytes_max = __cpu_to_le32(16384), 332*d8899132SKalle Valo .flags = __cpu_to_le32(CE_ATTR_FLAGS), 333*d8899132SKalle Valo .reserved = __cpu_to_le32(0), 334*d8899132SKalle Valo }, 335*d8899132SKalle Valo /* CE 9, 10, 11 are used by MHI driver */ 336*d8899132SKalle Valo }; 337*d8899132SKalle Valo 338*d8899132SKalle Valo /* Map from service/endpoint to Copy Engine. 339*d8899132SKalle Valo * This table is derived from the CE_PCI TABLE, above. 340*d8899132SKalle Valo * It is passed to the Target at startup for use by firmware. 341*d8899132SKalle Valo */ 342*d8899132SKalle Valo static const struct service_to_pipe ath12k_target_service_to_ce_map_wlan_qcn9274[] = { 343*d8899132SKalle Valo { 344*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO), 345*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 346*d8899132SKalle Valo __cpu_to_le32(3), 347*d8899132SKalle Valo }, 348*d8899132SKalle Valo { 349*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO), 350*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 351*d8899132SKalle Valo __cpu_to_le32(2), 352*d8899132SKalle Valo }, 353*d8899132SKalle Valo { 354*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK), 355*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 356*d8899132SKalle Valo __cpu_to_le32(3), 357*d8899132SKalle Valo }, 358*d8899132SKalle Valo { 359*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK), 360*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 361*d8899132SKalle Valo __cpu_to_le32(2), 362*d8899132SKalle Valo }, 363*d8899132SKalle Valo { 364*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE), 365*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 366*d8899132SKalle Valo __cpu_to_le32(3), 367*d8899132SKalle Valo }, 368*d8899132SKalle Valo { 369*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE), 370*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 371*d8899132SKalle Valo __cpu_to_le32(2), 372*d8899132SKalle Valo }, 373*d8899132SKalle Valo { 374*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI), 375*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 376*d8899132SKalle Valo __cpu_to_le32(3), 377*d8899132SKalle Valo }, 378*d8899132SKalle Valo { 379*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI), 380*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 381*d8899132SKalle Valo __cpu_to_le32(2), 382*d8899132SKalle Valo }, 383*d8899132SKalle Valo { 384*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL), 385*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 386*d8899132SKalle Valo __cpu_to_le32(3), 387*d8899132SKalle Valo }, 388*d8899132SKalle Valo { 389*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL), 390*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 391*d8899132SKalle Valo __cpu_to_le32(2), 392*d8899132SKalle Valo }, 393*d8899132SKalle Valo { 394*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL), 395*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 396*d8899132SKalle Valo __cpu_to_le32(0), 397*d8899132SKalle Valo }, 398*d8899132SKalle Valo { 399*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL), 400*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 401*d8899132SKalle Valo __cpu_to_le32(1), 402*d8899132SKalle Valo }, 403*d8899132SKalle Valo { 404*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_TEST_RAW_STREAMS), 405*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 406*d8899132SKalle Valo __cpu_to_le32(0), 407*d8899132SKalle Valo }, 408*d8899132SKalle Valo { 409*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_TEST_RAW_STREAMS), 410*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 411*d8899132SKalle Valo __cpu_to_le32(1), 412*d8899132SKalle Valo }, 413*d8899132SKalle Valo { 414*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG), 415*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 416*d8899132SKalle Valo __cpu_to_le32(4), 417*d8899132SKalle Valo }, 418*d8899132SKalle Valo { 419*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG), 420*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 421*d8899132SKalle Valo __cpu_to_le32(1), 422*d8899132SKalle Valo }, 423*d8899132SKalle Valo { 424*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL_MAC1), 425*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 426*d8899132SKalle Valo __cpu_to_le32(7), 427*d8899132SKalle Valo }, 428*d8899132SKalle Valo { 429*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL_MAC1), 430*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 431*d8899132SKalle Valo __cpu_to_le32(2), 432*d8899132SKalle Valo }, 433*d8899132SKalle Valo { 434*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_PKT_LOG), 435*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 436*d8899132SKalle Valo __cpu_to_le32(5), 437*d8899132SKalle Valo }, 438*d8899132SKalle Valo { 439*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL_DIAG), 440*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 441*d8899132SKalle Valo __cpu_to_le32(14), 442*d8899132SKalle Valo }, 443*d8899132SKalle Valo 444*d8899132SKalle Valo /* (Additions here) */ 445*d8899132SKalle Valo 446*d8899132SKalle Valo { /* must be last */ 447*d8899132SKalle Valo __cpu_to_le32(0), 448*d8899132SKalle Valo __cpu_to_le32(0), 449*d8899132SKalle Valo __cpu_to_le32(0), 450*d8899132SKalle Valo }, 451*d8899132SKalle Valo }; 452*d8899132SKalle Valo 453*d8899132SKalle Valo static const struct service_to_pipe ath12k_target_service_to_ce_map_wlan_wcn7850[] = { 454*d8899132SKalle Valo { 455*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO), 456*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 457*d8899132SKalle Valo __cpu_to_le32(3), 458*d8899132SKalle Valo }, 459*d8899132SKalle Valo { 460*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO), 461*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 462*d8899132SKalle Valo __cpu_to_le32(2), 463*d8899132SKalle Valo }, 464*d8899132SKalle Valo { 465*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK), 466*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 467*d8899132SKalle Valo __cpu_to_le32(3), 468*d8899132SKalle Valo }, 469*d8899132SKalle Valo { 470*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK), 471*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 472*d8899132SKalle Valo __cpu_to_le32(2), 473*d8899132SKalle Valo }, 474*d8899132SKalle Valo { 475*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE), 476*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 477*d8899132SKalle Valo __cpu_to_le32(3), 478*d8899132SKalle Valo }, 479*d8899132SKalle Valo { 480*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE), 481*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 482*d8899132SKalle Valo __cpu_to_le32(2), 483*d8899132SKalle Valo }, 484*d8899132SKalle Valo { 485*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI), 486*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 487*d8899132SKalle Valo __cpu_to_le32(3), 488*d8899132SKalle Valo }, 489*d8899132SKalle Valo { 490*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI), 491*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 492*d8899132SKalle Valo __cpu_to_le32(2), 493*d8899132SKalle Valo }, 494*d8899132SKalle Valo { 495*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL), 496*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 497*d8899132SKalle Valo __cpu_to_le32(3), 498*d8899132SKalle Valo }, 499*d8899132SKalle Valo { 500*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL), 501*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 502*d8899132SKalle Valo __cpu_to_le32(2), 503*d8899132SKalle Valo }, 504*d8899132SKalle Valo { 505*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL), 506*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 507*d8899132SKalle Valo __cpu_to_le32(0), 508*d8899132SKalle Valo }, 509*d8899132SKalle Valo { 510*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL), 511*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 512*d8899132SKalle Valo __cpu_to_le32(2), 513*d8899132SKalle Valo }, 514*d8899132SKalle Valo { 515*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG), 516*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 517*d8899132SKalle Valo __cpu_to_le32(4), 518*d8899132SKalle Valo }, 519*d8899132SKalle Valo { 520*d8899132SKalle Valo __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG), 521*d8899132SKalle Valo __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 522*d8899132SKalle Valo __cpu_to_le32(1), 523*d8899132SKalle Valo }, 524*d8899132SKalle Valo 525*d8899132SKalle Valo /* (Additions here) */ 526*d8899132SKalle Valo 527*d8899132SKalle Valo { /* must be last */ 528*d8899132SKalle Valo __cpu_to_le32(0), 529*d8899132SKalle Valo __cpu_to_le32(0), 530*d8899132SKalle Valo __cpu_to_le32(0), 531*d8899132SKalle Valo }, 532*d8899132SKalle Valo }; 533*d8899132SKalle Valo 534*d8899132SKalle Valo static const struct ath12k_hw_ring_mask ath12k_hw_ring_mask_qcn9274 = { 535*d8899132SKalle Valo .tx = { 536*d8899132SKalle Valo ATH12K_TX_RING_MASK_0, 537*d8899132SKalle Valo ATH12K_TX_RING_MASK_1, 538*d8899132SKalle Valo ATH12K_TX_RING_MASK_2, 539*d8899132SKalle Valo ATH12K_TX_RING_MASK_3, 540*d8899132SKalle Valo }, 541*d8899132SKalle Valo .rx_mon_dest = { 542*d8899132SKalle Valo 0, 0, 0, 543*d8899132SKalle Valo ATH12K_RX_MON_RING_MASK_0, 544*d8899132SKalle Valo ATH12K_RX_MON_RING_MASK_1, 545*d8899132SKalle Valo ATH12K_RX_MON_RING_MASK_2, 546*d8899132SKalle Valo }, 547*d8899132SKalle Valo .rx = { 548*d8899132SKalle Valo 0, 0, 0, 0, 549*d8899132SKalle Valo ATH12K_RX_RING_MASK_0, 550*d8899132SKalle Valo ATH12K_RX_RING_MASK_1, 551*d8899132SKalle Valo ATH12K_RX_RING_MASK_2, 552*d8899132SKalle Valo ATH12K_RX_RING_MASK_3, 553*d8899132SKalle Valo }, 554*d8899132SKalle Valo .rx_err = { 555*d8899132SKalle Valo 0, 0, 0, 556*d8899132SKalle Valo ATH12K_RX_ERR_RING_MASK_0, 557*d8899132SKalle Valo }, 558*d8899132SKalle Valo .rx_wbm_rel = { 559*d8899132SKalle Valo 0, 0, 0, 560*d8899132SKalle Valo ATH12K_RX_WBM_REL_RING_MASK_0, 561*d8899132SKalle Valo }, 562*d8899132SKalle Valo .reo_status = { 563*d8899132SKalle Valo 0, 0, 0, 564*d8899132SKalle Valo ATH12K_REO_STATUS_RING_MASK_0, 565*d8899132SKalle Valo }, 566*d8899132SKalle Valo .host2rxdma = { 567*d8899132SKalle Valo 0, 0, 0, 568*d8899132SKalle Valo ATH12K_HOST2RXDMA_RING_MASK_0, 569*d8899132SKalle Valo }, 570*d8899132SKalle Valo .tx_mon_dest = { 571*d8899132SKalle Valo ATH12K_TX_MON_RING_MASK_0, 572*d8899132SKalle Valo ATH12K_TX_MON_RING_MASK_1, 573*d8899132SKalle Valo }, 574*d8899132SKalle Valo }; 575*d8899132SKalle Valo 576*d8899132SKalle Valo static const struct ath12k_hw_ring_mask ath12k_hw_ring_mask_wcn7850 = { 577*d8899132SKalle Valo .tx = { 578*d8899132SKalle Valo ATH12K_TX_RING_MASK_0, 579*d8899132SKalle Valo ATH12K_TX_RING_MASK_2, 580*d8899132SKalle Valo ATH12K_TX_RING_MASK_4, 581*d8899132SKalle Valo }, 582*d8899132SKalle Valo .rx_mon_dest = { 583*d8899132SKalle Valo }, 584*d8899132SKalle Valo .rx = { 585*d8899132SKalle Valo 0, 0, 0, 586*d8899132SKalle Valo ATH12K_RX_RING_MASK_0, 587*d8899132SKalle Valo ATH12K_RX_RING_MASK_1, 588*d8899132SKalle Valo ATH12K_RX_RING_MASK_2, 589*d8899132SKalle Valo ATH12K_RX_RING_MASK_3, 590*d8899132SKalle Valo }, 591*d8899132SKalle Valo .rx_err = { 592*d8899132SKalle Valo ATH12K_RX_ERR_RING_MASK_0, 593*d8899132SKalle Valo }, 594*d8899132SKalle Valo .rx_wbm_rel = { 595*d8899132SKalle Valo ATH12K_RX_WBM_REL_RING_MASK_0, 596*d8899132SKalle Valo }, 597*d8899132SKalle Valo .reo_status = { 598*d8899132SKalle Valo ATH12K_REO_STATUS_RING_MASK_0, 599*d8899132SKalle Valo }, 600*d8899132SKalle Valo .host2rxdma = { 601*d8899132SKalle Valo }, 602*d8899132SKalle Valo .tx_mon_dest = { 603*d8899132SKalle Valo }, 604*d8899132SKalle Valo }; 605*d8899132SKalle Valo 606*d8899132SKalle Valo static const struct ath12k_hw_regs qcn9274_v1_regs = { 607*d8899132SKalle Valo /* SW2TCL(x) R0 ring configuration address */ 608*d8899132SKalle Valo .hal_tcl1_ring_id = 0x00000908, 609*d8899132SKalle Valo .hal_tcl1_ring_misc = 0x00000910, 610*d8899132SKalle Valo .hal_tcl1_ring_tp_addr_lsb = 0x0000091c, 611*d8899132SKalle Valo .hal_tcl1_ring_tp_addr_msb = 0x00000920, 612*d8899132SKalle Valo .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000930, 613*d8899132SKalle Valo .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000934, 614*d8899132SKalle Valo .hal_tcl1_ring_msi1_base_lsb = 0x00000948, 615*d8899132SKalle Valo .hal_tcl1_ring_msi1_base_msb = 0x0000094c, 616*d8899132SKalle Valo .hal_tcl1_ring_msi1_data = 0x00000950, 617*d8899132SKalle Valo .hal_tcl_ring_base_lsb = 0x00000b58, 618*d8899132SKalle Valo 619*d8899132SKalle Valo /* TCL STATUS ring address */ 620*d8899132SKalle Valo .hal_tcl_status_ring_base_lsb = 0x00000d38, 621*d8899132SKalle Valo 622*d8899132SKalle Valo .hal_wbm_idle_ring_base_lsb = 0x00000d0c, 623*d8899132SKalle Valo .hal_wbm_idle_ring_misc_addr = 0x00000d1c, 624*d8899132SKalle Valo .hal_wbm_r0_idle_list_cntl_addr = 0x00000210, 625*d8899132SKalle Valo .hal_wbm_r0_idle_list_size_addr = 0x00000214, 626*d8899132SKalle Valo .hal_wbm_scattered_ring_base_lsb = 0x00000220, 627*d8899132SKalle Valo .hal_wbm_scattered_ring_base_msb = 0x00000224, 628*d8899132SKalle Valo .hal_wbm_scattered_desc_head_info_ix0 = 0x00000230, 629*d8899132SKalle Valo .hal_wbm_scattered_desc_head_info_ix1 = 0x00000234, 630*d8899132SKalle Valo .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000240, 631*d8899132SKalle Valo .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000244, 632*d8899132SKalle Valo .hal_wbm_scattered_desc_ptr_hp_addr = 0x0000024c, 633*d8899132SKalle Valo 634*d8899132SKalle Valo .hal_wbm_sw_release_ring_base_lsb = 0x0000034c, 635*d8899132SKalle Valo .hal_wbm_sw1_release_ring_base_lsb = 0x000003c4, 636*d8899132SKalle Valo .hal_wbm0_release_ring_base_lsb = 0x00000dd8, 637*d8899132SKalle Valo .hal_wbm1_release_ring_base_lsb = 0x00000e50, 638*d8899132SKalle Valo 639*d8899132SKalle Valo /* PCIe base address */ 640*d8899132SKalle Valo .pcie_qserdes_sysclk_en_sel = 0x01e0c0a8, 641*d8899132SKalle Valo .pcie_pcs_osc_dtct_config_base = 0x01e0d45c, 642*d8899132SKalle Valo 643*d8899132SKalle Valo /* PPE release ring address */ 644*d8899132SKalle Valo .hal_ppe_rel_ring_base = 0x0000043c, 645*d8899132SKalle Valo 646*d8899132SKalle Valo /* REO DEST ring address */ 647*d8899132SKalle Valo .hal_reo2_ring_base = 0x0000055c, 648*d8899132SKalle Valo .hal_reo1_misc_ctrl_addr = 0x00000b7c, 649*d8899132SKalle Valo .hal_reo1_sw_cookie_cfg0 = 0x00000050, 650*d8899132SKalle Valo .hal_reo1_sw_cookie_cfg1 = 0x00000054, 651*d8899132SKalle Valo .hal_reo1_qdesc_lut_base0 = 0x00000058, 652*d8899132SKalle Valo .hal_reo1_qdesc_lut_base1 = 0x0000005c, 653*d8899132SKalle Valo .hal_reo1_ring_base_lsb = 0x000004e4, 654*d8899132SKalle Valo .hal_reo1_ring_base_msb = 0x000004e8, 655*d8899132SKalle Valo .hal_reo1_ring_id = 0x000004ec, 656*d8899132SKalle Valo .hal_reo1_ring_misc = 0x000004f4, 657*d8899132SKalle Valo .hal_reo1_ring_hp_addr_lsb = 0x000004f8, 658*d8899132SKalle Valo .hal_reo1_ring_hp_addr_msb = 0x000004fc, 659*d8899132SKalle Valo .hal_reo1_ring_producer_int_setup = 0x00000508, 660*d8899132SKalle Valo .hal_reo1_ring_msi1_base_lsb = 0x0000052C, 661*d8899132SKalle Valo .hal_reo1_ring_msi1_base_msb = 0x00000530, 662*d8899132SKalle Valo .hal_reo1_ring_msi1_data = 0x00000534, 663*d8899132SKalle Valo .hal_reo1_aging_thres_ix0 = 0x00000b08, 664*d8899132SKalle Valo .hal_reo1_aging_thres_ix1 = 0x00000b0c, 665*d8899132SKalle Valo .hal_reo1_aging_thres_ix2 = 0x00000b10, 666*d8899132SKalle Valo .hal_reo1_aging_thres_ix3 = 0x00000b14, 667*d8899132SKalle Valo 668*d8899132SKalle Valo /* REO Exception ring address */ 669*d8899132SKalle Valo .hal_reo2_sw0_ring_base = 0x000008a4, 670*d8899132SKalle Valo 671*d8899132SKalle Valo /* REO Reinject ring address */ 672*d8899132SKalle Valo .hal_sw2reo_ring_base = 0x00000304, 673*d8899132SKalle Valo .hal_sw2reo1_ring_base = 0x0000037c, 674*d8899132SKalle Valo 675*d8899132SKalle Valo /* REO cmd ring address */ 676*d8899132SKalle Valo .hal_reo_cmd_ring_base = 0x0000028c, 677*d8899132SKalle Valo 678*d8899132SKalle Valo /* REO status ring address */ 679*d8899132SKalle Valo .hal_reo_status_ring_base = 0x00000a84, 680*d8899132SKalle Valo }; 681*d8899132SKalle Valo 682*d8899132SKalle Valo static const struct ath12k_hw_regs qcn9274_v2_regs = { 683*d8899132SKalle Valo /* SW2TCL(x) R0 ring configuration address */ 684*d8899132SKalle Valo .hal_tcl1_ring_id = 0x00000908, 685*d8899132SKalle Valo .hal_tcl1_ring_misc = 0x00000910, 686*d8899132SKalle Valo .hal_tcl1_ring_tp_addr_lsb = 0x0000091c, 687*d8899132SKalle Valo .hal_tcl1_ring_tp_addr_msb = 0x00000920, 688*d8899132SKalle Valo .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000930, 689*d8899132SKalle Valo .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000934, 690*d8899132SKalle Valo .hal_tcl1_ring_msi1_base_lsb = 0x00000948, 691*d8899132SKalle Valo .hal_tcl1_ring_msi1_base_msb = 0x0000094c, 692*d8899132SKalle Valo .hal_tcl1_ring_msi1_data = 0x00000950, 693*d8899132SKalle Valo .hal_tcl_ring_base_lsb = 0x00000b58, 694*d8899132SKalle Valo 695*d8899132SKalle Valo /* TCL STATUS ring address */ 696*d8899132SKalle Valo .hal_tcl_status_ring_base_lsb = 0x00000d38, 697*d8899132SKalle Valo 698*d8899132SKalle Valo /* WBM idle link ring address */ 699*d8899132SKalle Valo .hal_wbm_idle_ring_base_lsb = 0x00000d3c, 700*d8899132SKalle Valo .hal_wbm_idle_ring_misc_addr = 0x00000d4c, 701*d8899132SKalle Valo .hal_wbm_r0_idle_list_cntl_addr = 0x00000240, 702*d8899132SKalle Valo .hal_wbm_r0_idle_list_size_addr = 0x00000244, 703*d8899132SKalle Valo .hal_wbm_scattered_ring_base_lsb = 0x00000250, 704*d8899132SKalle Valo .hal_wbm_scattered_ring_base_msb = 0x00000254, 705*d8899132SKalle Valo .hal_wbm_scattered_desc_head_info_ix0 = 0x00000260, 706*d8899132SKalle Valo .hal_wbm_scattered_desc_head_info_ix1 = 0x00000264, 707*d8899132SKalle Valo .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000270, 708*d8899132SKalle Valo .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000274, 709*d8899132SKalle Valo .hal_wbm_scattered_desc_ptr_hp_addr = 0x0000027c, 710*d8899132SKalle Valo 711*d8899132SKalle Valo /* SW2WBM release ring address */ 712*d8899132SKalle Valo .hal_wbm_sw_release_ring_base_lsb = 0x0000037c, 713*d8899132SKalle Valo .hal_wbm_sw1_release_ring_base_lsb = 0x000003f4, 714*d8899132SKalle Valo 715*d8899132SKalle Valo /* WBM2SW release ring address */ 716*d8899132SKalle Valo .hal_wbm0_release_ring_base_lsb = 0x00000e08, 717*d8899132SKalle Valo .hal_wbm1_release_ring_base_lsb = 0x00000e80, 718*d8899132SKalle Valo 719*d8899132SKalle Valo /* PCIe base address */ 720*d8899132SKalle Valo .pcie_qserdes_sysclk_en_sel = 0x01e0c0a8, 721*d8899132SKalle Valo .pcie_pcs_osc_dtct_config_base = 0x01e0d45c, 722*d8899132SKalle Valo 723*d8899132SKalle Valo /* PPE release ring address */ 724*d8899132SKalle Valo .hal_ppe_rel_ring_base = 0x0000046c, 725*d8899132SKalle Valo 726*d8899132SKalle Valo /* REO DEST ring address */ 727*d8899132SKalle Valo .hal_reo2_ring_base = 0x00000578, 728*d8899132SKalle Valo .hal_reo1_misc_ctrl_addr = 0x00000b9c, 729*d8899132SKalle Valo .hal_reo1_sw_cookie_cfg0 = 0x0000006c, 730*d8899132SKalle Valo .hal_reo1_sw_cookie_cfg1 = 0x00000070, 731*d8899132SKalle Valo .hal_reo1_qdesc_lut_base0 = 0x00000074, 732*d8899132SKalle Valo .hal_reo1_qdesc_lut_base1 = 0x00000078, 733*d8899132SKalle Valo .hal_reo1_ring_base_lsb = 0x00000500, 734*d8899132SKalle Valo .hal_reo1_ring_base_msb = 0x00000504, 735*d8899132SKalle Valo .hal_reo1_ring_id = 0x00000508, 736*d8899132SKalle Valo .hal_reo1_ring_misc = 0x00000510, 737*d8899132SKalle Valo .hal_reo1_ring_hp_addr_lsb = 0x00000514, 738*d8899132SKalle Valo .hal_reo1_ring_hp_addr_msb = 0x00000518, 739*d8899132SKalle Valo .hal_reo1_ring_producer_int_setup = 0x00000524, 740*d8899132SKalle Valo .hal_reo1_ring_msi1_base_lsb = 0x00000548, 741*d8899132SKalle Valo .hal_reo1_ring_msi1_base_msb = 0x0000054C, 742*d8899132SKalle Valo .hal_reo1_ring_msi1_data = 0x00000550, 743*d8899132SKalle Valo .hal_reo1_aging_thres_ix0 = 0x00000B28, 744*d8899132SKalle Valo .hal_reo1_aging_thres_ix1 = 0x00000B2C, 745*d8899132SKalle Valo .hal_reo1_aging_thres_ix2 = 0x00000B30, 746*d8899132SKalle Valo .hal_reo1_aging_thres_ix3 = 0x00000B34, 747*d8899132SKalle Valo 748*d8899132SKalle Valo /* REO Exception ring address */ 749*d8899132SKalle Valo .hal_reo2_sw0_ring_base = 0x000008c0, 750*d8899132SKalle Valo 751*d8899132SKalle Valo /* REO Reinject ring address */ 752*d8899132SKalle Valo .hal_sw2reo_ring_base = 0x00000320, 753*d8899132SKalle Valo .hal_sw2reo1_ring_base = 0x00000398, 754*d8899132SKalle Valo 755*d8899132SKalle Valo /* REO cmd ring address */ 756*d8899132SKalle Valo .hal_reo_cmd_ring_base = 0x000002A8, 757*d8899132SKalle Valo 758*d8899132SKalle Valo /* REO status ring address */ 759*d8899132SKalle Valo .hal_reo_status_ring_base = 0x00000aa0, 760*d8899132SKalle Valo }; 761*d8899132SKalle Valo 762*d8899132SKalle Valo static const struct ath12k_hw_regs wcn7850_regs = { 763*d8899132SKalle Valo /* SW2TCL(x) R0 ring configuration address */ 764*d8899132SKalle Valo .hal_tcl1_ring_id = 0x00000908, 765*d8899132SKalle Valo .hal_tcl1_ring_misc = 0x00000910, 766*d8899132SKalle Valo .hal_tcl1_ring_tp_addr_lsb = 0x0000091c, 767*d8899132SKalle Valo .hal_tcl1_ring_tp_addr_msb = 0x00000920, 768*d8899132SKalle Valo .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000930, 769*d8899132SKalle Valo .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000934, 770*d8899132SKalle Valo .hal_tcl1_ring_msi1_base_lsb = 0x00000948, 771*d8899132SKalle Valo .hal_tcl1_ring_msi1_base_msb = 0x0000094c, 772*d8899132SKalle Valo .hal_tcl1_ring_msi1_data = 0x00000950, 773*d8899132SKalle Valo .hal_tcl_ring_base_lsb = 0x00000b58, 774*d8899132SKalle Valo 775*d8899132SKalle Valo /* TCL STATUS ring address */ 776*d8899132SKalle Valo .hal_tcl_status_ring_base_lsb = 0x00000d38, 777*d8899132SKalle Valo 778*d8899132SKalle Valo .hal_wbm_idle_ring_base_lsb = 0x00000d3c, 779*d8899132SKalle Valo .hal_wbm_idle_ring_misc_addr = 0x00000d4c, 780*d8899132SKalle Valo .hal_wbm_r0_idle_list_cntl_addr = 0x00000240, 781*d8899132SKalle Valo .hal_wbm_r0_idle_list_size_addr = 0x00000244, 782*d8899132SKalle Valo .hal_wbm_scattered_ring_base_lsb = 0x00000250, 783*d8899132SKalle Valo .hal_wbm_scattered_ring_base_msb = 0x00000254, 784*d8899132SKalle Valo .hal_wbm_scattered_desc_head_info_ix0 = 0x00000260, 785*d8899132SKalle Valo .hal_wbm_scattered_desc_head_info_ix1 = 0x00000264, 786*d8899132SKalle Valo .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000270, 787*d8899132SKalle Valo .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000274, 788*d8899132SKalle Valo .hal_wbm_scattered_desc_ptr_hp_addr = 0x00000027c, 789*d8899132SKalle Valo 790*d8899132SKalle Valo .hal_wbm_sw_release_ring_base_lsb = 0x0000037c, 791*d8899132SKalle Valo .hal_wbm_sw1_release_ring_base_lsb = 0x00000284, 792*d8899132SKalle Valo .hal_wbm0_release_ring_base_lsb = 0x00000e08, 793*d8899132SKalle Valo .hal_wbm1_release_ring_base_lsb = 0x00000e80, 794*d8899132SKalle Valo 795*d8899132SKalle Valo /* PCIe base address */ 796*d8899132SKalle Valo .pcie_qserdes_sysclk_en_sel = 0x01e0e0a8, 797*d8899132SKalle Valo .pcie_pcs_osc_dtct_config_base = 0x01e0f45c, 798*d8899132SKalle Valo 799*d8899132SKalle Valo /* PPE release ring address */ 800*d8899132SKalle Valo .hal_ppe_rel_ring_base = 0x0000043c, 801*d8899132SKalle Valo 802*d8899132SKalle Valo /* REO DEST ring address */ 803*d8899132SKalle Valo .hal_reo2_ring_base = 0x0000055c, 804*d8899132SKalle Valo .hal_reo1_misc_ctrl_addr = 0x00000b7c, 805*d8899132SKalle Valo .hal_reo1_sw_cookie_cfg0 = 0x00000050, 806*d8899132SKalle Valo .hal_reo1_sw_cookie_cfg1 = 0x00000054, 807*d8899132SKalle Valo .hal_reo1_qdesc_lut_base0 = 0x00000058, 808*d8899132SKalle Valo .hal_reo1_qdesc_lut_base1 = 0x0000005c, 809*d8899132SKalle Valo .hal_reo1_ring_base_lsb = 0x000004e4, 810*d8899132SKalle Valo .hal_reo1_ring_base_msb = 0x000004e8, 811*d8899132SKalle Valo .hal_reo1_ring_id = 0x000004ec, 812*d8899132SKalle Valo .hal_reo1_ring_misc = 0x000004f4, 813*d8899132SKalle Valo .hal_reo1_ring_hp_addr_lsb = 0x000004f8, 814*d8899132SKalle Valo .hal_reo1_ring_hp_addr_msb = 0x000004fc, 815*d8899132SKalle Valo .hal_reo1_ring_producer_int_setup = 0x00000508, 816*d8899132SKalle Valo .hal_reo1_ring_msi1_base_lsb = 0x0000052C, 817*d8899132SKalle Valo .hal_reo1_ring_msi1_base_msb = 0x00000530, 818*d8899132SKalle Valo .hal_reo1_ring_msi1_data = 0x00000534, 819*d8899132SKalle Valo .hal_reo1_aging_thres_ix0 = 0x00000b08, 820*d8899132SKalle Valo .hal_reo1_aging_thres_ix1 = 0x00000b0c, 821*d8899132SKalle Valo .hal_reo1_aging_thres_ix2 = 0x00000b10, 822*d8899132SKalle Valo .hal_reo1_aging_thres_ix3 = 0x00000b14, 823*d8899132SKalle Valo 824*d8899132SKalle Valo /* REO Exception ring address */ 825*d8899132SKalle Valo .hal_reo2_sw0_ring_base = 0x000008a4, 826*d8899132SKalle Valo 827*d8899132SKalle Valo /* REO Reinject ring address */ 828*d8899132SKalle Valo .hal_sw2reo_ring_base = 0x00000304, 829*d8899132SKalle Valo .hal_sw2reo1_ring_base = 0x0000037c, 830*d8899132SKalle Valo 831*d8899132SKalle Valo /* REO cmd ring address */ 832*d8899132SKalle Valo .hal_reo_cmd_ring_base = 0x0000028c, 833*d8899132SKalle Valo 834*d8899132SKalle Valo /* REO status ring address */ 835*d8899132SKalle Valo .hal_reo_status_ring_base = 0x00000a84, 836*d8899132SKalle Valo }; 837*d8899132SKalle Valo 838*d8899132SKalle Valo static const struct ath12k_hw_hal_params ath12k_hw_hal_params_qcn9274 = { 839*d8899132SKalle Valo .rx_buf_rbm = HAL_RX_BUF_RBM_SW3_BM, 840*d8899132SKalle Valo .wbm2sw_cc_enable = HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN | 841*d8899132SKalle Valo HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW1_EN | 842*d8899132SKalle Valo HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN | 843*d8899132SKalle Valo HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN | 844*d8899132SKalle Valo HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN, 845*d8899132SKalle Valo }; 846*d8899132SKalle Valo 847*d8899132SKalle Valo static const struct ath12k_hw_hal_params ath12k_hw_hal_params_wcn7850 = { 848*d8899132SKalle Valo .rx_buf_rbm = HAL_RX_BUF_RBM_SW1_BM, 849*d8899132SKalle Valo .wbm2sw_cc_enable = HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN | 850*d8899132SKalle Valo HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN | 851*d8899132SKalle Valo HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN | 852*d8899132SKalle Valo HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN, 853*d8899132SKalle Valo }; 854*d8899132SKalle Valo 855*d8899132SKalle Valo static const struct ath12k_hw_params ath12k_hw_params[] = { 856*d8899132SKalle Valo { 857*d8899132SKalle Valo .name = "qcn9274 hw1.0", 858*d8899132SKalle Valo .hw_rev = ATH12K_HW_QCN9274_HW10, 859*d8899132SKalle Valo .fw = { 860*d8899132SKalle Valo .dir = "QCN9274/hw1.0", 861*d8899132SKalle Valo .board_size = 256 * 1024, 862*d8899132SKalle Valo .cal_offset = 128 * 1024, 863*d8899132SKalle Valo }, 864*d8899132SKalle Valo .max_radios = 1, 865*d8899132SKalle Valo .single_pdev_only = false, 866*d8899132SKalle Valo .qmi_service_ins_id = ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274, 867*d8899132SKalle Valo .internal_sleep_clock = false, 868*d8899132SKalle Valo 869*d8899132SKalle Valo .hw_ops = &qcn9274_ops, 870*d8899132SKalle Valo .ring_mask = &ath12k_hw_ring_mask_qcn9274, 871*d8899132SKalle Valo .regs = &qcn9274_v1_regs, 872*d8899132SKalle Valo 873*d8899132SKalle Valo .host_ce_config = ath12k_host_ce_config_qcn9274, 874*d8899132SKalle Valo .ce_count = 16, 875*d8899132SKalle Valo .target_ce_config = ath12k_target_ce_config_wlan_qcn9274, 876*d8899132SKalle Valo .target_ce_count = 12, 877*d8899132SKalle Valo .svc_to_ce_map = ath12k_target_service_to_ce_map_wlan_qcn9274, 878*d8899132SKalle Valo .svc_to_ce_map_len = 18, 879*d8899132SKalle Valo 880*d8899132SKalle Valo .hal_params = &ath12k_hw_hal_params_qcn9274, 881*d8899132SKalle Valo 882*d8899132SKalle Valo .rxdma1_enable = false, 883*d8899132SKalle Valo .num_rxmda_per_pdev = 1, 884*d8899132SKalle Valo .num_rxdma_dst_ring = 0, 885*d8899132SKalle Valo .rx_mac_buf_ring = false, 886*d8899132SKalle Valo .vdev_start_delay = false, 887*d8899132SKalle Valo 888*d8899132SKalle Valo .interface_modes = BIT(NL80211_IFTYPE_STATION) | 889*d8899132SKalle Valo BIT(NL80211_IFTYPE_AP), 890*d8899132SKalle Valo .supports_monitor = false, 891*d8899132SKalle Valo 892*d8899132SKalle Valo .idle_ps = false, 893*d8899132SKalle Valo .download_calib = true, 894*d8899132SKalle Valo .supports_suspend = false, 895*d8899132SKalle Valo .tcl_ring_retry = true, 896*d8899132SKalle Valo .reoq_lut_support = false, 897*d8899132SKalle Valo .supports_shadow_regs = false, 898*d8899132SKalle Valo 899*d8899132SKalle Valo .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9274), 900*d8899132SKalle Valo .num_tcl_banks = 48, 901*d8899132SKalle Valo .max_tx_ring = 4, 902*d8899132SKalle Valo 903*d8899132SKalle Valo .mhi_config = &ath12k_mhi_config_qcn9274, 904*d8899132SKalle Valo 905*d8899132SKalle Valo .wmi_init = ath12k_wmi_init_qcn9274, 906*d8899132SKalle Valo 907*d8899132SKalle Valo .hal_ops = &hal_qcn9274_ops, 908*d8899132SKalle Valo 909*d8899132SKalle Valo }, 910*d8899132SKalle Valo { 911*d8899132SKalle Valo .name = "wcn7850 hw2.0", 912*d8899132SKalle Valo .hw_rev = ATH12K_HW_WCN7850_HW20, 913*d8899132SKalle Valo 914*d8899132SKalle Valo .fw = { 915*d8899132SKalle Valo .dir = "WCN7850/hw2.0", 916*d8899132SKalle Valo .board_size = 256 * 1024, 917*d8899132SKalle Valo .cal_offset = 256 * 1024, 918*d8899132SKalle Valo }, 919*d8899132SKalle Valo 920*d8899132SKalle Valo .max_radios = 1, 921*d8899132SKalle Valo .single_pdev_only = true, 922*d8899132SKalle Valo .qmi_service_ins_id = ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_WCN7850, 923*d8899132SKalle Valo .internal_sleep_clock = true, 924*d8899132SKalle Valo 925*d8899132SKalle Valo .hw_ops = &wcn7850_ops, 926*d8899132SKalle Valo .ring_mask = &ath12k_hw_ring_mask_wcn7850, 927*d8899132SKalle Valo .regs = &wcn7850_regs, 928*d8899132SKalle Valo 929*d8899132SKalle Valo .host_ce_config = ath12k_host_ce_config_wcn7850, 930*d8899132SKalle Valo .ce_count = 9, 931*d8899132SKalle Valo .target_ce_config = ath12k_target_ce_config_wlan_wcn7850, 932*d8899132SKalle Valo .target_ce_count = 9, 933*d8899132SKalle Valo .svc_to_ce_map = ath12k_target_service_to_ce_map_wlan_wcn7850, 934*d8899132SKalle Valo .svc_to_ce_map_len = 14, 935*d8899132SKalle Valo 936*d8899132SKalle Valo .hal_params = &ath12k_hw_hal_params_wcn7850, 937*d8899132SKalle Valo 938*d8899132SKalle Valo .rxdma1_enable = false, 939*d8899132SKalle Valo .num_rxmda_per_pdev = 2, 940*d8899132SKalle Valo .num_rxdma_dst_ring = 1, 941*d8899132SKalle Valo .rx_mac_buf_ring = true, 942*d8899132SKalle Valo .vdev_start_delay = true, 943*d8899132SKalle Valo 944*d8899132SKalle Valo .interface_modes = BIT(NL80211_IFTYPE_STATION), 945*d8899132SKalle Valo .supports_monitor = false, 946*d8899132SKalle Valo 947*d8899132SKalle Valo .idle_ps = false, 948*d8899132SKalle Valo .download_calib = false, 949*d8899132SKalle Valo .supports_suspend = false, 950*d8899132SKalle Valo .tcl_ring_retry = false, 951*d8899132SKalle Valo .reoq_lut_support = false, 952*d8899132SKalle Valo .supports_shadow_regs = true, 953*d8899132SKalle Valo 954*d8899132SKalle Valo .hal_desc_sz = sizeof(struct hal_rx_desc_wcn7850), 955*d8899132SKalle Valo .num_tcl_banks = 7, 956*d8899132SKalle Valo .max_tx_ring = 3, 957*d8899132SKalle Valo 958*d8899132SKalle Valo .mhi_config = &ath12k_mhi_config_wcn7850, 959*d8899132SKalle Valo 960*d8899132SKalle Valo .wmi_init = ath12k_wmi_init_wcn7850, 961*d8899132SKalle Valo 962*d8899132SKalle Valo .hal_ops = &hal_wcn7850_ops, 963*d8899132SKalle Valo }, 964*d8899132SKalle Valo { 965*d8899132SKalle Valo .name = "qcn9274 hw2.0", 966*d8899132SKalle Valo .hw_rev = ATH12K_HW_QCN9274_HW20, 967*d8899132SKalle Valo .fw = { 968*d8899132SKalle Valo .dir = "QCN9274/hw2.0", 969*d8899132SKalle Valo .board_size = 256 * 1024, 970*d8899132SKalle Valo .cal_offset = 128 * 1024, 971*d8899132SKalle Valo }, 972*d8899132SKalle Valo .max_radios = 1, 973*d8899132SKalle Valo .single_pdev_only = false, 974*d8899132SKalle Valo .qmi_service_ins_id = ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274, 975*d8899132SKalle Valo .internal_sleep_clock = false, 976*d8899132SKalle Valo 977*d8899132SKalle Valo .hw_ops = &qcn9274_ops, 978*d8899132SKalle Valo .ring_mask = &ath12k_hw_ring_mask_qcn9274, 979*d8899132SKalle Valo .regs = &qcn9274_v2_regs, 980*d8899132SKalle Valo 981*d8899132SKalle Valo .host_ce_config = ath12k_host_ce_config_qcn9274, 982*d8899132SKalle Valo .ce_count = 16, 983*d8899132SKalle Valo .target_ce_config = ath12k_target_ce_config_wlan_qcn9274, 984*d8899132SKalle Valo .target_ce_count = 12, 985*d8899132SKalle Valo .svc_to_ce_map = ath12k_target_service_to_ce_map_wlan_qcn9274, 986*d8899132SKalle Valo .svc_to_ce_map_len = 18, 987*d8899132SKalle Valo 988*d8899132SKalle Valo .hal_params = &ath12k_hw_hal_params_qcn9274, 989*d8899132SKalle Valo 990*d8899132SKalle Valo .rxdma1_enable = false, 991*d8899132SKalle Valo .num_rxmda_per_pdev = 1, 992*d8899132SKalle Valo .num_rxdma_dst_ring = 0, 993*d8899132SKalle Valo .rx_mac_buf_ring = false, 994*d8899132SKalle Valo .vdev_start_delay = false, 995*d8899132SKalle Valo 996*d8899132SKalle Valo .interface_modes = BIT(NL80211_IFTYPE_STATION) | 997*d8899132SKalle Valo BIT(NL80211_IFTYPE_AP), 998*d8899132SKalle Valo .supports_monitor = false, 999*d8899132SKalle Valo 1000*d8899132SKalle Valo .idle_ps = false, 1001*d8899132SKalle Valo .download_calib = true, 1002*d8899132SKalle Valo .supports_suspend = false, 1003*d8899132SKalle Valo .tcl_ring_retry = true, 1004*d8899132SKalle Valo .reoq_lut_support = false, 1005*d8899132SKalle Valo .supports_shadow_regs = false, 1006*d8899132SKalle Valo 1007*d8899132SKalle Valo .hal_desc_sz = sizeof(struct hal_rx_desc_qcn9274), 1008*d8899132SKalle Valo .num_tcl_banks = 48, 1009*d8899132SKalle Valo .max_tx_ring = 4, 1010*d8899132SKalle Valo 1011*d8899132SKalle Valo .mhi_config = &ath12k_mhi_config_qcn9274, 1012*d8899132SKalle Valo 1013*d8899132SKalle Valo .wmi_init = ath12k_wmi_init_qcn9274, 1014*d8899132SKalle Valo 1015*d8899132SKalle Valo .hal_ops = &hal_qcn9274_ops, 1016*d8899132SKalle Valo }, 1017*d8899132SKalle Valo }; 1018*d8899132SKalle Valo 1019*d8899132SKalle Valo int ath12k_hw_init(struct ath12k_base *ab) 1020*d8899132SKalle Valo { 1021*d8899132SKalle Valo const struct ath12k_hw_params *hw_params = NULL; 1022*d8899132SKalle Valo int i; 1023*d8899132SKalle Valo 1024*d8899132SKalle Valo for (i = 0; i < ARRAY_SIZE(ath12k_hw_params); i++) { 1025*d8899132SKalle Valo hw_params = &ath12k_hw_params[i]; 1026*d8899132SKalle Valo 1027*d8899132SKalle Valo if (hw_params->hw_rev == ab->hw_rev) 1028*d8899132SKalle Valo break; 1029*d8899132SKalle Valo } 1030*d8899132SKalle Valo 1031*d8899132SKalle Valo if (i == ARRAY_SIZE(ath12k_hw_params)) { 1032*d8899132SKalle Valo ath12k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev); 1033*d8899132SKalle Valo return -EINVAL; 1034*d8899132SKalle Valo } 1035*d8899132SKalle Valo 1036*d8899132SKalle Valo ab->hw_params = hw_params; 1037*d8899132SKalle Valo 1038*d8899132SKalle Valo ath12k_info(ab, "Hardware name: %s\n", ab->hw_params->name); 1039*d8899132SKalle Valo 1040*d8899132SKalle Valo return 0; 1041*d8899132SKalle Valo } 1042