1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include "core.h" 8 #include "dp_tx.h" 9 #include "debug.h" 10 #include "hw.h" 11 12 static enum hal_tcl_encap_type 13 ath12k_dp_tx_get_encap_type(struct ath12k_vif *arvif, struct sk_buff *skb) 14 { 15 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 16 struct ath12k_base *ab = arvif->ar->ab; 17 18 if (test_bit(ATH12K_FLAG_RAW_MODE, &ab->dev_flags)) 19 return HAL_TCL_ENCAP_TYPE_RAW; 20 21 if (tx_info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) 22 return HAL_TCL_ENCAP_TYPE_ETHERNET; 23 24 return HAL_TCL_ENCAP_TYPE_NATIVE_WIFI; 25 } 26 27 static void ath12k_dp_tx_encap_nwifi(struct sk_buff *skb) 28 { 29 struct ieee80211_hdr *hdr = (void *)skb->data; 30 u8 *qos_ctl; 31 32 if (!ieee80211_is_data_qos(hdr->frame_control)) 33 return; 34 35 qos_ctl = ieee80211_get_qos_ctl(hdr); 36 memmove(skb->data + IEEE80211_QOS_CTL_LEN, 37 skb->data, (void *)qos_ctl - (void *)skb->data); 38 skb_pull(skb, IEEE80211_QOS_CTL_LEN); 39 40 hdr = (void *)skb->data; 41 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 42 } 43 44 static u8 ath12k_dp_tx_get_tid(struct sk_buff *skb) 45 { 46 struct ieee80211_hdr *hdr = (void *)skb->data; 47 struct ath12k_skb_cb *cb = ATH12K_SKB_CB(skb); 48 49 if (cb->flags & ATH12K_SKB_HW_80211_ENCAP) 50 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 51 else if (!ieee80211_is_data_qos(hdr->frame_control)) 52 return HAL_DESC_REO_NON_QOS_TID; 53 else 54 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 55 } 56 57 enum hal_encrypt_type ath12k_dp_tx_get_encrypt_type(u32 cipher) 58 { 59 switch (cipher) { 60 case WLAN_CIPHER_SUITE_WEP40: 61 return HAL_ENCRYPT_TYPE_WEP_40; 62 case WLAN_CIPHER_SUITE_WEP104: 63 return HAL_ENCRYPT_TYPE_WEP_104; 64 case WLAN_CIPHER_SUITE_TKIP: 65 return HAL_ENCRYPT_TYPE_TKIP_MIC; 66 case WLAN_CIPHER_SUITE_CCMP: 67 return HAL_ENCRYPT_TYPE_CCMP_128; 68 case WLAN_CIPHER_SUITE_CCMP_256: 69 return HAL_ENCRYPT_TYPE_CCMP_256; 70 case WLAN_CIPHER_SUITE_GCMP: 71 return HAL_ENCRYPT_TYPE_GCMP_128; 72 case WLAN_CIPHER_SUITE_GCMP_256: 73 return HAL_ENCRYPT_TYPE_AES_GCMP_256; 74 default: 75 return HAL_ENCRYPT_TYPE_OPEN; 76 } 77 } 78 79 static void ath12k_dp_tx_release_txbuf(struct ath12k_dp *dp, 80 struct ath12k_tx_desc_info *tx_desc, 81 u8 pool_id) 82 { 83 spin_lock_bh(&dp->tx_desc_lock[pool_id]); 84 list_move_tail(&tx_desc->list, &dp->tx_desc_free_list[pool_id]); 85 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 86 } 87 88 static struct ath12k_tx_desc_info *ath12k_dp_tx_assign_buffer(struct ath12k_dp *dp, 89 u8 pool_id) 90 { 91 struct ath12k_tx_desc_info *desc; 92 93 spin_lock_bh(&dp->tx_desc_lock[pool_id]); 94 desc = list_first_entry_or_null(&dp->tx_desc_free_list[pool_id], 95 struct ath12k_tx_desc_info, 96 list); 97 if (!desc) { 98 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 99 ath12k_warn(dp->ab, "failed to allocate data Tx buffer\n"); 100 return NULL; 101 } 102 103 list_move_tail(&desc->list, &dp->tx_desc_used_list[pool_id]); 104 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 105 106 return desc; 107 } 108 109 static void ath12k_hal_tx_cmd_ext_desc_setup(struct ath12k_base *ab, void *cmd, 110 struct hal_tx_info *ti) 111 { 112 struct hal_tx_msdu_ext_desc *tcl_ext_cmd = (struct hal_tx_msdu_ext_desc *)cmd; 113 114 tcl_ext_cmd->info0 = le32_encode_bits(ti->paddr, 115 HAL_TX_MSDU_EXT_INFO0_BUF_PTR_LO); 116 tcl_ext_cmd->info1 = le32_encode_bits(0x0, 117 HAL_TX_MSDU_EXT_INFO1_BUF_PTR_HI) | 118 le32_encode_bits(ti->data_len, 119 HAL_TX_MSDU_EXT_INFO1_BUF_LEN); 120 121 tcl_ext_cmd->info1 = le32_encode_bits(1, HAL_TX_MSDU_EXT_INFO1_EXTN_OVERRIDE) | 122 le32_encode_bits(ti->encap_type, 123 HAL_TX_MSDU_EXT_INFO1_ENCAP_TYPE) | 124 le32_encode_bits(ti->encrypt_type, 125 HAL_TX_MSDU_EXT_INFO1_ENCRYPT_TYPE); 126 } 127 128 int ath12k_dp_tx(struct ath12k *ar, struct ath12k_vif *arvif, 129 struct sk_buff *skb) 130 { 131 struct ath12k_base *ab = ar->ab; 132 struct ath12k_dp *dp = &ab->dp; 133 struct hal_tx_info ti = {0}; 134 struct ath12k_tx_desc_info *tx_desc; 135 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 136 struct ath12k_skb_cb *skb_cb = ATH12K_SKB_CB(skb); 137 struct hal_tcl_data_cmd *hal_tcl_desc; 138 struct hal_tx_msdu_ext_desc *msg; 139 struct sk_buff *skb_ext_desc; 140 struct hal_srng *tcl_ring; 141 struct ieee80211_hdr *hdr = (void *)skb->data; 142 struct dp_tx_ring *tx_ring; 143 u8 pool_id; 144 u8 hal_ring_id; 145 int ret; 146 u8 ring_selector, ring_map = 0; 147 bool tcl_ring_retry; 148 bool msdu_ext_desc = false; 149 150 if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags)) 151 return -ESHUTDOWN; 152 153 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 154 !ieee80211_is_data(hdr->frame_control)) 155 return -ENOTSUPP; 156 157 pool_id = skb_get_queue_mapping(skb) & (ATH12K_HW_MAX_QUEUES - 1); 158 159 /* Let the default ring selection be based on current processor 160 * number, where one of the 3 tcl rings are selected based on 161 * the smp_processor_id(). In case that ring 162 * is full/busy, we resort to other available rings. 163 * If all rings are full, we drop the packet. 164 * TODO: Add throttling logic when all rings are full 165 */ 166 ring_selector = ab->hw_params->hw_ops->get_ring_selector(skb); 167 168 tcl_ring_sel: 169 tcl_ring_retry = false; 170 ti.ring_id = ring_selector % ab->hw_params->max_tx_ring; 171 172 ring_map |= BIT(ti.ring_id); 173 ti.rbm_id = ab->hw_params->hal_ops->tcl_to_wbm_rbm_map[ti.ring_id].rbm_id; 174 175 tx_ring = &dp->tx_ring[ti.ring_id]; 176 177 tx_desc = ath12k_dp_tx_assign_buffer(dp, pool_id); 178 if (!tx_desc) 179 return -ENOMEM; 180 181 ti.bank_id = arvif->bank_id; 182 ti.meta_data_flags = arvif->tcl_metadata; 183 184 if (arvif->tx_encap_type == HAL_TCL_ENCAP_TYPE_RAW && 185 test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ar->ab->dev_flags)) { 186 if (skb_cb->flags & ATH12K_SKB_CIPHER_SET) { 187 ti.encrypt_type = 188 ath12k_dp_tx_get_encrypt_type(skb_cb->cipher); 189 190 if (ieee80211_has_protected(hdr->frame_control)) 191 skb_put(skb, IEEE80211_CCMP_MIC_LEN); 192 } else { 193 ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; 194 } 195 196 msdu_ext_desc = true; 197 } 198 199 ti.encap_type = ath12k_dp_tx_get_encap_type(arvif, skb); 200 ti.addr_search_flags = arvif->hal_addr_search_flags; 201 ti.search_type = arvif->search_type; 202 ti.type = HAL_TCL_DESC_TYPE_BUFFER; 203 ti.pkt_offset = 0; 204 ti.lmac_id = ar->lmac_id; 205 ti.vdev_id = arvif->vdev_id; 206 ti.bss_ast_hash = arvif->ast_hash; 207 ti.bss_ast_idx = arvif->ast_idx; 208 ti.dscp_tid_tbl_idx = 0; 209 210 if (skb->ip_summed == CHECKSUM_PARTIAL && 211 ti.encap_type != HAL_TCL_ENCAP_TYPE_RAW) { 212 ti.flags0 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_IP4_CKSUM_EN) | 213 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_UDP4_CKSUM_EN) | 214 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_UDP6_CKSUM_EN) | 215 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TCP4_CKSUM_EN) | 216 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TCP6_CKSUM_EN); 217 } 218 219 ti.flags1 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO3_TID_OVERWRITE); 220 221 ti.tid = ath12k_dp_tx_get_tid(skb); 222 223 switch (ti.encap_type) { 224 case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI: 225 ath12k_dp_tx_encap_nwifi(skb); 226 break; 227 case HAL_TCL_ENCAP_TYPE_RAW: 228 if (!test_bit(ATH12K_FLAG_RAW_MODE, &ab->dev_flags)) { 229 ret = -EINVAL; 230 goto fail_remove_tx_buf; 231 } 232 break; 233 case HAL_TCL_ENCAP_TYPE_ETHERNET: 234 /* no need to encap */ 235 break; 236 case HAL_TCL_ENCAP_TYPE_802_3: 237 default: 238 /* TODO: Take care of other encap modes as well */ 239 ret = -EINVAL; 240 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 241 goto fail_remove_tx_buf; 242 } 243 244 ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE); 245 if (dma_mapping_error(ab->dev, ti.paddr)) { 246 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 247 ath12k_warn(ab, "failed to DMA map data Tx buffer\n"); 248 ret = -ENOMEM; 249 goto fail_remove_tx_buf; 250 } 251 252 tx_desc->skb = skb; 253 tx_desc->mac_id = ar->pdev_idx; 254 ti.desc_id = tx_desc->desc_id; 255 ti.data_len = skb->len; 256 skb_cb->paddr = ti.paddr; 257 skb_cb->vif = arvif->vif; 258 skb_cb->ar = ar; 259 260 if (msdu_ext_desc) { 261 skb_ext_desc = dev_alloc_skb(sizeof(struct hal_tx_msdu_ext_desc)); 262 if (!skb_ext_desc) { 263 ret = -ENOMEM; 264 goto fail_unmap_dma; 265 } 266 267 skb_put(skb_ext_desc, sizeof(struct hal_tx_msdu_ext_desc)); 268 memset(skb_ext_desc->data, 0, skb_ext_desc->len); 269 270 msg = (struct hal_tx_msdu_ext_desc *)skb_ext_desc->data; 271 ath12k_hal_tx_cmd_ext_desc_setup(ab, msg, &ti); 272 273 ti.paddr = dma_map_single(ab->dev, skb_ext_desc->data, 274 skb_ext_desc->len, DMA_TO_DEVICE); 275 ret = dma_mapping_error(ab->dev, ti.paddr); 276 if (ret) { 277 kfree_skb(skb_ext_desc); 278 goto fail_unmap_dma; 279 } 280 281 ti.data_len = skb_ext_desc->len; 282 ti.type = HAL_TCL_DESC_TYPE_EXT_DESC; 283 284 skb_cb->paddr_ext_desc = ti.paddr; 285 } 286 287 hal_ring_id = tx_ring->tcl_data_ring.ring_id; 288 tcl_ring = &ab->hal.srng_list[hal_ring_id]; 289 290 spin_lock_bh(&tcl_ring->lock); 291 292 ath12k_hal_srng_access_begin(ab, tcl_ring); 293 294 hal_tcl_desc = ath12k_hal_srng_src_get_next_entry(ab, tcl_ring); 295 if (!hal_tcl_desc) { 296 /* NOTE: It is highly unlikely we'll be running out of tcl_ring 297 * desc because the desc is directly enqueued onto hw queue. 298 */ 299 ath12k_hal_srng_access_end(ab, tcl_ring); 300 ab->soc_stats.tx_err.desc_na[ti.ring_id]++; 301 spin_unlock_bh(&tcl_ring->lock); 302 ret = -ENOMEM; 303 304 /* Checking for available tcl descritors in another ring in 305 * case of failure due to full tcl ring now, is better than 306 * checking this ring earlier for each pkt tx. 307 * Restart ring selection if some rings are not checked yet. 308 */ 309 if (ring_map != (BIT(ab->hw_params->max_tx_ring) - 1) && 310 ab->hw_params->tcl_ring_retry) { 311 tcl_ring_retry = true; 312 ring_selector++; 313 } 314 315 goto fail_unmap_dma; 316 } 317 318 ath12k_hal_tx_cmd_desc_setup(ab, hal_tcl_desc, &ti); 319 320 ath12k_hal_srng_access_end(ab, tcl_ring); 321 322 spin_unlock_bh(&tcl_ring->lock); 323 324 ath12k_dbg_dump(ab, ATH12K_DBG_DP_TX, NULL, "dp tx msdu: ", 325 skb->data, skb->len); 326 327 atomic_inc(&ar->dp.num_tx_pending); 328 329 return 0; 330 331 fail_unmap_dma: 332 dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE); 333 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, 334 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE); 335 336 fail_remove_tx_buf: 337 ath12k_dp_tx_release_txbuf(dp, tx_desc, pool_id); 338 if (tcl_ring_retry) 339 goto tcl_ring_sel; 340 341 return ret; 342 } 343 344 static void ath12k_dp_tx_free_txbuf(struct ath12k_base *ab, 345 struct sk_buff *msdu, u8 mac_id, 346 struct dp_tx_ring *tx_ring) 347 { 348 struct ath12k *ar; 349 struct ath12k_skb_cb *skb_cb; 350 351 skb_cb = ATH12K_SKB_CB(msdu); 352 353 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 354 if (skb_cb->paddr_ext_desc) 355 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, 356 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE); 357 358 dev_kfree_skb_any(msdu); 359 360 ar = ab->pdevs[mac_id].ar; 361 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 362 wake_up(&ar->dp.tx_empty_waitq); 363 } 364 365 static void 366 ath12k_dp_tx_htt_tx_complete_buf(struct ath12k_base *ab, 367 struct sk_buff *msdu, 368 struct dp_tx_ring *tx_ring, 369 struct ath12k_dp_htt_wbm_tx_status *ts) 370 { 371 struct ieee80211_tx_info *info; 372 struct ath12k_skb_cb *skb_cb; 373 struct ath12k *ar; 374 375 skb_cb = ATH12K_SKB_CB(msdu); 376 info = IEEE80211_SKB_CB(msdu); 377 378 ar = skb_cb->ar; 379 380 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 381 wake_up(&ar->dp.tx_empty_waitq); 382 383 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 384 if (skb_cb->paddr_ext_desc) 385 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, 386 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE); 387 388 memset(&info->status, 0, sizeof(info->status)); 389 390 if (ts->acked) { 391 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 392 info->flags |= IEEE80211_TX_STAT_ACK; 393 info->status.ack_signal = ATH12K_DEFAULT_NOISE_FLOOR + 394 ts->ack_rssi; 395 info->status.flags = IEEE80211_TX_STATUS_ACK_SIGNAL_VALID; 396 } else { 397 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 398 } 399 } 400 401 ieee80211_tx_status(ar->hw, msdu); 402 } 403 404 static void 405 ath12k_dp_tx_process_htt_tx_complete(struct ath12k_base *ab, 406 void *desc, u8 mac_id, 407 struct sk_buff *msdu, 408 struct dp_tx_ring *tx_ring) 409 { 410 struct htt_tx_wbm_completion *status_desc; 411 struct ath12k_dp_htt_wbm_tx_status ts = {0}; 412 enum hal_wbm_htt_tx_comp_status wbm_status; 413 414 status_desc = desc + HTT_TX_WBM_COMP_STATUS_OFFSET; 415 416 wbm_status = le32_get_bits(status_desc->info0, 417 HTT_TX_WBM_COMP_INFO0_STATUS); 418 419 switch (wbm_status) { 420 case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK: 421 case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP: 422 case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL: 423 ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK); 424 ts.ack_rssi = le32_get_bits(status_desc->info2, 425 HTT_TX_WBM_COMP_INFO2_ACK_RSSI); 426 ath12k_dp_tx_htt_tx_complete_buf(ab, msdu, tx_ring, &ts); 427 break; 428 case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ: 429 case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT: 430 ath12k_dp_tx_free_txbuf(ab, msdu, mac_id, tx_ring); 431 break; 432 case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY: 433 /* This event is to be handled only when the driver decides to 434 * use WDS offload functionality. 435 */ 436 break; 437 default: 438 ath12k_warn(ab, "Unknown htt tx status %d\n", wbm_status); 439 break; 440 } 441 } 442 443 static void ath12k_dp_tx_complete_msdu(struct ath12k *ar, 444 struct sk_buff *msdu, 445 struct hal_tx_status *ts) 446 { 447 struct ath12k_base *ab = ar->ab; 448 struct ieee80211_tx_info *info; 449 struct ath12k_skb_cb *skb_cb; 450 451 if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) { 452 /* Must not happen */ 453 return; 454 } 455 456 skb_cb = ATH12K_SKB_CB(msdu); 457 458 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 459 if (skb_cb->paddr_ext_desc) 460 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, 461 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE); 462 463 rcu_read_lock(); 464 465 if (!rcu_dereference(ab->pdevs_active[ar->pdev_idx])) { 466 dev_kfree_skb_any(msdu); 467 goto exit; 468 } 469 470 if (!skb_cb->vif) { 471 dev_kfree_skb_any(msdu); 472 goto exit; 473 } 474 475 info = IEEE80211_SKB_CB(msdu); 476 memset(&info->status, 0, sizeof(info->status)); 477 478 /* skip tx rate update from ieee80211_status*/ 479 info->status.rates[0].idx = -1; 480 481 if (ts->status == HAL_WBM_TQM_REL_REASON_FRAME_ACKED && 482 !(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 483 info->flags |= IEEE80211_TX_STAT_ACK; 484 info->status.ack_signal = ATH12K_DEFAULT_NOISE_FLOOR + 485 ts->ack_rssi; 486 info->status.flags = IEEE80211_TX_STATUS_ACK_SIGNAL_VALID; 487 } 488 489 if (ts->status == HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX && 490 (info->flags & IEEE80211_TX_CTL_NO_ACK)) 491 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 492 493 /* NOTE: Tx rate status reporting. Tx completion status does not have 494 * necessary information (for example nss) to build the tx rate. 495 * Might end up reporting it out-of-band from HTT stats. 496 */ 497 498 ieee80211_tx_status(ar->hw, msdu); 499 500 exit: 501 rcu_read_unlock(); 502 } 503 504 static void ath12k_dp_tx_status_parse(struct ath12k_base *ab, 505 struct hal_wbm_completion_ring_tx *desc, 506 struct hal_tx_status *ts) 507 { 508 ts->buf_rel_source = 509 le32_get_bits(desc->info0, HAL_WBM_COMPL_TX_INFO0_REL_SRC_MODULE); 510 if (ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW && 511 ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM) 512 return; 513 514 if (ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) 515 return; 516 517 ts->status = le32_get_bits(desc->info0, 518 HAL_WBM_COMPL_TX_INFO0_TQM_RELEASE_REASON); 519 520 ts->ppdu_id = le32_get_bits(desc->info1, 521 HAL_WBM_COMPL_TX_INFO1_TQM_STATUS_NUMBER); 522 if (le32_to_cpu(desc->rate_stats.info0) & HAL_TX_RATE_STATS_INFO0_VALID) 523 ts->rate_stats = le32_to_cpu(desc->rate_stats.info0); 524 else 525 ts->rate_stats = 0; 526 } 527 528 void ath12k_dp_tx_completion_handler(struct ath12k_base *ab, int ring_id) 529 { 530 struct ath12k *ar; 531 struct ath12k_dp *dp = &ab->dp; 532 int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id; 533 struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id]; 534 struct ath12k_tx_desc_info *tx_desc = NULL; 535 struct sk_buff *msdu; 536 struct hal_tx_status ts = { 0 }; 537 struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id]; 538 struct hal_wbm_release_ring *desc; 539 u8 mac_id; 540 u64 desc_va; 541 542 spin_lock_bh(&status_ring->lock); 543 544 ath12k_hal_srng_access_begin(ab, status_ring); 545 546 while (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head) != tx_ring->tx_status_tail) { 547 desc = ath12k_hal_srng_dst_get_next_entry(ab, status_ring); 548 if (!desc) 549 break; 550 551 memcpy(&tx_ring->tx_status[tx_ring->tx_status_head], 552 desc, sizeof(*desc)); 553 tx_ring->tx_status_head = 554 ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head); 555 } 556 557 if (ath12k_hal_srng_dst_peek(ab, status_ring) && 558 (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head) == tx_ring->tx_status_tail)) { 559 /* TODO: Process pending tx_status messages when kfifo_is_full() */ 560 ath12k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n"); 561 } 562 563 ath12k_hal_srng_access_end(ab, status_ring); 564 565 spin_unlock_bh(&status_ring->lock); 566 567 while (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_tail) != tx_ring->tx_status_head) { 568 struct hal_wbm_completion_ring_tx *tx_status; 569 u32 desc_id; 570 571 tx_ring->tx_status_tail = 572 ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_tail); 573 tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail]; 574 ath12k_dp_tx_status_parse(ab, tx_status, &ts); 575 576 if (le32_get_bits(tx_status->info0, HAL_WBM_COMPL_TX_INFO0_CC_DONE)) { 577 /* HW done cookie conversion */ 578 desc_va = ((u64)le32_to_cpu(tx_status->buf_va_hi) << 32 | 579 le32_to_cpu(tx_status->buf_va_lo)); 580 tx_desc = (struct ath12k_tx_desc_info *)((unsigned long)desc_va); 581 } else { 582 /* SW does cookie conversion to VA */ 583 desc_id = le32_get_bits(tx_status->buf_va_hi, 584 BUFFER_ADDR_INFO1_SW_COOKIE); 585 586 tx_desc = ath12k_dp_get_tx_desc(ab, desc_id); 587 } 588 if (!tx_desc) { 589 ath12k_warn(ab, "unable to retrieve tx_desc!"); 590 continue; 591 } 592 593 msdu = tx_desc->skb; 594 mac_id = tx_desc->mac_id; 595 596 /* Release descriptor as soon as extracting necessary info 597 * to reduce contention 598 */ 599 ath12k_dp_tx_release_txbuf(dp, tx_desc, tx_desc->pool_id); 600 if (ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) { 601 ath12k_dp_tx_process_htt_tx_complete(ab, 602 (void *)tx_status, 603 mac_id, msdu, 604 tx_ring); 605 continue; 606 } 607 608 ar = ab->pdevs[mac_id].ar; 609 610 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 611 wake_up(&ar->dp.tx_empty_waitq); 612 613 ath12k_dp_tx_complete_msdu(ar, msdu, &ts); 614 } 615 } 616 617 static int 618 ath12k_dp_tx_get_ring_id_type(struct ath12k_base *ab, 619 int mac_id, u32 ring_id, 620 enum hal_ring_type ring_type, 621 enum htt_srng_ring_type *htt_ring_type, 622 enum htt_srng_ring_id *htt_ring_id) 623 { 624 int ret = 0; 625 626 switch (ring_type) { 627 case HAL_RXDMA_BUF: 628 /* for some targets, host fills rx buffer to fw and fw fills to 629 * rxbuf ring for each rxdma 630 */ 631 if (!ab->hw_params->rx_mac_buf_ring) { 632 if (!(ring_id == HAL_SRNG_SW2RXDMA_BUF0 || 633 ring_id == HAL_SRNG_SW2RXDMA_BUF1)) { 634 ret = -EINVAL; 635 } 636 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 637 *htt_ring_type = HTT_SW_TO_HW_RING; 638 } else { 639 if (ring_id == HAL_SRNG_SW2RXDMA_BUF0) { 640 *htt_ring_id = HTT_HOST1_TO_FW_RXBUF_RING; 641 *htt_ring_type = HTT_SW_TO_SW_RING; 642 } else { 643 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 644 *htt_ring_type = HTT_SW_TO_HW_RING; 645 } 646 } 647 break; 648 case HAL_RXDMA_DST: 649 *htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING; 650 *htt_ring_type = HTT_HW_TO_SW_RING; 651 break; 652 case HAL_RXDMA_MONITOR_BUF: 653 *htt_ring_id = HTT_RXDMA_MONITOR_BUF_RING; 654 *htt_ring_type = HTT_SW_TO_HW_RING; 655 break; 656 case HAL_RXDMA_MONITOR_STATUS: 657 *htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING; 658 *htt_ring_type = HTT_SW_TO_HW_RING; 659 break; 660 case HAL_RXDMA_MONITOR_DST: 661 *htt_ring_id = HTT_RXDMA_MONITOR_DEST_RING; 662 *htt_ring_type = HTT_HW_TO_SW_RING; 663 break; 664 case HAL_RXDMA_MONITOR_DESC: 665 *htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING; 666 *htt_ring_type = HTT_SW_TO_HW_RING; 667 break; 668 case HAL_TX_MONITOR_BUF: 669 *htt_ring_id = HTT_TX_MON_HOST2MON_BUF_RING; 670 *htt_ring_type = HTT_SW_TO_HW_RING; 671 break; 672 case HAL_TX_MONITOR_DST: 673 *htt_ring_id = HTT_TX_MON_MON2HOST_DEST_RING; 674 *htt_ring_type = HTT_HW_TO_SW_RING; 675 break; 676 default: 677 ath12k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type); 678 ret = -EINVAL; 679 } 680 return ret; 681 } 682 683 int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id, 684 int mac_id, enum hal_ring_type ring_type) 685 { 686 struct htt_srng_setup_cmd *cmd; 687 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 688 struct hal_srng_params params; 689 struct sk_buff *skb; 690 u32 ring_entry_sz; 691 int len = sizeof(*cmd); 692 dma_addr_t hp_addr, tp_addr; 693 enum htt_srng_ring_type htt_ring_type; 694 enum htt_srng_ring_id htt_ring_id; 695 int ret; 696 697 skb = ath12k_htc_alloc_skb(ab, len); 698 if (!skb) 699 return -ENOMEM; 700 701 memset(¶ms, 0, sizeof(params)); 702 ath12k_hal_srng_get_params(ab, srng, ¶ms); 703 704 hp_addr = ath12k_hal_srng_get_hp_addr(ab, srng); 705 tp_addr = ath12k_hal_srng_get_tp_addr(ab, srng); 706 707 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 708 ring_type, &htt_ring_type, 709 &htt_ring_id); 710 if (ret) 711 goto err_free; 712 713 skb_put(skb, len); 714 cmd = (struct htt_srng_setup_cmd *)skb->data; 715 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_SRING_SETUP, 716 HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE); 717 if (htt_ring_type == HTT_SW_TO_HW_RING || 718 htt_ring_type == HTT_HW_TO_SW_RING) 719 cmd->info0 |= le32_encode_bits(DP_SW2HW_MACID(mac_id), 720 HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID); 721 else 722 cmd->info0 |= le32_encode_bits(mac_id, 723 HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID); 724 cmd->info0 |= le32_encode_bits(htt_ring_type, 725 HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE); 726 cmd->info0 |= le32_encode_bits(htt_ring_id, 727 HTT_SRNG_SETUP_CMD_INFO0_RING_ID); 728 729 cmd->ring_base_addr_lo = cpu_to_le32(params.ring_base_paddr & 730 HAL_ADDR_LSB_REG_MASK); 731 732 cmd->ring_base_addr_hi = cpu_to_le32((u64)params.ring_base_paddr >> 733 HAL_ADDR_MSB_REG_SHIFT); 734 735 ret = ath12k_hal_srng_get_entrysize(ab, ring_type); 736 if (ret < 0) 737 goto err_free; 738 739 ring_entry_sz = ret; 740 741 ring_entry_sz >>= 2; 742 cmd->info1 = le32_encode_bits(ring_entry_sz, 743 HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE); 744 cmd->info1 |= le32_encode_bits(params.num_entries * ring_entry_sz, 745 HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE); 746 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP), 747 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP); 748 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP), 749 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP); 750 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP), 751 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP); 752 if (htt_ring_type == HTT_SW_TO_HW_RING) 753 cmd->info1 |= cpu_to_le32(HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS); 754 755 cmd->ring_head_off32_remote_addr_lo = cpu_to_le32(lower_32_bits(hp_addr)); 756 cmd->ring_head_off32_remote_addr_hi = cpu_to_le32(upper_32_bits(hp_addr)); 757 758 cmd->ring_tail_off32_remote_addr_lo = cpu_to_le32(lower_32_bits(tp_addr)); 759 cmd->ring_tail_off32_remote_addr_hi = cpu_to_le32(upper_32_bits(tp_addr)); 760 761 cmd->ring_msi_addr_lo = cpu_to_le32(lower_32_bits(params.msi_addr)); 762 cmd->ring_msi_addr_hi = cpu_to_le32(upper_32_bits(params.msi_addr)); 763 cmd->msi_data = cpu_to_le32(params.msi_data); 764 765 cmd->intr_info = 766 le32_encode_bits(params.intr_batch_cntr_thres_entries * ring_entry_sz, 767 HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH); 768 cmd->intr_info |= 769 le32_encode_bits(params.intr_timer_thres_us >> 3, 770 HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH); 771 772 cmd->info2 = 0; 773 if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) { 774 cmd->info2 = le32_encode_bits(params.low_threshold, 775 HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH); 776 } 777 778 ath12k_dbg(ab, ATH12K_DBG_HAL, 779 "%s msi_addr_lo:0x%x, msi_addr_hi:0x%x, msi_data:0x%x\n", 780 __func__, cmd->ring_msi_addr_lo, cmd->ring_msi_addr_hi, 781 cmd->msi_data); 782 783 ath12k_dbg(ab, ATH12K_DBG_HAL, 784 "ring_id:%d, ring_type:%d, intr_info:0x%x, flags:0x%x\n", 785 ring_id, ring_type, cmd->intr_info, cmd->info2); 786 787 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb); 788 if (ret) 789 goto err_free; 790 791 return 0; 792 793 err_free: 794 dev_kfree_skb_any(skb); 795 796 return ret; 797 } 798 799 #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ) 800 801 int ath12k_dp_tx_htt_h2t_ver_req_msg(struct ath12k_base *ab) 802 { 803 struct ath12k_dp *dp = &ab->dp; 804 struct sk_buff *skb; 805 struct htt_ver_req_cmd *cmd; 806 int len = sizeof(*cmd); 807 int ret; 808 809 init_completion(&dp->htt_tgt_version_received); 810 811 skb = ath12k_htc_alloc_skb(ab, len); 812 if (!skb) 813 return -ENOMEM; 814 815 skb_put(skb, len); 816 cmd = (struct htt_ver_req_cmd *)skb->data; 817 cmd->ver_reg_info = le32_encode_bits(HTT_H2T_MSG_TYPE_VERSION_REQ, 818 HTT_VER_REQ_INFO_MSG_ID); 819 820 ret = ath12k_htc_send(&ab->htc, dp->eid, skb); 821 if (ret) { 822 dev_kfree_skb_any(skb); 823 return ret; 824 } 825 826 ret = wait_for_completion_timeout(&dp->htt_tgt_version_received, 827 HTT_TARGET_VERSION_TIMEOUT_HZ); 828 if (ret == 0) { 829 ath12k_warn(ab, "htt target version request timed out\n"); 830 return -ETIMEDOUT; 831 } 832 833 if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) { 834 ath12k_err(ab, "unsupported htt major version %d supported version is %d\n", 835 dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR); 836 return -ENOTSUPP; 837 } 838 839 return 0; 840 } 841 842 int ath12k_dp_tx_htt_h2t_ppdu_stats_req(struct ath12k *ar, u32 mask) 843 { 844 struct ath12k_base *ab = ar->ab; 845 struct ath12k_dp *dp = &ab->dp; 846 struct sk_buff *skb; 847 struct htt_ppdu_stats_cfg_cmd *cmd; 848 int len = sizeof(*cmd); 849 u8 pdev_mask; 850 int ret; 851 int i; 852 853 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) { 854 skb = ath12k_htc_alloc_skb(ab, len); 855 if (!skb) 856 return -ENOMEM; 857 858 skb_put(skb, len); 859 cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data; 860 cmd->msg = le32_encode_bits(HTT_H2T_MSG_TYPE_PPDU_STATS_CFG, 861 HTT_PPDU_STATS_CFG_MSG_TYPE); 862 863 pdev_mask = 1 << (i + 1); 864 cmd->msg |= le32_encode_bits(pdev_mask, HTT_PPDU_STATS_CFG_PDEV_ID); 865 cmd->msg |= le32_encode_bits(mask, HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK); 866 867 ret = ath12k_htc_send(&ab->htc, dp->eid, skb); 868 if (ret) { 869 dev_kfree_skb_any(skb); 870 return ret; 871 } 872 } 873 874 return 0; 875 } 876 877 int ath12k_dp_tx_htt_rx_filter_setup(struct ath12k_base *ab, u32 ring_id, 878 int mac_id, enum hal_ring_type ring_type, 879 int rx_buf_size, 880 struct htt_rx_ring_tlv_filter *tlv_filter) 881 { 882 struct htt_rx_ring_selection_cfg_cmd *cmd; 883 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 884 struct hal_srng_params params; 885 struct sk_buff *skb; 886 int len = sizeof(*cmd); 887 enum htt_srng_ring_type htt_ring_type; 888 enum htt_srng_ring_id htt_ring_id; 889 int ret; 890 891 skb = ath12k_htc_alloc_skb(ab, len); 892 if (!skb) 893 return -ENOMEM; 894 895 memset(¶ms, 0, sizeof(params)); 896 ath12k_hal_srng_get_params(ab, srng, ¶ms); 897 898 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 899 ring_type, &htt_ring_type, 900 &htt_ring_id); 901 if (ret) 902 goto err_free; 903 904 skb_put(skb, len); 905 cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data; 906 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG, 907 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE); 908 if (htt_ring_type == HTT_SW_TO_HW_RING || 909 htt_ring_type == HTT_HW_TO_SW_RING) 910 cmd->info0 |= 911 le32_encode_bits(DP_SW2HW_MACID(mac_id), 912 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID); 913 else 914 cmd->info0 |= 915 le32_encode_bits(mac_id, 916 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID); 917 cmd->info0 |= le32_encode_bits(htt_ring_id, 918 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID); 919 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP), 920 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS); 921 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP), 922 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS); 923 cmd->info0 |= le32_encode_bits(tlv_filter->offset_valid, 924 HTT_RX_RING_SELECTION_CFG_CMD_OFFSET_VALID); 925 cmd->info1 = le32_encode_bits(rx_buf_size, 926 HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE); 927 cmd->pkt_type_en_flags0 = cpu_to_le32(tlv_filter->pkt_filter_flags0); 928 cmd->pkt_type_en_flags1 = cpu_to_le32(tlv_filter->pkt_filter_flags1); 929 cmd->pkt_type_en_flags2 = cpu_to_le32(tlv_filter->pkt_filter_flags2); 930 cmd->pkt_type_en_flags3 = cpu_to_le32(tlv_filter->pkt_filter_flags3); 931 cmd->rx_filter_tlv = cpu_to_le32(tlv_filter->rx_filter); 932 933 if (tlv_filter->offset_valid) { 934 cmd->rx_packet_offset = 935 le32_encode_bits(tlv_filter->rx_packet_offset, 936 HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET); 937 938 cmd->rx_packet_offset |= 939 le32_encode_bits(tlv_filter->rx_header_offset, 940 HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET); 941 942 cmd->rx_mpdu_offset = 943 le32_encode_bits(tlv_filter->rx_mpdu_end_offset, 944 HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET); 945 946 cmd->rx_mpdu_offset |= 947 le32_encode_bits(tlv_filter->rx_mpdu_start_offset, 948 HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET); 949 950 cmd->rx_msdu_offset = 951 le32_encode_bits(tlv_filter->rx_msdu_end_offset, 952 HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET); 953 954 cmd->rx_msdu_offset |= 955 le32_encode_bits(tlv_filter->rx_msdu_start_offset, 956 HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET); 957 958 cmd->rx_attn_offset = 959 le32_encode_bits(tlv_filter->rx_attn_offset, 960 HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET); 961 } 962 963 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb); 964 if (ret) 965 goto err_free; 966 967 return 0; 968 969 err_free: 970 dev_kfree_skb_any(skb); 971 972 return ret; 973 } 974 975 int 976 ath12k_dp_tx_htt_h2t_ext_stats_req(struct ath12k *ar, u8 type, 977 struct htt_ext_stats_cfg_params *cfg_params, 978 u64 cookie) 979 { 980 struct ath12k_base *ab = ar->ab; 981 struct ath12k_dp *dp = &ab->dp; 982 struct sk_buff *skb; 983 struct htt_ext_stats_cfg_cmd *cmd; 984 int len = sizeof(*cmd); 985 int ret; 986 987 skb = ath12k_htc_alloc_skb(ab, len); 988 if (!skb) 989 return -ENOMEM; 990 991 skb_put(skb, len); 992 993 cmd = (struct htt_ext_stats_cfg_cmd *)skb->data; 994 memset(cmd, 0, sizeof(*cmd)); 995 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG; 996 997 cmd->hdr.pdev_mask = 1 << ar->pdev->pdev_id; 998 999 cmd->hdr.stats_type = type; 1000 cmd->cfg_param0 = cpu_to_le32(cfg_params->cfg0); 1001 cmd->cfg_param1 = cpu_to_le32(cfg_params->cfg1); 1002 cmd->cfg_param2 = cpu_to_le32(cfg_params->cfg2); 1003 cmd->cfg_param3 = cpu_to_le32(cfg_params->cfg3); 1004 cmd->cookie_lsb = cpu_to_le32(lower_32_bits(cookie)); 1005 cmd->cookie_msb = cpu_to_le32(upper_32_bits(cookie)); 1006 1007 ret = ath12k_htc_send(&ab->htc, dp->eid, skb); 1008 if (ret) { 1009 ath12k_warn(ab, "failed to send htt type stats request: %d", 1010 ret); 1011 dev_kfree_skb_any(skb); 1012 return ret; 1013 } 1014 1015 return 0; 1016 } 1017 1018 int ath12k_dp_tx_htt_monitor_mode_ring_config(struct ath12k *ar, bool reset) 1019 { 1020 struct ath12k_base *ab = ar->ab; 1021 int ret; 1022 1023 ret = ath12k_dp_tx_htt_tx_monitor_mode_ring_config(ar, reset); 1024 if (ret) { 1025 ath12k_err(ab, "failed to setup tx monitor filter %d\n", ret); 1026 return ret; 1027 } 1028 1029 ret = ath12k_dp_tx_htt_tx_monitor_mode_ring_config(ar, reset); 1030 if (ret) { 1031 ath12k_err(ab, "failed to setup rx monitor filter %d\n", ret); 1032 return ret; 1033 } 1034 1035 return 0; 1036 } 1037 1038 int ath12k_dp_tx_htt_rx_monitor_mode_ring_config(struct ath12k *ar, bool reset) 1039 { 1040 struct ath12k_base *ab = ar->ab; 1041 struct ath12k_dp *dp = &ab->dp; 1042 struct htt_rx_ring_tlv_filter tlv_filter = {0}; 1043 int ret, ring_id; 1044 1045 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 1046 tlv_filter.offset_valid = false; 1047 1048 if (!reset) { 1049 tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING; 1050 tlv_filter.pkt_filter_flags0 = 1051 HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 | 1052 HTT_RX_MON_MO_MGMT_FILTER_FLAGS0; 1053 tlv_filter.pkt_filter_flags1 = 1054 HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 | 1055 HTT_RX_MON_MO_MGMT_FILTER_FLAGS1; 1056 tlv_filter.pkt_filter_flags2 = 1057 HTT_RX_MON_FP_CTRL_FILTER_FLASG2 | 1058 HTT_RX_MON_MO_CTRL_FILTER_FLASG2; 1059 tlv_filter.pkt_filter_flags3 = 1060 HTT_RX_MON_FP_CTRL_FILTER_FLASG3 | 1061 HTT_RX_MON_MO_CTRL_FILTER_FLASG3 | 1062 HTT_RX_MON_FP_DATA_FILTER_FLASG3 | 1063 HTT_RX_MON_MO_DATA_FILTER_FLASG3; 1064 } 1065 1066 if (ab->hw_params->rxdma1_enable) { 1067 ret = ath12k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, 0, 1068 HAL_RXDMA_MONITOR_BUF, 1069 DP_RXDMA_REFILL_RING_SIZE, 1070 &tlv_filter); 1071 if (ret) { 1072 ath12k_err(ab, 1073 "failed to setup filter for monitor buf %d\n", ret); 1074 return ret; 1075 } 1076 } 1077 1078 return 0; 1079 } 1080 1081 int ath12k_dp_tx_htt_tx_filter_setup(struct ath12k_base *ab, u32 ring_id, 1082 int mac_id, enum hal_ring_type ring_type, 1083 int tx_buf_size, 1084 struct htt_tx_ring_tlv_filter *htt_tlv_filter) 1085 { 1086 struct htt_tx_ring_selection_cfg_cmd *cmd; 1087 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 1088 struct hal_srng_params params; 1089 struct sk_buff *skb; 1090 int len = sizeof(*cmd); 1091 enum htt_srng_ring_type htt_ring_type; 1092 enum htt_srng_ring_id htt_ring_id; 1093 int ret; 1094 1095 skb = ath12k_htc_alloc_skb(ab, len); 1096 if (!skb) 1097 return -ENOMEM; 1098 1099 memset(¶ms, 0, sizeof(params)); 1100 ath12k_hal_srng_get_params(ab, srng, ¶ms); 1101 1102 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 1103 ring_type, &htt_ring_type, 1104 &htt_ring_id); 1105 1106 if (ret) 1107 goto err_free; 1108 1109 skb_put(skb, len); 1110 cmd = (struct htt_tx_ring_selection_cfg_cmd *)skb->data; 1111 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_TX_MONITOR_CFG, 1112 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE); 1113 if (htt_ring_type == HTT_SW_TO_HW_RING || 1114 htt_ring_type == HTT_HW_TO_SW_RING) 1115 cmd->info0 |= 1116 le32_encode_bits(DP_SW2HW_MACID(mac_id), 1117 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID); 1118 else 1119 cmd->info0 |= 1120 le32_encode_bits(mac_id, 1121 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID); 1122 cmd->info0 |= le32_encode_bits(htt_ring_id, 1123 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_RING_ID); 1124 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP), 1125 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_SS); 1126 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP), 1127 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PS); 1128 1129 cmd->info1 |= 1130 le32_encode_bits(tx_buf_size, 1131 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_RING_BUFF_SIZE); 1132 1133 if (htt_tlv_filter->tx_mon_mgmt_filter) { 1134 cmd->info1 |= 1135 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_MGMT, 1136 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE); 1137 cmd->info1 |= 1138 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len, 1139 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT); 1140 cmd->info2 |= 1141 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_MGMT, 1142 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG); 1143 } 1144 1145 if (htt_tlv_filter->tx_mon_data_filter) { 1146 cmd->info1 |= 1147 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_CTRL, 1148 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE); 1149 cmd->info1 |= 1150 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len, 1151 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL); 1152 cmd->info2 |= 1153 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_CTRL, 1154 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG); 1155 } 1156 1157 if (htt_tlv_filter->tx_mon_ctrl_filter) { 1158 cmd->info1 |= 1159 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_DATA, 1160 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE); 1161 cmd->info1 |= 1162 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len, 1163 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA); 1164 cmd->info2 |= 1165 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_DATA, 1166 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG); 1167 } 1168 1169 cmd->tlv_filter_mask_in0 = 1170 cpu_to_le32(htt_tlv_filter->tx_mon_downstream_tlv_flags); 1171 cmd->tlv_filter_mask_in1 = 1172 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags0); 1173 cmd->tlv_filter_mask_in2 = 1174 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags1); 1175 cmd->tlv_filter_mask_in3 = 1176 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags2); 1177 1178 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb); 1179 if (ret) 1180 goto err_free; 1181 1182 return 0; 1183 1184 err_free: 1185 dev_kfree_skb_any(skb); 1186 return ret; 1187 } 1188 1189 int ath12k_dp_tx_htt_tx_monitor_mode_ring_config(struct ath12k *ar, bool reset) 1190 { 1191 struct ath12k_base *ab = ar->ab; 1192 struct ath12k_dp *dp = &ab->dp; 1193 struct htt_tx_ring_tlv_filter tlv_filter = {0}; 1194 int ret, ring_id; 1195 1196 ring_id = dp->tx_mon_buf_ring.refill_buf_ring.ring_id; 1197 1198 /* TODO: Need to set upstream/downstream tlv filters 1199 * here 1200 */ 1201 1202 if (ab->hw_params->rxdma1_enable) { 1203 ret = ath12k_dp_tx_htt_tx_filter_setup(ar->ab, ring_id, 0, 1204 HAL_TX_MONITOR_BUF, 1205 DP_RXDMA_REFILL_RING_SIZE, 1206 &tlv_filter); 1207 if (ret) { 1208 ath12k_err(ab, 1209 "failed to setup filter for monitor buf %d\n", ret); 1210 return ret; 1211 } 1212 } 1213 1214 return 0; 1215 } 1216