1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include "core.h" 8 #include "dp_tx.h" 9 #include "debug.h" 10 #include "hw.h" 11 12 static enum hal_tcl_encap_type 13 ath12k_dp_tx_get_encap_type(struct ath12k_vif *arvif, struct sk_buff *skb) 14 { 15 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 16 struct ath12k_base *ab = arvif->ar->ab; 17 18 if (test_bit(ATH12K_FLAG_RAW_MODE, &ab->dev_flags)) 19 return HAL_TCL_ENCAP_TYPE_RAW; 20 21 if (tx_info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) 22 return HAL_TCL_ENCAP_TYPE_ETHERNET; 23 24 return HAL_TCL_ENCAP_TYPE_NATIVE_WIFI; 25 } 26 27 static void ath12k_dp_tx_encap_nwifi(struct sk_buff *skb) 28 { 29 struct ieee80211_hdr *hdr = (void *)skb->data; 30 u8 *qos_ctl; 31 32 if (!ieee80211_is_data_qos(hdr->frame_control)) 33 return; 34 35 qos_ctl = ieee80211_get_qos_ctl(hdr); 36 memmove(skb->data + IEEE80211_QOS_CTL_LEN, 37 skb->data, (void *)qos_ctl - (void *)skb->data); 38 skb_pull(skb, IEEE80211_QOS_CTL_LEN); 39 40 hdr = (void *)skb->data; 41 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 42 } 43 44 static u8 ath12k_dp_tx_get_tid(struct sk_buff *skb) 45 { 46 struct ieee80211_hdr *hdr = (void *)skb->data; 47 struct ath12k_skb_cb *cb = ATH12K_SKB_CB(skb); 48 49 if (cb->flags & ATH12K_SKB_HW_80211_ENCAP) 50 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 51 else if (!ieee80211_is_data_qos(hdr->frame_control)) 52 return HAL_DESC_REO_NON_QOS_TID; 53 else 54 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 55 } 56 57 enum hal_encrypt_type ath12k_dp_tx_get_encrypt_type(u32 cipher) 58 { 59 switch (cipher) { 60 case WLAN_CIPHER_SUITE_WEP40: 61 return HAL_ENCRYPT_TYPE_WEP_40; 62 case WLAN_CIPHER_SUITE_WEP104: 63 return HAL_ENCRYPT_TYPE_WEP_104; 64 case WLAN_CIPHER_SUITE_TKIP: 65 return HAL_ENCRYPT_TYPE_TKIP_MIC; 66 case WLAN_CIPHER_SUITE_CCMP: 67 return HAL_ENCRYPT_TYPE_CCMP_128; 68 case WLAN_CIPHER_SUITE_CCMP_256: 69 return HAL_ENCRYPT_TYPE_CCMP_256; 70 case WLAN_CIPHER_SUITE_GCMP: 71 return HAL_ENCRYPT_TYPE_GCMP_128; 72 case WLAN_CIPHER_SUITE_GCMP_256: 73 return HAL_ENCRYPT_TYPE_AES_GCMP_256; 74 default: 75 return HAL_ENCRYPT_TYPE_OPEN; 76 } 77 } 78 79 static void ath12k_dp_tx_release_txbuf(struct ath12k_dp *dp, 80 struct ath12k_tx_desc_info *tx_desc, 81 u8 pool_id) 82 { 83 spin_lock_bh(&dp->tx_desc_lock[pool_id]); 84 list_move_tail(&tx_desc->list, &dp->tx_desc_free_list[pool_id]); 85 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 86 } 87 88 static struct ath12k_tx_desc_info *ath12k_dp_tx_assign_buffer(struct ath12k_dp *dp, 89 u8 pool_id) 90 { 91 struct ath12k_tx_desc_info *desc; 92 93 spin_lock_bh(&dp->tx_desc_lock[pool_id]); 94 desc = list_first_entry_or_null(&dp->tx_desc_free_list[pool_id], 95 struct ath12k_tx_desc_info, 96 list); 97 if (!desc) { 98 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 99 ath12k_warn(dp->ab, "failed to allocate data Tx buffer\n"); 100 return NULL; 101 } 102 103 list_move_tail(&desc->list, &dp->tx_desc_used_list[pool_id]); 104 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 105 106 return desc; 107 } 108 109 static void ath12k_hal_tx_cmd_ext_desc_setup(struct ath12k_base *ab, void *cmd, 110 struct hal_tx_info *ti) 111 { 112 struct hal_tx_msdu_ext_desc *tcl_ext_cmd = (struct hal_tx_msdu_ext_desc *)cmd; 113 114 tcl_ext_cmd->info0 = le32_encode_bits(ti->paddr, 115 HAL_TX_MSDU_EXT_INFO0_BUF_PTR_LO); 116 tcl_ext_cmd->info1 = le32_encode_bits(0x0, 117 HAL_TX_MSDU_EXT_INFO1_BUF_PTR_HI) | 118 le32_encode_bits(ti->data_len, 119 HAL_TX_MSDU_EXT_INFO1_BUF_LEN); 120 121 tcl_ext_cmd->info1 = le32_encode_bits(1, HAL_TX_MSDU_EXT_INFO1_EXTN_OVERRIDE) | 122 le32_encode_bits(ti->encap_type, 123 HAL_TX_MSDU_EXT_INFO1_ENCAP_TYPE) | 124 le32_encode_bits(ti->encrypt_type, 125 HAL_TX_MSDU_EXT_INFO1_ENCRYPT_TYPE); 126 } 127 128 int ath12k_dp_tx(struct ath12k *ar, struct ath12k_vif *arvif, 129 struct sk_buff *skb) 130 { 131 struct ath12k_base *ab = ar->ab; 132 struct ath12k_dp *dp = &ab->dp; 133 struct hal_tx_info ti = {0}; 134 struct ath12k_tx_desc_info *tx_desc; 135 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 136 struct ath12k_skb_cb *skb_cb = ATH12K_SKB_CB(skb); 137 struct hal_tcl_data_cmd *hal_tcl_desc; 138 struct hal_tx_msdu_ext_desc *msg; 139 struct sk_buff *skb_ext_desc; 140 struct hal_srng *tcl_ring; 141 struct ieee80211_hdr *hdr = (void *)skb->data; 142 struct dp_tx_ring *tx_ring; 143 u8 pool_id; 144 u8 hal_ring_id; 145 int ret; 146 u8 ring_selector, ring_map = 0; 147 bool tcl_ring_retry; 148 bool msdu_ext_desc = false; 149 150 if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags)) 151 return -ESHUTDOWN; 152 153 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 154 !ieee80211_is_data(hdr->frame_control)) 155 return -ENOTSUPP; 156 157 pool_id = skb_get_queue_mapping(skb) & (ATH12K_HW_MAX_QUEUES - 1); 158 159 /* Let the default ring selection be based on current processor 160 * number, where one of the 3 tcl rings are selected based on 161 * the smp_processor_id(). In case that ring 162 * is full/busy, we resort to other available rings. 163 * If all rings are full, we drop the packet. 164 * TODO: Add throttling logic when all rings are full 165 */ 166 ring_selector = ab->hw_params->hw_ops->get_ring_selector(skb); 167 168 tcl_ring_sel: 169 tcl_ring_retry = false; 170 ti.ring_id = ring_selector % ab->hw_params->max_tx_ring; 171 172 ring_map |= BIT(ti.ring_id); 173 ti.rbm_id = ab->hw_params->hal_ops->tcl_to_wbm_rbm_map[ti.ring_id].rbm_id; 174 175 tx_ring = &dp->tx_ring[ti.ring_id]; 176 177 tx_desc = ath12k_dp_tx_assign_buffer(dp, pool_id); 178 if (!tx_desc) 179 return -ENOMEM; 180 181 ti.bank_id = arvif->bank_id; 182 ti.meta_data_flags = arvif->tcl_metadata; 183 184 if (arvif->tx_encap_type == HAL_TCL_ENCAP_TYPE_RAW && 185 test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ar->ab->dev_flags)) { 186 if (skb_cb->flags & ATH12K_SKB_CIPHER_SET) { 187 ti.encrypt_type = 188 ath12k_dp_tx_get_encrypt_type(skb_cb->cipher); 189 190 if (ieee80211_has_protected(hdr->frame_control)) 191 skb_put(skb, IEEE80211_CCMP_MIC_LEN); 192 } else { 193 ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; 194 } 195 196 msdu_ext_desc = true; 197 } 198 199 ti.encap_type = ath12k_dp_tx_get_encap_type(arvif, skb); 200 ti.addr_search_flags = arvif->hal_addr_search_flags; 201 ti.search_type = arvif->search_type; 202 ti.type = HAL_TCL_DESC_TYPE_BUFFER; 203 ti.pkt_offset = 0; 204 ti.lmac_id = ar->lmac_id; 205 ti.vdev_id = arvif->vdev_id; 206 ti.bss_ast_hash = arvif->ast_hash; 207 ti.bss_ast_idx = arvif->ast_idx; 208 ti.dscp_tid_tbl_idx = 0; 209 210 if (skb->ip_summed == CHECKSUM_PARTIAL && 211 ti.encap_type != HAL_TCL_ENCAP_TYPE_RAW) { 212 ti.flags0 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_IP4_CKSUM_EN) | 213 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_UDP4_CKSUM_EN) | 214 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_UDP6_CKSUM_EN) | 215 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TCP4_CKSUM_EN) | 216 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TCP6_CKSUM_EN); 217 } 218 219 ti.flags1 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO3_TID_OVERWRITE); 220 221 ti.tid = ath12k_dp_tx_get_tid(skb); 222 223 switch (ti.encap_type) { 224 case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI: 225 ath12k_dp_tx_encap_nwifi(skb); 226 break; 227 case HAL_TCL_ENCAP_TYPE_RAW: 228 if (!test_bit(ATH12K_FLAG_RAW_MODE, &ab->dev_flags)) { 229 ret = -EINVAL; 230 goto fail_remove_tx_buf; 231 } 232 break; 233 case HAL_TCL_ENCAP_TYPE_ETHERNET: 234 /* no need to encap */ 235 break; 236 case HAL_TCL_ENCAP_TYPE_802_3: 237 default: 238 /* TODO: Take care of other encap modes as well */ 239 ret = -EINVAL; 240 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 241 goto fail_remove_tx_buf; 242 } 243 244 ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE); 245 if (dma_mapping_error(ab->dev, ti.paddr)) { 246 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 247 ath12k_warn(ab, "failed to DMA map data Tx buffer\n"); 248 ret = -ENOMEM; 249 goto fail_remove_tx_buf; 250 } 251 252 tx_desc->skb = skb; 253 tx_desc->mac_id = ar->pdev_idx; 254 ti.desc_id = tx_desc->desc_id; 255 ti.data_len = skb->len; 256 skb_cb->paddr = ti.paddr; 257 skb_cb->vif = arvif->vif; 258 skb_cb->ar = ar; 259 260 if (msdu_ext_desc) { 261 skb_ext_desc = dev_alloc_skb(sizeof(struct hal_tx_msdu_ext_desc)); 262 if (!skb_ext_desc) { 263 ret = -ENOMEM; 264 goto fail_unmap_dma; 265 } 266 267 skb_put(skb_ext_desc, sizeof(struct hal_tx_msdu_ext_desc)); 268 memset(skb_ext_desc->data, 0, skb_ext_desc->len); 269 270 msg = (struct hal_tx_msdu_ext_desc *)skb_ext_desc->data; 271 ath12k_hal_tx_cmd_ext_desc_setup(ab, msg, &ti); 272 273 ti.paddr = dma_map_single(ab->dev, skb_ext_desc->data, 274 skb_ext_desc->len, DMA_TO_DEVICE); 275 ret = dma_mapping_error(ab->dev, ti.paddr); 276 if (ret) { 277 kfree_skb(skb_ext_desc); 278 goto fail_unmap_dma; 279 } 280 281 ti.data_len = skb_ext_desc->len; 282 ti.type = HAL_TCL_DESC_TYPE_EXT_DESC; 283 284 skb_cb->paddr_ext_desc = ti.paddr; 285 } 286 287 hal_ring_id = tx_ring->tcl_data_ring.ring_id; 288 tcl_ring = &ab->hal.srng_list[hal_ring_id]; 289 290 spin_lock_bh(&tcl_ring->lock); 291 292 ath12k_hal_srng_access_begin(ab, tcl_ring); 293 294 hal_tcl_desc = ath12k_hal_srng_src_get_next_entry(ab, tcl_ring); 295 if (!hal_tcl_desc) { 296 /* NOTE: It is highly unlikely we'll be running out of tcl_ring 297 * desc because the desc is directly enqueued onto hw queue. 298 */ 299 ath12k_hal_srng_access_end(ab, tcl_ring); 300 ab->soc_stats.tx_err.desc_na[ti.ring_id]++; 301 spin_unlock_bh(&tcl_ring->lock); 302 ret = -ENOMEM; 303 304 /* Checking for available tcl descriptors in another ring in 305 * case of failure due to full tcl ring now, is better than 306 * checking this ring earlier for each pkt tx. 307 * Restart ring selection if some rings are not checked yet. 308 */ 309 if (ring_map != (BIT(ab->hw_params->max_tx_ring) - 1) && 310 ab->hw_params->tcl_ring_retry) { 311 tcl_ring_retry = true; 312 ring_selector++; 313 } 314 315 goto fail_unmap_dma; 316 } 317 318 ath12k_hal_tx_cmd_desc_setup(ab, hal_tcl_desc, &ti); 319 320 ath12k_hal_srng_access_end(ab, tcl_ring); 321 322 spin_unlock_bh(&tcl_ring->lock); 323 324 ath12k_dbg_dump(ab, ATH12K_DBG_DP_TX, NULL, "dp tx msdu: ", 325 skb->data, skb->len); 326 327 atomic_inc(&ar->dp.num_tx_pending); 328 329 return 0; 330 331 fail_unmap_dma: 332 dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE); 333 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, 334 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE); 335 336 fail_remove_tx_buf: 337 ath12k_dp_tx_release_txbuf(dp, tx_desc, pool_id); 338 if (tcl_ring_retry) 339 goto tcl_ring_sel; 340 341 return ret; 342 } 343 344 static void ath12k_dp_tx_free_txbuf(struct ath12k_base *ab, 345 struct sk_buff *msdu, u8 mac_id, 346 struct dp_tx_ring *tx_ring) 347 { 348 struct ath12k *ar; 349 struct ath12k_skb_cb *skb_cb; 350 u8 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id); 351 352 skb_cb = ATH12K_SKB_CB(msdu); 353 354 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 355 if (skb_cb->paddr_ext_desc) 356 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, 357 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE); 358 359 dev_kfree_skb_any(msdu); 360 361 ar = ab->pdevs[pdev_id].ar; 362 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 363 wake_up(&ar->dp.tx_empty_waitq); 364 } 365 366 static void 367 ath12k_dp_tx_htt_tx_complete_buf(struct ath12k_base *ab, 368 struct sk_buff *msdu, 369 struct dp_tx_ring *tx_ring, 370 struct ath12k_dp_htt_wbm_tx_status *ts) 371 { 372 struct ieee80211_tx_info *info; 373 struct ath12k_skb_cb *skb_cb; 374 struct ath12k *ar; 375 376 skb_cb = ATH12K_SKB_CB(msdu); 377 info = IEEE80211_SKB_CB(msdu); 378 379 ar = skb_cb->ar; 380 381 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 382 wake_up(&ar->dp.tx_empty_waitq); 383 384 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 385 if (skb_cb->paddr_ext_desc) 386 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, 387 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE); 388 389 memset(&info->status, 0, sizeof(info->status)); 390 391 if (ts->acked) { 392 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 393 info->flags |= IEEE80211_TX_STAT_ACK; 394 info->status.ack_signal = ATH12K_DEFAULT_NOISE_FLOOR + 395 ts->ack_rssi; 396 info->status.flags = IEEE80211_TX_STATUS_ACK_SIGNAL_VALID; 397 } else { 398 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 399 } 400 } 401 402 ieee80211_tx_status(ar->hw, msdu); 403 } 404 405 static void 406 ath12k_dp_tx_process_htt_tx_complete(struct ath12k_base *ab, 407 void *desc, u8 mac_id, 408 struct sk_buff *msdu, 409 struct dp_tx_ring *tx_ring) 410 { 411 struct htt_tx_wbm_completion *status_desc; 412 struct ath12k_dp_htt_wbm_tx_status ts = {0}; 413 enum hal_wbm_htt_tx_comp_status wbm_status; 414 415 status_desc = desc + HTT_TX_WBM_COMP_STATUS_OFFSET; 416 417 wbm_status = le32_get_bits(status_desc->info0, 418 HTT_TX_WBM_COMP_INFO0_STATUS); 419 420 switch (wbm_status) { 421 case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK: 422 case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP: 423 case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL: 424 ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK); 425 ts.ack_rssi = le32_get_bits(status_desc->info2, 426 HTT_TX_WBM_COMP_INFO2_ACK_RSSI); 427 ath12k_dp_tx_htt_tx_complete_buf(ab, msdu, tx_ring, &ts); 428 break; 429 case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ: 430 case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT: 431 ath12k_dp_tx_free_txbuf(ab, msdu, mac_id, tx_ring); 432 break; 433 case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY: 434 /* This event is to be handled only when the driver decides to 435 * use WDS offload functionality. 436 */ 437 break; 438 default: 439 ath12k_warn(ab, "Unknown htt tx status %d\n", wbm_status); 440 break; 441 } 442 } 443 444 static void ath12k_dp_tx_complete_msdu(struct ath12k *ar, 445 struct sk_buff *msdu, 446 struct hal_tx_status *ts) 447 { 448 struct ath12k_base *ab = ar->ab; 449 struct ieee80211_tx_info *info; 450 struct ath12k_skb_cb *skb_cb; 451 452 if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) { 453 /* Must not happen */ 454 return; 455 } 456 457 skb_cb = ATH12K_SKB_CB(msdu); 458 459 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 460 if (skb_cb->paddr_ext_desc) 461 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, 462 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE); 463 464 rcu_read_lock(); 465 466 if (!rcu_dereference(ab->pdevs_active[ar->pdev_idx])) { 467 dev_kfree_skb_any(msdu); 468 goto exit; 469 } 470 471 if (!skb_cb->vif) { 472 dev_kfree_skb_any(msdu); 473 goto exit; 474 } 475 476 info = IEEE80211_SKB_CB(msdu); 477 memset(&info->status, 0, sizeof(info->status)); 478 479 /* skip tx rate update from ieee80211_status*/ 480 info->status.rates[0].idx = -1; 481 482 if (ts->status == HAL_WBM_TQM_REL_REASON_FRAME_ACKED && 483 !(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 484 info->flags |= IEEE80211_TX_STAT_ACK; 485 info->status.ack_signal = ATH12K_DEFAULT_NOISE_FLOOR + 486 ts->ack_rssi; 487 info->status.flags = IEEE80211_TX_STATUS_ACK_SIGNAL_VALID; 488 } 489 490 if (ts->status == HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX && 491 (info->flags & IEEE80211_TX_CTL_NO_ACK)) 492 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 493 494 /* NOTE: Tx rate status reporting. Tx completion status does not have 495 * necessary information (for example nss) to build the tx rate. 496 * Might end up reporting it out-of-band from HTT stats. 497 */ 498 499 ieee80211_tx_status(ar->hw, msdu); 500 501 exit: 502 rcu_read_unlock(); 503 } 504 505 static void ath12k_dp_tx_status_parse(struct ath12k_base *ab, 506 struct hal_wbm_completion_ring_tx *desc, 507 struct hal_tx_status *ts) 508 { 509 ts->buf_rel_source = 510 le32_get_bits(desc->info0, HAL_WBM_COMPL_TX_INFO0_REL_SRC_MODULE); 511 if (ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW && 512 ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM) 513 return; 514 515 if (ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) 516 return; 517 518 ts->status = le32_get_bits(desc->info0, 519 HAL_WBM_COMPL_TX_INFO0_TQM_RELEASE_REASON); 520 521 ts->ppdu_id = le32_get_bits(desc->info1, 522 HAL_WBM_COMPL_TX_INFO1_TQM_STATUS_NUMBER); 523 if (le32_to_cpu(desc->rate_stats.info0) & HAL_TX_RATE_STATS_INFO0_VALID) 524 ts->rate_stats = le32_to_cpu(desc->rate_stats.info0); 525 else 526 ts->rate_stats = 0; 527 } 528 529 void ath12k_dp_tx_completion_handler(struct ath12k_base *ab, int ring_id) 530 { 531 struct ath12k *ar; 532 struct ath12k_dp *dp = &ab->dp; 533 int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id; 534 struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id]; 535 struct ath12k_tx_desc_info *tx_desc = NULL; 536 struct sk_buff *msdu; 537 struct hal_tx_status ts = { 0 }; 538 struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id]; 539 struct hal_wbm_release_ring *desc; 540 u8 mac_id, pdev_id; 541 u64 desc_va; 542 543 spin_lock_bh(&status_ring->lock); 544 545 ath12k_hal_srng_access_begin(ab, status_ring); 546 547 while (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head) != tx_ring->tx_status_tail) { 548 desc = ath12k_hal_srng_dst_get_next_entry(ab, status_ring); 549 if (!desc) 550 break; 551 552 memcpy(&tx_ring->tx_status[tx_ring->tx_status_head], 553 desc, sizeof(*desc)); 554 tx_ring->tx_status_head = 555 ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head); 556 } 557 558 if (ath12k_hal_srng_dst_peek(ab, status_ring) && 559 (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head) == tx_ring->tx_status_tail)) { 560 /* TODO: Process pending tx_status messages when kfifo_is_full() */ 561 ath12k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n"); 562 } 563 564 ath12k_hal_srng_access_end(ab, status_ring); 565 566 spin_unlock_bh(&status_ring->lock); 567 568 while (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_tail) != tx_ring->tx_status_head) { 569 struct hal_wbm_completion_ring_tx *tx_status; 570 u32 desc_id; 571 572 tx_ring->tx_status_tail = 573 ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_tail); 574 tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail]; 575 ath12k_dp_tx_status_parse(ab, tx_status, &ts); 576 577 if (le32_get_bits(tx_status->info0, HAL_WBM_COMPL_TX_INFO0_CC_DONE)) { 578 /* HW done cookie conversion */ 579 desc_va = ((u64)le32_to_cpu(tx_status->buf_va_hi) << 32 | 580 le32_to_cpu(tx_status->buf_va_lo)); 581 tx_desc = (struct ath12k_tx_desc_info *)((unsigned long)desc_va); 582 } else { 583 /* SW does cookie conversion to VA */ 584 desc_id = le32_get_bits(tx_status->buf_va_hi, 585 BUFFER_ADDR_INFO1_SW_COOKIE); 586 587 tx_desc = ath12k_dp_get_tx_desc(ab, desc_id); 588 } 589 if (!tx_desc) { 590 ath12k_warn(ab, "unable to retrieve tx_desc!"); 591 continue; 592 } 593 594 msdu = tx_desc->skb; 595 mac_id = tx_desc->mac_id; 596 597 /* Release descriptor as soon as extracting necessary info 598 * to reduce contention 599 */ 600 ath12k_dp_tx_release_txbuf(dp, tx_desc, tx_desc->pool_id); 601 if (ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) { 602 ath12k_dp_tx_process_htt_tx_complete(ab, 603 (void *)tx_status, 604 mac_id, msdu, 605 tx_ring); 606 continue; 607 } 608 609 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id); 610 ar = ab->pdevs[pdev_id].ar; 611 612 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 613 wake_up(&ar->dp.tx_empty_waitq); 614 615 ath12k_dp_tx_complete_msdu(ar, msdu, &ts); 616 } 617 } 618 619 static int 620 ath12k_dp_tx_get_ring_id_type(struct ath12k_base *ab, 621 int mac_id, u32 ring_id, 622 enum hal_ring_type ring_type, 623 enum htt_srng_ring_type *htt_ring_type, 624 enum htt_srng_ring_id *htt_ring_id) 625 { 626 int ret = 0; 627 628 switch (ring_type) { 629 case HAL_RXDMA_BUF: 630 /* for some targets, host fills rx buffer to fw and fw fills to 631 * rxbuf ring for each rxdma 632 */ 633 if (!ab->hw_params->rx_mac_buf_ring) { 634 if (!(ring_id == HAL_SRNG_SW2RXDMA_BUF0 || 635 ring_id == HAL_SRNG_SW2RXDMA_BUF1)) { 636 ret = -EINVAL; 637 } 638 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 639 *htt_ring_type = HTT_SW_TO_HW_RING; 640 } else { 641 if (ring_id == HAL_SRNG_SW2RXDMA_BUF0) { 642 *htt_ring_id = HTT_HOST1_TO_FW_RXBUF_RING; 643 *htt_ring_type = HTT_SW_TO_SW_RING; 644 } else { 645 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 646 *htt_ring_type = HTT_SW_TO_HW_RING; 647 } 648 } 649 break; 650 case HAL_RXDMA_DST: 651 *htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING; 652 *htt_ring_type = HTT_HW_TO_SW_RING; 653 break; 654 case HAL_RXDMA_MONITOR_BUF: 655 *htt_ring_id = HTT_RXDMA_MONITOR_BUF_RING; 656 *htt_ring_type = HTT_SW_TO_HW_RING; 657 break; 658 case HAL_RXDMA_MONITOR_STATUS: 659 *htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING; 660 *htt_ring_type = HTT_SW_TO_HW_RING; 661 break; 662 case HAL_RXDMA_MONITOR_DST: 663 *htt_ring_id = HTT_RXDMA_MONITOR_DEST_RING; 664 *htt_ring_type = HTT_HW_TO_SW_RING; 665 break; 666 case HAL_RXDMA_MONITOR_DESC: 667 *htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING; 668 *htt_ring_type = HTT_SW_TO_HW_RING; 669 break; 670 case HAL_TX_MONITOR_BUF: 671 *htt_ring_id = HTT_TX_MON_HOST2MON_BUF_RING; 672 *htt_ring_type = HTT_SW_TO_HW_RING; 673 break; 674 case HAL_TX_MONITOR_DST: 675 *htt_ring_id = HTT_TX_MON_MON2HOST_DEST_RING; 676 *htt_ring_type = HTT_HW_TO_SW_RING; 677 break; 678 default: 679 ath12k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type); 680 ret = -EINVAL; 681 } 682 return ret; 683 } 684 685 int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id, 686 int mac_id, enum hal_ring_type ring_type) 687 { 688 struct htt_srng_setup_cmd *cmd; 689 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 690 struct hal_srng_params params; 691 struct sk_buff *skb; 692 u32 ring_entry_sz; 693 int len = sizeof(*cmd); 694 dma_addr_t hp_addr, tp_addr; 695 enum htt_srng_ring_type htt_ring_type; 696 enum htt_srng_ring_id htt_ring_id; 697 int ret; 698 699 skb = ath12k_htc_alloc_skb(ab, len); 700 if (!skb) 701 return -ENOMEM; 702 703 memset(¶ms, 0, sizeof(params)); 704 ath12k_hal_srng_get_params(ab, srng, ¶ms); 705 706 hp_addr = ath12k_hal_srng_get_hp_addr(ab, srng); 707 tp_addr = ath12k_hal_srng_get_tp_addr(ab, srng); 708 709 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 710 ring_type, &htt_ring_type, 711 &htt_ring_id); 712 if (ret) 713 goto err_free; 714 715 skb_put(skb, len); 716 cmd = (struct htt_srng_setup_cmd *)skb->data; 717 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_SRING_SETUP, 718 HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE); 719 if (htt_ring_type == HTT_SW_TO_HW_RING || 720 htt_ring_type == HTT_HW_TO_SW_RING) 721 cmd->info0 |= le32_encode_bits(DP_SW2HW_MACID(mac_id), 722 HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID); 723 else 724 cmd->info0 |= le32_encode_bits(mac_id, 725 HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID); 726 cmd->info0 |= le32_encode_bits(htt_ring_type, 727 HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE); 728 cmd->info0 |= le32_encode_bits(htt_ring_id, 729 HTT_SRNG_SETUP_CMD_INFO0_RING_ID); 730 731 cmd->ring_base_addr_lo = cpu_to_le32(params.ring_base_paddr & 732 HAL_ADDR_LSB_REG_MASK); 733 734 cmd->ring_base_addr_hi = cpu_to_le32((u64)params.ring_base_paddr >> 735 HAL_ADDR_MSB_REG_SHIFT); 736 737 ret = ath12k_hal_srng_get_entrysize(ab, ring_type); 738 if (ret < 0) 739 goto err_free; 740 741 ring_entry_sz = ret; 742 743 ring_entry_sz >>= 2; 744 cmd->info1 = le32_encode_bits(ring_entry_sz, 745 HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE); 746 cmd->info1 |= le32_encode_bits(params.num_entries * ring_entry_sz, 747 HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE); 748 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP), 749 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP); 750 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP), 751 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP); 752 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP), 753 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP); 754 if (htt_ring_type == HTT_SW_TO_HW_RING) 755 cmd->info1 |= cpu_to_le32(HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS); 756 757 cmd->ring_head_off32_remote_addr_lo = cpu_to_le32(lower_32_bits(hp_addr)); 758 cmd->ring_head_off32_remote_addr_hi = cpu_to_le32(upper_32_bits(hp_addr)); 759 760 cmd->ring_tail_off32_remote_addr_lo = cpu_to_le32(lower_32_bits(tp_addr)); 761 cmd->ring_tail_off32_remote_addr_hi = cpu_to_le32(upper_32_bits(tp_addr)); 762 763 cmd->ring_msi_addr_lo = cpu_to_le32(lower_32_bits(params.msi_addr)); 764 cmd->ring_msi_addr_hi = cpu_to_le32(upper_32_bits(params.msi_addr)); 765 cmd->msi_data = cpu_to_le32(params.msi_data); 766 767 cmd->intr_info = 768 le32_encode_bits(params.intr_batch_cntr_thres_entries * ring_entry_sz, 769 HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH); 770 cmd->intr_info |= 771 le32_encode_bits(params.intr_timer_thres_us >> 3, 772 HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH); 773 774 cmd->info2 = 0; 775 if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) { 776 cmd->info2 = le32_encode_bits(params.low_threshold, 777 HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH); 778 } 779 780 ath12k_dbg(ab, ATH12K_DBG_HAL, 781 "%s msi_addr_lo:0x%x, msi_addr_hi:0x%x, msi_data:0x%x\n", 782 __func__, cmd->ring_msi_addr_lo, cmd->ring_msi_addr_hi, 783 cmd->msi_data); 784 785 ath12k_dbg(ab, ATH12K_DBG_HAL, 786 "ring_id:%d, ring_type:%d, intr_info:0x%x, flags:0x%x\n", 787 ring_id, ring_type, cmd->intr_info, cmd->info2); 788 789 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb); 790 if (ret) 791 goto err_free; 792 793 return 0; 794 795 err_free: 796 dev_kfree_skb_any(skb); 797 798 return ret; 799 } 800 801 #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ) 802 803 int ath12k_dp_tx_htt_h2t_ver_req_msg(struct ath12k_base *ab) 804 { 805 struct ath12k_dp *dp = &ab->dp; 806 struct sk_buff *skb; 807 struct htt_ver_req_cmd *cmd; 808 int len = sizeof(*cmd); 809 int ret; 810 811 init_completion(&dp->htt_tgt_version_received); 812 813 skb = ath12k_htc_alloc_skb(ab, len); 814 if (!skb) 815 return -ENOMEM; 816 817 skb_put(skb, len); 818 cmd = (struct htt_ver_req_cmd *)skb->data; 819 cmd->ver_reg_info = le32_encode_bits(HTT_H2T_MSG_TYPE_VERSION_REQ, 820 HTT_VER_REQ_INFO_MSG_ID); 821 822 ret = ath12k_htc_send(&ab->htc, dp->eid, skb); 823 if (ret) { 824 dev_kfree_skb_any(skb); 825 return ret; 826 } 827 828 ret = wait_for_completion_timeout(&dp->htt_tgt_version_received, 829 HTT_TARGET_VERSION_TIMEOUT_HZ); 830 if (ret == 0) { 831 ath12k_warn(ab, "htt target version request timed out\n"); 832 return -ETIMEDOUT; 833 } 834 835 if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) { 836 ath12k_err(ab, "unsupported htt major version %d supported version is %d\n", 837 dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR); 838 return -ENOTSUPP; 839 } 840 841 return 0; 842 } 843 844 int ath12k_dp_tx_htt_h2t_ppdu_stats_req(struct ath12k *ar, u32 mask) 845 { 846 struct ath12k_base *ab = ar->ab; 847 struct ath12k_dp *dp = &ab->dp; 848 struct sk_buff *skb; 849 struct htt_ppdu_stats_cfg_cmd *cmd; 850 int len = sizeof(*cmd); 851 u8 pdev_mask; 852 int ret; 853 int i; 854 855 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) { 856 skb = ath12k_htc_alloc_skb(ab, len); 857 if (!skb) 858 return -ENOMEM; 859 860 skb_put(skb, len); 861 cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data; 862 cmd->msg = le32_encode_bits(HTT_H2T_MSG_TYPE_PPDU_STATS_CFG, 863 HTT_PPDU_STATS_CFG_MSG_TYPE); 864 865 pdev_mask = 1 << (i + 1); 866 cmd->msg |= le32_encode_bits(pdev_mask, HTT_PPDU_STATS_CFG_PDEV_ID); 867 cmd->msg |= le32_encode_bits(mask, HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK); 868 869 ret = ath12k_htc_send(&ab->htc, dp->eid, skb); 870 if (ret) { 871 dev_kfree_skb_any(skb); 872 return ret; 873 } 874 } 875 876 return 0; 877 } 878 879 int ath12k_dp_tx_htt_rx_filter_setup(struct ath12k_base *ab, u32 ring_id, 880 int mac_id, enum hal_ring_type ring_type, 881 int rx_buf_size, 882 struct htt_rx_ring_tlv_filter *tlv_filter) 883 { 884 struct htt_rx_ring_selection_cfg_cmd *cmd; 885 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 886 struct hal_srng_params params; 887 struct sk_buff *skb; 888 int len = sizeof(*cmd); 889 enum htt_srng_ring_type htt_ring_type; 890 enum htt_srng_ring_id htt_ring_id; 891 int ret; 892 893 skb = ath12k_htc_alloc_skb(ab, len); 894 if (!skb) 895 return -ENOMEM; 896 897 memset(¶ms, 0, sizeof(params)); 898 ath12k_hal_srng_get_params(ab, srng, ¶ms); 899 900 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 901 ring_type, &htt_ring_type, 902 &htt_ring_id); 903 if (ret) 904 goto err_free; 905 906 skb_put(skb, len); 907 cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data; 908 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG, 909 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE); 910 if (htt_ring_type == HTT_SW_TO_HW_RING || 911 htt_ring_type == HTT_HW_TO_SW_RING) 912 cmd->info0 |= 913 le32_encode_bits(DP_SW2HW_MACID(mac_id), 914 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID); 915 else 916 cmd->info0 |= 917 le32_encode_bits(mac_id, 918 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID); 919 cmd->info0 |= le32_encode_bits(htt_ring_id, 920 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID); 921 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP), 922 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS); 923 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP), 924 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS); 925 cmd->info0 |= le32_encode_bits(tlv_filter->offset_valid, 926 HTT_RX_RING_SELECTION_CFG_CMD_OFFSET_VALID); 927 cmd->info1 = le32_encode_bits(rx_buf_size, 928 HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE); 929 cmd->pkt_type_en_flags0 = cpu_to_le32(tlv_filter->pkt_filter_flags0); 930 cmd->pkt_type_en_flags1 = cpu_to_le32(tlv_filter->pkt_filter_flags1); 931 cmd->pkt_type_en_flags2 = cpu_to_le32(tlv_filter->pkt_filter_flags2); 932 cmd->pkt_type_en_flags3 = cpu_to_le32(tlv_filter->pkt_filter_flags3); 933 cmd->rx_filter_tlv = cpu_to_le32(tlv_filter->rx_filter); 934 935 if (tlv_filter->offset_valid) { 936 cmd->rx_packet_offset = 937 le32_encode_bits(tlv_filter->rx_packet_offset, 938 HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET); 939 940 cmd->rx_packet_offset |= 941 le32_encode_bits(tlv_filter->rx_header_offset, 942 HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET); 943 944 cmd->rx_mpdu_offset = 945 le32_encode_bits(tlv_filter->rx_mpdu_end_offset, 946 HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET); 947 948 cmd->rx_mpdu_offset |= 949 le32_encode_bits(tlv_filter->rx_mpdu_start_offset, 950 HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET); 951 952 cmd->rx_msdu_offset = 953 le32_encode_bits(tlv_filter->rx_msdu_end_offset, 954 HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET); 955 956 cmd->rx_msdu_offset |= 957 le32_encode_bits(tlv_filter->rx_msdu_start_offset, 958 HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET); 959 960 cmd->rx_attn_offset = 961 le32_encode_bits(tlv_filter->rx_attn_offset, 962 HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET); 963 } 964 965 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb); 966 if (ret) 967 goto err_free; 968 969 return 0; 970 971 err_free: 972 dev_kfree_skb_any(skb); 973 974 return ret; 975 } 976 977 int 978 ath12k_dp_tx_htt_h2t_ext_stats_req(struct ath12k *ar, u8 type, 979 struct htt_ext_stats_cfg_params *cfg_params, 980 u64 cookie) 981 { 982 struct ath12k_base *ab = ar->ab; 983 struct ath12k_dp *dp = &ab->dp; 984 struct sk_buff *skb; 985 struct htt_ext_stats_cfg_cmd *cmd; 986 int len = sizeof(*cmd); 987 int ret; 988 989 skb = ath12k_htc_alloc_skb(ab, len); 990 if (!skb) 991 return -ENOMEM; 992 993 skb_put(skb, len); 994 995 cmd = (struct htt_ext_stats_cfg_cmd *)skb->data; 996 memset(cmd, 0, sizeof(*cmd)); 997 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG; 998 999 cmd->hdr.pdev_mask = 1 << ar->pdev->pdev_id; 1000 1001 cmd->hdr.stats_type = type; 1002 cmd->cfg_param0 = cpu_to_le32(cfg_params->cfg0); 1003 cmd->cfg_param1 = cpu_to_le32(cfg_params->cfg1); 1004 cmd->cfg_param2 = cpu_to_le32(cfg_params->cfg2); 1005 cmd->cfg_param3 = cpu_to_le32(cfg_params->cfg3); 1006 cmd->cookie_lsb = cpu_to_le32(lower_32_bits(cookie)); 1007 cmd->cookie_msb = cpu_to_le32(upper_32_bits(cookie)); 1008 1009 ret = ath12k_htc_send(&ab->htc, dp->eid, skb); 1010 if (ret) { 1011 ath12k_warn(ab, "failed to send htt type stats request: %d", 1012 ret); 1013 dev_kfree_skb_any(skb); 1014 return ret; 1015 } 1016 1017 return 0; 1018 } 1019 1020 int ath12k_dp_tx_htt_monitor_mode_ring_config(struct ath12k *ar, bool reset) 1021 { 1022 struct ath12k_base *ab = ar->ab; 1023 int ret; 1024 1025 ret = ath12k_dp_tx_htt_tx_monitor_mode_ring_config(ar, reset); 1026 if (ret) { 1027 ath12k_err(ab, "failed to setup tx monitor filter %d\n", ret); 1028 return ret; 1029 } 1030 1031 ret = ath12k_dp_tx_htt_tx_monitor_mode_ring_config(ar, reset); 1032 if (ret) { 1033 ath12k_err(ab, "failed to setup rx monitor filter %d\n", ret); 1034 return ret; 1035 } 1036 1037 return 0; 1038 } 1039 1040 int ath12k_dp_tx_htt_rx_monitor_mode_ring_config(struct ath12k *ar, bool reset) 1041 { 1042 struct ath12k_base *ab = ar->ab; 1043 struct ath12k_dp *dp = &ab->dp; 1044 struct htt_rx_ring_tlv_filter tlv_filter = {0}; 1045 int ret, ring_id; 1046 1047 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 1048 tlv_filter.offset_valid = false; 1049 1050 if (!reset) { 1051 tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING; 1052 tlv_filter.pkt_filter_flags0 = 1053 HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 | 1054 HTT_RX_MON_MO_MGMT_FILTER_FLAGS0; 1055 tlv_filter.pkt_filter_flags1 = 1056 HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 | 1057 HTT_RX_MON_MO_MGMT_FILTER_FLAGS1; 1058 tlv_filter.pkt_filter_flags2 = 1059 HTT_RX_MON_FP_CTRL_FILTER_FLASG2 | 1060 HTT_RX_MON_MO_CTRL_FILTER_FLASG2; 1061 tlv_filter.pkt_filter_flags3 = 1062 HTT_RX_MON_FP_CTRL_FILTER_FLASG3 | 1063 HTT_RX_MON_MO_CTRL_FILTER_FLASG3 | 1064 HTT_RX_MON_FP_DATA_FILTER_FLASG3 | 1065 HTT_RX_MON_MO_DATA_FILTER_FLASG3; 1066 } 1067 1068 if (ab->hw_params->rxdma1_enable) { 1069 ret = ath12k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, 0, 1070 HAL_RXDMA_MONITOR_BUF, 1071 DP_RXDMA_REFILL_RING_SIZE, 1072 &tlv_filter); 1073 if (ret) { 1074 ath12k_err(ab, 1075 "failed to setup filter for monitor buf %d\n", ret); 1076 return ret; 1077 } 1078 } 1079 1080 return 0; 1081 } 1082 1083 int ath12k_dp_tx_htt_tx_filter_setup(struct ath12k_base *ab, u32 ring_id, 1084 int mac_id, enum hal_ring_type ring_type, 1085 int tx_buf_size, 1086 struct htt_tx_ring_tlv_filter *htt_tlv_filter) 1087 { 1088 struct htt_tx_ring_selection_cfg_cmd *cmd; 1089 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 1090 struct hal_srng_params params; 1091 struct sk_buff *skb; 1092 int len = sizeof(*cmd); 1093 enum htt_srng_ring_type htt_ring_type; 1094 enum htt_srng_ring_id htt_ring_id; 1095 int ret; 1096 1097 skb = ath12k_htc_alloc_skb(ab, len); 1098 if (!skb) 1099 return -ENOMEM; 1100 1101 memset(¶ms, 0, sizeof(params)); 1102 ath12k_hal_srng_get_params(ab, srng, ¶ms); 1103 1104 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 1105 ring_type, &htt_ring_type, 1106 &htt_ring_id); 1107 1108 if (ret) 1109 goto err_free; 1110 1111 skb_put(skb, len); 1112 cmd = (struct htt_tx_ring_selection_cfg_cmd *)skb->data; 1113 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_TX_MONITOR_CFG, 1114 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE); 1115 if (htt_ring_type == HTT_SW_TO_HW_RING || 1116 htt_ring_type == HTT_HW_TO_SW_RING) 1117 cmd->info0 |= 1118 le32_encode_bits(DP_SW2HW_MACID(mac_id), 1119 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID); 1120 else 1121 cmd->info0 |= 1122 le32_encode_bits(mac_id, 1123 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID); 1124 cmd->info0 |= le32_encode_bits(htt_ring_id, 1125 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_RING_ID); 1126 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP), 1127 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_SS); 1128 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP), 1129 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PS); 1130 1131 cmd->info1 |= 1132 le32_encode_bits(tx_buf_size, 1133 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_RING_BUFF_SIZE); 1134 1135 if (htt_tlv_filter->tx_mon_mgmt_filter) { 1136 cmd->info1 |= 1137 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_MGMT, 1138 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE); 1139 cmd->info1 |= 1140 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len, 1141 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT); 1142 cmd->info2 |= 1143 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_MGMT, 1144 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG); 1145 } 1146 1147 if (htt_tlv_filter->tx_mon_data_filter) { 1148 cmd->info1 |= 1149 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_CTRL, 1150 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE); 1151 cmd->info1 |= 1152 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len, 1153 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL); 1154 cmd->info2 |= 1155 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_CTRL, 1156 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG); 1157 } 1158 1159 if (htt_tlv_filter->tx_mon_ctrl_filter) { 1160 cmd->info1 |= 1161 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_DATA, 1162 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE); 1163 cmd->info1 |= 1164 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len, 1165 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA); 1166 cmd->info2 |= 1167 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_DATA, 1168 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG); 1169 } 1170 1171 cmd->tlv_filter_mask_in0 = 1172 cpu_to_le32(htt_tlv_filter->tx_mon_downstream_tlv_flags); 1173 cmd->tlv_filter_mask_in1 = 1174 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags0); 1175 cmd->tlv_filter_mask_in2 = 1176 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags1); 1177 cmd->tlv_filter_mask_in3 = 1178 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags2); 1179 1180 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb); 1181 if (ret) 1182 goto err_free; 1183 1184 return 0; 1185 1186 err_free: 1187 dev_kfree_skb_any(skb); 1188 return ret; 1189 } 1190 1191 int ath12k_dp_tx_htt_tx_monitor_mode_ring_config(struct ath12k *ar, bool reset) 1192 { 1193 struct ath12k_base *ab = ar->ab; 1194 struct ath12k_dp *dp = &ab->dp; 1195 struct htt_tx_ring_tlv_filter tlv_filter = {0}; 1196 int ret, ring_id; 1197 1198 ring_id = dp->tx_mon_buf_ring.refill_buf_ring.ring_id; 1199 1200 /* TODO: Need to set upstream/downstream tlv filters 1201 * here 1202 */ 1203 1204 if (ab->hw_params->rxdma1_enable) { 1205 ret = ath12k_dp_tx_htt_tx_filter_setup(ar->ab, ring_id, 0, 1206 HAL_TX_MONITOR_BUF, 1207 DP_RXDMA_REFILL_RING_SIZE, 1208 &tlv_filter); 1209 if (ret) { 1210 ath12k_err(ab, 1211 "failed to setup filter for monitor buf %d\n", ret); 1212 return ret; 1213 } 1214 } 1215 1216 return 0; 1217 } 1218