1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3  * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4  * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
5  */
6 
7 #include "core.h"
8 #include "dp_tx.h"
9 #include "debug.h"
10 #include "hw.h"
11 
12 static enum hal_tcl_encap_type
13 ath12k_dp_tx_get_encap_type(struct ath12k_vif *arvif, struct sk_buff *skb)
14 {
15 	struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
16 	struct ath12k_base *ab = arvif->ar->ab;
17 
18 	if (test_bit(ATH12K_FLAG_RAW_MODE, &ab->dev_flags))
19 		return HAL_TCL_ENCAP_TYPE_RAW;
20 
21 	if (tx_info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP)
22 		return HAL_TCL_ENCAP_TYPE_ETHERNET;
23 
24 	return HAL_TCL_ENCAP_TYPE_NATIVE_WIFI;
25 }
26 
27 static void ath12k_dp_tx_encap_nwifi(struct sk_buff *skb)
28 {
29 	struct ieee80211_hdr *hdr = (void *)skb->data;
30 	u8 *qos_ctl;
31 
32 	if (!ieee80211_is_data_qos(hdr->frame_control))
33 		return;
34 
35 	qos_ctl = ieee80211_get_qos_ctl(hdr);
36 	memmove(skb->data + IEEE80211_QOS_CTL_LEN,
37 		skb->data, (void *)qos_ctl - (void *)skb->data);
38 	skb_pull(skb, IEEE80211_QOS_CTL_LEN);
39 
40 	hdr = (void *)skb->data;
41 	hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA);
42 }
43 
44 static u8 ath12k_dp_tx_get_tid(struct sk_buff *skb)
45 {
46 	struct ieee80211_hdr *hdr = (void *)skb->data;
47 	struct ath12k_skb_cb *cb = ATH12K_SKB_CB(skb);
48 
49 	if (cb->flags & ATH12K_SKB_HW_80211_ENCAP)
50 		return skb->priority & IEEE80211_QOS_CTL_TID_MASK;
51 	else if (!ieee80211_is_data_qos(hdr->frame_control))
52 		return HAL_DESC_REO_NON_QOS_TID;
53 	else
54 		return skb->priority & IEEE80211_QOS_CTL_TID_MASK;
55 }
56 
57 enum hal_encrypt_type ath12k_dp_tx_get_encrypt_type(u32 cipher)
58 {
59 	switch (cipher) {
60 	case WLAN_CIPHER_SUITE_WEP40:
61 		return HAL_ENCRYPT_TYPE_WEP_40;
62 	case WLAN_CIPHER_SUITE_WEP104:
63 		return HAL_ENCRYPT_TYPE_WEP_104;
64 	case WLAN_CIPHER_SUITE_TKIP:
65 		return HAL_ENCRYPT_TYPE_TKIP_MIC;
66 	case WLAN_CIPHER_SUITE_CCMP:
67 		return HAL_ENCRYPT_TYPE_CCMP_128;
68 	case WLAN_CIPHER_SUITE_CCMP_256:
69 		return HAL_ENCRYPT_TYPE_CCMP_256;
70 	case WLAN_CIPHER_SUITE_GCMP:
71 		return HAL_ENCRYPT_TYPE_GCMP_128;
72 	case WLAN_CIPHER_SUITE_GCMP_256:
73 		return HAL_ENCRYPT_TYPE_AES_GCMP_256;
74 	default:
75 		return HAL_ENCRYPT_TYPE_OPEN;
76 	}
77 }
78 
79 static void ath12k_dp_tx_release_txbuf(struct ath12k_dp *dp,
80 				       struct ath12k_tx_desc_info *tx_desc,
81 				       u8 pool_id)
82 {
83 	spin_lock_bh(&dp->tx_desc_lock[pool_id]);
84 	list_move_tail(&tx_desc->list, &dp->tx_desc_free_list[pool_id]);
85 	spin_unlock_bh(&dp->tx_desc_lock[pool_id]);
86 }
87 
88 static struct ath12k_tx_desc_info *ath12k_dp_tx_assign_buffer(struct ath12k_dp *dp,
89 							      u8 pool_id)
90 {
91 	struct ath12k_tx_desc_info *desc;
92 
93 	spin_lock_bh(&dp->tx_desc_lock[pool_id]);
94 	desc = list_first_entry_or_null(&dp->tx_desc_free_list[pool_id],
95 					struct ath12k_tx_desc_info,
96 					list);
97 	if (!desc) {
98 		spin_unlock_bh(&dp->tx_desc_lock[pool_id]);
99 		ath12k_warn(dp->ab, "failed to allocate data Tx buffer\n");
100 		return NULL;
101 	}
102 
103 	list_move_tail(&desc->list, &dp->tx_desc_used_list[pool_id]);
104 	spin_unlock_bh(&dp->tx_desc_lock[pool_id]);
105 
106 	return desc;
107 }
108 
109 static void ath12k_hal_tx_cmd_ext_desc_setup(struct ath12k_base *ab, void *cmd,
110 					     struct hal_tx_info *ti)
111 {
112 	struct hal_tx_msdu_ext_desc *tcl_ext_cmd = (struct hal_tx_msdu_ext_desc *)cmd;
113 
114 	tcl_ext_cmd->info0 = le32_encode_bits(ti->paddr,
115 					      HAL_TX_MSDU_EXT_INFO0_BUF_PTR_LO);
116 	tcl_ext_cmd->info1 = le32_encode_bits(0x0,
117 					      HAL_TX_MSDU_EXT_INFO1_BUF_PTR_HI) |
118 			       le32_encode_bits(ti->data_len,
119 						HAL_TX_MSDU_EXT_INFO1_BUF_LEN);
120 
121 	tcl_ext_cmd->info1 = le32_encode_bits(1, HAL_TX_MSDU_EXT_INFO1_EXTN_OVERRIDE) |
122 				le32_encode_bits(ti->encap_type,
123 						 HAL_TX_MSDU_EXT_INFO1_ENCAP_TYPE) |
124 				le32_encode_bits(ti->encrypt_type,
125 						 HAL_TX_MSDU_EXT_INFO1_ENCRYPT_TYPE);
126 }
127 
128 int ath12k_dp_tx(struct ath12k *ar, struct ath12k_vif *arvif,
129 		 struct sk_buff *skb)
130 {
131 	struct ath12k_base *ab = ar->ab;
132 	struct ath12k_dp *dp = &ab->dp;
133 	struct hal_tx_info ti = {0};
134 	struct ath12k_tx_desc_info *tx_desc;
135 	struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
136 	struct ath12k_skb_cb *skb_cb = ATH12K_SKB_CB(skb);
137 	struct hal_tcl_data_cmd *hal_tcl_desc;
138 	struct hal_tx_msdu_ext_desc *msg;
139 	struct sk_buff *skb_ext_desc;
140 	struct hal_srng *tcl_ring;
141 	struct ieee80211_hdr *hdr = (void *)skb->data;
142 	struct dp_tx_ring *tx_ring;
143 	u8 pool_id;
144 	u8 hal_ring_id;
145 	int ret;
146 	u8 ring_selector, ring_map = 0;
147 	bool tcl_ring_retry;
148 	bool msdu_ext_desc = false;
149 
150 	if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags))
151 		return -ESHUTDOWN;
152 
153 	if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) &&
154 	    !ieee80211_is_data(hdr->frame_control))
155 		return -ENOTSUPP;
156 
157 	pool_id = skb_get_queue_mapping(skb) & (ATH12K_HW_MAX_QUEUES - 1);
158 
159 	/* Let the default ring selection be based on current processor
160 	 * number, where one of the 3 tcl rings are selected based on
161 	 * the smp_processor_id(). In case that ring
162 	 * is full/busy, we resort to other available rings.
163 	 * If all rings are full, we drop the packet.
164 	 * TODO: Add throttling logic when all rings are full
165 	 */
166 	ring_selector = ab->hw_params->hw_ops->get_ring_selector(skb);
167 
168 tcl_ring_sel:
169 	tcl_ring_retry = false;
170 	ti.ring_id = ring_selector % ab->hw_params->max_tx_ring;
171 
172 	ring_map |= BIT(ti.ring_id);
173 	ti.rbm_id = ab->hw_params->hal_ops->tcl_to_wbm_rbm_map[ti.ring_id].rbm_id;
174 
175 	tx_ring = &dp->tx_ring[ti.ring_id];
176 
177 	tx_desc = ath12k_dp_tx_assign_buffer(dp, pool_id);
178 	if (!tx_desc)
179 		return -ENOMEM;
180 
181 	ti.bank_id = arvif->bank_id;
182 	ti.meta_data_flags = arvif->tcl_metadata;
183 
184 	if (arvif->tx_encap_type == HAL_TCL_ENCAP_TYPE_RAW &&
185 	    test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ar->ab->dev_flags)) {
186 		if (skb_cb->flags & ATH12K_SKB_CIPHER_SET) {
187 			ti.encrypt_type =
188 				ath12k_dp_tx_get_encrypt_type(skb_cb->cipher);
189 
190 			if (ieee80211_has_protected(hdr->frame_control))
191 				skb_put(skb, IEEE80211_CCMP_MIC_LEN);
192 		} else {
193 			ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN;
194 		}
195 
196 		msdu_ext_desc = true;
197 	}
198 
199 	ti.encap_type = ath12k_dp_tx_get_encap_type(arvif, skb);
200 	ti.addr_search_flags = arvif->hal_addr_search_flags;
201 	ti.search_type = arvif->search_type;
202 	ti.type = HAL_TCL_DESC_TYPE_BUFFER;
203 	ti.pkt_offset = 0;
204 	ti.lmac_id = ar->lmac_id;
205 	ti.vdev_id = arvif->vdev_id;
206 	ti.bss_ast_hash = arvif->ast_hash;
207 	ti.bss_ast_idx = arvif->ast_idx;
208 	ti.dscp_tid_tbl_idx = 0;
209 
210 	if (skb->ip_summed == CHECKSUM_PARTIAL &&
211 	    ti.encap_type != HAL_TCL_ENCAP_TYPE_RAW) {
212 		ti.flags0 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_IP4_CKSUM_EN) |
213 			     u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_UDP4_CKSUM_EN) |
214 			     u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_UDP6_CKSUM_EN) |
215 			     u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TCP4_CKSUM_EN) |
216 			     u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TCP6_CKSUM_EN);
217 	}
218 
219 	ti.flags1 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO3_TID_OVERWRITE);
220 
221 	ti.tid = ath12k_dp_tx_get_tid(skb);
222 
223 	switch (ti.encap_type) {
224 	case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI:
225 		ath12k_dp_tx_encap_nwifi(skb);
226 		break;
227 	case HAL_TCL_ENCAP_TYPE_RAW:
228 		if (!test_bit(ATH12K_FLAG_RAW_MODE, &ab->dev_flags)) {
229 			ret = -EINVAL;
230 			goto fail_remove_tx_buf;
231 		}
232 		break;
233 	case HAL_TCL_ENCAP_TYPE_ETHERNET:
234 		/* no need to encap */
235 		break;
236 	case HAL_TCL_ENCAP_TYPE_802_3:
237 	default:
238 		/* TODO: Take care of other encap modes as well */
239 		ret = -EINVAL;
240 		atomic_inc(&ab->soc_stats.tx_err.misc_fail);
241 		goto fail_remove_tx_buf;
242 	}
243 
244 	ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE);
245 	if (dma_mapping_error(ab->dev, ti.paddr)) {
246 		atomic_inc(&ab->soc_stats.tx_err.misc_fail);
247 		ath12k_warn(ab, "failed to DMA map data Tx buffer\n");
248 		ret = -ENOMEM;
249 		goto fail_remove_tx_buf;
250 	}
251 
252 	tx_desc->skb = skb;
253 	tx_desc->mac_id = ar->pdev_idx;
254 	ti.desc_id = tx_desc->desc_id;
255 	ti.data_len = skb->len;
256 	skb_cb->paddr = ti.paddr;
257 	skb_cb->vif = arvif->vif;
258 	skb_cb->ar = ar;
259 
260 	if (msdu_ext_desc) {
261 		skb_ext_desc = dev_alloc_skb(sizeof(struct hal_tx_msdu_ext_desc));
262 		if (!skb_ext_desc) {
263 			ret = -ENOMEM;
264 			goto fail_unmap_dma;
265 		}
266 
267 		skb_put(skb_ext_desc, sizeof(struct hal_tx_msdu_ext_desc));
268 		memset(skb_ext_desc->data, 0, skb_ext_desc->len);
269 
270 		msg = (struct hal_tx_msdu_ext_desc *)skb_ext_desc->data;
271 		ath12k_hal_tx_cmd_ext_desc_setup(ab, msg, &ti);
272 
273 		ti.paddr = dma_map_single(ab->dev, skb_ext_desc->data,
274 					  skb_ext_desc->len, DMA_TO_DEVICE);
275 		ret = dma_mapping_error(ab->dev, ti.paddr);
276 		if (ret) {
277 			kfree_skb(skb_ext_desc);
278 			goto fail_unmap_dma;
279 		}
280 
281 		ti.data_len = skb_ext_desc->len;
282 		ti.type = HAL_TCL_DESC_TYPE_EXT_DESC;
283 
284 		skb_cb->paddr_ext_desc = ti.paddr;
285 	}
286 
287 	hal_ring_id = tx_ring->tcl_data_ring.ring_id;
288 	tcl_ring = &ab->hal.srng_list[hal_ring_id];
289 
290 	spin_lock_bh(&tcl_ring->lock);
291 
292 	ath12k_hal_srng_access_begin(ab, tcl_ring);
293 
294 	hal_tcl_desc = ath12k_hal_srng_src_get_next_entry(ab, tcl_ring);
295 	if (!hal_tcl_desc) {
296 		/* NOTE: It is highly unlikely we'll be running out of tcl_ring
297 		 * desc because the desc is directly enqueued onto hw queue.
298 		 */
299 		ath12k_hal_srng_access_end(ab, tcl_ring);
300 		ab->soc_stats.tx_err.desc_na[ti.ring_id]++;
301 		spin_unlock_bh(&tcl_ring->lock);
302 		ret = -ENOMEM;
303 
304 		/* Checking for available tcl descriptors in another ring in
305 		 * case of failure due to full tcl ring now, is better than
306 		 * checking this ring earlier for each pkt tx.
307 		 * Restart ring selection if some rings are not checked yet.
308 		 */
309 		if (ring_map != (BIT(ab->hw_params->max_tx_ring) - 1) &&
310 		    ab->hw_params->tcl_ring_retry) {
311 			tcl_ring_retry = true;
312 			ring_selector++;
313 		}
314 
315 		goto fail_unmap_dma;
316 	}
317 
318 	ath12k_hal_tx_cmd_desc_setup(ab, hal_tcl_desc, &ti);
319 
320 	ath12k_hal_srng_access_end(ab, tcl_ring);
321 
322 	spin_unlock_bh(&tcl_ring->lock);
323 
324 	ath12k_dbg_dump(ab, ATH12K_DBG_DP_TX, NULL, "dp tx msdu: ",
325 			skb->data, skb->len);
326 
327 	atomic_inc(&ar->dp.num_tx_pending);
328 
329 	return 0;
330 
331 fail_unmap_dma:
332 	dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE);
333 
334 	if (skb_cb->paddr_ext_desc)
335 		dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc,
336 				 sizeof(struct hal_tx_msdu_ext_desc),
337 				 DMA_TO_DEVICE);
338 
339 fail_remove_tx_buf:
340 	ath12k_dp_tx_release_txbuf(dp, tx_desc, pool_id);
341 	if (tcl_ring_retry)
342 		goto tcl_ring_sel;
343 
344 	return ret;
345 }
346 
347 static void ath12k_dp_tx_free_txbuf(struct ath12k_base *ab,
348 				    struct sk_buff *msdu, u8 mac_id,
349 				    struct dp_tx_ring *tx_ring)
350 {
351 	struct ath12k *ar;
352 	struct ath12k_skb_cb *skb_cb;
353 	u8 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id);
354 
355 	skb_cb = ATH12K_SKB_CB(msdu);
356 
357 	dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
358 	if (skb_cb->paddr_ext_desc)
359 		dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc,
360 				 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE);
361 
362 	dev_kfree_skb_any(msdu);
363 
364 	ar = ab->pdevs[pdev_id].ar;
365 	if (atomic_dec_and_test(&ar->dp.num_tx_pending))
366 		wake_up(&ar->dp.tx_empty_waitq);
367 }
368 
369 static void
370 ath12k_dp_tx_htt_tx_complete_buf(struct ath12k_base *ab,
371 				 struct sk_buff *msdu,
372 				 struct dp_tx_ring *tx_ring,
373 				 struct ath12k_dp_htt_wbm_tx_status *ts)
374 {
375 	struct ieee80211_tx_info *info;
376 	struct ath12k_skb_cb *skb_cb;
377 	struct ath12k *ar;
378 
379 	skb_cb = ATH12K_SKB_CB(msdu);
380 	info = IEEE80211_SKB_CB(msdu);
381 
382 	ar = skb_cb->ar;
383 
384 	if (atomic_dec_and_test(&ar->dp.num_tx_pending))
385 		wake_up(&ar->dp.tx_empty_waitq);
386 
387 	dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
388 	if (skb_cb->paddr_ext_desc)
389 		dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc,
390 				 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE);
391 
392 	memset(&info->status, 0, sizeof(info->status));
393 
394 	if (ts->acked) {
395 		if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
396 			info->flags |= IEEE80211_TX_STAT_ACK;
397 			info->status.ack_signal = ATH12K_DEFAULT_NOISE_FLOOR +
398 						  ts->ack_rssi;
399 			info->status.flags = IEEE80211_TX_STATUS_ACK_SIGNAL_VALID;
400 		} else {
401 			info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
402 		}
403 	}
404 
405 	ieee80211_tx_status(ar->hw, msdu);
406 }
407 
408 static void
409 ath12k_dp_tx_process_htt_tx_complete(struct ath12k_base *ab,
410 				     void *desc, u8 mac_id,
411 				     struct sk_buff *msdu,
412 				     struct dp_tx_ring *tx_ring)
413 {
414 	struct htt_tx_wbm_completion *status_desc;
415 	struct ath12k_dp_htt_wbm_tx_status ts = {0};
416 	enum hal_wbm_htt_tx_comp_status wbm_status;
417 
418 	status_desc = desc + HTT_TX_WBM_COMP_STATUS_OFFSET;
419 
420 	wbm_status = le32_get_bits(status_desc->info0,
421 				   HTT_TX_WBM_COMP_INFO0_STATUS);
422 
423 	switch (wbm_status) {
424 	case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK:
425 	case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP:
426 	case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL:
427 		ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK);
428 		ts.ack_rssi = le32_get_bits(status_desc->info2,
429 					    HTT_TX_WBM_COMP_INFO2_ACK_RSSI);
430 		ath12k_dp_tx_htt_tx_complete_buf(ab, msdu, tx_ring, &ts);
431 		break;
432 	case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ:
433 	case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT:
434 		ath12k_dp_tx_free_txbuf(ab, msdu, mac_id, tx_ring);
435 		break;
436 	case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY:
437 		/* This event is to be handled only when the driver decides to
438 		 * use WDS offload functionality.
439 		 */
440 		break;
441 	default:
442 		ath12k_warn(ab, "Unknown htt tx status %d\n", wbm_status);
443 		break;
444 	}
445 }
446 
447 static void ath12k_dp_tx_complete_msdu(struct ath12k *ar,
448 				       struct sk_buff *msdu,
449 				       struct hal_tx_status *ts)
450 {
451 	struct ath12k_base *ab = ar->ab;
452 	struct ieee80211_tx_info *info;
453 	struct ath12k_skb_cb *skb_cb;
454 
455 	if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) {
456 		/* Must not happen */
457 		return;
458 	}
459 
460 	skb_cb = ATH12K_SKB_CB(msdu);
461 
462 	dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE);
463 	if (skb_cb->paddr_ext_desc)
464 		dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc,
465 				 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE);
466 
467 	rcu_read_lock();
468 
469 	if (!rcu_dereference(ab->pdevs_active[ar->pdev_idx])) {
470 		dev_kfree_skb_any(msdu);
471 		goto exit;
472 	}
473 
474 	if (!skb_cb->vif) {
475 		dev_kfree_skb_any(msdu);
476 		goto exit;
477 	}
478 
479 	info = IEEE80211_SKB_CB(msdu);
480 	memset(&info->status, 0, sizeof(info->status));
481 
482 	/* skip tx rate update from ieee80211_status*/
483 	info->status.rates[0].idx = -1;
484 
485 	if (ts->status == HAL_WBM_TQM_REL_REASON_FRAME_ACKED &&
486 	    !(info->flags & IEEE80211_TX_CTL_NO_ACK)) {
487 		info->flags |= IEEE80211_TX_STAT_ACK;
488 		info->status.ack_signal = ATH12K_DEFAULT_NOISE_FLOOR +
489 					  ts->ack_rssi;
490 		info->status.flags = IEEE80211_TX_STATUS_ACK_SIGNAL_VALID;
491 	}
492 
493 	if (ts->status == HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX &&
494 	    (info->flags & IEEE80211_TX_CTL_NO_ACK))
495 		info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED;
496 
497 	/* NOTE: Tx rate status reporting. Tx completion status does not have
498 	 * necessary information (for example nss) to build the tx rate.
499 	 * Might end up reporting it out-of-band from HTT stats.
500 	 */
501 
502 	ieee80211_tx_status(ar->hw, msdu);
503 
504 exit:
505 	rcu_read_unlock();
506 }
507 
508 static void ath12k_dp_tx_status_parse(struct ath12k_base *ab,
509 				      struct hal_wbm_completion_ring_tx *desc,
510 				      struct hal_tx_status *ts)
511 {
512 	ts->buf_rel_source =
513 		le32_get_bits(desc->info0, HAL_WBM_COMPL_TX_INFO0_REL_SRC_MODULE);
514 	if (ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW &&
515 	    ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)
516 		return;
517 
518 	if (ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW)
519 		return;
520 
521 	ts->status = le32_get_bits(desc->info0,
522 				   HAL_WBM_COMPL_TX_INFO0_TQM_RELEASE_REASON);
523 
524 	ts->ppdu_id = le32_get_bits(desc->info1,
525 				    HAL_WBM_COMPL_TX_INFO1_TQM_STATUS_NUMBER);
526 	if (le32_to_cpu(desc->rate_stats.info0) & HAL_TX_RATE_STATS_INFO0_VALID)
527 		ts->rate_stats = le32_to_cpu(desc->rate_stats.info0);
528 	else
529 		ts->rate_stats = 0;
530 }
531 
532 void ath12k_dp_tx_completion_handler(struct ath12k_base *ab, int ring_id)
533 {
534 	struct ath12k *ar;
535 	struct ath12k_dp *dp = &ab->dp;
536 	int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id;
537 	struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id];
538 	struct ath12k_tx_desc_info *tx_desc = NULL;
539 	struct sk_buff *msdu;
540 	struct hal_tx_status ts = { 0 };
541 	struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id];
542 	struct hal_wbm_release_ring *desc;
543 	u8 mac_id, pdev_id;
544 	u64 desc_va;
545 
546 	spin_lock_bh(&status_ring->lock);
547 
548 	ath12k_hal_srng_access_begin(ab, status_ring);
549 
550 	while (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head) != tx_ring->tx_status_tail) {
551 		desc = ath12k_hal_srng_dst_get_next_entry(ab, status_ring);
552 		if (!desc)
553 			break;
554 
555 		memcpy(&tx_ring->tx_status[tx_ring->tx_status_head],
556 		       desc, sizeof(*desc));
557 		tx_ring->tx_status_head =
558 			ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head);
559 	}
560 
561 	if (ath12k_hal_srng_dst_peek(ab, status_ring) &&
562 	    (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head) == tx_ring->tx_status_tail)) {
563 		/* TODO: Process pending tx_status messages when kfifo_is_full() */
564 		ath12k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n");
565 	}
566 
567 	ath12k_hal_srng_access_end(ab, status_ring);
568 
569 	spin_unlock_bh(&status_ring->lock);
570 
571 	while (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_tail) != tx_ring->tx_status_head) {
572 		struct hal_wbm_completion_ring_tx *tx_status;
573 		u32 desc_id;
574 
575 		tx_ring->tx_status_tail =
576 			ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_tail);
577 		tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail];
578 		ath12k_dp_tx_status_parse(ab, tx_status, &ts);
579 
580 		if (le32_get_bits(tx_status->info0, HAL_WBM_COMPL_TX_INFO0_CC_DONE)) {
581 			/* HW done cookie conversion */
582 			desc_va = ((u64)le32_to_cpu(tx_status->buf_va_hi) << 32 |
583 				   le32_to_cpu(tx_status->buf_va_lo));
584 			tx_desc = (struct ath12k_tx_desc_info *)((unsigned long)desc_va);
585 		} else {
586 			/* SW does cookie conversion to VA */
587 			desc_id = le32_get_bits(tx_status->buf_va_hi,
588 						BUFFER_ADDR_INFO1_SW_COOKIE);
589 
590 			tx_desc = ath12k_dp_get_tx_desc(ab, desc_id);
591 		}
592 		if (!tx_desc) {
593 			ath12k_warn(ab, "unable to retrieve tx_desc!");
594 			continue;
595 		}
596 
597 		msdu = tx_desc->skb;
598 		mac_id = tx_desc->mac_id;
599 
600 		/* Release descriptor as soon as extracting necessary info
601 		 * to reduce contention
602 		 */
603 		ath12k_dp_tx_release_txbuf(dp, tx_desc, tx_desc->pool_id);
604 		if (ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) {
605 			ath12k_dp_tx_process_htt_tx_complete(ab,
606 							     (void *)tx_status,
607 							     mac_id, msdu,
608 							     tx_ring);
609 			continue;
610 		}
611 
612 		pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id);
613 		ar = ab->pdevs[pdev_id].ar;
614 
615 		if (atomic_dec_and_test(&ar->dp.num_tx_pending))
616 			wake_up(&ar->dp.tx_empty_waitq);
617 
618 		ath12k_dp_tx_complete_msdu(ar, msdu, &ts);
619 	}
620 }
621 
622 static int
623 ath12k_dp_tx_get_ring_id_type(struct ath12k_base *ab,
624 			      int mac_id, u32 ring_id,
625 			      enum hal_ring_type ring_type,
626 			      enum htt_srng_ring_type *htt_ring_type,
627 			      enum htt_srng_ring_id *htt_ring_id)
628 {
629 	int ret = 0;
630 
631 	switch (ring_type) {
632 	case HAL_RXDMA_BUF:
633 		/* for some targets, host fills rx buffer to fw and fw fills to
634 		 * rxbuf ring for each rxdma
635 		 */
636 		if (!ab->hw_params->rx_mac_buf_ring) {
637 			if (!(ring_id == HAL_SRNG_SW2RXDMA_BUF0 ||
638 			      ring_id == HAL_SRNG_SW2RXDMA_BUF1)) {
639 				ret = -EINVAL;
640 			}
641 			*htt_ring_id = HTT_RXDMA_HOST_BUF_RING;
642 			*htt_ring_type = HTT_SW_TO_HW_RING;
643 		} else {
644 			if (ring_id == HAL_SRNG_SW2RXDMA_BUF0) {
645 				*htt_ring_id = HTT_HOST1_TO_FW_RXBUF_RING;
646 				*htt_ring_type = HTT_SW_TO_SW_RING;
647 			} else {
648 				*htt_ring_id = HTT_RXDMA_HOST_BUF_RING;
649 				*htt_ring_type = HTT_SW_TO_HW_RING;
650 			}
651 		}
652 		break;
653 	case HAL_RXDMA_DST:
654 		*htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING;
655 		*htt_ring_type = HTT_HW_TO_SW_RING;
656 		break;
657 	case HAL_RXDMA_MONITOR_BUF:
658 		*htt_ring_id = HTT_RXDMA_MONITOR_BUF_RING;
659 		*htt_ring_type = HTT_SW_TO_HW_RING;
660 		break;
661 	case HAL_RXDMA_MONITOR_STATUS:
662 		*htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING;
663 		*htt_ring_type = HTT_SW_TO_HW_RING;
664 		break;
665 	case HAL_RXDMA_MONITOR_DST:
666 		*htt_ring_id = HTT_RXDMA_MONITOR_DEST_RING;
667 		*htt_ring_type = HTT_HW_TO_SW_RING;
668 		break;
669 	case HAL_RXDMA_MONITOR_DESC:
670 		*htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING;
671 		*htt_ring_type = HTT_SW_TO_HW_RING;
672 		break;
673 	case HAL_TX_MONITOR_BUF:
674 		*htt_ring_id = HTT_TX_MON_HOST2MON_BUF_RING;
675 		*htt_ring_type = HTT_SW_TO_HW_RING;
676 		break;
677 	case HAL_TX_MONITOR_DST:
678 		*htt_ring_id = HTT_TX_MON_MON2HOST_DEST_RING;
679 		*htt_ring_type = HTT_HW_TO_SW_RING;
680 		break;
681 	default:
682 		ath12k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type);
683 		ret = -EINVAL;
684 	}
685 	return ret;
686 }
687 
688 int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id,
689 				int mac_id, enum hal_ring_type ring_type)
690 {
691 	struct htt_srng_setup_cmd *cmd;
692 	struct hal_srng *srng = &ab->hal.srng_list[ring_id];
693 	struct hal_srng_params params;
694 	struct sk_buff *skb;
695 	u32 ring_entry_sz;
696 	int len = sizeof(*cmd);
697 	dma_addr_t hp_addr, tp_addr;
698 	enum htt_srng_ring_type htt_ring_type;
699 	enum htt_srng_ring_id htt_ring_id;
700 	int ret;
701 
702 	skb = ath12k_htc_alloc_skb(ab, len);
703 	if (!skb)
704 		return -ENOMEM;
705 
706 	memset(&params, 0, sizeof(params));
707 	ath12k_hal_srng_get_params(ab, srng, &params);
708 
709 	hp_addr = ath12k_hal_srng_get_hp_addr(ab, srng);
710 	tp_addr = ath12k_hal_srng_get_tp_addr(ab, srng);
711 
712 	ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,
713 					    ring_type, &htt_ring_type,
714 					    &htt_ring_id);
715 	if (ret)
716 		goto err_free;
717 
718 	skb_put(skb, len);
719 	cmd = (struct htt_srng_setup_cmd *)skb->data;
720 	cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_SRING_SETUP,
721 				      HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE);
722 	if (htt_ring_type == HTT_SW_TO_HW_RING ||
723 	    htt_ring_type == HTT_HW_TO_SW_RING)
724 		cmd->info0 |= le32_encode_bits(DP_SW2HW_MACID(mac_id),
725 					       HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID);
726 	else
727 		cmd->info0 |= le32_encode_bits(mac_id,
728 					       HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID);
729 	cmd->info0 |= le32_encode_bits(htt_ring_type,
730 				       HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE);
731 	cmd->info0 |= le32_encode_bits(htt_ring_id,
732 				       HTT_SRNG_SETUP_CMD_INFO0_RING_ID);
733 
734 	cmd->ring_base_addr_lo = cpu_to_le32(params.ring_base_paddr &
735 					     HAL_ADDR_LSB_REG_MASK);
736 
737 	cmd->ring_base_addr_hi = cpu_to_le32((u64)params.ring_base_paddr >>
738 					     HAL_ADDR_MSB_REG_SHIFT);
739 
740 	ret = ath12k_hal_srng_get_entrysize(ab, ring_type);
741 	if (ret < 0)
742 		goto err_free;
743 
744 	ring_entry_sz = ret;
745 
746 	ring_entry_sz >>= 2;
747 	cmd->info1 = le32_encode_bits(ring_entry_sz,
748 				      HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE);
749 	cmd->info1 |= le32_encode_bits(params.num_entries * ring_entry_sz,
750 				       HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE);
751 	cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP),
752 				       HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP);
753 	cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP),
754 				       HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP);
755 	cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP),
756 				       HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP);
757 	if (htt_ring_type == HTT_SW_TO_HW_RING)
758 		cmd->info1 |= cpu_to_le32(HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS);
759 
760 	cmd->ring_head_off32_remote_addr_lo = cpu_to_le32(lower_32_bits(hp_addr));
761 	cmd->ring_head_off32_remote_addr_hi = cpu_to_le32(upper_32_bits(hp_addr));
762 
763 	cmd->ring_tail_off32_remote_addr_lo = cpu_to_le32(lower_32_bits(tp_addr));
764 	cmd->ring_tail_off32_remote_addr_hi = cpu_to_le32(upper_32_bits(tp_addr));
765 
766 	cmd->ring_msi_addr_lo = cpu_to_le32(lower_32_bits(params.msi_addr));
767 	cmd->ring_msi_addr_hi = cpu_to_le32(upper_32_bits(params.msi_addr));
768 	cmd->msi_data = cpu_to_le32(params.msi_data);
769 
770 	cmd->intr_info =
771 		le32_encode_bits(params.intr_batch_cntr_thres_entries * ring_entry_sz,
772 				 HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH);
773 	cmd->intr_info |=
774 		le32_encode_bits(params.intr_timer_thres_us >> 3,
775 				 HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH);
776 
777 	cmd->info2 = 0;
778 	if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) {
779 		cmd->info2 = le32_encode_bits(params.low_threshold,
780 					      HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH);
781 	}
782 
783 	ath12k_dbg(ab, ATH12K_DBG_HAL,
784 		   "%s msi_addr_lo:0x%x, msi_addr_hi:0x%x, msi_data:0x%x\n",
785 		   __func__, cmd->ring_msi_addr_lo, cmd->ring_msi_addr_hi,
786 		   cmd->msi_data);
787 
788 	ath12k_dbg(ab, ATH12K_DBG_HAL,
789 		   "ring_id:%d, ring_type:%d, intr_info:0x%x, flags:0x%x\n",
790 		   ring_id, ring_type, cmd->intr_info, cmd->info2);
791 
792 	ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb);
793 	if (ret)
794 		goto err_free;
795 
796 	return 0;
797 
798 err_free:
799 	dev_kfree_skb_any(skb);
800 
801 	return ret;
802 }
803 
804 #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ)
805 
806 int ath12k_dp_tx_htt_h2t_ver_req_msg(struct ath12k_base *ab)
807 {
808 	struct ath12k_dp *dp = &ab->dp;
809 	struct sk_buff *skb;
810 	struct htt_ver_req_cmd *cmd;
811 	int len = sizeof(*cmd);
812 	int ret;
813 
814 	init_completion(&dp->htt_tgt_version_received);
815 
816 	skb = ath12k_htc_alloc_skb(ab, len);
817 	if (!skb)
818 		return -ENOMEM;
819 
820 	skb_put(skb, len);
821 	cmd = (struct htt_ver_req_cmd *)skb->data;
822 	cmd->ver_reg_info = le32_encode_bits(HTT_H2T_MSG_TYPE_VERSION_REQ,
823 					     HTT_VER_REQ_INFO_MSG_ID);
824 
825 	ret = ath12k_htc_send(&ab->htc, dp->eid, skb);
826 	if (ret) {
827 		dev_kfree_skb_any(skb);
828 		return ret;
829 	}
830 
831 	ret = wait_for_completion_timeout(&dp->htt_tgt_version_received,
832 					  HTT_TARGET_VERSION_TIMEOUT_HZ);
833 	if (ret == 0) {
834 		ath12k_warn(ab, "htt target version request timed out\n");
835 		return -ETIMEDOUT;
836 	}
837 
838 	if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) {
839 		ath12k_err(ab, "unsupported htt major version %d supported version is %d\n",
840 			   dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR);
841 		return -ENOTSUPP;
842 	}
843 
844 	return 0;
845 }
846 
847 int ath12k_dp_tx_htt_h2t_ppdu_stats_req(struct ath12k *ar, u32 mask)
848 {
849 	struct ath12k_base *ab = ar->ab;
850 	struct ath12k_dp *dp = &ab->dp;
851 	struct sk_buff *skb;
852 	struct htt_ppdu_stats_cfg_cmd *cmd;
853 	int len = sizeof(*cmd);
854 	u8 pdev_mask;
855 	int ret;
856 	int i;
857 
858 	for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) {
859 		skb = ath12k_htc_alloc_skb(ab, len);
860 		if (!skb)
861 			return -ENOMEM;
862 
863 		skb_put(skb, len);
864 		cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data;
865 		cmd->msg = le32_encode_bits(HTT_H2T_MSG_TYPE_PPDU_STATS_CFG,
866 					    HTT_PPDU_STATS_CFG_MSG_TYPE);
867 
868 		pdev_mask = 1 << (i + 1);
869 		cmd->msg |= le32_encode_bits(pdev_mask, HTT_PPDU_STATS_CFG_PDEV_ID);
870 		cmd->msg |= le32_encode_bits(mask, HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK);
871 
872 		ret = ath12k_htc_send(&ab->htc, dp->eid, skb);
873 		if (ret) {
874 			dev_kfree_skb_any(skb);
875 			return ret;
876 		}
877 	}
878 
879 	return 0;
880 }
881 
882 int ath12k_dp_tx_htt_rx_filter_setup(struct ath12k_base *ab, u32 ring_id,
883 				     int mac_id, enum hal_ring_type ring_type,
884 				     int rx_buf_size,
885 				     struct htt_rx_ring_tlv_filter *tlv_filter)
886 {
887 	struct htt_rx_ring_selection_cfg_cmd *cmd;
888 	struct hal_srng *srng = &ab->hal.srng_list[ring_id];
889 	struct hal_srng_params params;
890 	struct sk_buff *skb;
891 	int len = sizeof(*cmd);
892 	enum htt_srng_ring_type htt_ring_type;
893 	enum htt_srng_ring_id htt_ring_id;
894 	int ret;
895 
896 	skb = ath12k_htc_alloc_skb(ab, len);
897 	if (!skb)
898 		return -ENOMEM;
899 
900 	memset(&params, 0, sizeof(params));
901 	ath12k_hal_srng_get_params(ab, srng, &params);
902 
903 	ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,
904 					    ring_type, &htt_ring_type,
905 					    &htt_ring_id);
906 	if (ret)
907 		goto err_free;
908 
909 	skb_put(skb, len);
910 	cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data;
911 	cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG,
912 				      HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE);
913 	if (htt_ring_type == HTT_SW_TO_HW_RING ||
914 	    htt_ring_type == HTT_HW_TO_SW_RING)
915 		cmd->info0 |=
916 			le32_encode_bits(DP_SW2HW_MACID(mac_id),
917 					 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID);
918 	else
919 		cmd->info0 |=
920 			le32_encode_bits(mac_id,
921 					 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID);
922 	cmd->info0 |= le32_encode_bits(htt_ring_id,
923 				       HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID);
924 	cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP),
925 				       HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS);
926 	cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP),
927 				       HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS);
928 	cmd->info0 |= le32_encode_bits(tlv_filter->offset_valid,
929 				       HTT_RX_RING_SELECTION_CFG_CMD_OFFSET_VALID);
930 	cmd->info1 = le32_encode_bits(rx_buf_size,
931 				      HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE);
932 	cmd->pkt_type_en_flags0 = cpu_to_le32(tlv_filter->pkt_filter_flags0);
933 	cmd->pkt_type_en_flags1 = cpu_to_le32(tlv_filter->pkt_filter_flags1);
934 	cmd->pkt_type_en_flags2 = cpu_to_le32(tlv_filter->pkt_filter_flags2);
935 	cmd->pkt_type_en_flags3 = cpu_to_le32(tlv_filter->pkt_filter_flags3);
936 	cmd->rx_filter_tlv = cpu_to_le32(tlv_filter->rx_filter);
937 
938 	if (tlv_filter->offset_valid) {
939 		cmd->rx_packet_offset =
940 			le32_encode_bits(tlv_filter->rx_packet_offset,
941 					 HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET);
942 
943 		cmd->rx_packet_offset |=
944 			le32_encode_bits(tlv_filter->rx_header_offset,
945 					 HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET);
946 
947 		cmd->rx_mpdu_offset =
948 			le32_encode_bits(tlv_filter->rx_mpdu_end_offset,
949 					 HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET);
950 
951 		cmd->rx_mpdu_offset |=
952 			le32_encode_bits(tlv_filter->rx_mpdu_start_offset,
953 					 HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET);
954 
955 		cmd->rx_msdu_offset =
956 			le32_encode_bits(tlv_filter->rx_msdu_end_offset,
957 					 HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET);
958 
959 		cmd->rx_msdu_offset |=
960 			le32_encode_bits(tlv_filter->rx_msdu_start_offset,
961 					 HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET);
962 
963 		cmd->rx_attn_offset =
964 			le32_encode_bits(tlv_filter->rx_attn_offset,
965 					 HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET);
966 	}
967 
968 	ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb);
969 	if (ret)
970 		goto err_free;
971 
972 	return 0;
973 
974 err_free:
975 	dev_kfree_skb_any(skb);
976 
977 	return ret;
978 }
979 
980 int
981 ath12k_dp_tx_htt_h2t_ext_stats_req(struct ath12k *ar, u8 type,
982 				   struct htt_ext_stats_cfg_params *cfg_params,
983 				   u64 cookie)
984 {
985 	struct ath12k_base *ab = ar->ab;
986 	struct ath12k_dp *dp = &ab->dp;
987 	struct sk_buff *skb;
988 	struct htt_ext_stats_cfg_cmd *cmd;
989 	int len = sizeof(*cmd);
990 	int ret;
991 
992 	skb = ath12k_htc_alloc_skb(ab, len);
993 	if (!skb)
994 		return -ENOMEM;
995 
996 	skb_put(skb, len);
997 
998 	cmd = (struct htt_ext_stats_cfg_cmd *)skb->data;
999 	memset(cmd, 0, sizeof(*cmd));
1000 	cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG;
1001 
1002 	cmd->hdr.pdev_mask = 1 << ar->pdev->pdev_id;
1003 
1004 	cmd->hdr.stats_type = type;
1005 	cmd->cfg_param0 = cpu_to_le32(cfg_params->cfg0);
1006 	cmd->cfg_param1 = cpu_to_le32(cfg_params->cfg1);
1007 	cmd->cfg_param2 = cpu_to_le32(cfg_params->cfg2);
1008 	cmd->cfg_param3 = cpu_to_le32(cfg_params->cfg3);
1009 	cmd->cookie_lsb = cpu_to_le32(lower_32_bits(cookie));
1010 	cmd->cookie_msb = cpu_to_le32(upper_32_bits(cookie));
1011 
1012 	ret = ath12k_htc_send(&ab->htc, dp->eid, skb);
1013 	if (ret) {
1014 		ath12k_warn(ab, "failed to send htt type stats request: %d",
1015 			    ret);
1016 		dev_kfree_skb_any(skb);
1017 		return ret;
1018 	}
1019 
1020 	return 0;
1021 }
1022 
1023 int ath12k_dp_tx_htt_monitor_mode_ring_config(struct ath12k *ar, bool reset)
1024 {
1025 	struct ath12k_base *ab = ar->ab;
1026 	int ret;
1027 
1028 	ret = ath12k_dp_tx_htt_tx_monitor_mode_ring_config(ar, reset);
1029 	if (ret) {
1030 		ath12k_err(ab, "failed to setup tx monitor filter %d\n", ret);
1031 		return ret;
1032 	}
1033 
1034 	ret = ath12k_dp_tx_htt_tx_monitor_mode_ring_config(ar, reset);
1035 	if (ret) {
1036 		ath12k_err(ab, "failed to setup rx monitor filter %d\n", ret);
1037 		return ret;
1038 	}
1039 
1040 	return 0;
1041 }
1042 
1043 int ath12k_dp_tx_htt_rx_monitor_mode_ring_config(struct ath12k *ar, bool reset)
1044 {
1045 	struct ath12k_base *ab = ar->ab;
1046 	struct ath12k_dp *dp = &ab->dp;
1047 	struct htt_rx_ring_tlv_filter tlv_filter = {0};
1048 	int ret, ring_id;
1049 
1050 	ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id;
1051 	tlv_filter.offset_valid = false;
1052 
1053 	if (!reset) {
1054 		tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING;
1055 		tlv_filter.pkt_filter_flags0 =
1056 					HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 |
1057 					HTT_RX_MON_MO_MGMT_FILTER_FLAGS0;
1058 		tlv_filter.pkt_filter_flags1 =
1059 					HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 |
1060 					HTT_RX_MON_MO_MGMT_FILTER_FLAGS1;
1061 		tlv_filter.pkt_filter_flags2 =
1062 					HTT_RX_MON_FP_CTRL_FILTER_FLASG2 |
1063 					HTT_RX_MON_MO_CTRL_FILTER_FLASG2;
1064 		tlv_filter.pkt_filter_flags3 =
1065 					HTT_RX_MON_FP_CTRL_FILTER_FLASG3 |
1066 					HTT_RX_MON_MO_CTRL_FILTER_FLASG3 |
1067 					HTT_RX_MON_FP_DATA_FILTER_FLASG3 |
1068 					HTT_RX_MON_MO_DATA_FILTER_FLASG3;
1069 	}
1070 
1071 	if (ab->hw_params->rxdma1_enable) {
1072 		ret = ath12k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, 0,
1073 						       HAL_RXDMA_MONITOR_BUF,
1074 						       DP_RXDMA_REFILL_RING_SIZE,
1075 						       &tlv_filter);
1076 		if (ret) {
1077 			ath12k_err(ab,
1078 				   "failed to setup filter for monitor buf %d\n", ret);
1079 			return ret;
1080 		}
1081 	}
1082 
1083 	return 0;
1084 }
1085 
1086 int ath12k_dp_tx_htt_tx_filter_setup(struct ath12k_base *ab, u32 ring_id,
1087 				     int mac_id, enum hal_ring_type ring_type,
1088 				     int tx_buf_size,
1089 				     struct htt_tx_ring_tlv_filter *htt_tlv_filter)
1090 {
1091 	struct htt_tx_ring_selection_cfg_cmd *cmd;
1092 	struct hal_srng *srng = &ab->hal.srng_list[ring_id];
1093 	struct hal_srng_params params;
1094 	struct sk_buff *skb;
1095 	int len = sizeof(*cmd);
1096 	enum htt_srng_ring_type htt_ring_type;
1097 	enum htt_srng_ring_id htt_ring_id;
1098 	int ret;
1099 
1100 	skb = ath12k_htc_alloc_skb(ab, len);
1101 	if (!skb)
1102 		return -ENOMEM;
1103 
1104 	memset(&params, 0, sizeof(params));
1105 	ath12k_hal_srng_get_params(ab, srng, &params);
1106 
1107 	ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id,
1108 					    ring_type, &htt_ring_type,
1109 					    &htt_ring_id);
1110 
1111 	if (ret)
1112 		goto err_free;
1113 
1114 	skb_put(skb, len);
1115 	cmd = (struct htt_tx_ring_selection_cfg_cmd *)skb->data;
1116 	cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_TX_MONITOR_CFG,
1117 				      HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE);
1118 	if (htt_ring_type == HTT_SW_TO_HW_RING ||
1119 	    htt_ring_type == HTT_HW_TO_SW_RING)
1120 		cmd->info0 |=
1121 			le32_encode_bits(DP_SW2HW_MACID(mac_id),
1122 					 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID);
1123 	else
1124 		cmd->info0 |=
1125 			le32_encode_bits(mac_id,
1126 					 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID);
1127 	cmd->info0 |= le32_encode_bits(htt_ring_id,
1128 				       HTT_TX_RING_SELECTION_CFG_CMD_INFO0_RING_ID);
1129 	cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP),
1130 				       HTT_TX_RING_SELECTION_CFG_CMD_INFO0_SS);
1131 	cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP),
1132 				       HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PS);
1133 
1134 	cmd->info1 |=
1135 		le32_encode_bits(tx_buf_size,
1136 				 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_RING_BUFF_SIZE);
1137 
1138 	if (htt_tlv_filter->tx_mon_mgmt_filter) {
1139 		cmd->info1 |=
1140 			le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_MGMT,
1141 					 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE);
1142 		cmd->info1 |=
1143 		le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len,
1144 				 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT);
1145 		cmd->info2 |=
1146 		le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_MGMT,
1147 				 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG);
1148 	}
1149 
1150 	if (htt_tlv_filter->tx_mon_data_filter) {
1151 		cmd->info1 |=
1152 			le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_CTRL,
1153 					 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE);
1154 		cmd->info1 |=
1155 		le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len,
1156 				 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL);
1157 		cmd->info2 |=
1158 		le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_CTRL,
1159 				 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG);
1160 	}
1161 
1162 	if (htt_tlv_filter->tx_mon_ctrl_filter) {
1163 		cmd->info1 |=
1164 			le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_DATA,
1165 					 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE);
1166 		cmd->info1 |=
1167 		le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len,
1168 				 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA);
1169 		cmd->info2 |=
1170 		le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_DATA,
1171 				 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG);
1172 	}
1173 
1174 	cmd->tlv_filter_mask_in0 =
1175 		cpu_to_le32(htt_tlv_filter->tx_mon_downstream_tlv_flags);
1176 	cmd->tlv_filter_mask_in1 =
1177 		cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags0);
1178 	cmd->tlv_filter_mask_in2 =
1179 		cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags1);
1180 	cmd->tlv_filter_mask_in3 =
1181 		cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags2);
1182 
1183 	ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb);
1184 	if (ret)
1185 		goto err_free;
1186 
1187 	return 0;
1188 
1189 err_free:
1190 	dev_kfree_skb_any(skb);
1191 	return ret;
1192 }
1193 
1194 int ath12k_dp_tx_htt_tx_monitor_mode_ring_config(struct ath12k *ar, bool reset)
1195 {
1196 	struct ath12k_base *ab = ar->ab;
1197 	struct ath12k_dp *dp = &ab->dp;
1198 	struct htt_tx_ring_tlv_filter tlv_filter = {0};
1199 	int ret, ring_id;
1200 
1201 	ring_id = dp->tx_mon_buf_ring.refill_buf_ring.ring_id;
1202 
1203 	/* TODO: Need to set upstream/downstream tlv filters
1204 	 * here
1205 	 */
1206 
1207 	if (ab->hw_params->rxdma1_enable) {
1208 		ret = ath12k_dp_tx_htt_tx_filter_setup(ar->ab, ring_id, 0,
1209 						       HAL_TX_MONITOR_BUF,
1210 						       DP_RXDMA_REFILL_RING_SIZE,
1211 						       &tlv_filter);
1212 		if (ret) {
1213 			ath12k_err(ab,
1214 				   "failed to setup filter for monitor buf %d\n", ret);
1215 			return ret;
1216 		}
1217 	}
1218 
1219 	return 0;
1220 }
1221