1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include "core.h" 8 #include "dp_tx.h" 9 #include "debug.h" 10 #include "hw.h" 11 12 static enum hal_tcl_encap_type 13 ath12k_dp_tx_get_encap_type(struct ath12k_vif *arvif, struct sk_buff *skb) 14 { 15 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); 16 17 if (tx_info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) 18 return HAL_TCL_ENCAP_TYPE_ETHERNET; 19 20 return HAL_TCL_ENCAP_TYPE_NATIVE_WIFI; 21 } 22 23 static void ath12k_dp_tx_encap_nwifi(struct sk_buff *skb) 24 { 25 struct ieee80211_hdr *hdr = (void *)skb->data; 26 u8 *qos_ctl; 27 28 if (!ieee80211_is_data_qos(hdr->frame_control)) 29 return; 30 31 qos_ctl = ieee80211_get_qos_ctl(hdr); 32 memmove(skb->data + IEEE80211_QOS_CTL_LEN, 33 skb->data, (void *)qos_ctl - (void *)skb->data); 34 skb_pull(skb, IEEE80211_QOS_CTL_LEN); 35 36 hdr = (void *)skb->data; 37 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 38 } 39 40 static u8 ath12k_dp_tx_get_tid(struct sk_buff *skb) 41 { 42 struct ieee80211_hdr *hdr = (void *)skb->data; 43 struct ath12k_skb_cb *cb = ATH12K_SKB_CB(skb); 44 45 if (cb->flags & ATH12K_SKB_HW_80211_ENCAP) 46 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 47 else if (!ieee80211_is_data_qos(hdr->frame_control)) 48 return HAL_DESC_REO_NON_QOS_TID; 49 else 50 return skb->priority & IEEE80211_QOS_CTL_TID_MASK; 51 } 52 53 enum hal_encrypt_type ath12k_dp_tx_get_encrypt_type(u32 cipher) 54 { 55 switch (cipher) { 56 case WLAN_CIPHER_SUITE_WEP40: 57 return HAL_ENCRYPT_TYPE_WEP_40; 58 case WLAN_CIPHER_SUITE_WEP104: 59 return HAL_ENCRYPT_TYPE_WEP_104; 60 case WLAN_CIPHER_SUITE_TKIP: 61 return HAL_ENCRYPT_TYPE_TKIP_MIC; 62 case WLAN_CIPHER_SUITE_CCMP: 63 return HAL_ENCRYPT_TYPE_CCMP_128; 64 case WLAN_CIPHER_SUITE_CCMP_256: 65 return HAL_ENCRYPT_TYPE_CCMP_256; 66 case WLAN_CIPHER_SUITE_GCMP: 67 return HAL_ENCRYPT_TYPE_GCMP_128; 68 case WLAN_CIPHER_SUITE_GCMP_256: 69 return HAL_ENCRYPT_TYPE_AES_GCMP_256; 70 default: 71 return HAL_ENCRYPT_TYPE_OPEN; 72 } 73 } 74 75 static void ath12k_dp_tx_release_txbuf(struct ath12k_dp *dp, 76 struct ath12k_tx_desc_info *tx_desc, 77 u8 pool_id) 78 { 79 spin_lock_bh(&dp->tx_desc_lock[pool_id]); 80 list_move_tail(&tx_desc->list, &dp->tx_desc_free_list[pool_id]); 81 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 82 } 83 84 static struct ath12k_tx_desc_info *ath12k_dp_tx_assign_buffer(struct ath12k_dp *dp, 85 u8 pool_id) 86 { 87 struct ath12k_tx_desc_info *desc; 88 89 spin_lock_bh(&dp->tx_desc_lock[pool_id]); 90 desc = list_first_entry_or_null(&dp->tx_desc_free_list[pool_id], 91 struct ath12k_tx_desc_info, 92 list); 93 if (!desc) { 94 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 95 ath12k_warn(dp->ab, "failed to allocate data Tx buffer\n"); 96 return NULL; 97 } 98 99 list_move_tail(&desc->list, &dp->tx_desc_used_list[pool_id]); 100 spin_unlock_bh(&dp->tx_desc_lock[pool_id]); 101 102 return desc; 103 } 104 105 static void ath12k_hal_tx_cmd_ext_desc_setup(struct ath12k_base *ab, void *cmd, 106 struct hal_tx_info *ti) 107 { 108 struct hal_tx_msdu_ext_desc *tcl_ext_cmd = (struct hal_tx_msdu_ext_desc *)cmd; 109 110 tcl_ext_cmd->info0 = le32_encode_bits(ti->paddr, 111 HAL_TX_MSDU_EXT_INFO0_BUF_PTR_LO); 112 tcl_ext_cmd->info1 = le32_encode_bits(0x0, 113 HAL_TX_MSDU_EXT_INFO1_BUF_PTR_HI) | 114 le32_encode_bits(ti->data_len, 115 HAL_TX_MSDU_EXT_INFO1_BUF_LEN); 116 117 tcl_ext_cmd->info1 = le32_encode_bits(1, HAL_TX_MSDU_EXT_INFO1_EXTN_OVERRIDE) | 118 le32_encode_bits(ti->encap_type, 119 HAL_TX_MSDU_EXT_INFO1_ENCAP_TYPE) | 120 le32_encode_bits(ti->encrypt_type, 121 HAL_TX_MSDU_EXT_INFO1_ENCRYPT_TYPE); 122 } 123 124 int ath12k_dp_tx(struct ath12k *ar, struct ath12k_vif *arvif, 125 struct sk_buff *skb) 126 { 127 struct ath12k_base *ab = ar->ab; 128 struct ath12k_dp *dp = &ab->dp; 129 struct hal_tx_info ti = {0}; 130 struct ath12k_tx_desc_info *tx_desc; 131 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 132 struct ath12k_skb_cb *skb_cb = ATH12K_SKB_CB(skb); 133 struct hal_tcl_data_cmd *hal_tcl_desc; 134 struct hal_tx_msdu_ext_desc *msg; 135 struct sk_buff *skb_ext_desc; 136 struct hal_srng *tcl_ring; 137 struct ieee80211_hdr *hdr = (void *)skb->data; 138 struct dp_tx_ring *tx_ring; 139 u8 pool_id; 140 u8 hal_ring_id; 141 int ret; 142 u8 ring_selector, ring_map = 0; 143 bool tcl_ring_retry; 144 bool msdu_ext_desc = false; 145 146 if (test_bit(ATH12K_FLAG_CRASH_FLUSH, &ar->ab->dev_flags)) 147 return -ESHUTDOWN; 148 149 if (!(info->flags & IEEE80211_TX_CTL_HW_80211_ENCAP) && 150 !ieee80211_is_data(hdr->frame_control)) 151 return -ENOTSUPP; 152 153 pool_id = skb_get_queue_mapping(skb) & (ATH12K_HW_MAX_QUEUES - 1); 154 155 /* Let the default ring selection be based on current processor 156 * number, where one of the 3 tcl rings are selected based on 157 * the smp_processor_id(). In case that ring 158 * is full/busy, we resort to other available rings. 159 * If all rings are full, we drop the packet. 160 * TODO: Add throttling logic when all rings are full 161 */ 162 ring_selector = ab->hw_params->hw_ops->get_ring_selector(skb); 163 164 tcl_ring_sel: 165 tcl_ring_retry = false; 166 ti.ring_id = ring_selector % ab->hw_params->max_tx_ring; 167 168 ring_map |= BIT(ti.ring_id); 169 ti.rbm_id = ab->hw_params->hal_ops->tcl_to_wbm_rbm_map[ti.ring_id].rbm_id; 170 171 tx_ring = &dp->tx_ring[ti.ring_id]; 172 173 tx_desc = ath12k_dp_tx_assign_buffer(dp, pool_id); 174 if (!tx_desc) 175 return -ENOMEM; 176 177 ti.bank_id = arvif->bank_id; 178 ti.meta_data_flags = arvif->tcl_metadata; 179 180 if (arvif->tx_encap_type == HAL_TCL_ENCAP_TYPE_RAW && 181 test_bit(ATH12K_FLAG_HW_CRYPTO_DISABLED, &ar->ab->dev_flags)) { 182 if (skb_cb->flags & ATH12K_SKB_CIPHER_SET) { 183 ti.encrypt_type = 184 ath12k_dp_tx_get_encrypt_type(skb_cb->cipher); 185 186 if (ieee80211_has_protected(hdr->frame_control)) 187 skb_put(skb, IEEE80211_CCMP_MIC_LEN); 188 } else { 189 ti.encrypt_type = HAL_ENCRYPT_TYPE_OPEN; 190 } 191 192 msdu_ext_desc = true; 193 } 194 195 ti.encap_type = ath12k_dp_tx_get_encap_type(arvif, skb); 196 ti.addr_search_flags = arvif->hal_addr_search_flags; 197 ti.search_type = arvif->search_type; 198 ti.type = HAL_TCL_DESC_TYPE_BUFFER; 199 ti.pkt_offset = 0; 200 ti.lmac_id = ar->lmac_id; 201 ti.vdev_id = arvif->vdev_id; 202 ti.bss_ast_hash = arvif->ast_hash; 203 ti.bss_ast_idx = arvif->ast_idx; 204 ti.dscp_tid_tbl_idx = 0; 205 206 if (skb->ip_summed == CHECKSUM_PARTIAL && 207 ti.encap_type != HAL_TCL_ENCAP_TYPE_RAW) { 208 ti.flags0 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_IP4_CKSUM_EN) | 209 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_UDP4_CKSUM_EN) | 210 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_UDP6_CKSUM_EN) | 211 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TCP4_CKSUM_EN) | 212 u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO2_TCP6_CKSUM_EN); 213 } 214 215 ti.flags1 |= u32_encode_bits(1, HAL_TCL_DATA_CMD_INFO3_TID_OVERWRITE); 216 217 ti.tid = ath12k_dp_tx_get_tid(skb); 218 219 switch (ti.encap_type) { 220 case HAL_TCL_ENCAP_TYPE_NATIVE_WIFI: 221 ath12k_dp_tx_encap_nwifi(skb); 222 break; 223 case HAL_TCL_ENCAP_TYPE_RAW: 224 if (!test_bit(ATH12K_FLAG_RAW_MODE, &ab->dev_flags)) { 225 ret = -EINVAL; 226 goto fail_remove_tx_buf; 227 } 228 break; 229 case HAL_TCL_ENCAP_TYPE_ETHERNET: 230 /* no need to encap */ 231 break; 232 case HAL_TCL_ENCAP_TYPE_802_3: 233 default: 234 /* TODO: Take care of other encap modes as well */ 235 ret = -EINVAL; 236 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 237 goto fail_remove_tx_buf; 238 } 239 240 ti.paddr = dma_map_single(ab->dev, skb->data, skb->len, DMA_TO_DEVICE); 241 if (dma_mapping_error(ab->dev, ti.paddr)) { 242 atomic_inc(&ab->soc_stats.tx_err.misc_fail); 243 ath12k_warn(ab, "failed to DMA map data Tx buffer\n"); 244 ret = -ENOMEM; 245 goto fail_remove_tx_buf; 246 } 247 248 tx_desc->skb = skb; 249 tx_desc->mac_id = ar->pdev_idx; 250 ti.desc_id = tx_desc->desc_id; 251 ti.data_len = skb->len; 252 skb_cb->paddr = ti.paddr; 253 skb_cb->vif = arvif->vif; 254 skb_cb->ar = ar; 255 256 if (msdu_ext_desc) { 257 skb_ext_desc = dev_alloc_skb(sizeof(struct hal_tx_msdu_ext_desc)); 258 if (!skb_ext_desc) { 259 ret = -ENOMEM; 260 goto fail_unmap_dma; 261 } 262 263 skb_put(skb_ext_desc, sizeof(struct hal_tx_msdu_ext_desc)); 264 memset(skb_ext_desc->data, 0, skb_ext_desc->len); 265 266 msg = (struct hal_tx_msdu_ext_desc *)skb_ext_desc->data; 267 ath12k_hal_tx_cmd_ext_desc_setup(ab, msg, &ti); 268 269 ti.paddr = dma_map_single(ab->dev, skb_ext_desc->data, 270 skb_ext_desc->len, DMA_TO_DEVICE); 271 ret = dma_mapping_error(ab->dev, ti.paddr); 272 if (ret) { 273 kfree(skb_ext_desc); 274 goto fail_unmap_dma; 275 } 276 277 ti.data_len = skb_ext_desc->len; 278 ti.type = HAL_TCL_DESC_TYPE_EXT_DESC; 279 280 skb_cb->paddr_ext_desc = ti.paddr; 281 } 282 283 hal_ring_id = tx_ring->tcl_data_ring.ring_id; 284 tcl_ring = &ab->hal.srng_list[hal_ring_id]; 285 286 spin_lock_bh(&tcl_ring->lock); 287 288 ath12k_hal_srng_access_begin(ab, tcl_ring); 289 290 hal_tcl_desc = ath12k_hal_srng_src_get_next_entry(ab, tcl_ring); 291 if (!hal_tcl_desc) { 292 /* NOTE: It is highly unlikely we'll be running out of tcl_ring 293 * desc because the desc is directly enqueued onto hw queue. 294 */ 295 ath12k_hal_srng_access_end(ab, tcl_ring); 296 ab->soc_stats.tx_err.desc_na[ti.ring_id]++; 297 spin_unlock_bh(&tcl_ring->lock); 298 ret = -ENOMEM; 299 300 /* Checking for available tcl descritors in another ring in 301 * case of failure due to full tcl ring now, is better than 302 * checking this ring earlier for each pkt tx. 303 * Restart ring selection if some rings are not checked yet. 304 */ 305 if (ring_map != (BIT(ab->hw_params->max_tx_ring) - 1) && 306 ab->hw_params->tcl_ring_retry) { 307 tcl_ring_retry = true; 308 ring_selector++; 309 } 310 311 goto fail_unmap_dma; 312 } 313 314 ath12k_hal_tx_cmd_desc_setup(ab, hal_tcl_desc, &ti); 315 316 ath12k_hal_srng_access_end(ab, tcl_ring); 317 318 spin_unlock_bh(&tcl_ring->lock); 319 320 ath12k_dbg_dump(ab, ATH12K_DBG_DP_TX, NULL, "dp tx msdu: ", 321 skb->data, skb->len); 322 323 atomic_inc(&ar->dp.num_tx_pending); 324 325 return 0; 326 327 fail_unmap_dma: 328 dma_unmap_single(ab->dev, ti.paddr, ti.data_len, DMA_TO_DEVICE); 329 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, 330 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE); 331 332 fail_remove_tx_buf: 333 ath12k_dp_tx_release_txbuf(dp, tx_desc, pool_id); 334 if (tcl_ring_retry) 335 goto tcl_ring_sel; 336 337 return ret; 338 } 339 340 static void ath12k_dp_tx_free_txbuf(struct ath12k_base *ab, 341 struct sk_buff *msdu, u8 mac_id, 342 struct dp_tx_ring *tx_ring) 343 { 344 struct ath12k *ar; 345 struct ath12k_skb_cb *skb_cb; 346 347 skb_cb = ATH12K_SKB_CB(msdu); 348 349 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 350 if (skb_cb->paddr_ext_desc) 351 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, 352 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE); 353 354 dev_kfree_skb_any(msdu); 355 356 ar = ab->pdevs[mac_id].ar; 357 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 358 wake_up(&ar->dp.tx_empty_waitq); 359 } 360 361 static void 362 ath12k_dp_tx_htt_tx_complete_buf(struct ath12k_base *ab, 363 struct sk_buff *msdu, 364 struct dp_tx_ring *tx_ring, 365 struct ath12k_dp_htt_wbm_tx_status *ts) 366 { 367 struct ieee80211_tx_info *info; 368 struct ath12k_skb_cb *skb_cb; 369 struct ath12k *ar; 370 371 skb_cb = ATH12K_SKB_CB(msdu); 372 info = IEEE80211_SKB_CB(msdu); 373 374 ar = skb_cb->ar; 375 376 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 377 wake_up(&ar->dp.tx_empty_waitq); 378 379 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 380 if (skb_cb->paddr_ext_desc) 381 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, 382 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE); 383 384 memset(&info->status, 0, sizeof(info->status)); 385 386 if (ts->acked) { 387 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 388 info->flags |= IEEE80211_TX_STAT_ACK; 389 info->status.ack_signal = ATH12K_DEFAULT_NOISE_FLOOR + 390 ts->ack_rssi; 391 info->status.flags = IEEE80211_TX_STATUS_ACK_SIGNAL_VALID; 392 } else { 393 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 394 } 395 } 396 397 ieee80211_tx_status(ar->hw, msdu); 398 } 399 400 static void 401 ath12k_dp_tx_process_htt_tx_complete(struct ath12k_base *ab, 402 void *desc, u8 mac_id, 403 struct sk_buff *msdu, 404 struct dp_tx_ring *tx_ring) 405 { 406 struct htt_tx_wbm_completion *status_desc; 407 struct ath12k_dp_htt_wbm_tx_status ts = {0}; 408 enum hal_wbm_htt_tx_comp_status wbm_status; 409 410 status_desc = desc + HTT_TX_WBM_COMP_STATUS_OFFSET; 411 412 wbm_status = le32_get_bits(status_desc->info0, 413 HTT_TX_WBM_COMP_INFO0_STATUS); 414 415 switch (wbm_status) { 416 case HAL_WBM_REL_HTT_TX_COMP_STATUS_OK: 417 case HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP: 418 case HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL: 419 ts.acked = (wbm_status == HAL_WBM_REL_HTT_TX_COMP_STATUS_OK); 420 ts.ack_rssi = le32_get_bits(status_desc->info2, 421 HTT_TX_WBM_COMP_INFO2_ACK_RSSI); 422 ath12k_dp_tx_htt_tx_complete_buf(ab, msdu, tx_ring, &ts); 423 break; 424 case HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ: 425 case HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT: 426 ath12k_dp_tx_free_txbuf(ab, msdu, mac_id, tx_ring); 427 break; 428 case HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY: 429 /* This event is to be handled only when the driver decides to 430 * use WDS offload functionality. 431 */ 432 break; 433 default: 434 ath12k_warn(ab, "Unknown htt tx status %d\n", wbm_status); 435 break; 436 } 437 } 438 439 static void ath12k_dp_tx_complete_msdu(struct ath12k *ar, 440 struct sk_buff *msdu, 441 struct hal_tx_status *ts) 442 { 443 struct ath12k_base *ab = ar->ab; 444 struct ieee80211_tx_info *info; 445 struct ath12k_skb_cb *skb_cb; 446 447 if (WARN_ON_ONCE(ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM)) { 448 /* Must not happen */ 449 return; 450 } 451 452 skb_cb = ATH12K_SKB_CB(msdu); 453 454 dma_unmap_single(ab->dev, skb_cb->paddr, msdu->len, DMA_TO_DEVICE); 455 if (skb_cb->paddr_ext_desc) 456 dma_unmap_single(ab->dev, skb_cb->paddr_ext_desc, 457 sizeof(struct hal_tx_msdu_ext_desc), DMA_TO_DEVICE); 458 459 rcu_read_lock(); 460 461 if (!rcu_dereference(ab->pdevs_active[ar->pdev_idx])) { 462 dev_kfree_skb_any(msdu); 463 goto exit; 464 } 465 466 if (!skb_cb->vif) { 467 dev_kfree_skb_any(msdu); 468 goto exit; 469 } 470 471 info = IEEE80211_SKB_CB(msdu); 472 memset(&info->status, 0, sizeof(info->status)); 473 474 /* skip tx rate update from ieee80211_status*/ 475 info->status.rates[0].idx = -1; 476 477 if (ts->status == HAL_WBM_TQM_REL_REASON_FRAME_ACKED && 478 !(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 479 info->flags |= IEEE80211_TX_STAT_ACK; 480 info->status.ack_signal = ATH12K_DEFAULT_NOISE_FLOOR + 481 ts->ack_rssi; 482 info->status.flags = IEEE80211_TX_STATUS_ACK_SIGNAL_VALID; 483 } 484 485 if (ts->status == HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX && 486 (info->flags & IEEE80211_TX_CTL_NO_ACK)) 487 info->flags |= IEEE80211_TX_STAT_NOACK_TRANSMITTED; 488 489 /* NOTE: Tx rate status reporting. Tx completion status does not have 490 * necessary information (for example nss) to build the tx rate. 491 * Might end up reporting it out-of-band from HTT stats. 492 */ 493 494 ieee80211_tx_status(ar->hw, msdu); 495 496 exit: 497 rcu_read_unlock(); 498 } 499 500 static void ath12k_dp_tx_status_parse(struct ath12k_base *ab, 501 struct hal_wbm_completion_ring_tx *desc, 502 struct hal_tx_status *ts) 503 { 504 ts->buf_rel_source = 505 le32_get_bits(desc->info0, HAL_WBM_COMPL_TX_INFO0_REL_SRC_MODULE); 506 if (ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW && 507 ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM) 508 return; 509 510 if (ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) 511 return; 512 513 ts->status = le32_get_bits(desc->info0, 514 HAL_WBM_COMPL_TX_INFO0_TQM_RELEASE_REASON); 515 516 ts->ppdu_id = le32_get_bits(desc->info1, 517 HAL_WBM_COMPL_TX_INFO1_TQM_STATUS_NUMBER); 518 if (le32_to_cpu(desc->rate_stats.info0) & HAL_TX_RATE_STATS_INFO0_VALID) 519 ts->rate_stats = le32_to_cpu(desc->rate_stats.info0); 520 else 521 ts->rate_stats = 0; 522 } 523 524 void ath12k_dp_tx_completion_handler(struct ath12k_base *ab, int ring_id) 525 { 526 struct ath12k *ar; 527 struct ath12k_dp *dp = &ab->dp; 528 int hal_ring_id = dp->tx_ring[ring_id].tcl_comp_ring.ring_id; 529 struct hal_srng *status_ring = &ab->hal.srng_list[hal_ring_id]; 530 struct ath12k_tx_desc_info *tx_desc = NULL; 531 struct sk_buff *msdu; 532 struct hal_tx_status ts = { 0 }; 533 struct dp_tx_ring *tx_ring = &dp->tx_ring[ring_id]; 534 struct hal_wbm_release_ring *desc; 535 u8 mac_id; 536 u64 desc_va; 537 538 spin_lock_bh(&status_ring->lock); 539 540 ath12k_hal_srng_access_begin(ab, status_ring); 541 542 while (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head) != tx_ring->tx_status_tail) { 543 desc = ath12k_hal_srng_dst_get_next_entry(ab, status_ring); 544 if (!desc) 545 break; 546 547 memcpy(&tx_ring->tx_status[tx_ring->tx_status_head], 548 desc, sizeof(*desc)); 549 tx_ring->tx_status_head = 550 ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head); 551 } 552 553 if (ath12k_hal_srng_dst_peek(ab, status_ring) && 554 (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_head) == tx_ring->tx_status_tail)) { 555 /* TODO: Process pending tx_status messages when kfifo_is_full() */ 556 ath12k_warn(ab, "Unable to process some of the tx_status ring desc because status_fifo is full\n"); 557 } 558 559 ath12k_hal_srng_access_end(ab, status_ring); 560 561 spin_unlock_bh(&status_ring->lock); 562 563 while (ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_tail) != tx_ring->tx_status_head) { 564 struct hal_wbm_completion_ring_tx *tx_status; 565 u32 desc_id; 566 567 tx_ring->tx_status_tail = 568 ATH12K_TX_COMPL_NEXT(tx_ring->tx_status_tail); 569 tx_status = &tx_ring->tx_status[tx_ring->tx_status_tail]; 570 ath12k_dp_tx_status_parse(ab, tx_status, &ts); 571 572 if (le32_get_bits(tx_status->info0, HAL_WBM_COMPL_TX_INFO0_CC_DONE)) { 573 /* HW done cookie conversion */ 574 desc_va = ((u64)le32_to_cpu(tx_status->buf_va_hi) << 32 | 575 le32_to_cpu(tx_status->buf_va_lo)); 576 tx_desc = (struct ath12k_tx_desc_info *)((unsigned long)desc_va); 577 } else { 578 /* SW does cookie conversion to VA */ 579 desc_id = le32_get_bits(tx_status->buf_va_hi, 580 BUFFER_ADDR_INFO1_SW_COOKIE); 581 582 tx_desc = ath12k_dp_get_tx_desc(ab, desc_id); 583 } 584 if (!tx_desc) { 585 ath12k_warn(ab, "unable to retrieve tx_desc!"); 586 continue; 587 } 588 589 msdu = tx_desc->skb; 590 mac_id = tx_desc->mac_id; 591 592 /* Release descriptor as soon as extracting necessary info 593 * to reduce contention 594 */ 595 ath12k_dp_tx_release_txbuf(dp, tx_desc, tx_desc->pool_id); 596 if (ts.buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) { 597 ath12k_dp_tx_process_htt_tx_complete(ab, 598 (void *)tx_status, 599 mac_id, msdu, 600 tx_ring); 601 continue; 602 } 603 604 ar = ab->pdevs[mac_id].ar; 605 606 if (atomic_dec_and_test(&ar->dp.num_tx_pending)) 607 wake_up(&ar->dp.tx_empty_waitq); 608 609 ath12k_dp_tx_complete_msdu(ar, msdu, &ts); 610 } 611 } 612 613 static int 614 ath12k_dp_tx_get_ring_id_type(struct ath12k_base *ab, 615 int mac_id, u32 ring_id, 616 enum hal_ring_type ring_type, 617 enum htt_srng_ring_type *htt_ring_type, 618 enum htt_srng_ring_id *htt_ring_id) 619 { 620 int ret = 0; 621 622 switch (ring_type) { 623 case HAL_RXDMA_BUF: 624 /* for some targets, host fills rx buffer to fw and fw fills to 625 * rxbuf ring for each rxdma 626 */ 627 if (!ab->hw_params->rx_mac_buf_ring) { 628 if (!(ring_id == HAL_SRNG_SW2RXDMA_BUF0 || 629 ring_id == HAL_SRNG_SW2RXDMA_BUF1)) { 630 ret = -EINVAL; 631 } 632 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 633 *htt_ring_type = HTT_SW_TO_HW_RING; 634 } else { 635 if (ring_id == HAL_SRNG_SW2RXDMA_BUF0) { 636 *htt_ring_id = HTT_HOST1_TO_FW_RXBUF_RING; 637 *htt_ring_type = HTT_SW_TO_SW_RING; 638 } else { 639 *htt_ring_id = HTT_RXDMA_HOST_BUF_RING; 640 *htt_ring_type = HTT_SW_TO_HW_RING; 641 } 642 } 643 break; 644 case HAL_RXDMA_DST: 645 *htt_ring_id = HTT_RXDMA_NON_MONITOR_DEST_RING; 646 *htt_ring_type = HTT_HW_TO_SW_RING; 647 break; 648 case HAL_RXDMA_MONITOR_BUF: 649 *htt_ring_id = HTT_RXDMA_MONITOR_BUF_RING; 650 *htt_ring_type = HTT_SW_TO_HW_RING; 651 break; 652 case HAL_RXDMA_MONITOR_STATUS: 653 *htt_ring_id = HTT_RXDMA_MONITOR_STATUS_RING; 654 *htt_ring_type = HTT_SW_TO_HW_RING; 655 break; 656 case HAL_RXDMA_MONITOR_DST: 657 *htt_ring_id = HTT_RXDMA_MONITOR_DEST_RING; 658 *htt_ring_type = HTT_HW_TO_SW_RING; 659 break; 660 case HAL_RXDMA_MONITOR_DESC: 661 *htt_ring_id = HTT_RXDMA_MONITOR_DESC_RING; 662 *htt_ring_type = HTT_SW_TO_HW_RING; 663 break; 664 case HAL_TX_MONITOR_BUF: 665 *htt_ring_id = HTT_TX_MON_HOST2MON_BUF_RING; 666 *htt_ring_type = HTT_SW_TO_HW_RING; 667 break; 668 case HAL_TX_MONITOR_DST: 669 *htt_ring_id = HTT_TX_MON_MON2HOST_DEST_RING; 670 *htt_ring_type = HTT_HW_TO_SW_RING; 671 break; 672 default: 673 ath12k_warn(ab, "Unsupported ring type in DP :%d\n", ring_type); 674 ret = -EINVAL; 675 } 676 return ret; 677 } 678 679 int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id, 680 int mac_id, enum hal_ring_type ring_type) 681 { 682 struct htt_srng_setup_cmd *cmd; 683 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 684 struct hal_srng_params params; 685 struct sk_buff *skb; 686 u32 ring_entry_sz; 687 int len = sizeof(*cmd); 688 dma_addr_t hp_addr, tp_addr; 689 enum htt_srng_ring_type htt_ring_type; 690 enum htt_srng_ring_id htt_ring_id; 691 int ret; 692 693 skb = ath12k_htc_alloc_skb(ab, len); 694 if (!skb) 695 return -ENOMEM; 696 697 memset(¶ms, 0, sizeof(params)); 698 ath12k_hal_srng_get_params(ab, srng, ¶ms); 699 700 hp_addr = ath12k_hal_srng_get_hp_addr(ab, srng); 701 tp_addr = ath12k_hal_srng_get_tp_addr(ab, srng); 702 703 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 704 ring_type, &htt_ring_type, 705 &htt_ring_id); 706 if (ret) 707 goto err_free; 708 709 skb_put(skb, len); 710 cmd = (struct htt_srng_setup_cmd *)skb->data; 711 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_SRING_SETUP, 712 HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE); 713 if (htt_ring_type == HTT_SW_TO_HW_RING || 714 htt_ring_type == HTT_HW_TO_SW_RING) 715 cmd->info0 |= le32_encode_bits(DP_SW2HW_MACID(mac_id), 716 HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID); 717 else 718 cmd->info0 |= le32_encode_bits(mac_id, 719 HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID); 720 cmd->info0 |= le32_encode_bits(htt_ring_type, 721 HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE); 722 cmd->info0 |= le32_encode_bits(htt_ring_id, 723 HTT_SRNG_SETUP_CMD_INFO0_RING_ID); 724 725 cmd->ring_base_addr_lo = cpu_to_le32(params.ring_base_paddr & 726 HAL_ADDR_LSB_REG_MASK); 727 728 cmd->ring_base_addr_hi = cpu_to_le32((u64)params.ring_base_paddr >> 729 HAL_ADDR_MSB_REG_SHIFT); 730 731 ret = ath12k_hal_srng_get_entrysize(ab, ring_type); 732 if (ret < 0) 733 goto err_free; 734 735 ring_entry_sz = ret; 736 737 ring_entry_sz >>= 2; 738 cmd->info1 = le32_encode_bits(ring_entry_sz, 739 HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE); 740 cmd->info1 |= le32_encode_bits(params.num_entries * ring_entry_sz, 741 HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE); 742 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP), 743 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP); 744 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP), 745 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP); 746 cmd->info1 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_RING_PTR_SWAP), 747 HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP); 748 if (htt_ring_type == HTT_SW_TO_HW_RING) 749 cmd->info1 |= cpu_to_le32(HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS); 750 751 cmd->ring_head_off32_remote_addr_lo = cpu_to_le32(lower_32_bits(hp_addr)); 752 cmd->ring_head_off32_remote_addr_hi = cpu_to_le32(upper_32_bits(hp_addr)); 753 754 cmd->ring_tail_off32_remote_addr_lo = cpu_to_le32(lower_32_bits(tp_addr)); 755 cmd->ring_tail_off32_remote_addr_hi = cpu_to_le32(upper_32_bits(tp_addr)); 756 757 cmd->ring_msi_addr_lo = cpu_to_le32(lower_32_bits(params.msi_addr)); 758 cmd->ring_msi_addr_hi = cpu_to_le32(upper_32_bits(params.msi_addr)); 759 cmd->msi_data = cpu_to_le32(params.msi_data); 760 761 cmd->intr_info = 762 le32_encode_bits(params.intr_batch_cntr_thres_entries * ring_entry_sz, 763 HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH); 764 cmd->intr_info |= 765 le32_encode_bits(params.intr_timer_thres_us >> 3, 766 HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH); 767 768 cmd->info2 = 0; 769 if (params.flags & HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN) { 770 cmd->info2 = le32_encode_bits(params.low_threshold, 771 HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH); 772 } 773 774 ath12k_dbg(ab, ATH12K_DBG_HAL, 775 "%s msi_addr_lo:0x%x, msi_addr_hi:0x%x, msi_data:0x%x\n", 776 __func__, cmd->ring_msi_addr_lo, cmd->ring_msi_addr_hi, 777 cmd->msi_data); 778 779 ath12k_dbg(ab, ATH12K_DBG_HAL, 780 "ring_id:%d, ring_type:%d, intr_info:0x%x, flags:0x%x\n", 781 ring_id, ring_type, cmd->intr_info, cmd->info2); 782 783 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb); 784 if (ret) 785 goto err_free; 786 787 return 0; 788 789 err_free: 790 dev_kfree_skb_any(skb); 791 792 return ret; 793 } 794 795 #define HTT_TARGET_VERSION_TIMEOUT_HZ (3 * HZ) 796 797 int ath12k_dp_tx_htt_h2t_ver_req_msg(struct ath12k_base *ab) 798 { 799 struct ath12k_dp *dp = &ab->dp; 800 struct sk_buff *skb; 801 struct htt_ver_req_cmd *cmd; 802 int len = sizeof(*cmd); 803 int ret; 804 805 init_completion(&dp->htt_tgt_version_received); 806 807 skb = ath12k_htc_alloc_skb(ab, len); 808 if (!skb) 809 return -ENOMEM; 810 811 skb_put(skb, len); 812 cmd = (struct htt_ver_req_cmd *)skb->data; 813 cmd->ver_reg_info = le32_encode_bits(HTT_H2T_MSG_TYPE_VERSION_REQ, 814 HTT_VER_REQ_INFO_MSG_ID); 815 816 ret = ath12k_htc_send(&ab->htc, dp->eid, skb); 817 if (ret) { 818 dev_kfree_skb_any(skb); 819 return ret; 820 } 821 822 ret = wait_for_completion_timeout(&dp->htt_tgt_version_received, 823 HTT_TARGET_VERSION_TIMEOUT_HZ); 824 if (ret == 0) { 825 ath12k_warn(ab, "htt target version request timed out\n"); 826 return -ETIMEDOUT; 827 } 828 829 if (dp->htt_tgt_ver_major != HTT_TARGET_VERSION_MAJOR) { 830 ath12k_err(ab, "unsupported htt major version %d supported version is %d\n", 831 dp->htt_tgt_ver_major, HTT_TARGET_VERSION_MAJOR); 832 return -ENOTSUPP; 833 } 834 835 return 0; 836 } 837 838 int ath12k_dp_tx_htt_h2t_ppdu_stats_req(struct ath12k *ar, u32 mask) 839 { 840 struct ath12k_base *ab = ar->ab; 841 struct ath12k_dp *dp = &ab->dp; 842 struct sk_buff *skb; 843 struct htt_ppdu_stats_cfg_cmd *cmd; 844 int len = sizeof(*cmd); 845 u8 pdev_mask; 846 int ret; 847 int i; 848 849 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) { 850 skb = ath12k_htc_alloc_skb(ab, len); 851 if (!skb) 852 return -ENOMEM; 853 854 skb_put(skb, len); 855 cmd = (struct htt_ppdu_stats_cfg_cmd *)skb->data; 856 cmd->msg = le32_encode_bits(HTT_H2T_MSG_TYPE_PPDU_STATS_CFG, 857 HTT_PPDU_STATS_CFG_MSG_TYPE); 858 859 pdev_mask = 1 << (i + 1); 860 cmd->msg |= le32_encode_bits(pdev_mask, HTT_PPDU_STATS_CFG_PDEV_ID); 861 cmd->msg |= le32_encode_bits(mask, HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK); 862 863 ret = ath12k_htc_send(&ab->htc, dp->eid, skb); 864 if (ret) { 865 dev_kfree_skb_any(skb); 866 return ret; 867 } 868 } 869 870 return 0; 871 } 872 873 int ath12k_dp_tx_htt_rx_filter_setup(struct ath12k_base *ab, u32 ring_id, 874 int mac_id, enum hal_ring_type ring_type, 875 int rx_buf_size, 876 struct htt_rx_ring_tlv_filter *tlv_filter) 877 { 878 struct htt_rx_ring_selection_cfg_cmd *cmd; 879 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 880 struct hal_srng_params params; 881 struct sk_buff *skb; 882 int len = sizeof(*cmd); 883 enum htt_srng_ring_type htt_ring_type; 884 enum htt_srng_ring_id htt_ring_id; 885 int ret; 886 887 skb = ath12k_htc_alloc_skb(ab, len); 888 if (!skb) 889 return -ENOMEM; 890 891 memset(¶ms, 0, sizeof(params)); 892 ath12k_hal_srng_get_params(ab, srng, ¶ms); 893 894 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 895 ring_type, &htt_ring_type, 896 &htt_ring_id); 897 if (ret) 898 goto err_free; 899 900 skb_put(skb, len); 901 cmd = (struct htt_rx_ring_selection_cfg_cmd *)skb->data; 902 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG, 903 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE); 904 if (htt_ring_type == HTT_SW_TO_HW_RING || 905 htt_ring_type == HTT_HW_TO_SW_RING) 906 cmd->info0 |= 907 le32_encode_bits(DP_SW2HW_MACID(mac_id), 908 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID); 909 else 910 cmd->info0 |= 911 le32_encode_bits(mac_id, 912 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID); 913 cmd->info0 |= le32_encode_bits(htt_ring_id, 914 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID); 915 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP), 916 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS); 917 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP), 918 HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS); 919 cmd->info0 |= le32_encode_bits(tlv_filter->offset_valid, 920 HTT_RX_RING_SELECTION_CFG_CMD_OFFSET_VALID); 921 cmd->info1 = le32_encode_bits(rx_buf_size, 922 HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE); 923 cmd->pkt_type_en_flags0 = cpu_to_le32(tlv_filter->pkt_filter_flags0); 924 cmd->pkt_type_en_flags1 = cpu_to_le32(tlv_filter->pkt_filter_flags1); 925 cmd->pkt_type_en_flags2 = cpu_to_le32(tlv_filter->pkt_filter_flags2); 926 cmd->pkt_type_en_flags3 = cpu_to_le32(tlv_filter->pkt_filter_flags3); 927 cmd->rx_filter_tlv = cpu_to_le32(tlv_filter->rx_filter); 928 929 if (tlv_filter->offset_valid) { 930 cmd->rx_packet_offset = 931 le32_encode_bits(tlv_filter->rx_packet_offset, 932 HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET); 933 934 cmd->rx_packet_offset |= 935 le32_encode_bits(tlv_filter->rx_header_offset, 936 HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET); 937 938 cmd->rx_mpdu_offset = 939 le32_encode_bits(tlv_filter->rx_mpdu_end_offset, 940 HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET); 941 942 cmd->rx_mpdu_offset |= 943 le32_encode_bits(tlv_filter->rx_mpdu_start_offset, 944 HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET); 945 946 cmd->rx_msdu_offset = 947 le32_encode_bits(tlv_filter->rx_msdu_end_offset, 948 HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET); 949 950 cmd->rx_msdu_offset |= 951 le32_encode_bits(tlv_filter->rx_msdu_start_offset, 952 HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET); 953 954 cmd->rx_attn_offset = 955 le32_encode_bits(tlv_filter->rx_attn_offset, 956 HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET); 957 } 958 959 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb); 960 if (ret) 961 goto err_free; 962 963 return 0; 964 965 err_free: 966 dev_kfree_skb_any(skb); 967 968 return ret; 969 } 970 971 int 972 ath12k_dp_tx_htt_h2t_ext_stats_req(struct ath12k *ar, u8 type, 973 struct htt_ext_stats_cfg_params *cfg_params, 974 u64 cookie) 975 { 976 struct ath12k_base *ab = ar->ab; 977 struct ath12k_dp *dp = &ab->dp; 978 struct sk_buff *skb; 979 struct htt_ext_stats_cfg_cmd *cmd; 980 int len = sizeof(*cmd); 981 int ret; 982 983 skb = ath12k_htc_alloc_skb(ab, len); 984 if (!skb) 985 return -ENOMEM; 986 987 skb_put(skb, len); 988 989 cmd = (struct htt_ext_stats_cfg_cmd *)skb->data; 990 memset(cmd, 0, sizeof(*cmd)); 991 cmd->hdr.msg_type = HTT_H2T_MSG_TYPE_EXT_STATS_CFG; 992 993 cmd->hdr.pdev_mask = 1 << ar->pdev->pdev_id; 994 995 cmd->hdr.stats_type = type; 996 cmd->cfg_param0 = cpu_to_le32(cfg_params->cfg0); 997 cmd->cfg_param1 = cpu_to_le32(cfg_params->cfg1); 998 cmd->cfg_param2 = cpu_to_le32(cfg_params->cfg2); 999 cmd->cfg_param3 = cpu_to_le32(cfg_params->cfg3); 1000 cmd->cookie_lsb = cpu_to_le32(lower_32_bits(cookie)); 1001 cmd->cookie_msb = cpu_to_le32(upper_32_bits(cookie)); 1002 1003 ret = ath12k_htc_send(&ab->htc, dp->eid, skb); 1004 if (ret) { 1005 ath12k_warn(ab, "failed to send htt type stats request: %d", 1006 ret); 1007 dev_kfree_skb_any(skb); 1008 return ret; 1009 } 1010 1011 return 0; 1012 } 1013 1014 int ath12k_dp_tx_htt_monitor_mode_ring_config(struct ath12k *ar, bool reset) 1015 { 1016 struct ath12k_base *ab = ar->ab; 1017 int ret; 1018 1019 ret = ath12k_dp_tx_htt_tx_monitor_mode_ring_config(ar, reset); 1020 if (ret) { 1021 ath12k_err(ab, "failed to setup tx monitor filter %d\n", ret); 1022 return ret; 1023 } 1024 1025 ret = ath12k_dp_tx_htt_tx_monitor_mode_ring_config(ar, reset); 1026 if (ret) { 1027 ath12k_err(ab, "failed to setup rx monitor filter %d\n", ret); 1028 return ret; 1029 } 1030 1031 return 0; 1032 } 1033 1034 int ath12k_dp_tx_htt_rx_monitor_mode_ring_config(struct ath12k *ar, bool reset) 1035 { 1036 struct ath12k_base *ab = ar->ab; 1037 struct ath12k_dp *dp = &ab->dp; 1038 struct htt_rx_ring_tlv_filter tlv_filter = {0}; 1039 int ret, ring_id; 1040 1041 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 1042 tlv_filter.offset_valid = false; 1043 1044 if (!reset) { 1045 tlv_filter.rx_filter = HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING; 1046 tlv_filter.pkt_filter_flags0 = 1047 HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 | 1048 HTT_RX_MON_MO_MGMT_FILTER_FLAGS0; 1049 tlv_filter.pkt_filter_flags1 = 1050 HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 | 1051 HTT_RX_MON_MO_MGMT_FILTER_FLAGS1; 1052 tlv_filter.pkt_filter_flags2 = 1053 HTT_RX_MON_FP_CTRL_FILTER_FLASG2 | 1054 HTT_RX_MON_MO_CTRL_FILTER_FLASG2; 1055 tlv_filter.pkt_filter_flags3 = 1056 HTT_RX_MON_FP_CTRL_FILTER_FLASG3 | 1057 HTT_RX_MON_MO_CTRL_FILTER_FLASG3 | 1058 HTT_RX_MON_FP_DATA_FILTER_FLASG3 | 1059 HTT_RX_MON_MO_DATA_FILTER_FLASG3; 1060 } 1061 1062 if (ab->hw_params->rxdma1_enable) { 1063 ret = ath12k_dp_tx_htt_rx_filter_setup(ar->ab, ring_id, 0, 1064 HAL_RXDMA_MONITOR_BUF, 1065 DP_RXDMA_REFILL_RING_SIZE, 1066 &tlv_filter); 1067 if (ret) { 1068 ath12k_err(ab, 1069 "failed to setup filter for monitor buf %d\n", ret); 1070 return ret; 1071 } 1072 } 1073 1074 return 0; 1075 } 1076 1077 int ath12k_dp_tx_htt_tx_filter_setup(struct ath12k_base *ab, u32 ring_id, 1078 int mac_id, enum hal_ring_type ring_type, 1079 int tx_buf_size, 1080 struct htt_tx_ring_tlv_filter *htt_tlv_filter) 1081 { 1082 struct htt_tx_ring_selection_cfg_cmd *cmd; 1083 struct hal_srng *srng = &ab->hal.srng_list[ring_id]; 1084 struct hal_srng_params params; 1085 struct sk_buff *skb; 1086 int len = sizeof(*cmd); 1087 enum htt_srng_ring_type htt_ring_type; 1088 enum htt_srng_ring_id htt_ring_id; 1089 int ret; 1090 1091 skb = ath12k_htc_alloc_skb(ab, len); 1092 if (!skb) 1093 return -ENOMEM; 1094 1095 memset(¶ms, 0, sizeof(params)); 1096 ath12k_hal_srng_get_params(ab, srng, ¶ms); 1097 1098 ret = ath12k_dp_tx_get_ring_id_type(ab, mac_id, ring_id, 1099 ring_type, &htt_ring_type, 1100 &htt_ring_id); 1101 1102 if (ret) 1103 goto err_free; 1104 1105 skb_put(skb, len); 1106 cmd = (struct htt_tx_ring_selection_cfg_cmd *)skb->data; 1107 cmd->info0 = le32_encode_bits(HTT_H2T_MSG_TYPE_TX_MONITOR_CFG, 1108 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE); 1109 if (htt_ring_type == HTT_SW_TO_HW_RING || 1110 htt_ring_type == HTT_HW_TO_SW_RING) 1111 cmd->info0 |= 1112 le32_encode_bits(DP_SW2HW_MACID(mac_id), 1113 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID); 1114 else 1115 cmd->info0 |= 1116 le32_encode_bits(mac_id, 1117 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID); 1118 cmd->info0 |= le32_encode_bits(htt_ring_id, 1119 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_RING_ID); 1120 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_MSI_SWAP), 1121 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_SS); 1122 cmd->info0 |= le32_encode_bits(!!(params.flags & HAL_SRNG_FLAGS_DATA_TLV_SWAP), 1123 HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PS); 1124 1125 cmd->info1 |= 1126 le32_encode_bits(tx_buf_size, 1127 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_RING_BUFF_SIZE); 1128 1129 if (htt_tlv_filter->tx_mon_mgmt_filter) { 1130 cmd->info1 |= 1131 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_MGMT, 1132 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE); 1133 cmd->info1 |= 1134 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len, 1135 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT); 1136 cmd->info2 |= 1137 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_MGMT, 1138 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG); 1139 } 1140 1141 if (htt_tlv_filter->tx_mon_data_filter) { 1142 cmd->info1 |= 1143 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_CTRL, 1144 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE); 1145 cmd->info1 |= 1146 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len, 1147 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL); 1148 cmd->info2 |= 1149 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_CTRL, 1150 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG); 1151 } 1152 1153 if (htt_tlv_filter->tx_mon_ctrl_filter) { 1154 cmd->info1 |= 1155 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_DATA, 1156 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE); 1157 cmd->info1 |= 1158 le32_encode_bits(htt_tlv_filter->tx_mon_pkt_dma_len, 1159 HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA); 1160 cmd->info2 |= 1161 le32_encode_bits(HTT_STATS_FRAME_CTRL_TYPE_DATA, 1162 HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG); 1163 } 1164 1165 cmd->tlv_filter_mask_in0 = 1166 cpu_to_le32(htt_tlv_filter->tx_mon_downstream_tlv_flags); 1167 cmd->tlv_filter_mask_in1 = 1168 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags0); 1169 cmd->tlv_filter_mask_in2 = 1170 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags1); 1171 cmd->tlv_filter_mask_in3 = 1172 cpu_to_le32(htt_tlv_filter->tx_mon_upstream_tlv_flags2); 1173 1174 ret = ath12k_htc_send(&ab->htc, ab->dp.eid, skb); 1175 if (ret) 1176 goto err_free; 1177 1178 return 0; 1179 1180 err_free: 1181 dev_kfree_skb_any(skb); 1182 return ret; 1183 } 1184 1185 int ath12k_dp_tx_htt_tx_monitor_mode_ring_config(struct ath12k *ar, bool reset) 1186 { 1187 struct ath12k_base *ab = ar->ab; 1188 struct ath12k_dp *dp = &ab->dp; 1189 struct htt_tx_ring_tlv_filter tlv_filter = {0}; 1190 int ret, ring_id; 1191 1192 ring_id = dp->tx_mon_buf_ring.refill_buf_ring.ring_id; 1193 1194 /* TODO: Need to set upstream/downstream tlv filters 1195 * here 1196 */ 1197 1198 if (ab->hw_params->rxdma1_enable) { 1199 ret = ath12k_dp_tx_htt_tx_filter_setup(ar->ab, ring_id, 0, 1200 HAL_TX_MONITOR_BUF, 1201 DP_RXDMA_REFILL_RING_SIZE, 1202 &tlv_filter); 1203 if (ret) { 1204 ath12k_err(ab, 1205 "failed to setup filter for monitor buf %d\n", ret); 1206 return ret; 1207 } 1208 } 1209 1210 return 0; 1211 } 1212