1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/ieee80211.h> 8 #include <linux/kernel.h> 9 #include <linux/skbuff.h> 10 #include <crypto/hash.h> 11 #include "core.h" 12 #include "debug.h" 13 #include "hal_desc.h" 14 #include "hw.h" 15 #include "dp_rx.h" 16 #include "hal_rx.h" 17 #include "dp_tx.h" 18 #include "peer.h" 19 #include "dp_mon.h" 20 21 #define ATH12K_DP_RX_FRAGMENT_TIMEOUT_MS (2 * HZ) 22 23 static enum hal_encrypt_type ath12k_dp_rx_h_enctype(struct ath12k_base *ab, 24 struct hal_rx_desc *desc) 25 { 26 if (!ab->hw_params->hal_ops->rx_desc_encrypt_valid(desc)) 27 return HAL_ENCRYPT_TYPE_OPEN; 28 29 return ab->hw_params->hal_ops->rx_desc_get_encrypt_type(desc); 30 } 31 32 u8 ath12k_dp_rx_h_decap_type(struct ath12k_base *ab, 33 struct hal_rx_desc *desc) 34 { 35 return ab->hw_params->hal_ops->rx_desc_get_decap_type(desc); 36 } 37 38 static u8 ath12k_dp_rx_h_mesh_ctl_present(struct ath12k_base *ab, 39 struct hal_rx_desc *desc) 40 { 41 return ab->hw_params->hal_ops->rx_desc_get_mesh_ctl(desc); 42 } 43 44 static bool ath12k_dp_rx_h_seq_ctrl_valid(struct ath12k_base *ab, 45 struct hal_rx_desc *desc) 46 { 47 return ab->hw_params->hal_ops->rx_desc_get_mpdu_seq_ctl_vld(desc); 48 } 49 50 static bool ath12k_dp_rx_h_fc_valid(struct ath12k_base *ab, 51 struct hal_rx_desc *desc) 52 { 53 return ab->hw_params->hal_ops->rx_desc_get_mpdu_fc_valid(desc); 54 } 55 56 static bool ath12k_dp_rx_h_more_frags(struct ath12k_base *ab, 57 struct sk_buff *skb) 58 { 59 struct ieee80211_hdr *hdr; 60 61 hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params->hal_desc_sz); 62 return ieee80211_has_morefrags(hdr->frame_control); 63 } 64 65 static u16 ath12k_dp_rx_h_frag_no(struct ath12k_base *ab, 66 struct sk_buff *skb) 67 { 68 struct ieee80211_hdr *hdr; 69 70 hdr = (struct ieee80211_hdr *)(skb->data + ab->hw_params->hal_desc_sz); 71 return le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_FRAG; 72 } 73 74 static u16 ath12k_dp_rx_h_seq_no(struct ath12k_base *ab, 75 struct hal_rx_desc *desc) 76 { 77 return ab->hw_params->hal_ops->rx_desc_get_mpdu_start_seq_no(desc); 78 } 79 80 static bool ath12k_dp_rx_h_msdu_done(struct ath12k_base *ab, 81 struct hal_rx_desc *desc) 82 { 83 return ab->hw_params->hal_ops->dp_rx_h_msdu_done(desc); 84 } 85 86 static bool ath12k_dp_rx_h_l4_cksum_fail(struct ath12k_base *ab, 87 struct hal_rx_desc *desc) 88 { 89 return ab->hw_params->hal_ops->dp_rx_h_l4_cksum_fail(desc); 90 } 91 92 static bool ath12k_dp_rx_h_ip_cksum_fail(struct ath12k_base *ab, 93 struct hal_rx_desc *desc) 94 { 95 return ab->hw_params->hal_ops->dp_rx_h_ip_cksum_fail(desc); 96 } 97 98 static bool ath12k_dp_rx_h_is_decrypted(struct ath12k_base *ab, 99 struct hal_rx_desc *desc) 100 { 101 return ab->hw_params->hal_ops->dp_rx_h_is_decrypted(desc); 102 } 103 104 u32 ath12k_dp_rx_h_mpdu_err(struct ath12k_base *ab, 105 struct hal_rx_desc *desc) 106 { 107 return ab->hw_params->hal_ops->dp_rx_h_mpdu_err(desc); 108 } 109 110 static u16 ath12k_dp_rx_h_msdu_len(struct ath12k_base *ab, 111 struct hal_rx_desc *desc) 112 { 113 return ab->hw_params->hal_ops->rx_desc_get_msdu_len(desc); 114 } 115 116 static u8 ath12k_dp_rx_h_sgi(struct ath12k_base *ab, 117 struct hal_rx_desc *desc) 118 { 119 return ab->hw_params->hal_ops->rx_desc_get_msdu_sgi(desc); 120 } 121 122 static u8 ath12k_dp_rx_h_rate_mcs(struct ath12k_base *ab, 123 struct hal_rx_desc *desc) 124 { 125 return ab->hw_params->hal_ops->rx_desc_get_msdu_rate_mcs(desc); 126 } 127 128 static u8 ath12k_dp_rx_h_rx_bw(struct ath12k_base *ab, 129 struct hal_rx_desc *desc) 130 { 131 return ab->hw_params->hal_ops->rx_desc_get_msdu_rx_bw(desc); 132 } 133 134 static u32 ath12k_dp_rx_h_freq(struct ath12k_base *ab, 135 struct hal_rx_desc *desc) 136 { 137 return ab->hw_params->hal_ops->rx_desc_get_msdu_freq(desc); 138 } 139 140 static u8 ath12k_dp_rx_h_pkt_type(struct ath12k_base *ab, 141 struct hal_rx_desc *desc) 142 { 143 return ab->hw_params->hal_ops->rx_desc_get_msdu_pkt_type(desc); 144 } 145 146 static u8 ath12k_dp_rx_h_nss(struct ath12k_base *ab, 147 struct hal_rx_desc *desc) 148 { 149 return hweight8(ab->hw_params->hal_ops->rx_desc_get_msdu_nss(desc)); 150 } 151 152 static u8 ath12k_dp_rx_h_tid(struct ath12k_base *ab, 153 struct hal_rx_desc *desc) 154 { 155 return ab->hw_params->hal_ops->rx_desc_get_mpdu_tid(desc); 156 } 157 158 static u16 ath12k_dp_rx_h_peer_id(struct ath12k_base *ab, 159 struct hal_rx_desc *desc) 160 { 161 return ab->hw_params->hal_ops->rx_desc_get_mpdu_peer_id(desc); 162 } 163 164 u8 ath12k_dp_rx_h_l3pad(struct ath12k_base *ab, 165 struct hal_rx_desc *desc) 166 { 167 return ab->hw_params->hal_ops->rx_desc_get_l3_pad_bytes(desc); 168 } 169 170 static bool ath12k_dp_rx_h_first_msdu(struct ath12k_base *ab, 171 struct hal_rx_desc *desc) 172 { 173 return ab->hw_params->hal_ops->rx_desc_get_first_msdu(desc); 174 } 175 176 static bool ath12k_dp_rx_h_last_msdu(struct ath12k_base *ab, 177 struct hal_rx_desc *desc) 178 { 179 return ab->hw_params->hal_ops->rx_desc_get_last_msdu(desc); 180 } 181 182 static void ath12k_dp_rx_desc_end_tlv_copy(struct ath12k_base *ab, 183 struct hal_rx_desc *fdesc, 184 struct hal_rx_desc *ldesc) 185 { 186 ab->hw_params->hal_ops->rx_desc_copy_end_tlv(fdesc, ldesc); 187 } 188 189 static void ath12k_dp_rxdesc_set_msdu_len(struct ath12k_base *ab, 190 struct hal_rx_desc *desc, 191 u16 len) 192 { 193 ab->hw_params->hal_ops->rx_desc_set_msdu_len(desc, len); 194 } 195 196 static bool ath12k_dp_rx_h_is_da_mcbc(struct ath12k_base *ab, 197 struct hal_rx_desc *desc) 198 { 199 return (ath12k_dp_rx_h_first_msdu(ab, desc) && 200 ab->hw_params->hal_ops->rx_desc_is_da_mcbc(desc)); 201 } 202 203 static bool ath12k_dp_rxdesc_mac_addr2_valid(struct ath12k_base *ab, 204 struct hal_rx_desc *desc) 205 { 206 return ab->hw_params->hal_ops->rx_desc_mac_addr2_valid(desc); 207 } 208 209 static u8 *ath12k_dp_rxdesc_get_mpdu_start_addr2(struct ath12k_base *ab, 210 struct hal_rx_desc *desc) 211 { 212 return ab->hw_params->hal_ops->rx_desc_mpdu_start_addr2(desc); 213 } 214 215 static void ath12k_dp_rx_desc_get_dot11_hdr(struct ath12k_base *ab, 216 struct hal_rx_desc *desc, 217 struct ieee80211_hdr *hdr) 218 { 219 ab->hw_params->hal_ops->rx_desc_get_dot11_hdr(desc, hdr); 220 } 221 222 static void ath12k_dp_rx_desc_get_crypto_header(struct ath12k_base *ab, 223 struct hal_rx_desc *desc, 224 u8 *crypto_hdr, 225 enum hal_encrypt_type enctype) 226 { 227 ab->hw_params->hal_ops->rx_desc_get_crypto_header(desc, crypto_hdr, enctype); 228 } 229 230 static u16 ath12k_dp_rxdesc_get_mpdu_frame_ctrl(struct ath12k_base *ab, 231 struct hal_rx_desc *desc) 232 { 233 return ab->hw_params->hal_ops->rx_desc_get_mpdu_frame_ctl(desc); 234 } 235 236 static int ath12k_dp_purge_mon_ring(struct ath12k_base *ab) 237 { 238 int i, reaped = 0; 239 unsigned long timeout = jiffies + msecs_to_jiffies(DP_MON_PURGE_TIMEOUT_MS); 240 241 do { 242 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) 243 reaped += ath12k_dp_mon_process_ring(ab, i, NULL, 244 DP_MON_SERVICE_BUDGET, 245 ATH12K_DP_RX_MONITOR_MODE); 246 247 /* nothing more to reap */ 248 if (reaped < DP_MON_SERVICE_BUDGET) 249 return 0; 250 251 } while (time_before(jiffies, timeout)); 252 253 ath12k_warn(ab, "dp mon ring purge timeout"); 254 255 return -ETIMEDOUT; 256 } 257 258 /* Returns number of Rx buffers replenished */ 259 int ath12k_dp_rx_bufs_replenish(struct ath12k_base *ab, int mac_id, 260 struct dp_rxdma_ring *rx_ring, 261 int req_entries, 262 enum hal_rx_buf_return_buf_manager mgr, 263 bool hw_cc) 264 { 265 struct ath12k_buffer_addr *desc; 266 struct hal_srng *srng; 267 struct sk_buff *skb; 268 int num_free; 269 int num_remain; 270 int buf_id; 271 u32 cookie; 272 dma_addr_t paddr; 273 struct ath12k_dp *dp = &ab->dp; 274 struct ath12k_rx_desc_info *rx_desc; 275 276 req_entries = min(req_entries, rx_ring->bufs_max); 277 278 srng = &ab->hal.srng_list[rx_ring->refill_buf_ring.ring_id]; 279 280 spin_lock_bh(&srng->lock); 281 282 ath12k_hal_srng_access_begin(ab, srng); 283 284 num_free = ath12k_hal_srng_src_num_free(ab, srng, true); 285 if (!req_entries && (num_free > (rx_ring->bufs_max * 3) / 4)) 286 req_entries = num_free; 287 288 req_entries = min(num_free, req_entries); 289 num_remain = req_entries; 290 291 while (num_remain > 0) { 292 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + 293 DP_RX_BUFFER_ALIGN_SIZE); 294 if (!skb) 295 break; 296 297 if (!IS_ALIGNED((unsigned long)skb->data, 298 DP_RX_BUFFER_ALIGN_SIZE)) { 299 skb_pull(skb, 300 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) - 301 skb->data); 302 } 303 304 paddr = dma_map_single(ab->dev, skb->data, 305 skb->len + skb_tailroom(skb), 306 DMA_FROM_DEVICE); 307 if (dma_mapping_error(ab->dev, paddr)) 308 goto fail_free_skb; 309 310 if (hw_cc) { 311 spin_lock_bh(&dp->rx_desc_lock); 312 313 /* Get desc from free list and store in used list 314 * for cleanup purposes 315 * 316 * TODO: pass the removed descs rather than 317 * add/read to optimize 318 */ 319 rx_desc = list_first_entry_or_null(&dp->rx_desc_free_list, 320 struct ath12k_rx_desc_info, 321 list); 322 if (!rx_desc) { 323 spin_unlock_bh(&dp->rx_desc_lock); 324 goto fail_dma_unmap; 325 } 326 327 rx_desc->skb = skb; 328 cookie = rx_desc->cookie; 329 list_del(&rx_desc->list); 330 list_add_tail(&rx_desc->list, &dp->rx_desc_used_list); 331 332 spin_unlock_bh(&dp->rx_desc_lock); 333 } else { 334 spin_lock_bh(&rx_ring->idr_lock); 335 buf_id = idr_alloc(&rx_ring->bufs_idr, skb, 0, 336 rx_ring->bufs_max * 3, GFP_ATOMIC); 337 spin_unlock_bh(&rx_ring->idr_lock); 338 if (buf_id < 0) 339 goto fail_dma_unmap; 340 cookie = u32_encode_bits(mac_id, 341 DP_RXDMA_BUF_COOKIE_PDEV_ID) | 342 u32_encode_bits(buf_id, 343 DP_RXDMA_BUF_COOKIE_BUF_ID); 344 } 345 346 desc = ath12k_hal_srng_src_get_next_entry(ab, srng); 347 if (!desc) 348 goto fail_buf_unassign; 349 350 ATH12K_SKB_RXCB(skb)->paddr = paddr; 351 352 num_remain--; 353 354 ath12k_hal_rx_buf_addr_info_set(desc, paddr, cookie, mgr); 355 } 356 357 ath12k_hal_srng_access_end(ab, srng); 358 359 spin_unlock_bh(&srng->lock); 360 361 return req_entries - num_remain; 362 363 fail_buf_unassign: 364 if (hw_cc) { 365 spin_lock_bh(&dp->rx_desc_lock); 366 list_del(&rx_desc->list); 367 list_add_tail(&rx_desc->list, &dp->rx_desc_free_list); 368 rx_desc->skb = NULL; 369 spin_unlock_bh(&dp->rx_desc_lock); 370 } else { 371 spin_lock_bh(&rx_ring->idr_lock); 372 idr_remove(&rx_ring->bufs_idr, buf_id); 373 spin_unlock_bh(&rx_ring->idr_lock); 374 } 375 fail_dma_unmap: 376 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb), 377 DMA_FROM_DEVICE); 378 fail_free_skb: 379 dev_kfree_skb_any(skb); 380 381 ath12k_hal_srng_access_end(ab, srng); 382 383 spin_unlock_bh(&srng->lock); 384 385 return req_entries - num_remain; 386 } 387 388 static int ath12k_dp_rxdma_buf_ring_free(struct ath12k_base *ab, 389 struct dp_rxdma_ring *rx_ring) 390 { 391 struct sk_buff *skb; 392 int buf_id; 393 394 spin_lock_bh(&rx_ring->idr_lock); 395 idr_for_each_entry(&rx_ring->bufs_idr, skb, buf_id) { 396 idr_remove(&rx_ring->bufs_idr, buf_id); 397 /* TODO: Understand where internal driver does this dma_unmap 398 * of rxdma_buffer. 399 */ 400 dma_unmap_single(ab->dev, ATH12K_SKB_RXCB(skb)->paddr, 401 skb->len + skb_tailroom(skb), DMA_FROM_DEVICE); 402 dev_kfree_skb_any(skb); 403 } 404 405 idr_destroy(&rx_ring->bufs_idr); 406 spin_unlock_bh(&rx_ring->idr_lock); 407 408 return 0; 409 } 410 411 static int ath12k_dp_rxdma_buf_free(struct ath12k_base *ab) 412 { 413 struct ath12k_dp *dp = &ab->dp; 414 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 415 416 ath12k_dp_rxdma_buf_ring_free(ab, rx_ring); 417 418 rx_ring = &dp->rxdma_mon_buf_ring; 419 ath12k_dp_rxdma_buf_ring_free(ab, rx_ring); 420 421 rx_ring = &dp->tx_mon_buf_ring; 422 ath12k_dp_rxdma_buf_ring_free(ab, rx_ring); 423 424 return 0; 425 } 426 427 static int ath12k_dp_rxdma_ring_buf_setup(struct ath12k_base *ab, 428 struct dp_rxdma_ring *rx_ring, 429 u32 ringtype) 430 { 431 int num_entries; 432 433 num_entries = rx_ring->refill_buf_ring.size / 434 ath12k_hal_srng_get_entrysize(ab, ringtype); 435 436 rx_ring->bufs_max = num_entries; 437 if ((ringtype == HAL_RXDMA_MONITOR_BUF) || (ringtype == HAL_TX_MONITOR_BUF)) 438 ath12k_dp_mon_buf_replenish(ab, rx_ring, num_entries); 439 else 440 ath12k_dp_rx_bufs_replenish(ab, 0, rx_ring, num_entries, 441 ab->hw_params->hal_params->rx_buf_rbm, 442 ringtype == HAL_RXDMA_BUF); 443 return 0; 444 } 445 446 static int ath12k_dp_rxdma_buf_setup(struct ath12k_base *ab) 447 { 448 struct ath12k_dp *dp = &ab->dp; 449 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 450 int ret; 451 452 ret = ath12k_dp_rxdma_ring_buf_setup(ab, rx_ring, 453 HAL_RXDMA_BUF); 454 if (ret) { 455 ath12k_warn(ab, 456 "failed to setup HAL_RXDMA_BUF\n"); 457 return ret; 458 } 459 460 if (ab->hw_params->rxdma1_enable) { 461 rx_ring = &dp->rxdma_mon_buf_ring; 462 ret = ath12k_dp_rxdma_ring_buf_setup(ab, rx_ring, 463 HAL_RXDMA_MONITOR_BUF); 464 if (ret) { 465 ath12k_warn(ab, 466 "failed to setup HAL_RXDMA_MONITOR_BUF\n"); 467 return ret; 468 } 469 470 rx_ring = &dp->tx_mon_buf_ring; 471 ret = ath12k_dp_rxdma_ring_buf_setup(ab, rx_ring, 472 HAL_TX_MONITOR_BUF); 473 if (ret) { 474 ath12k_warn(ab, 475 "failed to setup HAL_TX_MONITOR_BUF\n"); 476 return ret; 477 } 478 } 479 480 return 0; 481 } 482 483 static void ath12k_dp_rx_pdev_srng_free(struct ath12k *ar) 484 { 485 struct ath12k_pdev_dp *dp = &ar->dp; 486 struct ath12k_base *ab = ar->ab; 487 int i; 488 489 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) { 490 ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_dst_ring[i]); 491 ath12k_dp_srng_cleanup(ab, &dp->tx_mon_dst_ring[i]); 492 } 493 } 494 495 void ath12k_dp_rx_pdev_reo_cleanup(struct ath12k_base *ab) 496 { 497 struct ath12k_dp *dp = &ab->dp; 498 int i; 499 500 for (i = 0; i < DP_REO_DST_RING_MAX; i++) 501 ath12k_dp_srng_cleanup(ab, &dp->reo_dst_ring[i]); 502 } 503 504 int ath12k_dp_rx_pdev_reo_setup(struct ath12k_base *ab) 505 { 506 struct ath12k_dp *dp = &ab->dp; 507 int ret; 508 int i; 509 510 for (i = 0; i < DP_REO_DST_RING_MAX; i++) { 511 ret = ath12k_dp_srng_setup(ab, &dp->reo_dst_ring[i], 512 HAL_REO_DST, i, 0, 513 DP_REO_DST_RING_SIZE); 514 if (ret) { 515 ath12k_warn(ab, "failed to setup reo_dst_ring\n"); 516 goto err_reo_cleanup; 517 } 518 } 519 520 return 0; 521 522 err_reo_cleanup: 523 ath12k_dp_rx_pdev_reo_cleanup(ab); 524 525 return ret; 526 } 527 528 static int ath12k_dp_rx_pdev_srng_alloc(struct ath12k *ar) 529 { 530 struct ath12k_pdev_dp *dp = &ar->dp; 531 struct ath12k_base *ab = ar->ab; 532 int i; 533 int ret; 534 u32 mac_id = dp->mac_id; 535 536 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) { 537 ret = ath12k_dp_srng_setup(ar->ab, 538 &dp->rxdma_mon_dst_ring[i], 539 HAL_RXDMA_MONITOR_DST, 540 0, mac_id + i, 541 DP_RXDMA_MONITOR_DST_RING_SIZE); 542 if (ret) { 543 ath12k_warn(ar->ab, 544 "failed to setup HAL_RXDMA_MONITOR_DST\n"); 545 return ret; 546 } 547 548 ret = ath12k_dp_srng_setup(ar->ab, 549 &dp->tx_mon_dst_ring[i], 550 HAL_TX_MONITOR_DST, 551 0, mac_id + i, 552 DP_TX_MONITOR_DEST_RING_SIZE); 553 if (ret) { 554 ath12k_warn(ar->ab, 555 "failed to setup HAL_TX_MONITOR_DST\n"); 556 return ret; 557 } 558 } 559 560 return 0; 561 } 562 563 void ath12k_dp_rx_reo_cmd_list_cleanup(struct ath12k_base *ab) 564 { 565 struct ath12k_dp *dp = &ab->dp; 566 struct ath12k_dp_rx_reo_cmd *cmd, *tmp; 567 struct ath12k_dp_rx_reo_cache_flush_elem *cmd_cache, *tmp_cache; 568 569 spin_lock_bh(&dp->reo_cmd_lock); 570 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 571 list_del(&cmd->list); 572 dma_unmap_single(ab->dev, cmd->data.paddr, 573 cmd->data.size, DMA_BIDIRECTIONAL); 574 kfree(cmd->data.vaddr); 575 kfree(cmd); 576 } 577 578 list_for_each_entry_safe(cmd_cache, tmp_cache, 579 &dp->reo_cmd_cache_flush_list, list) { 580 list_del(&cmd_cache->list); 581 dp->reo_cmd_cache_flush_count--; 582 dma_unmap_single(ab->dev, cmd_cache->data.paddr, 583 cmd_cache->data.size, DMA_BIDIRECTIONAL); 584 kfree(cmd_cache->data.vaddr); 585 kfree(cmd_cache); 586 } 587 spin_unlock_bh(&dp->reo_cmd_lock); 588 } 589 590 static void ath12k_dp_reo_cmd_free(struct ath12k_dp *dp, void *ctx, 591 enum hal_reo_cmd_status status) 592 { 593 struct ath12k_dp_rx_tid *rx_tid = ctx; 594 595 if (status != HAL_REO_CMD_SUCCESS) 596 ath12k_warn(dp->ab, "failed to flush rx tid hw desc, tid %d status %d\n", 597 rx_tid->tid, status); 598 599 dma_unmap_single(dp->ab->dev, rx_tid->paddr, rx_tid->size, 600 DMA_BIDIRECTIONAL); 601 kfree(rx_tid->vaddr); 602 rx_tid->vaddr = NULL; 603 } 604 605 static int ath12k_dp_reo_cmd_send(struct ath12k_base *ab, struct ath12k_dp_rx_tid *rx_tid, 606 enum hal_reo_cmd_type type, 607 struct ath12k_hal_reo_cmd *cmd, 608 void (*cb)(struct ath12k_dp *dp, void *ctx, 609 enum hal_reo_cmd_status status)) 610 { 611 struct ath12k_dp *dp = &ab->dp; 612 struct ath12k_dp_rx_reo_cmd *dp_cmd; 613 struct hal_srng *cmd_ring; 614 int cmd_num; 615 616 cmd_ring = &ab->hal.srng_list[dp->reo_cmd_ring.ring_id]; 617 cmd_num = ath12k_hal_reo_cmd_send(ab, cmd_ring, type, cmd); 618 619 /* cmd_num should start from 1, during failure return the error code */ 620 if (cmd_num < 0) 621 return cmd_num; 622 623 /* reo cmd ring descriptors has cmd_num starting from 1 */ 624 if (cmd_num == 0) 625 return -EINVAL; 626 627 if (!cb) 628 return 0; 629 630 /* Can this be optimized so that we keep the pending command list only 631 * for tid delete command to free up the resource on the command status 632 * indication? 633 */ 634 dp_cmd = kzalloc(sizeof(*dp_cmd), GFP_ATOMIC); 635 636 if (!dp_cmd) 637 return -ENOMEM; 638 639 memcpy(&dp_cmd->data, rx_tid, sizeof(*rx_tid)); 640 dp_cmd->cmd_num = cmd_num; 641 dp_cmd->handler = cb; 642 643 spin_lock_bh(&dp->reo_cmd_lock); 644 list_add_tail(&dp_cmd->list, &dp->reo_cmd_list); 645 spin_unlock_bh(&dp->reo_cmd_lock); 646 647 return 0; 648 } 649 650 static void ath12k_dp_reo_cache_flush(struct ath12k_base *ab, 651 struct ath12k_dp_rx_tid *rx_tid) 652 { 653 struct ath12k_hal_reo_cmd cmd = {0}; 654 unsigned long tot_desc_sz, desc_sz; 655 int ret; 656 657 tot_desc_sz = rx_tid->size; 658 desc_sz = ath12k_hal_reo_qdesc_size(0, HAL_DESC_REO_NON_QOS_TID); 659 660 while (tot_desc_sz > desc_sz) { 661 tot_desc_sz -= desc_sz; 662 cmd.addr_lo = lower_32_bits(rx_tid->paddr + tot_desc_sz); 663 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 664 ret = ath12k_dp_reo_cmd_send(ab, rx_tid, 665 HAL_REO_CMD_FLUSH_CACHE, &cmd, 666 NULL); 667 if (ret) 668 ath12k_warn(ab, 669 "failed to send HAL_REO_CMD_FLUSH_CACHE, tid %d (%d)\n", 670 rx_tid->tid, ret); 671 } 672 673 memset(&cmd, 0, sizeof(cmd)); 674 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 675 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 676 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 677 ret = ath12k_dp_reo_cmd_send(ab, rx_tid, 678 HAL_REO_CMD_FLUSH_CACHE, 679 &cmd, ath12k_dp_reo_cmd_free); 680 if (ret) { 681 ath12k_err(ab, "failed to send HAL_REO_CMD_FLUSH_CACHE cmd, tid %d (%d)\n", 682 rx_tid->tid, ret); 683 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, 684 DMA_BIDIRECTIONAL); 685 kfree(rx_tid->vaddr); 686 rx_tid->vaddr = NULL; 687 } 688 } 689 690 static void ath12k_dp_rx_tid_del_func(struct ath12k_dp *dp, void *ctx, 691 enum hal_reo_cmd_status status) 692 { 693 struct ath12k_base *ab = dp->ab; 694 struct ath12k_dp_rx_tid *rx_tid = ctx; 695 struct ath12k_dp_rx_reo_cache_flush_elem *elem, *tmp; 696 697 if (status == HAL_REO_CMD_DRAIN) { 698 goto free_desc; 699 } else if (status != HAL_REO_CMD_SUCCESS) { 700 /* Shouldn't happen! Cleanup in case of other failure? */ 701 ath12k_warn(ab, "failed to delete rx tid %d hw descriptor %d\n", 702 rx_tid->tid, status); 703 return; 704 } 705 706 elem = kzalloc(sizeof(*elem), GFP_ATOMIC); 707 if (!elem) 708 goto free_desc; 709 710 elem->ts = jiffies; 711 memcpy(&elem->data, rx_tid, sizeof(*rx_tid)); 712 713 spin_lock_bh(&dp->reo_cmd_lock); 714 list_add_tail(&elem->list, &dp->reo_cmd_cache_flush_list); 715 dp->reo_cmd_cache_flush_count++; 716 717 /* Flush and invalidate aged REO desc from HW cache */ 718 list_for_each_entry_safe(elem, tmp, &dp->reo_cmd_cache_flush_list, 719 list) { 720 if (dp->reo_cmd_cache_flush_count > ATH12K_DP_RX_REO_DESC_FREE_THRES || 721 time_after(jiffies, elem->ts + 722 msecs_to_jiffies(ATH12K_DP_RX_REO_DESC_FREE_TIMEOUT_MS))) { 723 list_del(&elem->list); 724 dp->reo_cmd_cache_flush_count--; 725 726 /* Unlock the reo_cmd_lock before using ath12k_dp_reo_cmd_send() 727 * within ath12k_dp_reo_cache_flush. The reo_cmd_cache_flush_list 728 * is used in only two contexts, one is in this function called 729 * from napi and the other in ath12k_dp_free during core destroy. 730 * Before dp_free, the irqs would be disabled and would wait to 731 * synchronize. Hence there wouldn’t be any race against add or 732 * delete to this list. Hence unlock-lock is safe here. 733 */ 734 spin_unlock_bh(&dp->reo_cmd_lock); 735 736 ath12k_dp_reo_cache_flush(ab, &elem->data); 737 kfree(elem); 738 spin_lock_bh(&dp->reo_cmd_lock); 739 } 740 } 741 spin_unlock_bh(&dp->reo_cmd_lock); 742 743 return; 744 free_desc: 745 dma_unmap_single(ab->dev, rx_tid->paddr, rx_tid->size, 746 DMA_BIDIRECTIONAL); 747 kfree(rx_tid->vaddr); 748 rx_tid->vaddr = NULL; 749 } 750 751 static void ath12k_peer_rx_tid_qref_setup(struct ath12k_base *ab, u16 peer_id, u16 tid, 752 dma_addr_t paddr) 753 { 754 struct ath12k_reo_queue_ref *qref; 755 struct ath12k_dp *dp = &ab->dp; 756 757 if (!ab->hw_params->reoq_lut_support) 758 return; 759 760 /* TODO: based on ML peer or not, select the LUT. below assumes non 761 * ML peer 762 */ 763 qref = (struct ath12k_reo_queue_ref *)dp->reoq_lut.vaddr + 764 (peer_id * (IEEE80211_NUM_TIDS + 1) + tid); 765 766 qref->info0 = u32_encode_bits(lower_32_bits(paddr), 767 BUFFER_ADDR_INFO0_ADDR); 768 qref->info1 = u32_encode_bits(upper_32_bits(paddr), 769 BUFFER_ADDR_INFO1_ADDR) | 770 u32_encode_bits(tid, DP_REO_QREF_NUM); 771 } 772 773 static void ath12k_peer_rx_tid_qref_reset(struct ath12k_base *ab, u16 peer_id, u16 tid) 774 { 775 struct ath12k_reo_queue_ref *qref; 776 struct ath12k_dp *dp = &ab->dp; 777 778 if (!ab->hw_params->reoq_lut_support) 779 return; 780 781 /* TODO: based on ML peer or not, select the LUT. below assumes non 782 * ML peer 783 */ 784 qref = (struct ath12k_reo_queue_ref *)dp->reoq_lut.vaddr + 785 (peer_id * (IEEE80211_NUM_TIDS + 1) + tid); 786 787 qref->info0 = u32_encode_bits(0, BUFFER_ADDR_INFO0_ADDR); 788 qref->info1 = u32_encode_bits(0, BUFFER_ADDR_INFO1_ADDR) | 789 u32_encode_bits(tid, DP_REO_QREF_NUM); 790 } 791 792 void ath12k_dp_rx_peer_tid_delete(struct ath12k *ar, 793 struct ath12k_peer *peer, u8 tid) 794 { 795 struct ath12k_hal_reo_cmd cmd = {0}; 796 struct ath12k_dp_rx_tid *rx_tid = &peer->rx_tid[tid]; 797 int ret; 798 799 if (!rx_tid->active) 800 return; 801 802 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 803 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 804 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 805 cmd.upd0 = HAL_REO_CMD_UPD0_VLD; 806 ret = ath12k_dp_reo_cmd_send(ar->ab, rx_tid, 807 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, 808 ath12k_dp_rx_tid_del_func); 809 if (ret) { 810 ath12k_err(ar->ab, "failed to send HAL_REO_CMD_UPDATE_RX_QUEUE cmd, tid %d (%d)\n", 811 tid, ret); 812 dma_unmap_single(ar->ab->dev, rx_tid->paddr, rx_tid->size, 813 DMA_BIDIRECTIONAL); 814 kfree(rx_tid->vaddr); 815 rx_tid->vaddr = NULL; 816 } 817 818 ath12k_peer_rx_tid_qref_reset(ar->ab, peer->peer_id, tid); 819 820 rx_tid->active = false; 821 } 822 823 /* TODO: it's strange (and ugly) that struct hal_reo_dest_ring is converted 824 * to struct hal_wbm_release_ring, I couldn't figure out the logic behind 825 * that. 826 */ 827 static int ath12k_dp_rx_link_desc_return(struct ath12k_base *ab, 828 struct hal_reo_dest_ring *ring, 829 enum hal_wbm_rel_bm_act action) 830 { 831 struct hal_wbm_release_ring *link_desc = (struct hal_wbm_release_ring *)ring; 832 struct hal_wbm_release_ring *desc; 833 struct ath12k_dp *dp = &ab->dp; 834 struct hal_srng *srng; 835 int ret = 0; 836 837 srng = &ab->hal.srng_list[dp->wbm_desc_rel_ring.ring_id]; 838 839 spin_lock_bh(&srng->lock); 840 841 ath12k_hal_srng_access_begin(ab, srng); 842 843 desc = ath12k_hal_srng_src_get_next_entry(ab, srng); 844 if (!desc) { 845 ret = -ENOBUFS; 846 goto exit; 847 } 848 849 ath12k_hal_rx_msdu_link_desc_set(ab, desc, link_desc, action); 850 851 exit: 852 ath12k_hal_srng_access_end(ab, srng); 853 854 spin_unlock_bh(&srng->lock); 855 856 return ret; 857 } 858 859 static void ath12k_dp_rx_frags_cleanup(struct ath12k_dp_rx_tid *rx_tid, 860 bool rel_link_desc) 861 { 862 struct ath12k_base *ab = rx_tid->ab; 863 864 lockdep_assert_held(&ab->base_lock); 865 866 if (rx_tid->dst_ring_desc) { 867 if (rel_link_desc) 868 ath12k_dp_rx_link_desc_return(ab, rx_tid->dst_ring_desc, 869 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 870 kfree(rx_tid->dst_ring_desc); 871 rx_tid->dst_ring_desc = NULL; 872 } 873 874 rx_tid->cur_sn = 0; 875 rx_tid->last_frag_no = 0; 876 rx_tid->rx_frag_bitmap = 0; 877 __skb_queue_purge(&rx_tid->rx_frags); 878 } 879 880 void ath12k_dp_rx_peer_tid_cleanup(struct ath12k *ar, struct ath12k_peer *peer) 881 { 882 struct ath12k_dp_rx_tid *rx_tid; 883 int i; 884 885 lockdep_assert_held(&ar->ab->base_lock); 886 887 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 888 rx_tid = &peer->rx_tid[i]; 889 890 ath12k_dp_rx_peer_tid_delete(ar, peer, i); 891 ath12k_dp_rx_frags_cleanup(rx_tid, true); 892 893 spin_unlock_bh(&ar->ab->base_lock); 894 del_timer_sync(&rx_tid->frag_timer); 895 spin_lock_bh(&ar->ab->base_lock); 896 } 897 } 898 899 static int ath12k_peer_rx_tid_reo_update(struct ath12k *ar, 900 struct ath12k_peer *peer, 901 struct ath12k_dp_rx_tid *rx_tid, 902 u32 ba_win_sz, u16 ssn, 903 bool update_ssn) 904 { 905 struct ath12k_hal_reo_cmd cmd = {0}; 906 int ret; 907 908 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 909 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 910 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 911 cmd.upd0 = HAL_REO_CMD_UPD0_BA_WINDOW_SIZE; 912 cmd.ba_window_size = ba_win_sz; 913 914 if (update_ssn) { 915 cmd.upd0 |= HAL_REO_CMD_UPD0_SSN; 916 cmd.upd2 = u32_encode_bits(ssn, HAL_REO_CMD_UPD2_SSN); 917 } 918 919 ret = ath12k_dp_reo_cmd_send(ar->ab, rx_tid, 920 HAL_REO_CMD_UPDATE_RX_QUEUE, &cmd, 921 NULL); 922 if (ret) { 923 ath12k_warn(ar->ab, "failed to update rx tid queue, tid %d (%d)\n", 924 rx_tid->tid, ret); 925 return ret; 926 } 927 928 rx_tid->ba_win_sz = ba_win_sz; 929 930 return 0; 931 } 932 933 int ath12k_dp_rx_peer_tid_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id, 934 u8 tid, u32 ba_win_sz, u16 ssn, 935 enum hal_pn_type pn_type) 936 { 937 struct ath12k_base *ab = ar->ab; 938 struct ath12k_dp *dp = &ab->dp; 939 struct hal_rx_reo_queue *addr_aligned; 940 struct ath12k_peer *peer; 941 struct ath12k_dp_rx_tid *rx_tid; 942 u32 hw_desc_sz; 943 void *vaddr; 944 dma_addr_t paddr; 945 int ret; 946 947 spin_lock_bh(&ab->base_lock); 948 949 peer = ath12k_peer_find(ab, vdev_id, peer_mac); 950 if (!peer) { 951 spin_unlock_bh(&ab->base_lock); 952 ath12k_warn(ab, "failed to find the peer to set up rx tid\n"); 953 return -ENOENT; 954 } 955 956 if (ab->hw_params->reoq_lut_support && !dp->reoq_lut.vaddr) { 957 spin_unlock_bh(&ab->base_lock); 958 ath12k_warn(ab, "reo qref table is not setup\n"); 959 return -EINVAL; 960 } 961 962 if (peer->peer_id > DP_MAX_PEER_ID || tid > IEEE80211_NUM_TIDS) { 963 ath12k_warn(ab, "peer id of peer %d or tid %d doesn't allow reoq setup\n", 964 peer->peer_id, tid); 965 spin_unlock_bh(&ab->base_lock); 966 return -EINVAL; 967 } 968 969 rx_tid = &peer->rx_tid[tid]; 970 /* Update the tid queue if it is already setup */ 971 if (rx_tid->active) { 972 paddr = rx_tid->paddr; 973 ret = ath12k_peer_rx_tid_reo_update(ar, peer, rx_tid, 974 ba_win_sz, ssn, true); 975 spin_unlock_bh(&ab->base_lock); 976 if (ret) { 977 ath12k_warn(ab, "failed to update reo for rx tid %d\n", tid); 978 return ret; 979 } 980 981 if (!ab->hw_params->reoq_lut_support) { 982 ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, 983 peer_mac, 984 paddr, tid, 1, 985 ba_win_sz); 986 if (ret) { 987 ath12k_warn(ab, "failed to setup peer rx reorder queuefor tid %d: %d\n", 988 tid, ret); 989 return ret; 990 } 991 } 992 993 return 0; 994 } 995 996 rx_tid->tid = tid; 997 998 rx_tid->ba_win_sz = ba_win_sz; 999 1000 /* TODO: Optimize the memory allocation for qos tid based on 1001 * the actual BA window size in REO tid update path. 1002 */ 1003 if (tid == HAL_DESC_REO_NON_QOS_TID) 1004 hw_desc_sz = ath12k_hal_reo_qdesc_size(ba_win_sz, tid); 1005 else 1006 hw_desc_sz = ath12k_hal_reo_qdesc_size(DP_BA_WIN_SZ_MAX, tid); 1007 1008 vaddr = kzalloc(hw_desc_sz + HAL_LINK_DESC_ALIGN - 1, GFP_ATOMIC); 1009 if (!vaddr) { 1010 spin_unlock_bh(&ab->base_lock); 1011 return -ENOMEM; 1012 } 1013 1014 addr_aligned = PTR_ALIGN(vaddr, HAL_LINK_DESC_ALIGN); 1015 1016 ath12k_hal_reo_qdesc_setup(addr_aligned, tid, ba_win_sz, 1017 ssn, pn_type); 1018 1019 paddr = dma_map_single(ab->dev, addr_aligned, hw_desc_sz, 1020 DMA_BIDIRECTIONAL); 1021 1022 ret = dma_mapping_error(ab->dev, paddr); 1023 if (ret) { 1024 spin_unlock_bh(&ab->base_lock); 1025 goto err_mem_free; 1026 } 1027 1028 rx_tid->vaddr = vaddr; 1029 rx_tid->paddr = paddr; 1030 rx_tid->size = hw_desc_sz; 1031 rx_tid->active = true; 1032 1033 if (ab->hw_params->reoq_lut_support) { 1034 /* Update the REO queue LUT at the corresponding peer id 1035 * and tid with qaddr. 1036 */ 1037 ath12k_peer_rx_tid_qref_setup(ab, peer->peer_id, tid, paddr); 1038 spin_unlock_bh(&ab->base_lock); 1039 } else { 1040 spin_unlock_bh(&ab->base_lock); 1041 ret = ath12k_wmi_peer_rx_reorder_queue_setup(ar, vdev_id, peer_mac, 1042 paddr, tid, 1, ba_win_sz); 1043 } 1044 1045 return ret; 1046 1047 err_mem_free: 1048 kfree(vaddr); 1049 1050 return ret; 1051 } 1052 1053 int ath12k_dp_rx_ampdu_start(struct ath12k *ar, 1054 struct ieee80211_ampdu_params *params) 1055 { 1056 struct ath12k_base *ab = ar->ab; 1057 struct ath12k_sta *arsta = (void *)params->sta->drv_priv; 1058 int vdev_id = arsta->arvif->vdev_id; 1059 int ret; 1060 1061 ret = ath12k_dp_rx_peer_tid_setup(ar, params->sta->addr, vdev_id, 1062 params->tid, params->buf_size, 1063 params->ssn, arsta->pn_type); 1064 if (ret) 1065 ath12k_warn(ab, "failed to setup rx tid %d\n", ret); 1066 1067 return ret; 1068 } 1069 1070 int ath12k_dp_rx_ampdu_stop(struct ath12k *ar, 1071 struct ieee80211_ampdu_params *params) 1072 { 1073 struct ath12k_base *ab = ar->ab; 1074 struct ath12k_peer *peer; 1075 struct ath12k_sta *arsta = (void *)params->sta->drv_priv; 1076 int vdev_id = arsta->arvif->vdev_id; 1077 bool active; 1078 int ret; 1079 1080 spin_lock_bh(&ab->base_lock); 1081 1082 peer = ath12k_peer_find(ab, vdev_id, params->sta->addr); 1083 if (!peer) { 1084 spin_unlock_bh(&ab->base_lock); 1085 ath12k_warn(ab, "failed to find the peer to stop rx aggregation\n"); 1086 return -ENOENT; 1087 } 1088 1089 active = peer->rx_tid[params->tid].active; 1090 1091 if (!active) { 1092 spin_unlock_bh(&ab->base_lock); 1093 return 0; 1094 } 1095 1096 ret = ath12k_peer_rx_tid_reo_update(ar, peer, peer->rx_tid, 1, 0, false); 1097 spin_unlock_bh(&ab->base_lock); 1098 if (ret) { 1099 ath12k_warn(ab, "failed to update reo for rx tid %d: %d\n", 1100 params->tid, ret); 1101 return ret; 1102 } 1103 1104 return ret; 1105 } 1106 1107 int ath12k_dp_rx_peer_pn_replay_config(struct ath12k_vif *arvif, 1108 const u8 *peer_addr, 1109 enum set_key_cmd key_cmd, 1110 struct ieee80211_key_conf *key) 1111 { 1112 struct ath12k *ar = arvif->ar; 1113 struct ath12k_base *ab = ar->ab; 1114 struct ath12k_hal_reo_cmd cmd = {0}; 1115 struct ath12k_peer *peer; 1116 struct ath12k_dp_rx_tid *rx_tid; 1117 u8 tid; 1118 int ret = 0; 1119 1120 /* NOTE: Enable PN/TSC replay check offload only for unicast frames. 1121 * We use mac80211 PN/TSC replay check functionality for bcast/mcast 1122 * for now. 1123 */ 1124 if (!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) 1125 return 0; 1126 1127 cmd.flag = HAL_REO_CMD_FLG_NEED_STATUS; 1128 cmd.upd0 = HAL_REO_CMD_UPD0_PN | 1129 HAL_REO_CMD_UPD0_PN_SIZE | 1130 HAL_REO_CMD_UPD0_PN_VALID | 1131 HAL_REO_CMD_UPD0_PN_CHECK | 1132 HAL_REO_CMD_UPD0_SVLD; 1133 1134 switch (key->cipher) { 1135 case WLAN_CIPHER_SUITE_TKIP: 1136 case WLAN_CIPHER_SUITE_CCMP: 1137 case WLAN_CIPHER_SUITE_CCMP_256: 1138 case WLAN_CIPHER_SUITE_GCMP: 1139 case WLAN_CIPHER_SUITE_GCMP_256: 1140 if (key_cmd == SET_KEY) { 1141 cmd.upd1 |= HAL_REO_CMD_UPD1_PN_CHECK; 1142 cmd.pn_size = 48; 1143 } 1144 break; 1145 default: 1146 break; 1147 } 1148 1149 spin_lock_bh(&ab->base_lock); 1150 1151 peer = ath12k_peer_find(ab, arvif->vdev_id, peer_addr); 1152 if (!peer) { 1153 spin_unlock_bh(&ab->base_lock); 1154 ath12k_warn(ab, "failed to find the peer %pM to configure pn replay detection\n", 1155 peer_addr); 1156 return -ENOENT; 1157 } 1158 1159 for (tid = 0; tid <= IEEE80211_NUM_TIDS; tid++) { 1160 rx_tid = &peer->rx_tid[tid]; 1161 if (!rx_tid->active) 1162 continue; 1163 cmd.addr_lo = lower_32_bits(rx_tid->paddr); 1164 cmd.addr_hi = upper_32_bits(rx_tid->paddr); 1165 ret = ath12k_dp_reo_cmd_send(ab, rx_tid, 1166 HAL_REO_CMD_UPDATE_RX_QUEUE, 1167 &cmd, NULL); 1168 if (ret) { 1169 ath12k_warn(ab, "failed to configure rx tid %d queue of peer %pM for pn replay detection %d\n", 1170 tid, peer_addr, ret); 1171 break; 1172 } 1173 } 1174 1175 spin_unlock_bh(&ab->base_lock); 1176 1177 return ret; 1178 } 1179 1180 static int ath12k_get_ppdu_user_index(struct htt_ppdu_stats *ppdu_stats, 1181 u16 peer_id) 1182 { 1183 int i; 1184 1185 for (i = 0; i < HTT_PPDU_STATS_MAX_USERS - 1; i++) { 1186 if (ppdu_stats->user_stats[i].is_valid_peer_id) { 1187 if (peer_id == ppdu_stats->user_stats[i].peer_id) 1188 return i; 1189 } else { 1190 return i; 1191 } 1192 } 1193 1194 return -EINVAL; 1195 } 1196 1197 static int ath12k_htt_tlv_ppdu_stats_parse(struct ath12k_base *ab, 1198 u16 tag, u16 len, const void *ptr, 1199 void *data) 1200 { 1201 const struct htt_ppdu_stats_usr_cmpltn_ack_ba_status *ba_status; 1202 const struct htt_ppdu_stats_usr_cmpltn_cmn *cmplt_cmn; 1203 const struct htt_ppdu_stats_user_rate *user_rate; 1204 struct htt_ppdu_stats_info *ppdu_info; 1205 struct htt_ppdu_user_stats *user_stats; 1206 int cur_user; 1207 u16 peer_id; 1208 1209 ppdu_info = data; 1210 1211 switch (tag) { 1212 case HTT_PPDU_STATS_TAG_COMMON: 1213 if (len < sizeof(struct htt_ppdu_stats_common)) { 1214 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1215 len, tag); 1216 return -EINVAL; 1217 } 1218 memcpy(&ppdu_info->ppdu_stats.common, ptr, 1219 sizeof(struct htt_ppdu_stats_common)); 1220 break; 1221 case HTT_PPDU_STATS_TAG_USR_RATE: 1222 if (len < sizeof(struct htt_ppdu_stats_user_rate)) { 1223 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1224 len, tag); 1225 return -EINVAL; 1226 } 1227 user_rate = ptr; 1228 peer_id = le16_to_cpu(user_rate->sw_peer_id); 1229 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1230 peer_id); 1231 if (cur_user < 0) 1232 return -EINVAL; 1233 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1234 user_stats->peer_id = peer_id; 1235 user_stats->is_valid_peer_id = true; 1236 memcpy(&user_stats->rate, ptr, 1237 sizeof(struct htt_ppdu_stats_user_rate)); 1238 user_stats->tlv_flags |= BIT(tag); 1239 break; 1240 case HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON: 1241 if (len < sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)) { 1242 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1243 len, tag); 1244 return -EINVAL; 1245 } 1246 1247 cmplt_cmn = ptr; 1248 peer_id = le16_to_cpu(cmplt_cmn->sw_peer_id); 1249 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1250 peer_id); 1251 if (cur_user < 0) 1252 return -EINVAL; 1253 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1254 user_stats->peer_id = peer_id; 1255 user_stats->is_valid_peer_id = true; 1256 memcpy(&user_stats->cmpltn_cmn, ptr, 1257 sizeof(struct htt_ppdu_stats_usr_cmpltn_cmn)); 1258 user_stats->tlv_flags |= BIT(tag); 1259 break; 1260 case HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS: 1261 if (len < 1262 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)) { 1263 ath12k_warn(ab, "Invalid len %d for the tag 0x%x\n", 1264 len, tag); 1265 return -EINVAL; 1266 } 1267 1268 ba_status = ptr; 1269 peer_id = le16_to_cpu(ba_status->sw_peer_id); 1270 cur_user = ath12k_get_ppdu_user_index(&ppdu_info->ppdu_stats, 1271 peer_id); 1272 if (cur_user < 0) 1273 return -EINVAL; 1274 user_stats = &ppdu_info->ppdu_stats.user_stats[cur_user]; 1275 user_stats->peer_id = peer_id; 1276 user_stats->is_valid_peer_id = true; 1277 memcpy(&user_stats->ack_ba, ptr, 1278 sizeof(struct htt_ppdu_stats_usr_cmpltn_ack_ba_status)); 1279 user_stats->tlv_flags |= BIT(tag); 1280 break; 1281 } 1282 return 0; 1283 } 1284 1285 static int ath12k_dp_htt_tlv_iter(struct ath12k_base *ab, const void *ptr, size_t len, 1286 int (*iter)(struct ath12k_base *ar, u16 tag, u16 len, 1287 const void *ptr, void *data), 1288 void *data) 1289 { 1290 const struct htt_tlv *tlv; 1291 const void *begin = ptr; 1292 u16 tlv_tag, tlv_len; 1293 int ret = -EINVAL; 1294 1295 while (len > 0) { 1296 if (len < sizeof(*tlv)) { 1297 ath12k_err(ab, "htt tlv parse failure at byte %zd (%zu bytes left, %zu expected)\n", 1298 ptr - begin, len, sizeof(*tlv)); 1299 return -EINVAL; 1300 } 1301 tlv = (struct htt_tlv *)ptr; 1302 tlv_tag = le32_get_bits(tlv->header, HTT_TLV_TAG); 1303 tlv_len = le32_get_bits(tlv->header, HTT_TLV_LEN); 1304 ptr += sizeof(*tlv); 1305 len -= sizeof(*tlv); 1306 1307 if (tlv_len > len) { 1308 ath12k_err(ab, "htt tlv parse failure of tag %u at byte %zd (%zu bytes left, %u expected)\n", 1309 tlv_tag, ptr - begin, len, tlv_len); 1310 return -EINVAL; 1311 } 1312 ret = iter(ab, tlv_tag, tlv_len, ptr, data); 1313 if (ret == -ENOMEM) 1314 return ret; 1315 1316 ptr += tlv_len; 1317 len -= tlv_len; 1318 } 1319 return 0; 1320 } 1321 1322 static void 1323 ath12k_update_per_peer_tx_stats(struct ath12k *ar, 1324 struct htt_ppdu_stats *ppdu_stats, u8 user) 1325 { 1326 struct ath12k_base *ab = ar->ab; 1327 struct ath12k_peer *peer; 1328 struct ieee80211_sta *sta; 1329 struct ath12k_sta *arsta; 1330 struct htt_ppdu_stats_user_rate *user_rate; 1331 struct ath12k_per_peer_tx_stats *peer_stats = &ar->peer_tx_stats; 1332 struct htt_ppdu_user_stats *usr_stats = &ppdu_stats->user_stats[user]; 1333 struct htt_ppdu_stats_common *common = &ppdu_stats->common; 1334 int ret; 1335 u8 flags, mcs, nss, bw, sgi, dcm, rate_idx = 0; 1336 u32 v, succ_bytes = 0; 1337 u16 tones, rate = 0, succ_pkts = 0; 1338 u32 tx_duration = 0; 1339 u8 tid = HTT_PPDU_STATS_NON_QOS_TID; 1340 bool is_ampdu = false; 1341 1342 if (!usr_stats) 1343 return; 1344 1345 if (!(usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_RATE))) 1346 return; 1347 1348 if (usr_stats->tlv_flags & BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON)) 1349 is_ampdu = 1350 HTT_USR_CMPLTN_IS_AMPDU(usr_stats->cmpltn_cmn.flags); 1351 1352 if (usr_stats->tlv_flags & 1353 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS)) { 1354 succ_bytes = le32_to_cpu(usr_stats->ack_ba.success_bytes); 1355 succ_pkts = le32_get_bits(usr_stats->ack_ba.info, 1356 HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M); 1357 tid = le32_get_bits(usr_stats->ack_ba.info, 1358 HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM); 1359 } 1360 1361 if (common->fes_duration_us) 1362 tx_duration = le32_to_cpu(common->fes_duration_us); 1363 1364 user_rate = &usr_stats->rate; 1365 flags = HTT_USR_RATE_PREAMBLE(user_rate->rate_flags); 1366 bw = HTT_USR_RATE_BW(user_rate->rate_flags) - 2; 1367 nss = HTT_USR_RATE_NSS(user_rate->rate_flags) + 1; 1368 mcs = HTT_USR_RATE_MCS(user_rate->rate_flags); 1369 sgi = HTT_USR_RATE_GI(user_rate->rate_flags); 1370 dcm = HTT_USR_RATE_DCM(user_rate->rate_flags); 1371 1372 /* Note: If host configured fixed rates and in some other special 1373 * cases, the broadcast/management frames are sent in different rates. 1374 * Firmware rate's control to be skipped for this? 1375 */ 1376 1377 if (flags == WMI_RATE_PREAMBLE_HE && mcs > ATH12K_HE_MCS_MAX) { 1378 ath12k_warn(ab, "Invalid HE mcs %d peer stats", mcs); 1379 return; 1380 } 1381 1382 if (flags == WMI_RATE_PREAMBLE_VHT && mcs > ATH12K_VHT_MCS_MAX) { 1383 ath12k_warn(ab, "Invalid VHT mcs %d peer stats", mcs); 1384 return; 1385 } 1386 1387 if (flags == WMI_RATE_PREAMBLE_HT && (mcs > ATH12K_HT_MCS_MAX || nss < 1)) { 1388 ath12k_warn(ab, "Invalid HT mcs %d nss %d peer stats", 1389 mcs, nss); 1390 return; 1391 } 1392 1393 if (flags == WMI_RATE_PREAMBLE_CCK || flags == WMI_RATE_PREAMBLE_OFDM) { 1394 ret = ath12k_mac_hw_ratecode_to_legacy_rate(mcs, 1395 flags, 1396 &rate_idx, 1397 &rate); 1398 if (ret < 0) 1399 return; 1400 } 1401 1402 rcu_read_lock(); 1403 spin_lock_bh(&ab->base_lock); 1404 peer = ath12k_peer_find_by_id(ab, usr_stats->peer_id); 1405 1406 if (!peer || !peer->sta) { 1407 spin_unlock_bh(&ab->base_lock); 1408 rcu_read_unlock(); 1409 return; 1410 } 1411 1412 sta = peer->sta; 1413 arsta = (struct ath12k_sta *)sta->drv_priv; 1414 1415 memset(&arsta->txrate, 0, sizeof(arsta->txrate)); 1416 1417 switch (flags) { 1418 case WMI_RATE_PREAMBLE_OFDM: 1419 arsta->txrate.legacy = rate; 1420 break; 1421 case WMI_RATE_PREAMBLE_CCK: 1422 arsta->txrate.legacy = rate; 1423 break; 1424 case WMI_RATE_PREAMBLE_HT: 1425 arsta->txrate.mcs = mcs + 8 * (nss - 1); 1426 arsta->txrate.flags = RATE_INFO_FLAGS_MCS; 1427 if (sgi) 1428 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1429 break; 1430 case WMI_RATE_PREAMBLE_VHT: 1431 arsta->txrate.mcs = mcs; 1432 arsta->txrate.flags = RATE_INFO_FLAGS_VHT_MCS; 1433 if (sgi) 1434 arsta->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI; 1435 break; 1436 case WMI_RATE_PREAMBLE_HE: 1437 arsta->txrate.mcs = mcs; 1438 arsta->txrate.flags = RATE_INFO_FLAGS_HE_MCS; 1439 arsta->txrate.he_dcm = dcm; 1440 arsta->txrate.he_gi = ath12k_he_gi_to_nl80211_he_gi(sgi); 1441 tones = le16_to_cpu(user_rate->ru_end) - 1442 le16_to_cpu(user_rate->ru_start) + 1; 1443 v = ath12k_he_ru_tones_to_nl80211_he_ru_alloc(tones); 1444 arsta->txrate.he_ru_alloc = v; 1445 break; 1446 } 1447 1448 arsta->txrate.nss = nss; 1449 arsta->txrate.bw = ath12k_mac_bw_to_mac80211_bw(bw); 1450 arsta->tx_duration += tx_duration; 1451 memcpy(&arsta->last_txrate, &arsta->txrate, sizeof(struct rate_info)); 1452 1453 /* PPDU stats reported for mgmt packet doesn't have valid tx bytes. 1454 * So skip peer stats update for mgmt packets. 1455 */ 1456 if (tid < HTT_PPDU_STATS_NON_QOS_TID) { 1457 memset(peer_stats, 0, sizeof(*peer_stats)); 1458 peer_stats->succ_pkts = succ_pkts; 1459 peer_stats->succ_bytes = succ_bytes; 1460 peer_stats->is_ampdu = is_ampdu; 1461 peer_stats->duration = tx_duration; 1462 peer_stats->ba_fails = 1463 HTT_USR_CMPLTN_LONG_RETRY(usr_stats->cmpltn_cmn.flags) + 1464 HTT_USR_CMPLTN_SHORT_RETRY(usr_stats->cmpltn_cmn.flags); 1465 } 1466 1467 spin_unlock_bh(&ab->base_lock); 1468 rcu_read_unlock(); 1469 } 1470 1471 static void ath12k_htt_update_ppdu_stats(struct ath12k *ar, 1472 struct htt_ppdu_stats *ppdu_stats) 1473 { 1474 u8 user; 1475 1476 for (user = 0; user < HTT_PPDU_STATS_MAX_USERS - 1; user++) 1477 ath12k_update_per_peer_tx_stats(ar, ppdu_stats, user); 1478 } 1479 1480 static 1481 struct htt_ppdu_stats_info *ath12k_dp_htt_get_ppdu_desc(struct ath12k *ar, 1482 u32 ppdu_id) 1483 { 1484 struct htt_ppdu_stats_info *ppdu_info; 1485 1486 lockdep_assert_held(&ar->data_lock); 1487 if (!list_empty(&ar->ppdu_stats_info)) { 1488 list_for_each_entry(ppdu_info, &ar->ppdu_stats_info, list) { 1489 if (ppdu_info->ppdu_id == ppdu_id) 1490 return ppdu_info; 1491 } 1492 1493 if (ar->ppdu_stat_list_depth > HTT_PPDU_DESC_MAX_DEPTH) { 1494 ppdu_info = list_first_entry(&ar->ppdu_stats_info, 1495 typeof(*ppdu_info), list); 1496 list_del(&ppdu_info->list); 1497 ar->ppdu_stat_list_depth--; 1498 ath12k_htt_update_ppdu_stats(ar, &ppdu_info->ppdu_stats); 1499 kfree(ppdu_info); 1500 } 1501 } 1502 1503 ppdu_info = kzalloc(sizeof(*ppdu_info), GFP_ATOMIC); 1504 if (!ppdu_info) 1505 return NULL; 1506 1507 list_add_tail(&ppdu_info->list, &ar->ppdu_stats_info); 1508 ar->ppdu_stat_list_depth++; 1509 1510 return ppdu_info; 1511 } 1512 1513 static void ath12k_copy_to_delay_stats(struct ath12k_peer *peer, 1514 struct htt_ppdu_user_stats *usr_stats) 1515 { 1516 peer->ppdu_stats_delayba.sw_peer_id = le16_to_cpu(usr_stats->rate.sw_peer_id); 1517 peer->ppdu_stats_delayba.info0 = le32_to_cpu(usr_stats->rate.info0); 1518 peer->ppdu_stats_delayba.ru_end = le16_to_cpu(usr_stats->rate.ru_end); 1519 peer->ppdu_stats_delayba.ru_start = le16_to_cpu(usr_stats->rate.ru_start); 1520 peer->ppdu_stats_delayba.info1 = le32_to_cpu(usr_stats->rate.info1); 1521 peer->ppdu_stats_delayba.rate_flags = le32_to_cpu(usr_stats->rate.rate_flags); 1522 peer->ppdu_stats_delayba.resp_rate_flags = 1523 le32_to_cpu(usr_stats->rate.resp_rate_flags); 1524 1525 peer->delayba_flag = true; 1526 } 1527 1528 static void ath12k_copy_to_bar(struct ath12k_peer *peer, 1529 struct htt_ppdu_user_stats *usr_stats) 1530 { 1531 usr_stats->rate.sw_peer_id = cpu_to_le16(peer->ppdu_stats_delayba.sw_peer_id); 1532 usr_stats->rate.info0 = cpu_to_le32(peer->ppdu_stats_delayba.info0); 1533 usr_stats->rate.ru_end = cpu_to_le16(peer->ppdu_stats_delayba.ru_end); 1534 usr_stats->rate.ru_start = cpu_to_le16(peer->ppdu_stats_delayba.ru_start); 1535 usr_stats->rate.info1 = cpu_to_le32(peer->ppdu_stats_delayba.info1); 1536 usr_stats->rate.rate_flags = cpu_to_le32(peer->ppdu_stats_delayba.rate_flags); 1537 usr_stats->rate.resp_rate_flags = 1538 cpu_to_le32(peer->ppdu_stats_delayba.resp_rate_flags); 1539 1540 peer->delayba_flag = false; 1541 } 1542 1543 static int ath12k_htt_pull_ppdu_stats(struct ath12k_base *ab, 1544 struct sk_buff *skb) 1545 { 1546 struct ath12k_htt_ppdu_stats_msg *msg; 1547 struct htt_ppdu_stats_info *ppdu_info; 1548 struct ath12k_peer *peer = NULL; 1549 struct htt_ppdu_user_stats *usr_stats = NULL; 1550 u32 peer_id = 0; 1551 struct ath12k *ar; 1552 int ret, i; 1553 u8 pdev_id; 1554 u32 ppdu_id, len; 1555 1556 msg = (struct ath12k_htt_ppdu_stats_msg *)skb->data; 1557 len = le32_get_bits(msg->info, HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE); 1558 if (len > (skb->len - struct_size(msg, data, 0))) { 1559 ath12k_warn(ab, 1560 "HTT PPDU STATS event has unexpected payload size %u, should be smaller than %u\n", 1561 len, skb->len); 1562 return -EINVAL; 1563 } 1564 1565 pdev_id = le32_get_bits(msg->info, HTT_T2H_PPDU_STATS_INFO_PDEV_ID); 1566 ppdu_id = le32_to_cpu(msg->ppdu_id); 1567 1568 rcu_read_lock(); 1569 ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id); 1570 if (!ar) { 1571 ret = -EINVAL; 1572 goto exit; 1573 } 1574 1575 spin_lock_bh(&ar->data_lock); 1576 ppdu_info = ath12k_dp_htt_get_ppdu_desc(ar, ppdu_id); 1577 if (!ppdu_info) { 1578 spin_unlock_bh(&ar->data_lock); 1579 ret = -EINVAL; 1580 goto exit; 1581 } 1582 1583 ppdu_info->ppdu_id = ppdu_id; 1584 ret = ath12k_dp_htt_tlv_iter(ab, msg->data, len, 1585 ath12k_htt_tlv_ppdu_stats_parse, 1586 (void *)ppdu_info); 1587 if (ret) { 1588 spin_unlock_bh(&ar->data_lock); 1589 ath12k_warn(ab, "Failed to parse tlv %d\n", ret); 1590 goto exit; 1591 } 1592 1593 if (ppdu_info->ppdu_stats.common.num_users >= HTT_PPDU_STATS_MAX_USERS) { 1594 spin_unlock_bh(&ar->data_lock); 1595 ath12k_warn(ab, 1596 "HTT PPDU STATS event has unexpected num_users %u, should be smaller than %u\n", 1597 ppdu_info->ppdu_stats.common.num_users, 1598 HTT_PPDU_STATS_MAX_USERS); 1599 ret = -EINVAL; 1600 goto exit; 1601 } 1602 1603 /* back up data rate tlv for all peers */ 1604 if (ppdu_info->frame_type == HTT_STATS_PPDU_FTYPE_DATA && 1605 (ppdu_info->tlv_bitmap & (1 << HTT_PPDU_STATS_TAG_USR_COMMON)) && 1606 ppdu_info->delay_ba) { 1607 for (i = 0; i < ppdu_info->ppdu_stats.common.num_users; i++) { 1608 peer_id = ppdu_info->ppdu_stats.user_stats[i].peer_id; 1609 spin_lock_bh(&ab->base_lock); 1610 peer = ath12k_peer_find_by_id(ab, peer_id); 1611 if (!peer) { 1612 spin_unlock_bh(&ab->base_lock); 1613 continue; 1614 } 1615 1616 usr_stats = &ppdu_info->ppdu_stats.user_stats[i]; 1617 if (usr_stats->delay_ba) 1618 ath12k_copy_to_delay_stats(peer, usr_stats); 1619 spin_unlock_bh(&ab->base_lock); 1620 } 1621 } 1622 1623 /* restore all peers' data rate tlv to mu-bar tlv */ 1624 if (ppdu_info->frame_type == HTT_STATS_PPDU_FTYPE_BAR && 1625 (ppdu_info->tlv_bitmap & (1 << HTT_PPDU_STATS_TAG_USR_COMMON))) { 1626 for (i = 0; i < ppdu_info->bar_num_users; i++) { 1627 peer_id = ppdu_info->ppdu_stats.user_stats[i].peer_id; 1628 spin_lock_bh(&ab->base_lock); 1629 peer = ath12k_peer_find_by_id(ab, peer_id); 1630 if (!peer) { 1631 spin_unlock_bh(&ab->base_lock); 1632 continue; 1633 } 1634 1635 usr_stats = &ppdu_info->ppdu_stats.user_stats[i]; 1636 if (peer->delayba_flag) 1637 ath12k_copy_to_bar(peer, usr_stats); 1638 spin_unlock_bh(&ab->base_lock); 1639 } 1640 } 1641 1642 spin_unlock_bh(&ar->data_lock); 1643 1644 exit: 1645 rcu_read_unlock(); 1646 1647 return ret; 1648 } 1649 1650 static void ath12k_htt_mlo_offset_event_handler(struct ath12k_base *ab, 1651 struct sk_buff *skb) 1652 { 1653 struct ath12k_htt_mlo_offset_msg *msg; 1654 struct ath12k_pdev *pdev; 1655 struct ath12k *ar; 1656 u8 pdev_id; 1657 1658 msg = (struct ath12k_htt_mlo_offset_msg *)skb->data; 1659 pdev_id = u32_get_bits(__le32_to_cpu(msg->info), 1660 HTT_T2H_MLO_OFFSET_INFO_PDEV_ID); 1661 ar = ath12k_mac_get_ar_by_pdev_id(ab, pdev_id); 1662 1663 if (!ar) { 1664 ath12k_warn(ab, "invalid pdev id %d on htt mlo offset\n", pdev_id); 1665 return; 1666 } 1667 1668 spin_lock_bh(&ar->data_lock); 1669 pdev = ar->pdev; 1670 1671 pdev->timestamp.info = __le32_to_cpu(msg->info); 1672 pdev->timestamp.sync_timestamp_lo_us = __le32_to_cpu(msg->sync_timestamp_lo_us); 1673 pdev->timestamp.sync_timestamp_hi_us = __le32_to_cpu(msg->sync_timestamp_hi_us); 1674 pdev->timestamp.mlo_offset_lo = __le32_to_cpu(msg->mlo_offset_lo); 1675 pdev->timestamp.mlo_offset_hi = __le32_to_cpu(msg->mlo_offset_hi); 1676 pdev->timestamp.mlo_offset_clks = __le32_to_cpu(msg->mlo_offset_clks); 1677 pdev->timestamp.mlo_comp_clks = __le32_to_cpu(msg->mlo_comp_clks); 1678 pdev->timestamp.mlo_comp_timer = __le32_to_cpu(msg->mlo_comp_timer); 1679 1680 spin_unlock_bh(&ar->data_lock); 1681 } 1682 1683 void ath12k_dp_htt_htc_t2h_msg_handler(struct ath12k_base *ab, 1684 struct sk_buff *skb) 1685 { 1686 struct ath12k_dp *dp = &ab->dp; 1687 struct htt_resp_msg *resp = (struct htt_resp_msg *)skb->data; 1688 enum htt_t2h_msg_type type; 1689 u16 peer_id; 1690 u8 vdev_id; 1691 u8 mac_addr[ETH_ALEN]; 1692 u16 peer_mac_h16; 1693 u16 ast_hash = 0; 1694 u16 hw_peer_id; 1695 1696 type = le32_get_bits(resp->version_msg.version, HTT_T2H_MSG_TYPE); 1697 1698 ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt rx msg type :0x%0x\n", type); 1699 1700 switch (type) { 1701 case HTT_T2H_MSG_TYPE_VERSION_CONF: 1702 dp->htt_tgt_ver_major = le32_get_bits(resp->version_msg.version, 1703 HTT_T2H_VERSION_CONF_MAJOR); 1704 dp->htt_tgt_ver_minor = le32_get_bits(resp->version_msg.version, 1705 HTT_T2H_VERSION_CONF_MINOR); 1706 complete(&dp->htt_tgt_version_received); 1707 break; 1708 /* TODO: remove unused peer map versions after testing */ 1709 case HTT_T2H_MSG_TYPE_PEER_MAP: 1710 vdev_id = le32_get_bits(resp->peer_map_ev.info, 1711 HTT_T2H_PEER_MAP_INFO_VDEV_ID); 1712 peer_id = le32_get_bits(resp->peer_map_ev.info, 1713 HTT_T2H_PEER_MAP_INFO_PEER_ID); 1714 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1, 1715 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16); 1716 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32), 1717 peer_mac_h16, mac_addr); 1718 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, 0, 0); 1719 break; 1720 case HTT_T2H_MSG_TYPE_PEER_MAP2: 1721 vdev_id = le32_get_bits(resp->peer_map_ev.info, 1722 HTT_T2H_PEER_MAP_INFO_VDEV_ID); 1723 peer_id = le32_get_bits(resp->peer_map_ev.info, 1724 HTT_T2H_PEER_MAP_INFO_PEER_ID); 1725 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1, 1726 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16); 1727 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32), 1728 peer_mac_h16, mac_addr); 1729 ast_hash = le32_get_bits(resp->peer_map_ev.info2, 1730 HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL); 1731 hw_peer_id = le32_get_bits(resp->peer_map_ev.info1, 1732 HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID); 1733 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash, 1734 hw_peer_id); 1735 break; 1736 case HTT_T2H_MSG_TYPE_PEER_MAP3: 1737 vdev_id = le32_get_bits(resp->peer_map_ev.info, 1738 HTT_T2H_PEER_MAP_INFO_VDEV_ID); 1739 peer_id = le32_get_bits(resp->peer_map_ev.info, 1740 HTT_T2H_PEER_MAP_INFO_PEER_ID); 1741 peer_mac_h16 = le32_get_bits(resp->peer_map_ev.info1, 1742 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16); 1743 ath12k_dp_get_mac_addr(le32_to_cpu(resp->peer_map_ev.mac_addr_l32), 1744 peer_mac_h16, mac_addr); 1745 ath12k_peer_map_event(ab, vdev_id, peer_id, mac_addr, ast_hash, 1746 peer_id); 1747 break; 1748 case HTT_T2H_MSG_TYPE_PEER_UNMAP: 1749 case HTT_T2H_MSG_TYPE_PEER_UNMAP2: 1750 peer_id = le32_get_bits(resp->peer_unmap_ev.info, 1751 HTT_T2H_PEER_UNMAP_INFO_PEER_ID); 1752 ath12k_peer_unmap_event(ab, peer_id); 1753 break; 1754 case HTT_T2H_MSG_TYPE_PPDU_STATS_IND: 1755 ath12k_htt_pull_ppdu_stats(ab, skb); 1756 break; 1757 case HTT_T2H_MSG_TYPE_EXT_STATS_CONF: 1758 break; 1759 case HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND: 1760 ath12k_htt_mlo_offset_event_handler(ab, skb); 1761 break; 1762 default: 1763 ath12k_dbg(ab, ATH12K_DBG_DP_HTT, "dp_htt event %d not handled\n", 1764 type); 1765 break; 1766 } 1767 1768 dev_kfree_skb_any(skb); 1769 } 1770 1771 static int ath12k_dp_rx_msdu_coalesce(struct ath12k *ar, 1772 struct sk_buff_head *msdu_list, 1773 struct sk_buff *first, struct sk_buff *last, 1774 u8 l3pad_bytes, int msdu_len) 1775 { 1776 struct ath12k_base *ab = ar->ab; 1777 struct sk_buff *skb; 1778 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(first); 1779 int buf_first_hdr_len, buf_first_len; 1780 struct hal_rx_desc *ldesc; 1781 int space_extra, rem_len, buf_len; 1782 u32 hal_rx_desc_sz = ar->ab->hw_params->hal_desc_sz; 1783 1784 /* As the msdu is spread across multiple rx buffers, 1785 * find the offset to the start of msdu for computing 1786 * the length of the msdu in the first buffer. 1787 */ 1788 buf_first_hdr_len = hal_rx_desc_sz + l3pad_bytes; 1789 buf_first_len = DP_RX_BUFFER_SIZE - buf_first_hdr_len; 1790 1791 if (WARN_ON_ONCE(msdu_len <= buf_first_len)) { 1792 skb_put(first, buf_first_hdr_len + msdu_len); 1793 skb_pull(first, buf_first_hdr_len); 1794 return 0; 1795 } 1796 1797 ldesc = (struct hal_rx_desc *)last->data; 1798 rxcb->is_first_msdu = ath12k_dp_rx_h_first_msdu(ab, ldesc); 1799 rxcb->is_last_msdu = ath12k_dp_rx_h_last_msdu(ab, ldesc); 1800 1801 /* MSDU spans over multiple buffers because the length of the MSDU 1802 * exceeds DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. So assume the data 1803 * in the first buf is of length DP_RX_BUFFER_SIZE - HAL_RX_DESC_SIZE. 1804 */ 1805 skb_put(first, DP_RX_BUFFER_SIZE); 1806 skb_pull(first, buf_first_hdr_len); 1807 1808 /* When an MSDU spread over multiple buffers MSDU_END 1809 * tlvs are valid only in the last buffer. Copy those tlvs. 1810 */ 1811 ath12k_dp_rx_desc_end_tlv_copy(ab, rxcb->rx_desc, ldesc); 1812 1813 space_extra = msdu_len - (buf_first_len + skb_tailroom(first)); 1814 if (space_extra > 0 && 1815 (pskb_expand_head(first, 0, space_extra, GFP_ATOMIC) < 0)) { 1816 /* Free up all buffers of the MSDU */ 1817 while ((skb = __skb_dequeue(msdu_list)) != NULL) { 1818 rxcb = ATH12K_SKB_RXCB(skb); 1819 if (!rxcb->is_continuation) { 1820 dev_kfree_skb_any(skb); 1821 break; 1822 } 1823 dev_kfree_skb_any(skb); 1824 } 1825 return -ENOMEM; 1826 } 1827 1828 rem_len = msdu_len - buf_first_len; 1829 while ((skb = __skb_dequeue(msdu_list)) != NULL && rem_len > 0) { 1830 rxcb = ATH12K_SKB_RXCB(skb); 1831 if (rxcb->is_continuation) 1832 buf_len = DP_RX_BUFFER_SIZE - hal_rx_desc_sz; 1833 else 1834 buf_len = rem_len; 1835 1836 if (buf_len > (DP_RX_BUFFER_SIZE - hal_rx_desc_sz)) { 1837 WARN_ON_ONCE(1); 1838 dev_kfree_skb_any(skb); 1839 return -EINVAL; 1840 } 1841 1842 skb_put(skb, buf_len + hal_rx_desc_sz); 1843 skb_pull(skb, hal_rx_desc_sz); 1844 skb_copy_from_linear_data(skb, skb_put(first, buf_len), 1845 buf_len); 1846 dev_kfree_skb_any(skb); 1847 1848 rem_len -= buf_len; 1849 if (!rxcb->is_continuation) 1850 break; 1851 } 1852 1853 return 0; 1854 } 1855 1856 static struct sk_buff *ath12k_dp_rx_get_msdu_last_buf(struct sk_buff_head *msdu_list, 1857 struct sk_buff *first) 1858 { 1859 struct sk_buff *skb; 1860 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(first); 1861 1862 if (!rxcb->is_continuation) 1863 return first; 1864 1865 skb_queue_walk(msdu_list, skb) { 1866 rxcb = ATH12K_SKB_RXCB(skb); 1867 if (!rxcb->is_continuation) 1868 return skb; 1869 } 1870 1871 return NULL; 1872 } 1873 1874 static void ath12k_dp_rx_h_csum_offload(struct ath12k *ar, struct sk_buff *msdu) 1875 { 1876 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 1877 struct ath12k_base *ab = ar->ab; 1878 bool ip_csum_fail, l4_csum_fail; 1879 1880 ip_csum_fail = ath12k_dp_rx_h_ip_cksum_fail(ab, rxcb->rx_desc); 1881 l4_csum_fail = ath12k_dp_rx_h_l4_cksum_fail(ab, rxcb->rx_desc); 1882 1883 msdu->ip_summed = (ip_csum_fail || l4_csum_fail) ? 1884 CHECKSUM_NONE : CHECKSUM_UNNECESSARY; 1885 } 1886 1887 static int ath12k_dp_rx_crypto_mic_len(struct ath12k *ar, 1888 enum hal_encrypt_type enctype) 1889 { 1890 switch (enctype) { 1891 case HAL_ENCRYPT_TYPE_OPEN: 1892 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1893 case HAL_ENCRYPT_TYPE_TKIP_MIC: 1894 return 0; 1895 case HAL_ENCRYPT_TYPE_CCMP_128: 1896 return IEEE80211_CCMP_MIC_LEN; 1897 case HAL_ENCRYPT_TYPE_CCMP_256: 1898 return IEEE80211_CCMP_256_MIC_LEN; 1899 case HAL_ENCRYPT_TYPE_GCMP_128: 1900 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1901 return IEEE80211_GCMP_MIC_LEN; 1902 case HAL_ENCRYPT_TYPE_WEP_40: 1903 case HAL_ENCRYPT_TYPE_WEP_104: 1904 case HAL_ENCRYPT_TYPE_WEP_128: 1905 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1906 case HAL_ENCRYPT_TYPE_WAPI: 1907 break; 1908 } 1909 1910 ath12k_warn(ar->ab, "unsupported encryption type %d for mic len\n", enctype); 1911 return 0; 1912 } 1913 1914 static int ath12k_dp_rx_crypto_param_len(struct ath12k *ar, 1915 enum hal_encrypt_type enctype) 1916 { 1917 switch (enctype) { 1918 case HAL_ENCRYPT_TYPE_OPEN: 1919 return 0; 1920 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1921 case HAL_ENCRYPT_TYPE_TKIP_MIC: 1922 return IEEE80211_TKIP_IV_LEN; 1923 case HAL_ENCRYPT_TYPE_CCMP_128: 1924 return IEEE80211_CCMP_HDR_LEN; 1925 case HAL_ENCRYPT_TYPE_CCMP_256: 1926 return IEEE80211_CCMP_256_HDR_LEN; 1927 case HAL_ENCRYPT_TYPE_GCMP_128: 1928 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1929 return IEEE80211_GCMP_HDR_LEN; 1930 case HAL_ENCRYPT_TYPE_WEP_40: 1931 case HAL_ENCRYPT_TYPE_WEP_104: 1932 case HAL_ENCRYPT_TYPE_WEP_128: 1933 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1934 case HAL_ENCRYPT_TYPE_WAPI: 1935 break; 1936 } 1937 1938 ath12k_warn(ar->ab, "unsupported encryption type %d\n", enctype); 1939 return 0; 1940 } 1941 1942 static int ath12k_dp_rx_crypto_icv_len(struct ath12k *ar, 1943 enum hal_encrypt_type enctype) 1944 { 1945 switch (enctype) { 1946 case HAL_ENCRYPT_TYPE_OPEN: 1947 case HAL_ENCRYPT_TYPE_CCMP_128: 1948 case HAL_ENCRYPT_TYPE_CCMP_256: 1949 case HAL_ENCRYPT_TYPE_GCMP_128: 1950 case HAL_ENCRYPT_TYPE_AES_GCMP_256: 1951 return 0; 1952 case HAL_ENCRYPT_TYPE_TKIP_NO_MIC: 1953 case HAL_ENCRYPT_TYPE_TKIP_MIC: 1954 return IEEE80211_TKIP_ICV_LEN; 1955 case HAL_ENCRYPT_TYPE_WEP_40: 1956 case HAL_ENCRYPT_TYPE_WEP_104: 1957 case HAL_ENCRYPT_TYPE_WEP_128: 1958 case HAL_ENCRYPT_TYPE_WAPI_GCM_SM4: 1959 case HAL_ENCRYPT_TYPE_WAPI: 1960 break; 1961 } 1962 1963 ath12k_warn(ar->ab, "unsupported encryption type %d\n", enctype); 1964 return 0; 1965 } 1966 1967 static void ath12k_dp_rx_h_undecap_nwifi(struct ath12k *ar, 1968 struct sk_buff *msdu, 1969 enum hal_encrypt_type enctype, 1970 struct ieee80211_rx_status *status) 1971 { 1972 struct ath12k_base *ab = ar->ab; 1973 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 1974 u8 decap_hdr[DP_MAX_NWIFI_HDR_LEN]; 1975 struct ieee80211_hdr *hdr; 1976 size_t hdr_len; 1977 u8 *crypto_hdr; 1978 u16 qos_ctl; 1979 1980 /* pull decapped header */ 1981 hdr = (struct ieee80211_hdr *)msdu->data; 1982 hdr_len = ieee80211_hdrlen(hdr->frame_control); 1983 skb_pull(msdu, hdr_len); 1984 1985 /* Rebuild qos header */ 1986 hdr->frame_control |= __cpu_to_le16(IEEE80211_STYPE_QOS_DATA); 1987 1988 /* Reset the order bit as the HT_Control header is stripped */ 1989 hdr->frame_control &= ~(__cpu_to_le16(IEEE80211_FCTL_ORDER)); 1990 1991 qos_ctl = rxcb->tid; 1992 1993 if (ath12k_dp_rx_h_mesh_ctl_present(ab, rxcb->rx_desc)) 1994 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT; 1995 1996 /* TODO: Add other QoS ctl fields when required */ 1997 1998 /* copy decap header before overwriting for reuse below */ 1999 memcpy(decap_hdr, hdr, hdr_len); 2000 2001 /* Rebuild crypto header for mac80211 use */ 2002 if (!(status->flag & RX_FLAG_IV_STRIPPED)) { 2003 crypto_hdr = skb_push(msdu, ath12k_dp_rx_crypto_param_len(ar, enctype)); 2004 ath12k_dp_rx_desc_get_crypto_header(ar->ab, 2005 rxcb->rx_desc, crypto_hdr, 2006 enctype); 2007 } 2008 2009 memcpy(skb_push(msdu, 2010 IEEE80211_QOS_CTL_LEN), &qos_ctl, 2011 IEEE80211_QOS_CTL_LEN); 2012 memcpy(skb_push(msdu, hdr_len), decap_hdr, hdr_len); 2013 } 2014 2015 static void ath12k_dp_rx_h_undecap_raw(struct ath12k *ar, struct sk_buff *msdu, 2016 enum hal_encrypt_type enctype, 2017 struct ieee80211_rx_status *status, 2018 bool decrypted) 2019 { 2020 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2021 struct ieee80211_hdr *hdr; 2022 size_t hdr_len; 2023 size_t crypto_len; 2024 2025 if (!rxcb->is_first_msdu || 2026 !(rxcb->is_first_msdu && rxcb->is_last_msdu)) { 2027 WARN_ON_ONCE(1); 2028 return; 2029 } 2030 2031 skb_trim(msdu, msdu->len - FCS_LEN); 2032 2033 if (!decrypted) 2034 return; 2035 2036 hdr = (void *)msdu->data; 2037 2038 /* Tail */ 2039 if (status->flag & RX_FLAG_IV_STRIPPED) { 2040 skb_trim(msdu, msdu->len - 2041 ath12k_dp_rx_crypto_mic_len(ar, enctype)); 2042 2043 skb_trim(msdu, msdu->len - 2044 ath12k_dp_rx_crypto_icv_len(ar, enctype)); 2045 } else { 2046 /* MIC */ 2047 if (status->flag & RX_FLAG_MIC_STRIPPED) 2048 skb_trim(msdu, msdu->len - 2049 ath12k_dp_rx_crypto_mic_len(ar, enctype)); 2050 2051 /* ICV */ 2052 if (status->flag & RX_FLAG_ICV_STRIPPED) 2053 skb_trim(msdu, msdu->len - 2054 ath12k_dp_rx_crypto_icv_len(ar, enctype)); 2055 } 2056 2057 /* MMIC */ 2058 if ((status->flag & RX_FLAG_MMIC_STRIPPED) && 2059 !ieee80211_has_morefrags(hdr->frame_control) && 2060 enctype == HAL_ENCRYPT_TYPE_TKIP_MIC) 2061 skb_trim(msdu, msdu->len - IEEE80211_CCMP_MIC_LEN); 2062 2063 /* Head */ 2064 if (status->flag & RX_FLAG_IV_STRIPPED) { 2065 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2066 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype); 2067 2068 memmove(msdu->data + crypto_len, msdu->data, hdr_len); 2069 skb_pull(msdu, crypto_len); 2070 } 2071 } 2072 2073 static void ath12k_get_dot11_hdr_from_rx_desc(struct ath12k *ar, 2074 struct sk_buff *msdu, 2075 struct ath12k_skb_rxcb *rxcb, 2076 struct ieee80211_rx_status *status, 2077 enum hal_encrypt_type enctype) 2078 { 2079 struct hal_rx_desc *rx_desc = rxcb->rx_desc; 2080 struct ath12k_base *ab = ar->ab; 2081 size_t hdr_len, crypto_len; 2082 struct ieee80211_hdr *hdr; 2083 u16 qos_ctl; 2084 __le16 fc; 2085 u8 *crypto_hdr; 2086 2087 if (!(status->flag & RX_FLAG_IV_STRIPPED)) { 2088 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype); 2089 crypto_hdr = skb_push(msdu, crypto_len); 2090 ath12k_dp_rx_desc_get_crypto_header(ab, rx_desc, crypto_hdr, enctype); 2091 } 2092 2093 fc = cpu_to_le16(ath12k_dp_rxdesc_get_mpdu_frame_ctrl(ab, rx_desc)); 2094 hdr_len = ieee80211_hdrlen(fc); 2095 skb_push(msdu, hdr_len); 2096 hdr = (struct ieee80211_hdr *)msdu->data; 2097 hdr->frame_control = fc; 2098 2099 /* Get wifi header from rx_desc */ 2100 ath12k_dp_rx_desc_get_dot11_hdr(ab, rx_desc, hdr); 2101 2102 if (rxcb->is_mcbc) 2103 status->flag &= ~RX_FLAG_PN_VALIDATED; 2104 2105 /* Add QOS header */ 2106 if (ieee80211_is_data_qos(hdr->frame_control)) { 2107 qos_ctl = rxcb->tid; 2108 if (ath12k_dp_rx_h_mesh_ctl_present(ab, rx_desc)) 2109 qos_ctl |= IEEE80211_QOS_CTL_MESH_CONTROL_PRESENT; 2110 2111 /* TODO: Add other QoS ctl fields when required */ 2112 memcpy(msdu->data + (hdr_len - IEEE80211_QOS_CTL_LEN), 2113 &qos_ctl, IEEE80211_QOS_CTL_LEN); 2114 } 2115 } 2116 2117 static void ath12k_dp_rx_h_undecap_eth(struct ath12k *ar, 2118 struct sk_buff *msdu, 2119 enum hal_encrypt_type enctype, 2120 struct ieee80211_rx_status *status) 2121 { 2122 struct ieee80211_hdr *hdr; 2123 struct ethhdr *eth; 2124 u8 da[ETH_ALEN]; 2125 u8 sa[ETH_ALEN]; 2126 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2127 struct ath12k_dp_rx_rfc1042_hdr rfc = {0xaa, 0xaa, 0x03, {0x00, 0x00, 0x00}}; 2128 2129 eth = (struct ethhdr *)msdu->data; 2130 ether_addr_copy(da, eth->h_dest); 2131 ether_addr_copy(sa, eth->h_source); 2132 rfc.snap_type = eth->h_proto; 2133 skb_pull(msdu, sizeof(*eth)); 2134 memcpy(skb_push(msdu, sizeof(rfc)), &rfc, 2135 sizeof(rfc)); 2136 ath12k_get_dot11_hdr_from_rx_desc(ar, msdu, rxcb, status, enctype); 2137 2138 /* original 802.11 header has a different DA and in 2139 * case of 4addr it may also have different SA 2140 */ 2141 hdr = (struct ieee80211_hdr *)msdu->data; 2142 ether_addr_copy(ieee80211_get_DA(hdr), da); 2143 ether_addr_copy(ieee80211_get_SA(hdr), sa); 2144 } 2145 2146 static void ath12k_dp_rx_h_undecap(struct ath12k *ar, struct sk_buff *msdu, 2147 struct hal_rx_desc *rx_desc, 2148 enum hal_encrypt_type enctype, 2149 struct ieee80211_rx_status *status, 2150 bool decrypted) 2151 { 2152 struct ath12k_base *ab = ar->ab; 2153 u8 decap; 2154 struct ethhdr *ehdr; 2155 2156 decap = ath12k_dp_rx_h_decap_type(ab, rx_desc); 2157 2158 switch (decap) { 2159 case DP_RX_DECAP_TYPE_NATIVE_WIFI: 2160 ath12k_dp_rx_h_undecap_nwifi(ar, msdu, enctype, status); 2161 break; 2162 case DP_RX_DECAP_TYPE_RAW: 2163 ath12k_dp_rx_h_undecap_raw(ar, msdu, enctype, status, 2164 decrypted); 2165 break; 2166 case DP_RX_DECAP_TYPE_ETHERNET2_DIX: 2167 ehdr = (struct ethhdr *)msdu->data; 2168 2169 /* mac80211 allows fast path only for authorized STA */ 2170 if (ehdr->h_proto == cpu_to_be16(ETH_P_PAE)) { 2171 ATH12K_SKB_RXCB(msdu)->is_eapol = true; 2172 ath12k_dp_rx_h_undecap_eth(ar, msdu, enctype, status); 2173 break; 2174 } 2175 2176 /* PN for mcast packets will be validated in mac80211; 2177 * remove eth header and add 802.11 header. 2178 */ 2179 if (ATH12K_SKB_RXCB(msdu)->is_mcbc && decrypted) 2180 ath12k_dp_rx_h_undecap_eth(ar, msdu, enctype, status); 2181 break; 2182 case DP_RX_DECAP_TYPE_8023: 2183 /* TODO: Handle undecap for these formats */ 2184 break; 2185 } 2186 } 2187 2188 struct ath12k_peer * 2189 ath12k_dp_rx_h_find_peer(struct ath12k_base *ab, struct sk_buff *msdu) 2190 { 2191 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2192 struct hal_rx_desc *rx_desc = rxcb->rx_desc; 2193 struct ath12k_peer *peer = NULL; 2194 2195 lockdep_assert_held(&ab->base_lock); 2196 2197 if (rxcb->peer_id) 2198 peer = ath12k_peer_find_by_id(ab, rxcb->peer_id); 2199 2200 if (peer) 2201 return peer; 2202 2203 if (!rx_desc || !(ath12k_dp_rxdesc_mac_addr2_valid(ab, rx_desc))) 2204 return NULL; 2205 2206 peer = ath12k_peer_find_by_addr(ab, 2207 ath12k_dp_rxdesc_get_mpdu_start_addr2(ab, 2208 rx_desc)); 2209 return peer; 2210 } 2211 2212 static void ath12k_dp_rx_h_mpdu(struct ath12k *ar, 2213 struct sk_buff *msdu, 2214 struct hal_rx_desc *rx_desc, 2215 struct ieee80211_rx_status *rx_status) 2216 { 2217 bool fill_crypto_hdr; 2218 struct ath12k_base *ab = ar->ab; 2219 struct ath12k_skb_rxcb *rxcb; 2220 enum hal_encrypt_type enctype; 2221 bool is_decrypted = false; 2222 struct ieee80211_hdr *hdr; 2223 struct ath12k_peer *peer; 2224 u32 err_bitmap; 2225 2226 /* PN for multicast packets will be checked in mac80211 */ 2227 rxcb = ATH12K_SKB_RXCB(msdu); 2228 fill_crypto_hdr = ath12k_dp_rx_h_is_da_mcbc(ar->ab, rx_desc); 2229 rxcb->is_mcbc = fill_crypto_hdr; 2230 2231 if (rxcb->is_mcbc) 2232 rxcb->peer_id = ath12k_dp_rx_h_peer_id(ar->ab, rx_desc); 2233 2234 spin_lock_bh(&ar->ab->base_lock); 2235 peer = ath12k_dp_rx_h_find_peer(ar->ab, msdu); 2236 if (peer) { 2237 if (rxcb->is_mcbc) 2238 enctype = peer->sec_type_grp; 2239 else 2240 enctype = peer->sec_type; 2241 } else { 2242 enctype = HAL_ENCRYPT_TYPE_OPEN; 2243 } 2244 spin_unlock_bh(&ar->ab->base_lock); 2245 2246 err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc); 2247 if (enctype != HAL_ENCRYPT_TYPE_OPEN && !err_bitmap) 2248 is_decrypted = ath12k_dp_rx_h_is_decrypted(ab, rx_desc); 2249 2250 /* Clear per-MPDU flags while leaving per-PPDU flags intact */ 2251 rx_status->flag &= ~(RX_FLAG_FAILED_FCS_CRC | 2252 RX_FLAG_MMIC_ERROR | 2253 RX_FLAG_DECRYPTED | 2254 RX_FLAG_IV_STRIPPED | 2255 RX_FLAG_MMIC_STRIPPED); 2256 2257 if (err_bitmap & HAL_RX_MPDU_ERR_FCS) 2258 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; 2259 if (err_bitmap & HAL_RX_MPDU_ERR_TKIP_MIC) 2260 rx_status->flag |= RX_FLAG_MMIC_ERROR; 2261 2262 if (is_decrypted) { 2263 rx_status->flag |= RX_FLAG_DECRYPTED | RX_FLAG_MMIC_STRIPPED; 2264 2265 if (fill_crypto_hdr) 2266 rx_status->flag |= RX_FLAG_MIC_STRIPPED | 2267 RX_FLAG_ICV_STRIPPED; 2268 else 2269 rx_status->flag |= RX_FLAG_IV_STRIPPED | 2270 RX_FLAG_PN_VALIDATED; 2271 } 2272 2273 ath12k_dp_rx_h_csum_offload(ar, msdu); 2274 ath12k_dp_rx_h_undecap(ar, msdu, rx_desc, 2275 enctype, rx_status, is_decrypted); 2276 2277 if (!is_decrypted || fill_crypto_hdr) 2278 return; 2279 2280 if (ath12k_dp_rx_h_decap_type(ar->ab, rx_desc) != 2281 DP_RX_DECAP_TYPE_ETHERNET2_DIX) { 2282 hdr = (void *)msdu->data; 2283 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_PROTECTED); 2284 } 2285 } 2286 2287 static void ath12k_dp_rx_h_rate(struct ath12k *ar, struct hal_rx_desc *rx_desc, 2288 struct ieee80211_rx_status *rx_status) 2289 { 2290 struct ath12k_base *ab = ar->ab; 2291 struct ieee80211_supported_band *sband; 2292 enum rx_msdu_start_pkt_type pkt_type; 2293 u8 bw; 2294 u8 rate_mcs, nss; 2295 u8 sgi; 2296 bool is_cck; 2297 2298 pkt_type = ath12k_dp_rx_h_pkt_type(ab, rx_desc); 2299 bw = ath12k_dp_rx_h_rx_bw(ab, rx_desc); 2300 rate_mcs = ath12k_dp_rx_h_rate_mcs(ab, rx_desc); 2301 nss = ath12k_dp_rx_h_nss(ab, rx_desc); 2302 sgi = ath12k_dp_rx_h_sgi(ab, rx_desc); 2303 2304 switch (pkt_type) { 2305 case RX_MSDU_START_PKT_TYPE_11A: 2306 case RX_MSDU_START_PKT_TYPE_11B: 2307 is_cck = (pkt_type == RX_MSDU_START_PKT_TYPE_11B); 2308 sband = &ar->mac.sbands[rx_status->band]; 2309 rx_status->rate_idx = ath12k_mac_hw_rate_to_idx(sband, rate_mcs, 2310 is_cck); 2311 break; 2312 case RX_MSDU_START_PKT_TYPE_11N: 2313 rx_status->encoding = RX_ENC_HT; 2314 if (rate_mcs > ATH12K_HT_MCS_MAX) { 2315 ath12k_warn(ar->ab, 2316 "Received with invalid mcs in HT mode %d\n", 2317 rate_mcs); 2318 break; 2319 } 2320 rx_status->rate_idx = rate_mcs + (8 * (nss - 1)); 2321 if (sgi) 2322 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2323 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 2324 break; 2325 case RX_MSDU_START_PKT_TYPE_11AC: 2326 rx_status->encoding = RX_ENC_VHT; 2327 rx_status->rate_idx = rate_mcs; 2328 if (rate_mcs > ATH12K_VHT_MCS_MAX) { 2329 ath12k_warn(ar->ab, 2330 "Received with invalid mcs in VHT mode %d\n", 2331 rate_mcs); 2332 break; 2333 } 2334 rx_status->nss = nss; 2335 if (sgi) 2336 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI; 2337 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 2338 break; 2339 case RX_MSDU_START_PKT_TYPE_11AX: 2340 rx_status->rate_idx = rate_mcs; 2341 if (rate_mcs > ATH12K_HE_MCS_MAX) { 2342 ath12k_warn(ar->ab, 2343 "Received with invalid mcs in HE mode %d\n", 2344 rate_mcs); 2345 break; 2346 } 2347 rx_status->encoding = RX_ENC_HE; 2348 rx_status->nss = nss; 2349 rx_status->he_gi = ath12k_he_gi_to_nl80211_he_gi(sgi); 2350 rx_status->bw = ath12k_mac_bw_to_mac80211_bw(bw); 2351 break; 2352 } 2353 } 2354 2355 void ath12k_dp_rx_h_ppdu(struct ath12k *ar, struct hal_rx_desc *rx_desc, 2356 struct ieee80211_rx_status *rx_status) 2357 { 2358 struct ath12k_base *ab = ar->ab; 2359 u8 channel_num; 2360 u32 center_freq, meta_data; 2361 struct ieee80211_channel *channel; 2362 2363 rx_status->freq = 0; 2364 rx_status->rate_idx = 0; 2365 rx_status->nss = 0; 2366 rx_status->encoding = RX_ENC_LEGACY; 2367 rx_status->bw = RATE_INFO_BW_20; 2368 rx_status->enc_flags = 0; 2369 2370 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL; 2371 2372 meta_data = ath12k_dp_rx_h_freq(ab, rx_desc); 2373 channel_num = meta_data; 2374 center_freq = meta_data >> 16; 2375 2376 if (center_freq >= 5935 && center_freq <= 7105) { 2377 rx_status->band = NL80211_BAND_6GHZ; 2378 } else if (channel_num >= 1 && channel_num <= 14) { 2379 rx_status->band = NL80211_BAND_2GHZ; 2380 } else if (channel_num >= 36 && channel_num <= 173) { 2381 rx_status->band = NL80211_BAND_5GHZ; 2382 } else { 2383 spin_lock_bh(&ar->data_lock); 2384 channel = ar->rx_channel; 2385 if (channel) { 2386 rx_status->band = channel->band; 2387 channel_num = 2388 ieee80211_frequency_to_channel(channel->center_freq); 2389 } 2390 spin_unlock_bh(&ar->data_lock); 2391 ath12k_dbg_dump(ar->ab, ATH12K_DBG_DATA, NULL, "rx_desc: ", 2392 rx_desc, sizeof(*rx_desc)); 2393 } 2394 2395 rx_status->freq = ieee80211_channel_to_frequency(channel_num, 2396 rx_status->band); 2397 2398 ath12k_dp_rx_h_rate(ar, rx_desc, rx_status); 2399 } 2400 2401 static void ath12k_dp_rx_deliver_msdu(struct ath12k *ar, struct napi_struct *napi, 2402 struct sk_buff *msdu, 2403 struct ieee80211_rx_status *status) 2404 { 2405 struct ath12k_base *ab = ar->ab; 2406 static const struct ieee80211_radiotap_he known = { 2407 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 2408 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 2409 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 2410 }; 2411 struct ieee80211_radiotap_he *he; 2412 struct ieee80211_rx_status *rx_status; 2413 struct ieee80211_sta *pubsta; 2414 struct ath12k_peer *peer; 2415 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 2416 u8 decap = DP_RX_DECAP_TYPE_RAW; 2417 bool is_mcbc = rxcb->is_mcbc; 2418 bool is_eapol = rxcb->is_eapol; 2419 2420 if (status->encoding == RX_ENC_HE && !(status->flag & RX_FLAG_RADIOTAP_HE) && 2421 !(status->flag & RX_FLAG_SKIP_MONITOR)) { 2422 he = skb_push(msdu, sizeof(known)); 2423 memcpy(he, &known, sizeof(known)); 2424 status->flag |= RX_FLAG_RADIOTAP_HE; 2425 } 2426 2427 if (!(status->flag & RX_FLAG_ONLY_MONITOR)) 2428 decap = ath12k_dp_rx_h_decap_type(ab, rxcb->rx_desc); 2429 2430 spin_lock_bh(&ab->base_lock); 2431 peer = ath12k_dp_rx_h_find_peer(ab, msdu); 2432 2433 pubsta = peer ? peer->sta : NULL; 2434 2435 spin_unlock_bh(&ab->base_lock); 2436 2437 ath12k_dbg(ab, ATH12K_DBG_DATA, 2438 "rx skb %pK len %u peer %pM %d %s sn %u %s%s%s%s%s%s%s%s rate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n", 2439 msdu, 2440 msdu->len, 2441 peer ? peer->addr : NULL, 2442 rxcb->tid, 2443 is_mcbc ? "mcast" : "ucast", 2444 ath12k_dp_rx_h_seq_no(ab, rxcb->rx_desc), 2445 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "", 2446 (status->encoding == RX_ENC_HT) ? "ht" : "", 2447 (status->encoding == RX_ENC_VHT) ? "vht" : "", 2448 (status->encoding == RX_ENC_HE) ? "he" : "", 2449 (status->bw == RATE_INFO_BW_40) ? "40" : "", 2450 (status->bw == RATE_INFO_BW_80) ? "80" : "", 2451 (status->bw == RATE_INFO_BW_160) ? "160" : "", 2452 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "", 2453 status->rate_idx, 2454 status->nss, 2455 status->freq, 2456 status->band, status->flag, 2457 !!(status->flag & RX_FLAG_FAILED_FCS_CRC), 2458 !!(status->flag & RX_FLAG_MMIC_ERROR), 2459 !!(status->flag & RX_FLAG_AMSDU_MORE)); 2460 2461 ath12k_dbg_dump(ab, ATH12K_DBG_DP_RX, NULL, "dp rx msdu: ", 2462 msdu->data, msdu->len); 2463 2464 rx_status = IEEE80211_SKB_RXCB(msdu); 2465 *rx_status = *status; 2466 2467 /* TODO: trace rx packet */ 2468 2469 /* PN for multicast packets are not validate in HW, 2470 * so skip 802.3 rx path 2471 * Also, fast_rx expects the STA to be authorized, hence 2472 * eapol packets are sent in slow path. 2473 */ 2474 if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol && 2475 !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED)) 2476 rx_status->flag |= RX_FLAG_8023; 2477 2478 ieee80211_rx_napi(ar->hw, pubsta, msdu, napi); 2479 } 2480 2481 static int ath12k_dp_rx_process_msdu(struct ath12k *ar, 2482 struct sk_buff *msdu, 2483 struct sk_buff_head *msdu_list, 2484 struct ieee80211_rx_status *rx_status) 2485 { 2486 struct ath12k_base *ab = ar->ab; 2487 struct hal_rx_desc *rx_desc, *lrx_desc; 2488 struct ath12k_skb_rxcb *rxcb; 2489 struct sk_buff *last_buf; 2490 u8 l3_pad_bytes; 2491 u16 msdu_len; 2492 int ret; 2493 u32 hal_rx_desc_sz = ar->ab->hw_params->hal_desc_sz; 2494 2495 last_buf = ath12k_dp_rx_get_msdu_last_buf(msdu_list, msdu); 2496 if (!last_buf) { 2497 ath12k_warn(ab, 2498 "No valid Rx buffer to access MSDU_END tlv\n"); 2499 ret = -EIO; 2500 goto free_out; 2501 } 2502 2503 rx_desc = (struct hal_rx_desc *)msdu->data; 2504 lrx_desc = (struct hal_rx_desc *)last_buf->data; 2505 if (!ath12k_dp_rx_h_msdu_done(ab, lrx_desc)) { 2506 ath12k_warn(ab, "msdu_done bit in msdu_end is not set\n"); 2507 ret = -EIO; 2508 goto free_out; 2509 } 2510 2511 rxcb = ATH12K_SKB_RXCB(msdu); 2512 rxcb->rx_desc = rx_desc; 2513 msdu_len = ath12k_dp_rx_h_msdu_len(ab, lrx_desc); 2514 l3_pad_bytes = ath12k_dp_rx_h_l3pad(ab, lrx_desc); 2515 2516 if (rxcb->is_frag) { 2517 skb_pull(msdu, hal_rx_desc_sz); 2518 } else if (!rxcb->is_continuation) { 2519 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) { 2520 ret = -EINVAL; 2521 ath12k_warn(ab, "invalid msdu len %u\n", msdu_len); 2522 ath12k_dbg_dump(ab, ATH12K_DBG_DATA, NULL, "", rx_desc, 2523 sizeof(*rx_desc)); 2524 goto free_out; 2525 } 2526 skb_put(msdu, hal_rx_desc_sz + l3_pad_bytes + msdu_len); 2527 skb_pull(msdu, hal_rx_desc_sz + l3_pad_bytes); 2528 } else { 2529 ret = ath12k_dp_rx_msdu_coalesce(ar, msdu_list, 2530 msdu, last_buf, 2531 l3_pad_bytes, msdu_len); 2532 if (ret) { 2533 ath12k_warn(ab, 2534 "failed to coalesce msdu rx buffer%d\n", ret); 2535 goto free_out; 2536 } 2537 } 2538 2539 ath12k_dp_rx_h_ppdu(ar, rx_desc, rx_status); 2540 ath12k_dp_rx_h_mpdu(ar, msdu, rx_desc, rx_status); 2541 2542 rx_status->flag |= RX_FLAG_SKIP_MONITOR | RX_FLAG_DUP_VALIDATED; 2543 2544 return 0; 2545 2546 free_out: 2547 return ret; 2548 } 2549 2550 static void ath12k_dp_rx_process_received_packets(struct ath12k_base *ab, 2551 struct napi_struct *napi, 2552 struct sk_buff_head *msdu_list, 2553 int ring_id) 2554 { 2555 struct ieee80211_rx_status rx_status = {0}; 2556 struct ath12k_skb_rxcb *rxcb; 2557 struct sk_buff *msdu; 2558 struct ath12k *ar; 2559 u8 mac_id, pdev_id; 2560 int ret; 2561 2562 if (skb_queue_empty(msdu_list)) 2563 return; 2564 2565 rcu_read_lock(); 2566 2567 while ((msdu = __skb_dequeue(msdu_list))) { 2568 rxcb = ATH12K_SKB_RXCB(msdu); 2569 mac_id = rxcb->mac_id; 2570 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id); 2571 ar = ab->pdevs[pdev_id].ar; 2572 if (!rcu_dereference(ab->pdevs_active[pdev_id])) { 2573 dev_kfree_skb_any(msdu); 2574 continue; 2575 } 2576 2577 if (test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) { 2578 dev_kfree_skb_any(msdu); 2579 continue; 2580 } 2581 2582 ret = ath12k_dp_rx_process_msdu(ar, msdu, msdu_list, &rx_status); 2583 if (ret) { 2584 ath12k_dbg(ab, ATH12K_DBG_DATA, 2585 "Unable to process msdu %d", ret); 2586 dev_kfree_skb_any(msdu); 2587 continue; 2588 } 2589 2590 ath12k_dp_rx_deliver_msdu(ar, napi, msdu, &rx_status); 2591 } 2592 2593 rcu_read_unlock(); 2594 } 2595 2596 int ath12k_dp_rx_process(struct ath12k_base *ab, int ring_id, 2597 struct napi_struct *napi, int budget) 2598 { 2599 struct ath12k_rx_desc_info *desc_info; 2600 struct ath12k_dp *dp = &ab->dp; 2601 struct dp_rxdma_ring *rx_ring = &dp->rx_refill_buf_ring; 2602 struct hal_reo_dest_ring *desc; 2603 int num_buffs_reaped = 0; 2604 struct sk_buff_head msdu_list; 2605 struct ath12k_skb_rxcb *rxcb; 2606 int total_msdu_reaped = 0; 2607 struct hal_srng *srng; 2608 struct sk_buff *msdu; 2609 bool done = false; 2610 int mac_id; 2611 u64 desc_va; 2612 2613 __skb_queue_head_init(&msdu_list); 2614 2615 srng = &ab->hal.srng_list[dp->reo_dst_ring[ring_id].ring_id]; 2616 2617 spin_lock_bh(&srng->lock); 2618 2619 try_again: 2620 ath12k_hal_srng_access_begin(ab, srng); 2621 2622 while ((desc = ath12k_hal_srng_dst_get_next_entry(ab, srng))) { 2623 enum hal_reo_dest_ring_push_reason push_reason; 2624 u32 cookie; 2625 2626 cookie = le32_get_bits(desc->buf_addr_info.info1, 2627 BUFFER_ADDR_INFO1_SW_COOKIE); 2628 2629 mac_id = le32_get_bits(desc->info0, 2630 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID); 2631 2632 desc_va = ((u64)le32_to_cpu(desc->buf_va_hi) << 32 | 2633 le32_to_cpu(desc->buf_va_lo)); 2634 desc_info = (struct ath12k_rx_desc_info *)((unsigned long)desc_va); 2635 2636 /* retry manual desc retrieval */ 2637 if (!desc_info) { 2638 desc_info = ath12k_dp_get_rx_desc(ab, cookie); 2639 if (!desc_info) { 2640 ath12k_warn(ab, "Invalid cookie in manual desc retrieval"); 2641 continue; 2642 } 2643 } 2644 2645 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC) 2646 ath12k_warn(ab, "Check HW CC implementation"); 2647 2648 msdu = desc_info->skb; 2649 desc_info->skb = NULL; 2650 2651 spin_lock_bh(&dp->rx_desc_lock); 2652 list_move_tail(&desc_info->list, &dp->rx_desc_free_list); 2653 spin_unlock_bh(&dp->rx_desc_lock); 2654 2655 rxcb = ATH12K_SKB_RXCB(msdu); 2656 dma_unmap_single(ab->dev, rxcb->paddr, 2657 msdu->len + skb_tailroom(msdu), 2658 DMA_FROM_DEVICE); 2659 2660 num_buffs_reaped++; 2661 2662 push_reason = le32_get_bits(desc->info0, 2663 HAL_REO_DEST_RING_INFO0_PUSH_REASON); 2664 if (push_reason != 2665 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) { 2666 dev_kfree_skb_any(msdu); 2667 ab->soc_stats.hal_reo_error[dp->reo_dst_ring[ring_id].ring_id]++; 2668 continue; 2669 } 2670 2671 rxcb->is_first_msdu = !!(le32_to_cpu(desc->rx_msdu_info.info0) & 2672 RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU); 2673 rxcb->is_last_msdu = !!(le32_to_cpu(desc->rx_msdu_info.info0) & 2674 RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU); 2675 rxcb->is_continuation = !!(le32_to_cpu(desc->rx_msdu_info.info0) & 2676 RX_MSDU_DESC_INFO0_MSDU_CONTINUATION); 2677 rxcb->mac_id = mac_id; 2678 rxcb->peer_id = le32_get_bits(desc->rx_mpdu_info.peer_meta_data, 2679 RX_MPDU_DESC_META_DATA_PEER_ID); 2680 rxcb->tid = le32_get_bits(desc->rx_mpdu_info.info0, 2681 RX_MPDU_DESC_INFO0_TID); 2682 2683 __skb_queue_tail(&msdu_list, msdu); 2684 2685 if (!rxcb->is_continuation) { 2686 total_msdu_reaped++; 2687 done = true; 2688 } else { 2689 done = false; 2690 } 2691 2692 if (total_msdu_reaped >= budget) 2693 break; 2694 } 2695 2696 /* Hw might have updated the head pointer after we cached it. 2697 * In this case, even though there are entries in the ring we'll 2698 * get rx_desc NULL. Give the read another try with updated cached 2699 * head pointer so that we can reap complete MPDU in the current 2700 * rx processing. 2701 */ 2702 if (!done && ath12k_hal_srng_dst_num_free(ab, srng, true)) { 2703 ath12k_hal_srng_access_end(ab, srng); 2704 goto try_again; 2705 } 2706 2707 ath12k_hal_srng_access_end(ab, srng); 2708 2709 spin_unlock_bh(&srng->lock); 2710 2711 if (!total_msdu_reaped) 2712 goto exit; 2713 2714 /* TODO: Move to implicit BM? */ 2715 ath12k_dp_rx_bufs_replenish(ab, 0, rx_ring, num_buffs_reaped, 2716 ab->hw_params->hal_params->rx_buf_rbm, true); 2717 2718 ath12k_dp_rx_process_received_packets(ab, napi, &msdu_list, 2719 ring_id); 2720 2721 exit: 2722 return total_msdu_reaped; 2723 } 2724 2725 static void ath12k_dp_rx_frag_timer(struct timer_list *timer) 2726 { 2727 struct ath12k_dp_rx_tid *rx_tid = from_timer(rx_tid, timer, frag_timer); 2728 2729 spin_lock_bh(&rx_tid->ab->base_lock); 2730 if (rx_tid->last_frag_no && 2731 rx_tid->rx_frag_bitmap == GENMASK(rx_tid->last_frag_no, 0)) { 2732 spin_unlock_bh(&rx_tid->ab->base_lock); 2733 return; 2734 } 2735 ath12k_dp_rx_frags_cleanup(rx_tid, true); 2736 spin_unlock_bh(&rx_tid->ab->base_lock); 2737 } 2738 2739 int ath12k_dp_rx_peer_frag_setup(struct ath12k *ar, const u8 *peer_mac, int vdev_id) 2740 { 2741 struct ath12k_base *ab = ar->ab; 2742 struct crypto_shash *tfm; 2743 struct ath12k_peer *peer; 2744 struct ath12k_dp_rx_tid *rx_tid; 2745 int i; 2746 2747 tfm = crypto_alloc_shash("michael_mic", 0, 0); 2748 if (IS_ERR(tfm)) 2749 return PTR_ERR(tfm); 2750 2751 spin_lock_bh(&ab->base_lock); 2752 2753 peer = ath12k_peer_find(ab, vdev_id, peer_mac); 2754 if (!peer) { 2755 spin_unlock_bh(&ab->base_lock); 2756 ath12k_warn(ab, "failed to find the peer to set up fragment info\n"); 2757 return -ENOENT; 2758 } 2759 2760 for (i = 0; i <= IEEE80211_NUM_TIDS; i++) { 2761 rx_tid = &peer->rx_tid[i]; 2762 rx_tid->ab = ab; 2763 timer_setup(&rx_tid->frag_timer, ath12k_dp_rx_frag_timer, 0); 2764 skb_queue_head_init(&rx_tid->rx_frags); 2765 } 2766 2767 peer->tfm_mmic = tfm; 2768 peer->dp_setup_done = true; 2769 spin_unlock_bh(&ab->base_lock); 2770 2771 return 0; 2772 } 2773 2774 static int ath12k_dp_rx_h_michael_mic(struct crypto_shash *tfm, u8 *key, 2775 struct ieee80211_hdr *hdr, u8 *data, 2776 size_t data_len, u8 *mic) 2777 { 2778 SHASH_DESC_ON_STACK(desc, tfm); 2779 u8 mic_hdr[16] = {0}; 2780 u8 tid = 0; 2781 int ret; 2782 2783 if (!tfm) 2784 return -EINVAL; 2785 2786 desc->tfm = tfm; 2787 2788 ret = crypto_shash_setkey(tfm, key, 8); 2789 if (ret) 2790 goto out; 2791 2792 ret = crypto_shash_init(desc); 2793 if (ret) 2794 goto out; 2795 2796 /* TKIP MIC header */ 2797 memcpy(mic_hdr, ieee80211_get_DA(hdr), ETH_ALEN); 2798 memcpy(mic_hdr + ETH_ALEN, ieee80211_get_SA(hdr), ETH_ALEN); 2799 if (ieee80211_is_data_qos(hdr->frame_control)) 2800 tid = ieee80211_get_tid(hdr); 2801 mic_hdr[12] = tid; 2802 2803 ret = crypto_shash_update(desc, mic_hdr, 16); 2804 if (ret) 2805 goto out; 2806 ret = crypto_shash_update(desc, data, data_len); 2807 if (ret) 2808 goto out; 2809 ret = crypto_shash_final(desc, mic); 2810 out: 2811 shash_desc_zero(desc); 2812 return ret; 2813 } 2814 2815 static int ath12k_dp_rx_h_verify_tkip_mic(struct ath12k *ar, struct ath12k_peer *peer, 2816 struct sk_buff *msdu) 2817 { 2818 struct ath12k_base *ab = ar->ab; 2819 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data; 2820 struct ieee80211_rx_status *rxs = IEEE80211_SKB_RXCB(msdu); 2821 struct ieee80211_key_conf *key_conf; 2822 struct ieee80211_hdr *hdr; 2823 u8 mic[IEEE80211_CCMP_MIC_LEN]; 2824 int head_len, tail_len, ret; 2825 size_t data_len; 2826 u32 hdr_len, hal_rx_desc_sz = ar->ab->hw_params->hal_desc_sz; 2827 u8 *key, *data; 2828 u8 key_idx; 2829 2830 if (ath12k_dp_rx_h_enctype(ab, rx_desc) != HAL_ENCRYPT_TYPE_TKIP_MIC) 2831 return 0; 2832 2833 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz); 2834 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2835 head_len = hdr_len + hal_rx_desc_sz + IEEE80211_TKIP_IV_LEN; 2836 tail_len = IEEE80211_CCMP_MIC_LEN + IEEE80211_TKIP_ICV_LEN + FCS_LEN; 2837 2838 if (!is_multicast_ether_addr(hdr->addr1)) 2839 key_idx = peer->ucast_keyidx; 2840 else 2841 key_idx = peer->mcast_keyidx; 2842 2843 key_conf = peer->keys[key_idx]; 2844 2845 data = msdu->data + head_len; 2846 data_len = msdu->len - head_len - tail_len; 2847 key = &key_conf->key[NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY]; 2848 2849 ret = ath12k_dp_rx_h_michael_mic(peer->tfm_mmic, key, hdr, data, data_len, mic); 2850 if (ret || memcmp(mic, data + data_len, IEEE80211_CCMP_MIC_LEN)) 2851 goto mic_fail; 2852 2853 return 0; 2854 2855 mic_fail: 2856 (ATH12K_SKB_RXCB(msdu))->is_first_msdu = true; 2857 (ATH12K_SKB_RXCB(msdu))->is_last_msdu = true; 2858 2859 rxs->flag |= RX_FLAG_MMIC_ERROR | RX_FLAG_MMIC_STRIPPED | 2860 RX_FLAG_IV_STRIPPED | RX_FLAG_DECRYPTED; 2861 skb_pull(msdu, hal_rx_desc_sz); 2862 2863 ath12k_dp_rx_h_ppdu(ar, rx_desc, rxs); 2864 ath12k_dp_rx_h_undecap(ar, msdu, rx_desc, 2865 HAL_ENCRYPT_TYPE_TKIP_MIC, rxs, true); 2866 ieee80211_rx(ar->hw, msdu); 2867 return -EINVAL; 2868 } 2869 2870 static void ath12k_dp_rx_h_undecap_frag(struct ath12k *ar, struct sk_buff *msdu, 2871 enum hal_encrypt_type enctype, u32 flags) 2872 { 2873 struct ieee80211_hdr *hdr; 2874 size_t hdr_len; 2875 size_t crypto_len; 2876 u32 hal_rx_desc_sz = ar->ab->hw_params->hal_desc_sz; 2877 2878 if (!flags) 2879 return; 2880 2881 hdr = (struct ieee80211_hdr *)(msdu->data + hal_rx_desc_sz); 2882 2883 if (flags & RX_FLAG_MIC_STRIPPED) 2884 skb_trim(msdu, msdu->len - 2885 ath12k_dp_rx_crypto_mic_len(ar, enctype)); 2886 2887 if (flags & RX_FLAG_ICV_STRIPPED) 2888 skb_trim(msdu, msdu->len - 2889 ath12k_dp_rx_crypto_icv_len(ar, enctype)); 2890 2891 if (flags & RX_FLAG_IV_STRIPPED) { 2892 hdr_len = ieee80211_hdrlen(hdr->frame_control); 2893 crypto_len = ath12k_dp_rx_crypto_param_len(ar, enctype); 2894 2895 memmove(msdu->data + hal_rx_desc_sz + crypto_len, 2896 msdu->data + hal_rx_desc_sz, hdr_len); 2897 skb_pull(msdu, crypto_len); 2898 } 2899 } 2900 2901 static int ath12k_dp_rx_h_defrag(struct ath12k *ar, 2902 struct ath12k_peer *peer, 2903 struct ath12k_dp_rx_tid *rx_tid, 2904 struct sk_buff **defrag_skb) 2905 { 2906 struct ath12k_base *ab = ar->ab; 2907 struct hal_rx_desc *rx_desc; 2908 struct sk_buff *skb, *first_frag, *last_frag; 2909 struct ieee80211_hdr *hdr; 2910 enum hal_encrypt_type enctype; 2911 bool is_decrypted = false; 2912 int msdu_len = 0; 2913 int extra_space; 2914 u32 flags, hal_rx_desc_sz = ar->ab->hw_params->hal_desc_sz; 2915 2916 first_frag = skb_peek(&rx_tid->rx_frags); 2917 last_frag = skb_peek_tail(&rx_tid->rx_frags); 2918 2919 skb_queue_walk(&rx_tid->rx_frags, skb) { 2920 flags = 0; 2921 rx_desc = (struct hal_rx_desc *)skb->data; 2922 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz); 2923 2924 enctype = ath12k_dp_rx_h_enctype(ab, rx_desc); 2925 if (enctype != HAL_ENCRYPT_TYPE_OPEN) 2926 is_decrypted = ath12k_dp_rx_h_is_decrypted(ab, 2927 rx_desc); 2928 2929 if (is_decrypted) { 2930 if (skb != first_frag) 2931 flags |= RX_FLAG_IV_STRIPPED; 2932 if (skb != last_frag) 2933 flags |= RX_FLAG_ICV_STRIPPED | 2934 RX_FLAG_MIC_STRIPPED; 2935 } 2936 2937 /* RX fragments are always raw packets */ 2938 if (skb != last_frag) 2939 skb_trim(skb, skb->len - FCS_LEN); 2940 ath12k_dp_rx_h_undecap_frag(ar, skb, enctype, flags); 2941 2942 if (skb != first_frag) 2943 skb_pull(skb, hal_rx_desc_sz + 2944 ieee80211_hdrlen(hdr->frame_control)); 2945 msdu_len += skb->len; 2946 } 2947 2948 extra_space = msdu_len - (DP_RX_BUFFER_SIZE + skb_tailroom(first_frag)); 2949 if (extra_space > 0 && 2950 (pskb_expand_head(first_frag, 0, extra_space, GFP_ATOMIC) < 0)) 2951 return -ENOMEM; 2952 2953 __skb_unlink(first_frag, &rx_tid->rx_frags); 2954 while ((skb = __skb_dequeue(&rx_tid->rx_frags))) { 2955 skb_put_data(first_frag, skb->data, skb->len); 2956 dev_kfree_skb_any(skb); 2957 } 2958 2959 hdr = (struct ieee80211_hdr *)(first_frag->data + hal_rx_desc_sz); 2960 hdr->frame_control &= ~__cpu_to_le16(IEEE80211_FCTL_MOREFRAGS); 2961 ATH12K_SKB_RXCB(first_frag)->is_frag = 1; 2962 2963 if (ath12k_dp_rx_h_verify_tkip_mic(ar, peer, first_frag)) 2964 first_frag = NULL; 2965 2966 *defrag_skb = first_frag; 2967 return 0; 2968 } 2969 2970 static int ath12k_dp_rx_h_defrag_reo_reinject(struct ath12k *ar, 2971 struct ath12k_dp_rx_tid *rx_tid, 2972 struct sk_buff *defrag_skb) 2973 { 2974 struct ath12k_base *ab = ar->ab; 2975 struct ath12k_dp *dp = &ab->dp; 2976 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)defrag_skb->data; 2977 struct hal_reo_entrance_ring *reo_ent_ring; 2978 struct hal_reo_dest_ring *reo_dest_ring; 2979 struct dp_link_desc_bank *link_desc_banks; 2980 struct hal_rx_msdu_link *msdu_link; 2981 struct hal_rx_msdu_details *msdu0; 2982 struct hal_srng *srng; 2983 dma_addr_t link_paddr, buf_paddr; 2984 u32 desc_bank, msdu_info, msdu_ext_info, mpdu_info; 2985 u32 cookie, hal_rx_desc_sz, dest_ring_info0; 2986 int ret; 2987 struct ath12k_rx_desc_info *desc_info; 2988 u8 dst_ind; 2989 2990 hal_rx_desc_sz = ab->hw_params->hal_desc_sz; 2991 link_desc_banks = dp->link_desc_banks; 2992 reo_dest_ring = rx_tid->dst_ring_desc; 2993 2994 ath12k_hal_rx_reo_ent_paddr_get(ab, &reo_dest_ring->buf_addr_info, 2995 &link_paddr, &cookie); 2996 desc_bank = u32_get_bits(cookie, DP_LINK_DESC_BANK_MASK); 2997 2998 msdu_link = (struct hal_rx_msdu_link *)(link_desc_banks[desc_bank].vaddr + 2999 (link_paddr - link_desc_banks[desc_bank].paddr)); 3000 msdu0 = &msdu_link->msdu_link[0]; 3001 msdu_ext_info = le32_to_cpu(msdu0->rx_msdu_ext_info.info0); 3002 dst_ind = u32_get_bits(msdu_ext_info, RX_MSDU_EXT_DESC_INFO0_REO_DEST_IND); 3003 3004 memset(msdu0, 0, sizeof(*msdu0)); 3005 3006 msdu_info = u32_encode_bits(1, RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU) | 3007 u32_encode_bits(1, RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU) | 3008 u32_encode_bits(0, RX_MSDU_DESC_INFO0_MSDU_CONTINUATION) | 3009 u32_encode_bits(defrag_skb->len - hal_rx_desc_sz, 3010 RX_MSDU_DESC_INFO0_MSDU_LENGTH) | 3011 u32_encode_bits(1, RX_MSDU_DESC_INFO0_VALID_SA) | 3012 u32_encode_bits(1, RX_MSDU_DESC_INFO0_VALID_DA); 3013 msdu0->rx_msdu_info.info0 = cpu_to_le32(msdu_info); 3014 msdu0->rx_msdu_ext_info.info0 = cpu_to_le32(msdu_ext_info); 3015 3016 /* change msdu len in hal rx desc */ 3017 ath12k_dp_rxdesc_set_msdu_len(ab, rx_desc, defrag_skb->len - hal_rx_desc_sz); 3018 3019 buf_paddr = dma_map_single(ab->dev, defrag_skb->data, 3020 defrag_skb->len + skb_tailroom(defrag_skb), 3021 DMA_FROM_DEVICE); 3022 if (dma_mapping_error(ab->dev, buf_paddr)) 3023 return -ENOMEM; 3024 3025 spin_lock_bh(&dp->rx_desc_lock); 3026 desc_info = list_first_entry_or_null(&dp->rx_desc_free_list, 3027 struct ath12k_rx_desc_info, 3028 list); 3029 if (!desc_info) { 3030 spin_unlock_bh(&dp->rx_desc_lock); 3031 ath12k_warn(ab, "failed to find rx desc for reinject\n"); 3032 ret = -ENOMEM; 3033 goto err_unmap_dma; 3034 } 3035 3036 desc_info->skb = defrag_skb; 3037 3038 list_del(&desc_info->list); 3039 list_add_tail(&desc_info->list, &dp->rx_desc_used_list); 3040 spin_unlock_bh(&dp->rx_desc_lock); 3041 3042 ATH12K_SKB_RXCB(defrag_skb)->paddr = buf_paddr; 3043 3044 ath12k_hal_rx_buf_addr_info_set(&msdu0->buf_addr_info, buf_paddr, 3045 desc_info->cookie, 3046 HAL_RX_BUF_RBM_SW3_BM); 3047 3048 /* Fill mpdu details into reo entrance ring */ 3049 srng = &ab->hal.srng_list[dp->reo_reinject_ring.ring_id]; 3050 3051 spin_lock_bh(&srng->lock); 3052 ath12k_hal_srng_access_begin(ab, srng); 3053 3054 reo_ent_ring = ath12k_hal_srng_src_get_next_entry(ab, srng); 3055 if (!reo_ent_ring) { 3056 ath12k_hal_srng_access_end(ab, srng); 3057 spin_unlock_bh(&srng->lock); 3058 ret = -ENOSPC; 3059 goto err_free_desc; 3060 } 3061 memset(reo_ent_ring, 0, sizeof(*reo_ent_ring)); 3062 3063 ath12k_hal_rx_buf_addr_info_set(&reo_ent_ring->buf_addr_info, link_paddr, 3064 cookie, 3065 HAL_RX_BUF_RBM_WBM_CHIP0_IDLE_DESC_LIST); 3066 3067 mpdu_info = u32_encode_bits(1, RX_MPDU_DESC_INFO0_MSDU_COUNT) | 3068 u32_encode_bits(0, RX_MPDU_DESC_INFO0_FRAG_FLAG) | 3069 u32_encode_bits(1, RX_MPDU_DESC_INFO0_RAW_MPDU) | 3070 u32_encode_bits(1, RX_MPDU_DESC_INFO0_VALID_PN) | 3071 u32_encode_bits(rx_tid->tid, RX_MPDU_DESC_INFO0_TID); 3072 3073 reo_ent_ring->rx_mpdu_info.info0 = cpu_to_le32(mpdu_info); 3074 reo_ent_ring->rx_mpdu_info.peer_meta_data = 3075 reo_dest_ring->rx_mpdu_info.peer_meta_data; 3076 3077 /* Firmware expects physical address to be filled in queue_addr_lo in 3078 * the MLO scenario and in case of non MLO peer meta data needs to be 3079 * filled. 3080 * TODO: Need to handle for MLO scenario. 3081 */ 3082 reo_ent_ring->queue_addr_lo = reo_dest_ring->rx_mpdu_info.peer_meta_data; 3083 reo_ent_ring->info0 = le32_encode_bits(dst_ind, 3084 HAL_REO_ENTR_RING_INFO0_DEST_IND); 3085 3086 reo_ent_ring->info1 = le32_encode_bits(rx_tid->cur_sn, 3087 HAL_REO_ENTR_RING_INFO1_MPDU_SEQ_NUM); 3088 dest_ring_info0 = le32_get_bits(reo_dest_ring->info0, 3089 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID); 3090 reo_ent_ring->info2 = 3091 cpu_to_le32(u32_get_bits(dest_ring_info0, 3092 HAL_REO_ENTR_RING_INFO2_SRC_LINK_ID)); 3093 3094 ath12k_hal_srng_access_end(ab, srng); 3095 spin_unlock_bh(&srng->lock); 3096 3097 return 0; 3098 3099 err_free_desc: 3100 spin_lock_bh(&dp->rx_desc_lock); 3101 list_del(&desc_info->list); 3102 list_add_tail(&desc_info->list, &dp->rx_desc_free_list); 3103 desc_info->skb = NULL; 3104 spin_unlock_bh(&dp->rx_desc_lock); 3105 err_unmap_dma: 3106 dma_unmap_single(ab->dev, buf_paddr, defrag_skb->len + skb_tailroom(defrag_skb), 3107 DMA_FROM_DEVICE); 3108 return ret; 3109 } 3110 3111 static int ath12k_dp_rx_h_cmp_frags(struct ath12k_base *ab, 3112 struct sk_buff *a, struct sk_buff *b) 3113 { 3114 int frag1, frag2; 3115 3116 frag1 = ath12k_dp_rx_h_frag_no(ab, a); 3117 frag2 = ath12k_dp_rx_h_frag_no(ab, b); 3118 3119 return frag1 - frag2; 3120 } 3121 3122 static void ath12k_dp_rx_h_sort_frags(struct ath12k_base *ab, 3123 struct sk_buff_head *frag_list, 3124 struct sk_buff *cur_frag) 3125 { 3126 struct sk_buff *skb; 3127 int cmp; 3128 3129 skb_queue_walk(frag_list, skb) { 3130 cmp = ath12k_dp_rx_h_cmp_frags(ab, skb, cur_frag); 3131 if (cmp < 0) 3132 continue; 3133 __skb_queue_before(frag_list, skb, cur_frag); 3134 return; 3135 } 3136 __skb_queue_tail(frag_list, cur_frag); 3137 } 3138 3139 static u64 ath12k_dp_rx_h_get_pn(struct ath12k *ar, struct sk_buff *skb) 3140 { 3141 struct ieee80211_hdr *hdr; 3142 u64 pn = 0; 3143 u8 *ehdr; 3144 u32 hal_rx_desc_sz = ar->ab->hw_params->hal_desc_sz; 3145 3146 hdr = (struct ieee80211_hdr *)(skb->data + hal_rx_desc_sz); 3147 ehdr = skb->data + hal_rx_desc_sz + ieee80211_hdrlen(hdr->frame_control); 3148 3149 pn = ehdr[0]; 3150 pn |= (u64)ehdr[1] << 8; 3151 pn |= (u64)ehdr[4] << 16; 3152 pn |= (u64)ehdr[5] << 24; 3153 pn |= (u64)ehdr[6] << 32; 3154 pn |= (u64)ehdr[7] << 40; 3155 3156 return pn; 3157 } 3158 3159 static bool 3160 ath12k_dp_rx_h_defrag_validate_incr_pn(struct ath12k *ar, struct ath12k_dp_rx_tid *rx_tid) 3161 { 3162 struct ath12k_base *ab = ar->ab; 3163 enum hal_encrypt_type encrypt_type; 3164 struct sk_buff *first_frag, *skb; 3165 struct hal_rx_desc *desc; 3166 u64 last_pn; 3167 u64 cur_pn; 3168 3169 first_frag = skb_peek(&rx_tid->rx_frags); 3170 desc = (struct hal_rx_desc *)first_frag->data; 3171 3172 encrypt_type = ath12k_dp_rx_h_enctype(ab, desc); 3173 if (encrypt_type != HAL_ENCRYPT_TYPE_CCMP_128 && 3174 encrypt_type != HAL_ENCRYPT_TYPE_CCMP_256 && 3175 encrypt_type != HAL_ENCRYPT_TYPE_GCMP_128 && 3176 encrypt_type != HAL_ENCRYPT_TYPE_AES_GCMP_256) 3177 return true; 3178 3179 last_pn = ath12k_dp_rx_h_get_pn(ar, first_frag); 3180 skb_queue_walk(&rx_tid->rx_frags, skb) { 3181 if (skb == first_frag) 3182 continue; 3183 3184 cur_pn = ath12k_dp_rx_h_get_pn(ar, skb); 3185 if (cur_pn != last_pn + 1) 3186 return false; 3187 last_pn = cur_pn; 3188 } 3189 return true; 3190 } 3191 3192 static int ath12k_dp_rx_frag_h_mpdu(struct ath12k *ar, 3193 struct sk_buff *msdu, 3194 struct hal_reo_dest_ring *ring_desc) 3195 { 3196 struct ath12k_base *ab = ar->ab; 3197 struct hal_rx_desc *rx_desc; 3198 struct ath12k_peer *peer; 3199 struct ath12k_dp_rx_tid *rx_tid; 3200 struct sk_buff *defrag_skb = NULL; 3201 u32 peer_id; 3202 u16 seqno, frag_no; 3203 u8 tid; 3204 int ret = 0; 3205 bool more_frags; 3206 3207 rx_desc = (struct hal_rx_desc *)msdu->data; 3208 peer_id = ath12k_dp_rx_h_peer_id(ab, rx_desc); 3209 tid = ath12k_dp_rx_h_tid(ab, rx_desc); 3210 seqno = ath12k_dp_rx_h_seq_no(ab, rx_desc); 3211 frag_no = ath12k_dp_rx_h_frag_no(ab, msdu); 3212 more_frags = ath12k_dp_rx_h_more_frags(ab, msdu); 3213 3214 if (!ath12k_dp_rx_h_seq_ctrl_valid(ab, rx_desc) || 3215 !ath12k_dp_rx_h_fc_valid(ab, rx_desc) || 3216 tid > IEEE80211_NUM_TIDS) 3217 return -EINVAL; 3218 3219 /* received unfragmented packet in reo 3220 * exception ring, this shouldn't happen 3221 * as these packets typically come from 3222 * reo2sw srngs. 3223 */ 3224 if (WARN_ON_ONCE(!frag_no && !more_frags)) 3225 return -EINVAL; 3226 3227 spin_lock_bh(&ab->base_lock); 3228 peer = ath12k_peer_find_by_id(ab, peer_id); 3229 if (!peer) { 3230 ath12k_warn(ab, "failed to find the peer to de-fragment received fragment peer_id %d\n", 3231 peer_id); 3232 ret = -ENOENT; 3233 goto out_unlock; 3234 } 3235 3236 if (!peer->dp_setup_done) { 3237 ath12k_warn(ab, "The peer %pM [%d] has uninitialized datapath\n", 3238 peer->addr, peer_id); 3239 ret = -ENOENT; 3240 goto out_unlock; 3241 } 3242 3243 rx_tid = &peer->rx_tid[tid]; 3244 3245 if ((!skb_queue_empty(&rx_tid->rx_frags) && seqno != rx_tid->cur_sn) || 3246 skb_queue_empty(&rx_tid->rx_frags)) { 3247 /* Flush stored fragments and start a new sequence */ 3248 ath12k_dp_rx_frags_cleanup(rx_tid, true); 3249 rx_tid->cur_sn = seqno; 3250 } 3251 3252 if (rx_tid->rx_frag_bitmap & BIT(frag_no)) { 3253 /* Fragment already present */ 3254 ret = -EINVAL; 3255 goto out_unlock; 3256 } 3257 3258 if ((!rx_tid->rx_frag_bitmap || frag_no > __fls(rx_tid->rx_frag_bitmap))) 3259 __skb_queue_tail(&rx_tid->rx_frags, msdu); 3260 else 3261 ath12k_dp_rx_h_sort_frags(ab, &rx_tid->rx_frags, msdu); 3262 3263 rx_tid->rx_frag_bitmap |= BIT(frag_no); 3264 if (!more_frags) 3265 rx_tid->last_frag_no = frag_no; 3266 3267 if (frag_no == 0) { 3268 rx_tid->dst_ring_desc = kmemdup(ring_desc, 3269 sizeof(*rx_tid->dst_ring_desc), 3270 GFP_ATOMIC); 3271 if (!rx_tid->dst_ring_desc) { 3272 ret = -ENOMEM; 3273 goto out_unlock; 3274 } 3275 } else { 3276 ath12k_dp_rx_link_desc_return(ab, ring_desc, 3277 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3278 } 3279 3280 if (!rx_tid->last_frag_no || 3281 rx_tid->rx_frag_bitmap != GENMASK(rx_tid->last_frag_no, 0)) { 3282 mod_timer(&rx_tid->frag_timer, jiffies + 3283 ATH12K_DP_RX_FRAGMENT_TIMEOUT_MS); 3284 goto out_unlock; 3285 } 3286 3287 spin_unlock_bh(&ab->base_lock); 3288 del_timer_sync(&rx_tid->frag_timer); 3289 spin_lock_bh(&ab->base_lock); 3290 3291 peer = ath12k_peer_find_by_id(ab, peer_id); 3292 if (!peer) 3293 goto err_frags_cleanup; 3294 3295 if (!ath12k_dp_rx_h_defrag_validate_incr_pn(ar, rx_tid)) 3296 goto err_frags_cleanup; 3297 3298 if (ath12k_dp_rx_h_defrag(ar, peer, rx_tid, &defrag_skb)) 3299 goto err_frags_cleanup; 3300 3301 if (!defrag_skb) 3302 goto err_frags_cleanup; 3303 3304 if (ath12k_dp_rx_h_defrag_reo_reinject(ar, rx_tid, defrag_skb)) 3305 goto err_frags_cleanup; 3306 3307 ath12k_dp_rx_frags_cleanup(rx_tid, false); 3308 goto out_unlock; 3309 3310 err_frags_cleanup: 3311 dev_kfree_skb_any(defrag_skb); 3312 ath12k_dp_rx_frags_cleanup(rx_tid, true); 3313 out_unlock: 3314 spin_unlock_bh(&ab->base_lock); 3315 return ret; 3316 } 3317 3318 static int 3319 ath12k_dp_process_rx_err_buf(struct ath12k *ar, struct hal_reo_dest_ring *desc, 3320 bool drop, u32 cookie) 3321 { 3322 struct ath12k_base *ab = ar->ab; 3323 struct sk_buff *msdu; 3324 struct ath12k_skb_rxcb *rxcb; 3325 struct hal_rx_desc *rx_desc; 3326 u16 msdu_len; 3327 u32 hal_rx_desc_sz = ab->hw_params->hal_desc_sz; 3328 struct ath12k_rx_desc_info *desc_info; 3329 u64 desc_va; 3330 3331 desc_va = ((u64)le32_to_cpu(desc->buf_va_hi) << 32 | 3332 le32_to_cpu(desc->buf_va_lo)); 3333 desc_info = (struct ath12k_rx_desc_info *)((unsigned long)desc_va); 3334 3335 /* retry manual desc retrieval */ 3336 if (!desc_info) { 3337 desc_info = ath12k_dp_get_rx_desc(ab, cookie); 3338 if (!desc_info) { 3339 ath12k_warn(ab, "Invalid cookie in manual desc retrieval"); 3340 return -EINVAL; 3341 } 3342 } 3343 3344 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC) 3345 ath12k_warn(ab, " RX Exception, Check HW CC implementation"); 3346 3347 msdu = desc_info->skb; 3348 desc_info->skb = NULL; 3349 spin_lock_bh(&ab->dp.rx_desc_lock); 3350 list_move_tail(&desc_info->list, &ab->dp.rx_desc_free_list); 3351 spin_unlock_bh(&ab->dp.rx_desc_lock); 3352 3353 rxcb = ATH12K_SKB_RXCB(msdu); 3354 dma_unmap_single(ar->ab->dev, rxcb->paddr, 3355 msdu->len + skb_tailroom(msdu), 3356 DMA_FROM_DEVICE); 3357 3358 if (drop) { 3359 dev_kfree_skb_any(msdu); 3360 return 0; 3361 } 3362 3363 rcu_read_lock(); 3364 if (!rcu_dereference(ar->ab->pdevs_active[ar->pdev_idx])) { 3365 dev_kfree_skb_any(msdu); 3366 goto exit; 3367 } 3368 3369 if (test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) { 3370 dev_kfree_skb_any(msdu); 3371 goto exit; 3372 } 3373 3374 rx_desc = (struct hal_rx_desc *)msdu->data; 3375 msdu_len = ath12k_dp_rx_h_msdu_len(ar->ab, rx_desc); 3376 if ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE) { 3377 ath12k_warn(ar->ab, "invalid msdu leng %u", msdu_len); 3378 ath12k_dbg_dump(ar->ab, ATH12K_DBG_DATA, NULL, "", rx_desc, 3379 sizeof(*rx_desc)); 3380 dev_kfree_skb_any(msdu); 3381 goto exit; 3382 } 3383 3384 skb_put(msdu, hal_rx_desc_sz + msdu_len); 3385 3386 if (ath12k_dp_rx_frag_h_mpdu(ar, msdu, desc)) { 3387 dev_kfree_skb_any(msdu); 3388 ath12k_dp_rx_link_desc_return(ar->ab, desc, 3389 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3390 } 3391 exit: 3392 rcu_read_unlock(); 3393 return 0; 3394 } 3395 3396 int ath12k_dp_rx_process_err(struct ath12k_base *ab, struct napi_struct *napi, 3397 int budget) 3398 { 3399 u32 msdu_cookies[HAL_NUM_RX_MSDUS_PER_LINK_DESC]; 3400 struct dp_link_desc_bank *link_desc_banks; 3401 enum hal_rx_buf_return_buf_manager rbm; 3402 struct hal_rx_msdu_link *link_desc_va; 3403 int tot_n_bufs_reaped, quota, ret, i; 3404 struct hal_reo_dest_ring *reo_desc; 3405 struct dp_rxdma_ring *rx_ring; 3406 struct dp_srng *reo_except; 3407 u32 desc_bank, num_msdus; 3408 struct hal_srng *srng; 3409 struct ath12k_dp *dp; 3410 int mac_id; 3411 struct ath12k *ar; 3412 dma_addr_t paddr; 3413 bool is_frag; 3414 bool drop = false; 3415 int pdev_id; 3416 3417 tot_n_bufs_reaped = 0; 3418 quota = budget; 3419 3420 dp = &ab->dp; 3421 reo_except = &dp->reo_except_ring; 3422 link_desc_banks = dp->link_desc_banks; 3423 3424 srng = &ab->hal.srng_list[reo_except->ring_id]; 3425 3426 spin_lock_bh(&srng->lock); 3427 3428 ath12k_hal_srng_access_begin(ab, srng); 3429 3430 while (budget && 3431 (reo_desc = ath12k_hal_srng_dst_get_next_entry(ab, srng))) { 3432 ab->soc_stats.err_ring_pkts++; 3433 ret = ath12k_hal_desc_reo_parse_err(ab, reo_desc, &paddr, 3434 &desc_bank); 3435 if (ret) { 3436 ath12k_warn(ab, "failed to parse error reo desc %d\n", 3437 ret); 3438 continue; 3439 } 3440 link_desc_va = link_desc_banks[desc_bank].vaddr + 3441 (paddr - link_desc_banks[desc_bank].paddr); 3442 ath12k_hal_rx_msdu_link_info_get(link_desc_va, &num_msdus, msdu_cookies, 3443 &rbm); 3444 if (rbm != HAL_RX_BUF_RBM_WBM_CHIP0_IDLE_DESC_LIST && 3445 rbm != HAL_RX_BUF_RBM_SW3_BM && 3446 rbm != ab->hw_params->hal_params->rx_buf_rbm) { 3447 ab->soc_stats.invalid_rbm++; 3448 ath12k_warn(ab, "invalid return buffer manager %d\n", rbm); 3449 ath12k_dp_rx_link_desc_return(ab, reo_desc, 3450 HAL_WBM_REL_BM_ACT_REL_MSDU); 3451 continue; 3452 } 3453 3454 is_frag = !!(le32_to_cpu(reo_desc->rx_mpdu_info.info0) & 3455 RX_MPDU_DESC_INFO0_FRAG_FLAG); 3456 3457 /* Process only rx fragments with one msdu per link desc below, and drop 3458 * msdu's indicated due to error reasons. 3459 */ 3460 if (!is_frag || num_msdus > 1) { 3461 drop = true; 3462 /* Return the link desc back to wbm idle list */ 3463 ath12k_dp_rx_link_desc_return(ab, reo_desc, 3464 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE); 3465 } 3466 3467 for (i = 0; i < num_msdus; i++) { 3468 mac_id = le32_get_bits(reo_desc->info0, 3469 HAL_REO_DEST_RING_INFO0_SRC_LINK_ID); 3470 3471 pdev_id = ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id); 3472 ar = ab->pdevs[pdev_id].ar; 3473 3474 if (!ath12k_dp_process_rx_err_buf(ar, reo_desc, drop, 3475 msdu_cookies[i])) 3476 tot_n_bufs_reaped++; 3477 } 3478 3479 if (tot_n_bufs_reaped >= quota) { 3480 tot_n_bufs_reaped = quota; 3481 goto exit; 3482 } 3483 3484 budget = quota - tot_n_bufs_reaped; 3485 } 3486 3487 exit: 3488 ath12k_hal_srng_access_end(ab, srng); 3489 3490 spin_unlock_bh(&srng->lock); 3491 3492 rx_ring = &dp->rx_refill_buf_ring; 3493 3494 ath12k_dp_rx_bufs_replenish(ab, 0, rx_ring, tot_n_bufs_reaped, 3495 ab->hw_params->hal_params->rx_buf_rbm, true); 3496 3497 return tot_n_bufs_reaped; 3498 } 3499 3500 static void ath12k_dp_rx_null_q_desc_sg_drop(struct ath12k *ar, 3501 int msdu_len, 3502 struct sk_buff_head *msdu_list) 3503 { 3504 struct sk_buff *skb, *tmp; 3505 struct ath12k_skb_rxcb *rxcb; 3506 int n_buffs; 3507 3508 n_buffs = DIV_ROUND_UP(msdu_len, 3509 (DP_RX_BUFFER_SIZE - ar->ab->hw_params->hal_desc_sz)); 3510 3511 skb_queue_walk_safe(msdu_list, skb, tmp) { 3512 rxcb = ATH12K_SKB_RXCB(skb); 3513 if (rxcb->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO && 3514 rxcb->err_code == HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO) { 3515 if (!n_buffs) 3516 break; 3517 __skb_unlink(skb, msdu_list); 3518 dev_kfree_skb_any(skb); 3519 n_buffs--; 3520 } 3521 } 3522 } 3523 3524 static int ath12k_dp_rx_h_null_q_desc(struct ath12k *ar, struct sk_buff *msdu, 3525 struct ieee80211_rx_status *status, 3526 struct sk_buff_head *msdu_list) 3527 { 3528 struct ath12k_base *ab = ar->ab; 3529 u16 msdu_len, peer_id; 3530 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data; 3531 u8 l3pad_bytes; 3532 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 3533 u32 hal_rx_desc_sz = ar->ab->hw_params->hal_desc_sz; 3534 3535 msdu_len = ath12k_dp_rx_h_msdu_len(ab, desc); 3536 peer_id = ath12k_dp_rx_h_peer_id(ab, desc); 3537 3538 spin_lock(&ab->base_lock); 3539 if (!ath12k_peer_find_by_id(ab, peer_id)) { 3540 spin_unlock(&ab->base_lock); 3541 ath12k_dbg(ab, ATH12K_DBG_DATA, "invalid peer id received in wbm err pkt%d\n", 3542 peer_id); 3543 return -EINVAL; 3544 } 3545 spin_unlock(&ab->base_lock); 3546 3547 if (!rxcb->is_frag && ((msdu_len + hal_rx_desc_sz) > DP_RX_BUFFER_SIZE)) { 3548 /* First buffer will be freed by the caller, so deduct it's length */ 3549 msdu_len = msdu_len - (DP_RX_BUFFER_SIZE - hal_rx_desc_sz); 3550 ath12k_dp_rx_null_q_desc_sg_drop(ar, msdu_len, msdu_list); 3551 return -EINVAL; 3552 } 3553 3554 /* Even after cleaning up the sg buffers in the msdu list with above check 3555 * any msdu received with continuation flag needs to be dropped as invalid. 3556 * This protects against some random err frame with continuation flag. 3557 */ 3558 if (rxcb->is_continuation) 3559 return -EINVAL; 3560 3561 if (!ath12k_dp_rx_h_msdu_done(ab, desc)) { 3562 ath12k_warn(ar->ab, 3563 "msdu_done bit not set in null_q_des processing\n"); 3564 __skb_queue_purge(msdu_list); 3565 return -EIO; 3566 } 3567 3568 /* Handle NULL queue descriptor violations arising out a missing 3569 * REO queue for a given peer or a given TID. This typically 3570 * may happen if a packet is received on a QOS enabled TID before the 3571 * ADDBA negotiation for that TID, when the TID queue is setup. Or 3572 * it may also happen for MC/BC frames if they are not routed to the 3573 * non-QOS TID queue, in the absence of any other default TID queue. 3574 * This error can show up both in a REO destination or WBM release ring. 3575 */ 3576 3577 if (rxcb->is_frag) { 3578 skb_pull(msdu, hal_rx_desc_sz); 3579 } else { 3580 l3pad_bytes = ath12k_dp_rx_h_l3pad(ab, desc); 3581 3582 if ((hal_rx_desc_sz + l3pad_bytes + msdu_len) > DP_RX_BUFFER_SIZE) 3583 return -EINVAL; 3584 3585 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len); 3586 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes); 3587 } 3588 ath12k_dp_rx_h_ppdu(ar, desc, status); 3589 3590 ath12k_dp_rx_h_mpdu(ar, msdu, desc, status); 3591 3592 rxcb->tid = ath12k_dp_rx_h_tid(ab, desc); 3593 3594 /* Please note that caller will having the access to msdu and completing 3595 * rx with mac80211. Need not worry about cleaning up amsdu_list. 3596 */ 3597 3598 return 0; 3599 } 3600 3601 static bool ath12k_dp_rx_h_reo_err(struct ath12k *ar, struct sk_buff *msdu, 3602 struct ieee80211_rx_status *status, 3603 struct sk_buff_head *msdu_list) 3604 { 3605 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 3606 bool drop = false; 3607 3608 ar->ab->soc_stats.reo_error[rxcb->err_code]++; 3609 3610 switch (rxcb->err_code) { 3611 case HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO: 3612 if (ath12k_dp_rx_h_null_q_desc(ar, msdu, status, msdu_list)) 3613 drop = true; 3614 break; 3615 case HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED: 3616 /* TODO: Do not drop PN failed packets in the driver; 3617 * instead, it is good to drop such packets in mac80211 3618 * after incrementing the replay counters. 3619 */ 3620 fallthrough; 3621 default: 3622 /* TODO: Review other errors and process them to mac80211 3623 * as appropriate. 3624 */ 3625 drop = true; 3626 break; 3627 } 3628 3629 return drop; 3630 } 3631 3632 static void ath12k_dp_rx_h_tkip_mic_err(struct ath12k *ar, struct sk_buff *msdu, 3633 struct ieee80211_rx_status *status) 3634 { 3635 struct ath12k_base *ab = ar->ab; 3636 u16 msdu_len; 3637 struct hal_rx_desc *desc = (struct hal_rx_desc *)msdu->data; 3638 u8 l3pad_bytes; 3639 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 3640 u32 hal_rx_desc_sz = ar->ab->hw_params->hal_desc_sz; 3641 3642 rxcb->is_first_msdu = ath12k_dp_rx_h_first_msdu(ab, desc); 3643 rxcb->is_last_msdu = ath12k_dp_rx_h_last_msdu(ab, desc); 3644 3645 l3pad_bytes = ath12k_dp_rx_h_l3pad(ab, desc); 3646 msdu_len = ath12k_dp_rx_h_msdu_len(ab, desc); 3647 skb_put(msdu, hal_rx_desc_sz + l3pad_bytes + msdu_len); 3648 skb_pull(msdu, hal_rx_desc_sz + l3pad_bytes); 3649 3650 ath12k_dp_rx_h_ppdu(ar, desc, status); 3651 3652 status->flag |= (RX_FLAG_MMIC_STRIPPED | RX_FLAG_MMIC_ERROR | 3653 RX_FLAG_DECRYPTED); 3654 3655 ath12k_dp_rx_h_undecap(ar, msdu, desc, 3656 HAL_ENCRYPT_TYPE_TKIP_MIC, status, false); 3657 } 3658 3659 static bool ath12k_dp_rx_h_rxdma_err(struct ath12k *ar, struct sk_buff *msdu, 3660 struct ieee80211_rx_status *status) 3661 { 3662 struct ath12k_base *ab = ar->ab; 3663 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 3664 struct hal_rx_desc *rx_desc = (struct hal_rx_desc *)msdu->data; 3665 bool drop = false; 3666 u32 err_bitmap; 3667 3668 ar->ab->soc_stats.rxdma_error[rxcb->err_code]++; 3669 3670 switch (rxcb->err_code) { 3671 case HAL_REO_ENTR_RING_RXDMA_ECODE_DECRYPT_ERR: 3672 case HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR: 3673 err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc); 3674 if (err_bitmap & HAL_RX_MPDU_ERR_TKIP_MIC) { 3675 ath12k_dp_rx_h_tkip_mic_err(ar, msdu, status); 3676 break; 3677 } 3678 fallthrough; 3679 default: 3680 /* TODO: Review other rxdma error code to check if anything is 3681 * worth reporting to mac80211 3682 */ 3683 drop = true; 3684 break; 3685 } 3686 3687 return drop; 3688 } 3689 3690 static void ath12k_dp_rx_wbm_err(struct ath12k *ar, 3691 struct napi_struct *napi, 3692 struct sk_buff *msdu, 3693 struct sk_buff_head *msdu_list) 3694 { 3695 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 3696 struct ieee80211_rx_status rxs = {0}; 3697 bool drop = true; 3698 3699 switch (rxcb->err_rel_src) { 3700 case HAL_WBM_REL_SRC_MODULE_REO: 3701 drop = ath12k_dp_rx_h_reo_err(ar, msdu, &rxs, msdu_list); 3702 break; 3703 case HAL_WBM_REL_SRC_MODULE_RXDMA: 3704 drop = ath12k_dp_rx_h_rxdma_err(ar, msdu, &rxs); 3705 break; 3706 default: 3707 /* msdu will get freed */ 3708 break; 3709 } 3710 3711 if (drop) { 3712 dev_kfree_skb_any(msdu); 3713 return; 3714 } 3715 3716 ath12k_dp_rx_deliver_msdu(ar, napi, msdu, &rxs); 3717 } 3718 3719 int ath12k_dp_rx_process_wbm_err(struct ath12k_base *ab, 3720 struct napi_struct *napi, int budget) 3721 { 3722 struct ath12k *ar; 3723 struct ath12k_dp *dp = &ab->dp; 3724 struct dp_rxdma_ring *rx_ring; 3725 struct hal_rx_wbm_rel_info err_info; 3726 struct hal_srng *srng; 3727 struct sk_buff *msdu; 3728 struct sk_buff_head msdu_list[MAX_RADIOS]; 3729 struct ath12k_skb_rxcb *rxcb; 3730 void *rx_desc; 3731 int mac_id; 3732 int num_buffs_reaped = 0; 3733 struct ath12k_rx_desc_info *desc_info; 3734 int ret, i; 3735 3736 for (i = 0; i < ab->num_radios; i++) 3737 __skb_queue_head_init(&msdu_list[i]); 3738 3739 srng = &ab->hal.srng_list[dp->rx_rel_ring.ring_id]; 3740 rx_ring = &dp->rx_refill_buf_ring; 3741 3742 spin_lock_bh(&srng->lock); 3743 3744 ath12k_hal_srng_access_begin(ab, srng); 3745 3746 while (budget) { 3747 rx_desc = ath12k_hal_srng_dst_get_next_entry(ab, srng); 3748 if (!rx_desc) 3749 break; 3750 3751 ret = ath12k_hal_wbm_desc_parse_err(ab, rx_desc, &err_info); 3752 if (ret) { 3753 ath12k_warn(ab, 3754 "failed to parse rx error in wbm_rel ring desc %d\n", 3755 ret); 3756 continue; 3757 } 3758 3759 desc_info = (struct ath12k_rx_desc_info *)err_info.rx_desc; 3760 3761 /* retry manual desc retrieval if hw cc is not done */ 3762 if (!desc_info) { 3763 desc_info = ath12k_dp_get_rx_desc(ab, err_info.cookie); 3764 if (!desc_info) { 3765 ath12k_warn(ab, "Invalid cookie in manual desc retrieval"); 3766 continue; 3767 } 3768 } 3769 3770 /* FIXME: Extract mac id correctly. Since descs are not tied 3771 * to mac, we can extract from vdev id in ring desc. 3772 */ 3773 mac_id = 0; 3774 3775 if (desc_info->magic != ATH12K_DP_RX_DESC_MAGIC) 3776 ath12k_warn(ab, "WBM RX err, Check HW CC implementation"); 3777 3778 msdu = desc_info->skb; 3779 desc_info->skb = NULL; 3780 3781 spin_lock_bh(&dp->rx_desc_lock); 3782 list_move_tail(&desc_info->list, &dp->rx_desc_free_list); 3783 spin_unlock_bh(&dp->rx_desc_lock); 3784 3785 rxcb = ATH12K_SKB_RXCB(msdu); 3786 dma_unmap_single(ab->dev, rxcb->paddr, 3787 msdu->len + skb_tailroom(msdu), 3788 DMA_FROM_DEVICE); 3789 3790 num_buffs_reaped++; 3791 3792 if (!err_info.continuation) 3793 budget--; 3794 3795 if (err_info.push_reason != 3796 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED) { 3797 dev_kfree_skb_any(msdu); 3798 continue; 3799 } 3800 3801 rxcb->err_rel_src = err_info.err_rel_src; 3802 rxcb->err_code = err_info.err_code; 3803 rxcb->rx_desc = (struct hal_rx_desc *)msdu->data; 3804 __skb_queue_tail(&msdu_list[mac_id], msdu); 3805 3806 rxcb->is_first_msdu = err_info.first_msdu; 3807 rxcb->is_last_msdu = err_info.last_msdu; 3808 rxcb->is_continuation = err_info.continuation; 3809 } 3810 3811 ath12k_hal_srng_access_end(ab, srng); 3812 3813 spin_unlock_bh(&srng->lock); 3814 3815 if (!num_buffs_reaped) 3816 goto done; 3817 3818 ath12k_dp_rx_bufs_replenish(ab, 0, rx_ring, num_buffs_reaped, 3819 ab->hw_params->hal_params->rx_buf_rbm, true); 3820 3821 rcu_read_lock(); 3822 for (i = 0; i < ab->num_radios; i++) { 3823 if (!rcu_dereference(ab->pdevs_active[i])) { 3824 __skb_queue_purge(&msdu_list[i]); 3825 continue; 3826 } 3827 3828 ar = ab->pdevs[i].ar; 3829 3830 if (test_bit(ATH12K_CAC_RUNNING, &ar->dev_flags)) { 3831 __skb_queue_purge(&msdu_list[i]); 3832 continue; 3833 } 3834 3835 while ((msdu = __skb_dequeue(&msdu_list[i])) != NULL) 3836 ath12k_dp_rx_wbm_err(ar, napi, msdu, &msdu_list[i]); 3837 } 3838 rcu_read_unlock(); 3839 done: 3840 return num_buffs_reaped; 3841 } 3842 3843 void ath12k_dp_rx_process_reo_status(struct ath12k_base *ab) 3844 { 3845 struct ath12k_dp *dp = &ab->dp; 3846 struct hal_tlv_64_hdr *hdr; 3847 struct hal_srng *srng; 3848 struct ath12k_dp_rx_reo_cmd *cmd, *tmp; 3849 bool found = false; 3850 u16 tag; 3851 struct hal_reo_status reo_status; 3852 3853 srng = &ab->hal.srng_list[dp->reo_status_ring.ring_id]; 3854 3855 memset(&reo_status, 0, sizeof(reo_status)); 3856 3857 spin_lock_bh(&srng->lock); 3858 3859 ath12k_hal_srng_access_begin(ab, srng); 3860 3861 while ((hdr = ath12k_hal_srng_dst_get_next_entry(ab, srng))) { 3862 tag = u64_get_bits(hdr->tl, HAL_SRNG_TLV_HDR_TAG); 3863 3864 switch (tag) { 3865 case HAL_REO_GET_QUEUE_STATS_STATUS: 3866 ath12k_hal_reo_status_queue_stats(ab, hdr, 3867 &reo_status); 3868 break; 3869 case HAL_REO_FLUSH_QUEUE_STATUS: 3870 ath12k_hal_reo_flush_queue_status(ab, hdr, 3871 &reo_status); 3872 break; 3873 case HAL_REO_FLUSH_CACHE_STATUS: 3874 ath12k_hal_reo_flush_cache_status(ab, hdr, 3875 &reo_status); 3876 break; 3877 case HAL_REO_UNBLOCK_CACHE_STATUS: 3878 ath12k_hal_reo_unblk_cache_status(ab, hdr, 3879 &reo_status); 3880 break; 3881 case HAL_REO_FLUSH_TIMEOUT_LIST_STATUS: 3882 ath12k_hal_reo_flush_timeout_list_status(ab, hdr, 3883 &reo_status); 3884 break; 3885 case HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS: 3886 ath12k_hal_reo_desc_thresh_reached_status(ab, hdr, 3887 &reo_status); 3888 break; 3889 case HAL_REO_UPDATE_RX_REO_QUEUE_STATUS: 3890 ath12k_hal_reo_update_rx_reo_queue_status(ab, hdr, 3891 &reo_status); 3892 break; 3893 default: 3894 ath12k_warn(ab, "Unknown reo status type %d\n", tag); 3895 continue; 3896 } 3897 3898 spin_lock_bh(&dp->reo_cmd_lock); 3899 list_for_each_entry_safe(cmd, tmp, &dp->reo_cmd_list, list) { 3900 if (reo_status.uniform_hdr.cmd_num == cmd->cmd_num) { 3901 found = true; 3902 list_del(&cmd->list); 3903 break; 3904 } 3905 } 3906 spin_unlock_bh(&dp->reo_cmd_lock); 3907 3908 if (found) { 3909 cmd->handler(dp, (void *)&cmd->data, 3910 reo_status.uniform_hdr.cmd_status); 3911 kfree(cmd); 3912 } 3913 3914 found = false; 3915 } 3916 3917 ath12k_hal_srng_access_end(ab, srng); 3918 3919 spin_unlock_bh(&srng->lock); 3920 } 3921 3922 void ath12k_dp_rx_free(struct ath12k_base *ab) 3923 { 3924 struct ath12k_dp *dp = &ab->dp; 3925 int i; 3926 3927 ath12k_dp_srng_cleanup(ab, &dp->rx_refill_buf_ring.refill_buf_ring); 3928 3929 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) { 3930 if (ab->hw_params->rx_mac_buf_ring) 3931 ath12k_dp_srng_cleanup(ab, &dp->rx_mac_buf_ring[i]); 3932 } 3933 3934 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) 3935 ath12k_dp_srng_cleanup(ab, &dp->rxdma_err_dst_ring[i]); 3936 3937 ath12k_dp_srng_cleanup(ab, &dp->rxdma_mon_buf_ring.refill_buf_ring); 3938 ath12k_dp_srng_cleanup(ab, &dp->tx_mon_buf_ring.refill_buf_ring); 3939 3940 ath12k_dp_rxdma_buf_free(ab); 3941 } 3942 3943 void ath12k_dp_rx_pdev_free(struct ath12k_base *ab, int mac_id) 3944 { 3945 struct ath12k *ar = ab->pdevs[mac_id].ar; 3946 3947 ath12k_dp_rx_pdev_srng_free(ar); 3948 } 3949 3950 int ath12k_dp_rxdma_ring_sel_config_qcn9274(struct ath12k_base *ab) 3951 { 3952 struct ath12k_dp *dp = &ab->dp; 3953 struct htt_rx_ring_tlv_filter tlv_filter = {0}; 3954 u32 ring_id; 3955 int ret; 3956 u32 hal_rx_desc_sz = ab->hw_params->hal_desc_sz; 3957 3958 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id; 3959 3960 tlv_filter.rx_filter = HTT_RX_TLV_FLAGS_RXDMA_RING; 3961 tlv_filter.pkt_filter_flags2 = HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR; 3962 tlv_filter.pkt_filter_flags3 = HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST | 3963 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST | 3964 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA; 3965 tlv_filter.offset_valid = true; 3966 tlv_filter.rx_packet_offset = hal_rx_desc_sz; 3967 3968 tlv_filter.rx_mpdu_start_offset = 3969 ab->hw_params->hal_ops->rx_desc_get_mpdu_start_offset(); 3970 tlv_filter.rx_msdu_end_offset = 3971 ab->hw_params->hal_ops->rx_desc_get_msdu_end_offset(); 3972 3973 /* TODO: Selectively subscribe to required qwords within msdu_end 3974 * and mpdu_start and setup the mask in below msg 3975 * and modify the rx_desc struct 3976 */ 3977 ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, 0, 3978 HAL_RXDMA_BUF, 3979 DP_RXDMA_REFILL_RING_SIZE, 3980 &tlv_filter); 3981 3982 return ret; 3983 } 3984 3985 int ath12k_dp_rxdma_ring_sel_config_wcn7850(struct ath12k_base *ab) 3986 { 3987 struct ath12k_dp *dp = &ab->dp; 3988 struct htt_rx_ring_tlv_filter tlv_filter = {0}; 3989 u32 ring_id; 3990 int ret; 3991 u32 hal_rx_desc_sz = ab->hw_params->hal_desc_sz; 3992 int i; 3993 3994 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id; 3995 3996 tlv_filter.rx_filter = HTT_RX_TLV_FLAGS_RXDMA_RING; 3997 tlv_filter.pkt_filter_flags2 = HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR; 3998 tlv_filter.pkt_filter_flags3 = HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST | 3999 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST | 4000 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA; 4001 tlv_filter.offset_valid = true; 4002 tlv_filter.rx_packet_offset = hal_rx_desc_sz; 4003 4004 tlv_filter.rx_header_offset = offsetof(struct hal_rx_desc_wcn7850, pkt_hdr_tlv); 4005 4006 tlv_filter.rx_mpdu_start_offset = 4007 ab->hw_params->hal_ops->rx_desc_get_mpdu_start_offset(); 4008 tlv_filter.rx_msdu_end_offset = 4009 ab->hw_params->hal_ops->rx_desc_get_msdu_end_offset(); 4010 4011 /* TODO: Selectively subscribe to required qwords within msdu_end 4012 * and mpdu_start and setup the mask in below msg 4013 * and modify the rx_desc struct 4014 */ 4015 4016 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) { 4017 ring_id = dp->rx_mac_buf_ring[i].ring_id; 4018 ret = ath12k_dp_tx_htt_rx_filter_setup(ab, ring_id, i, 4019 HAL_RXDMA_BUF, 4020 DP_RXDMA_REFILL_RING_SIZE, 4021 &tlv_filter); 4022 } 4023 4024 return ret; 4025 } 4026 4027 int ath12k_dp_rx_htt_setup(struct ath12k_base *ab) 4028 { 4029 struct ath12k_dp *dp = &ab->dp; 4030 u32 ring_id; 4031 int i, ret; 4032 4033 /* TODO: Need to verify the HTT setup for QCN9224 */ 4034 ring_id = dp->rx_refill_buf_ring.refill_buf_ring.ring_id; 4035 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 0, HAL_RXDMA_BUF); 4036 if (ret) { 4037 ath12k_warn(ab, "failed to configure rx_refill_buf_ring %d\n", 4038 ret); 4039 return ret; 4040 } 4041 4042 if (ab->hw_params->rx_mac_buf_ring) { 4043 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) { 4044 ring_id = dp->rx_mac_buf_ring[i].ring_id; 4045 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4046 i, HAL_RXDMA_BUF); 4047 if (ret) { 4048 ath12k_warn(ab, "failed to configure rx_mac_buf_ring%d %d\n", 4049 i, ret); 4050 return ret; 4051 } 4052 } 4053 } 4054 4055 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) { 4056 ring_id = dp->rxdma_err_dst_ring[i].ring_id; 4057 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4058 i, HAL_RXDMA_DST); 4059 if (ret) { 4060 ath12k_warn(ab, "failed to configure rxdma_err_dest_ring%d %d\n", 4061 i, ret); 4062 return ret; 4063 } 4064 } 4065 4066 if (ab->hw_params->rxdma1_enable) { 4067 ring_id = dp->rxdma_mon_buf_ring.refill_buf_ring.ring_id; 4068 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4069 0, HAL_RXDMA_MONITOR_BUF); 4070 if (ret) { 4071 ath12k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n", 4072 ret); 4073 return ret; 4074 } 4075 4076 ring_id = dp->tx_mon_buf_ring.refill_buf_ring.ring_id; 4077 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4078 0, HAL_TX_MONITOR_BUF); 4079 if (ret) { 4080 ath12k_warn(ab, "failed to configure rxdma_mon_buf_ring %d\n", 4081 ret); 4082 return ret; 4083 } 4084 } 4085 4086 ret = ab->hw_params->hw_ops->rxdma_ring_sel_config(ab); 4087 if (ret) { 4088 ath12k_warn(ab, "failed to setup rxdma ring selection config\n"); 4089 return ret; 4090 } 4091 4092 return 0; 4093 } 4094 4095 int ath12k_dp_rx_alloc(struct ath12k_base *ab) 4096 { 4097 struct ath12k_dp *dp = &ab->dp; 4098 int i, ret; 4099 4100 idr_init(&dp->rx_refill_buf_ring.bufs_idr); 4101 spin_lock_init(&dp->rx_refill_buf_ring.idr_lock); 4102 4103 idr_init(&dp->rxdma_mon_buf_ring.bufs_idr); 4104 spin_lock_init(&dp->rxdma_mon_buf_ring.idr_lock); 4105 4106 idr_init(&dp->tx_mon_buf_ring.bufs_idr); 4107 spin_lock_init(&dp->tx_mon_buf_ring.idr_lock); 4108 4109 ret = ath12k_dp_srng_setup(ab, 4110 &dp->rx_refill_buf_ring.refill_buf_ring, 4111 HAL_RXDMA_BUF, 0, 0, 4112 DP_RXDMA_BUF_RING_SIZE); 4113 if (ret) { 4114 ath12k_warn(ab, "failed to setup rx_refill_buf_ring\n"); 4115 return ret; 4116 } 4117 4118 if (ab->hw_params->rx_mac_buf_ring) { 4119 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) { 4120 ret = ath12k_dp_srng_setup(ab, 4121 &dp->rx_mac_buf_ring[i], 4122 HAL_RXDMA_BUF, 1, 4123 i, 1024); 4124 if (ret) { 4125 ath12k_warn(ab, "failed to setup rx_mac_buf_ring %d\n", 4126 i); 4127 return ret; 4128 } 4129 } 4130 } 4131 4132 for (i = 0; i < ab->hw_params->num_rxdma_dst_ring; i++) { 4133 ret = ath12k_dp_srng_setup(ab, &dp->rxdma_err_dst_ring[i], 4134 HAL_RXDMA_DST, 0, i, 4135 DP_RXDMA_ERR_DST_RING_SIZE); 4136 if (ret) { 4137 ath12k_warn(ab, "failed to setup rxdma_err_dst_ring %d\n", i); 4138 return ret; 4139 } 4140 } 4141 4142 if (ab->hw_params->rxdma1_enable) { 4143 ret = ath12k_dp_srng_setup(ab, 4144 &dp->rxdma_mon_buf_ring.refill_buf_ring, 4145 HAL_RXDMA_MONITOR_BUF, 0, 0, 4146 DP_RXDMA_MONITOR_BUF_RING_SIZE); 4147 if (ret) { 4148 ath12k_warn(ab, "failed to setup HAL_RXDMA_MONITOR_BUF\n"); 4149 return ret; 4150 } 4151 4152 ret = ath12k_dp_srng_setup(ab, 4153 &dp->tx_mon_buf_ring.refill_buf_ring, 4154 HAL_TX_MONITOR_BUF, 0, 0, 4155 DP_TX_MONITOR_BUF_RING_SIZE); 4156 if (ret) { 4157 ath12k_warn(ab, "failed to setup DP_TX_MONITOR_BUF_RING_SIZE\n"); 4158 return ret; 4159 } 4160 } 4161 4162 ret = ath12k_dp_rxdma_buf_setup(ab); 4163 if (ret) { 4164 ath12k_warn(ab, "failed to setup rxdma ring\n"); 4165 return ret; 4166 } 4167 4168 return 0; 4169 } 4170 4171 int ath12k_dp_rx_pdev_alloc(struct ath12k_base *ab, int mac_id) 4172 { 4173 struct ath12k *ar = ab->pdevs[mac_id].ar; 4174 struct ath12k_pdev_dp *dp = &ar->dp; 4175 u32 ring_id; 4176 int i; 4177 int ret; 4178 4179 if (!ab->hw_params->rxdma1_enable) 4180 goto out; 4181 4182 ret = ath12k_dp_rx_pdev_srng_alloc(ar); 4183 if (ret) { 4184 ath12k_warn(ab, "failed to setup rx srngs\n"); 4185 return ret; 4186 } 4187 4188 for (i = 0; i < ab->hw_params->num_rxmda_per_pdev; i++) { 4189 ring_id = dp->rxdma_mon_dst_ring[i].ring_id; 4190 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4191 mac_id + i, 4192 HAL_RXDMA_MONITOR_DST); 4193 if (ret) { 4194 ath12k_warn(ab, 4195 "failed to configure rxdma_mon_dst_ring %d %d\n", 4196 i, ret); 4197 return ret; 4198 } 4199 4200 ring_id = dp->tx_mon_dst_ring[i].ring_id; 4201 ret = ath12k_dp_tx_htt_srng_setup(ab, ring_id, 4202 mac_id + i, 4203 HAL_TX_MONITOR_DST); 4204 if (ret) { 4205 ath12k_warn(ab, 4206 "failed to configure tx_mon_dst_ring %d %d\n", 4207 i, ret); 4208 return ret; 4209 } 4210 } 4211 out: 4212 return 0; 4213 } 4214 4215 static int ath12k_dp_rx_pdev_mon_status_attach(struct ath12k *ar) 4216 { 4217 struct ath12k_pdev_dp *dp = &ar->dp; 4218 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&dp->mon_data; 4219 4220 skb_queue_head_init(&pmon->rx_status_q); 4221 4222 pmon->mon_ppdu_status = DP_PPDU_STATUS_START; 4223 4224 memset(&pmon->rx_mon_stats, 0, 4225 sizeof(pmon->rx_mon_stats)); 4226 return 0; 4227 } 4228 4229 int ath12k_dp_rx_pdev_mon_attach(struct ath12k *ar) 4230 { 4231 struct ath12k_pdev_dp *dp = &ar->dp; 4232 struct ath12k_mon_data *pmon = &dp->mon_data; 4233 int ret = 0; 4234 4235 ret = ath12k_dp_rx_pdev_mon_status_attach(ar); 4236 if (ret) { 4237 ath12k_warn(ar->ab, "pdev_mon_status_attach() failed"); 4238 return ret; 4239 } 4240 4241 /* if rxdma1_enable is false, no need to setup 4242 * rxdma_mon_desc_ring. 4243 */ 4244 if (!ar->ab->hw_params->rxdma1_enable) 4245 return 0; 4246 4247 pmon->mon_last_linkdesc_paddr = 0; 4248 pmon->mon_last_buf_cookie = DP_RX_DESC_COOKIE_MAX + 1; 4249 spin_lock_init(&pmon->mon_lock); 4250 4251 return 0; 4252 } 4253 4254 int ath12k_dp_rx_pktlog_start(struct ath12k_base *ab) 4255 { 4256 /* start reap timer */ 4257 mod_timer(&ab->mon_reap_timer, 4258 jiffies + msecs_to_jiffies(ATH12K_MON_TIMER_INTERVAL)); 4259 4260 return 0; 4261 } 4262 4263 int ath12k_dp_rx_pktlog_stop(struct ath12k_base *ab, bool stop_timer) 4264 { 4265 int ret; 4266 4267 if (stop_timer) 4268 del_timer_sync(&ab->mon_reap_timer); 4269 4270 /* reap all the monitor related rings */ 4271 ret = ath12k_dp_purge_mon_ring(ab); 4272 if (ret) { 4273 ath12k_warn(ab, "failed to purge dp mon ring: %d\n", ret); 4274 return ret; 4275 } 4276 4277 return 0; 4278 } 4279