1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include "dp_mon.h" 8 #include "debug.h" 9 #include "dp_rx.h" 10 #include "dp_tx.h" 11 #include "peer.h" 12 13 static void ath12k_dp_mon_rx_handle_ofdma_info(void *rx_tlv, 14 struct hal_rx_user_status *rx_user_status) 15 { 16 struct hal_rx_ppdu_end_user_stats *ppdu_end_user = 17 (struct hal_rx_ppdu_end_user_stats *)rx_tlv; 18 19 rx_user_status->ul_ofdma_user_v0_word0 = 20 __le32_to_cpu(ppdu_end_user->usr_resp_ref); 21 rx_user_status->ul_ofdma_user_v0_word1 = 22 __le32_to_cpu(ppdu_end_user->usr_resp_ref_ext); 23 } 24 25 static void 26 ath12k_dp_mon_rx_populate_byte_count(void *rx_tlv, void *ppduinfo, 27 struct hal_rx_user_status *rx_user_status) 28 { 29 struct hal_rx_ppdu_end_user_stats *ppdu_end_user = 30 (struct hal_rx_ppdu_end_user_stats *)rx_tlv; 31 u32 mpdu_ok_byte_count = __le32_to_cpu(ppdu_end_user->mpdu_ok_cnt); 32 u32 mpdu_err_byte_count = __le32_to_cpu(ppdu_end_user->mpdu_err_cnt); 33 34 rx_user_status->mpdu_ok_byte_count = 35 u32_get_bits(mpdu_ok_byte_count, 36 HAL_RX_PPDU_END_USER_STATS_MPDU_DELIM_OK_BYTE_COUNT); 37 rx_user_status->mpdu_err_byte_count = 38 u32_get_bits(mpdu_err_byte_count, 39 HAL_RX_PPDU_END_USER_STATS_MPDU_DELIM_ERR_BYTE_COUNT); 40 } 41 42 static void 43 ath12k_dp_mon_rx_populate_mu_user_info(void *rx_tlv, 44 struct hal_rx_mon_ppdu_info *ppdu_info, 45 struct hal_rx_user_status *rx_user_status) 46 { 47 rx_user_status->ast_index = ppdu_info->ast_index; 48 rx_user_status->tid = ppdu_info->tid; 49 rx_user_status->tcp_ack_msdu_count = 50 ppdu_info->tcp_ack_msdu_count; 51 rx_user_status->tcp_msdu_count = 52 ppdu_info->tcp_msdu_count; 53 rx_user_status->udp_msdu_count = 54 ppdu_info->udp_msdu_count; 55 rx_user_status->other_msdu_count = 56 ppdu_info->other_msdu_count; 57 rx_user_status->frame_control = ppdu_info->frame_control; 58 rx_user_status->frame_control_info_valid = 59 ppdu_info->frame_control_info_valid; 60 rx_user_status->data_sequence_control_info_valid = 61 ppdu_info->data_sequence_control_info_valid; 62 rx_user_status->first_data_seq_ctrl = 63 ppdu_info->first_data_seq_ctrl; 64 rx_user_status->preamble_type = ppdu_info->preamble_type; 65 rx_user_status->ht_flags = ppdu_info->ht_flags; 66 rx_user_status->vht_flags = ppdu_info->vht_flags; 67 rx_user_status->he_flags = ppdu_info->he_flags; 68 rx_user_status->rs_flags = ppdu_info->rs_flags; 69 70 rx_user_status->mpdu_cnt_fcs_ok = 71 ppdu_info->num_mpdu_fcs_ok; 72 rx_user_status->mpdu_cnt_fcs_err = 73 ppdu_info->num_mpdu_fcs_err; 74 memcpy(&rx_user_status->mpdu_fcs_ok_bitmap[0], &ppdu_info->mpdu_fcs_ok_bitmap[0], 75 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 76 sizeof(ppdu_info->mpdu_fcs_ok_bitmap[0])); 77 78 ath12k_dp_mon_rx_populate_byte_count(rx_tlv, ppdu_info, rx_user_status); 79 } 80 81 static void ath12k_dp_mon_parse_vht_sig_a(u8 *tlv_data, 82 struct hal_rx_mon_ppdu_info *ppdu_info) 83 { 84 struct hal_rx_vht_sig_a_info *vht_sig = 85 (struct hal_rx_vht_sig_a_info *)tlv_data; 86 u32 nsts, group_id, info0, info1; 87 u8 gi_setting; 88 89 info0 = __le32_to_cpu(vht_sig->info0); 90 info1 = __le32_to_cpu(vht_sig->info1); 91 92 ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING); 93 ppdu_info->mcs = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_MCS); 94 gi_setting = u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING); 95 switch (gi_setting) { 96 case HAL_RX_VHT_SIG_A_NORMAL_GI: 97 ppdu_info->gi = HAL_RX_GI_0_8_US; 98 break; 99 case HAL_RX_VHT_SIG_A_SHORT_GI: 100 case HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY: 101 ppdu_info->gi = HAL_RX_GI_0_4_US; 102 break; 103 } 104 105 ppdu_info->is_stbc = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_STBC); 106 nsts = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS); 107 if (ppdu_info->is_stbc && nsts > 0) 108 nsts = ((nsts + 1) >> 1) - 1; 109 110 ppdu_info->nss = u32_get_bits(nsts, VHT_SIG_SU_NSS_MASK); 111 ppdu_info->bw = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_BW); 112 ppdu_info->beamformed = u32_get_bits(info1, 113 HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED); 114 group_id = u32_get_bits(info0, HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID); 115 if (group_id == 0 || group_id == 63) 116 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 117 else 118 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO; 119 ppdu_info->vht_flag_values5 = group_id; 120 ppdu_info->vht_flag_values3[0] = (((ppdu_info->mcs) << 4) | 121 ppdu_info->nss); 122 ppdu_info->vht_flag_values2 = ppdu_info->bw; 123 ppdu_info->vht_flag_values4 = 124 u32_get_bits(info1, HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING); 125 } 126 127 static void ath12k_dp_mon_parse_ht_sig(u8 *tlv_data, 128 struct hal_rx_mon_ppdu_info *ppdu_info) 129 { 130 struct hal_rx_ht_sig_info *ht_sig = 131 (struct hal_rx_ht_sig_info *)tlv_data; 132 u32 info0 = __le32_to_cpu(ht_sig->info0); 133 u32 info1 = __le32_to_cpu(ht_sig->info1); 134 135 ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HT_SIG_INFO_INFO0_MCS); 136 ppdu_info->bw = u32_get_bits(info0, HAL_RX_HT_SIG_INFO_INFO0_BW); 137 ppdu_info->is_stbc = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_STBC); 138 ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING); 139 ppdu_info->gi = u32_get_bits(info1, HAL_RX_HT_SIG_INFO_INFO1_GI); 140 ppdu_info->nss = (ppdu_info->mcs >> 3); 141 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 142 } 143 144 static void ath12k_dp_mon_parse_l_sig_b(u8 *tlv_data, 145 struct hal_rx_mon_ppdu_info *ppdu_info) 146 { 147 struct hal_rx_lsig_b_info *lsigb = 148 (struct hal_rx_lsig_b_info *)tlv_data; 149 u32 info0 = __le32_to_cpu(lsigb->info0); 150 u8 rate; 151 152 rate = u32_get_bits(info0, HAL_RX_LSIG_B_INFO_INFO0_RATE); 153 switch (rate) { 154 case 1: 155 rate = HAL_RX_LEGACY_RATE_1_MBPS; 156 break; 157 case 2: 158 case 5: 159 rate = HAL_RX_LEGACY_RATE_2_MBPS; 160 break; 161 case 3: 162 case 6: 163 rate = HAL_RX_LEGACY_RATE_5_5_MBPS; 164 break; 165 case 4: 166 case 7: 167 rate = HAL_RX_LEGACY_RATE_11_MBPS; 168 break; 169 default: 170 rate = HAL_RX_LEGACY_RATE_INVALID; 171 } 172 173 ppdu_info->rate = rate; 174 ppdu_info->cck_flag = 1; 175 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 176 } 177 178 static void ath12k_dp_mon_parse_l_sig_a(u8 *tlv_data, 179 struct hal_rx_mon_ppdu_info *ppdu_info) 180 { 181 struct hal_rx_lsig_a_info *lsiga = 182 (struct hal_rx_lsig_a_info *)tlv_data; 183 u32 info0 = __le32_to_cpu(lsiga->info0); 184 u8 rate; 185 186 rate = u32_get_bits(info0, HAL_RX_LSIG_A_INFO_INFO0_RATE); 187 switch (rate) { 188 case 8: 189 rate = HAL_RX_LEGACY_RATE_48_MBPS; 190 break; 191 case 9: 192 rate = HAL_RX_LEGACY_RATE_24_MBPS; 193 break; 194 case 10: 195 rate = HAL_RX_LEGACY_RATE_12_MBPS; 196 break; 197 case 11: 198 rate = HAL_RX_LEGACY_RATE_6_MBPS; 199 break; 200 case 12: 201 rate = HAL_RX_LEGACY_RATE_54_MBPS; 202 break; 203 case 13: 204 rate = HAL_RX_LEGACY_RATE_36_MBPS; 205 break; 206 case 14: 207 rate = HAL_RX_LEGACY_RATE_18_MBPS; 208 break; 209 case 15: 210 rate = HAL_RX_LEGACY_RATE_9_MBPS; 211 break; 212 default: 213 rate = HAL_RX_LEGACY_RATE_INVALID; 214 } 215 216 ppdu_info->rate = rate; 217 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 218 } 219 220 static void ath12k_dp_mon_parse_he_sig_b2_ofdma(u8 *tlv_data, 221 struct hal_rx_mon_ppdu_info *ppdu_info) 222 { 223 struct hal_rx_he_sig_b2_ofdma_info *he_sig_b2_ofdma = 224 (struct hal_rx_he_sig_b2_ofdma_info *)tlv_data; 225 u32 info0, value; 226 227 info0 = __le32_to_cpu(he_sig_b2_ofdma->info0); 228 229 ppdu_info->he_data1 |= HE_MCS_KNOWN | HE_DCM_KNOWN | HE_CODING_KNOWN; 230 231 /* HE-data2 */ 232 ppdu_info->he_data2 |= HE_TXBF_KNOWN; 233 234 ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS); 235 value = ppdu_info->mcs << HE_TRANSMIT_MCS_SHIFT; 236 ppdu_info->he_data3 |= value; 237 238 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM); 239 value = value << HE_DCM_SHIFT; 240 ppdu_info->he_data3 |= value; 241 242 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING); 243 ppdu_info->ldpc = value; 244 value = value << HE_CODING_SHIFT; 245 ppdu_info->he_data3 |= value; 246 247 /* HE-data4 */ 248 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID); 249 value = value << HE_STA_ID_SHIFT; 250 ppdu_info->he_data4 |= value; 251 252 ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS); 253 ppdu_info->beamformed = u32_get_bits(info0, 254 HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF); 255 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA; 256 } 257 258 static void ath12k_dp_mon_parse_he_sig_b2_mu(u8 *tlv_data, 259 struct hal_rx_mon_ppdu_info *ppdu_info) 260 { 261 struct hal_rx_he_sig_b2_mu_info *he_sig_b2_mu = 262 (struct hal_rx_he_sig_b2_mu_info *)tlv_data; 263 u32 info0, value; 264 265 info0 = __le32_to_cpu(he_sig_b2_mu->info0); 266 267 ppdu_info->he_data1 |= HE_MCS_KNOWN | HE_CODING_KNOWN; 268 269 ppdu_info->mcs = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS); 270 value = ppdu_info->mcs << HE_TRANSMIT_MCS_SHIFT; 271 ppdu_info->he_data3 |= value; 272 273 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING); 274 ppdu_info->ldpc = value; 275 value = value << HE_CODING_SHIFT; 276 ppdu_info->he_data3 |= value; 277 278 value = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID); 279 value = value << HE_STA_ID_SHIFT; 280 ppdu_info->he_data4 |= value; 281 282 ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS); 283 } 284 285 static void ath12k_dp_mon_parse_he_sig_b1_mu(u8 *tlv_data, 286 struct hal_rx_mon_ppdu_info *ppdu_info) 287 { 288 struct hal_rx_he_sig_b1_mu_info *he_sig_b1_mu = 289 (struct hal_rx_he_sig_b1_mu_info *)tlv_data; 290 u32 info0 = __le32_to_cpu(he_sig_b1_mu->info0); 291 u16 ru_tones; 292 293 ru_tones = u32_get_bits(info0, 294 HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION); 295 ppdu_info->ru_alloc = ath12k_he_ru_tones_to_nl80211_he_ru_alloc(ru_tones); 296 ppdu_info->he_RU[0] = ru_tones; 297 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO; 298 } 299 300 static void ath12k_dp_mon_parse_he_sig_mu(u8 *tlv_data, 301 struct hal_rx_mon_ppdu_info *ppdu_info) 302 { 303 struct hal_rx_he_sig_a_mu_dl_info *he_sig_a_mu_dl = 304 (struct hal_rx_he_sig_a_mu_dl_info *)tlv_data; 305 u32 info0, info1, value; 306 u16 he_gi = 0, he_ltf = 0; 307 308 info0 = __le32_to_cpu(he_sig_a_mu_dl->info0); 309 info1 = __le32_to_cpu(he_sig_a_mu_dl->info1); 310 311 ppdu_info->he_mu_flags = 1; 312 313 ppdu_info->he_data1 = HE_MU_FORMAT_TYPE; 314 ppdu_info->he_data1 |= 315 HE_BSS_COLOR_KNOWN | 316 HE_DL_UL_KNOWN | 317 HE_LDPC_EXTRA_SYMBOL_KNOWN | 318 HE_STBC_KNOWN | 319 HE_DATA_BW_RU_KNOWN | 320 HE_DOPPLER_KNOWN; 321 322 ppdu_info->he_data2 = 323 HE_GI_KNOWN | 324 HE_LTF_SYMBOLS_KNOWN | 325 HE_PRE_FEC_PADDING_KNOWN | 326 HE_PE_DISAMBIGUITY_KNOWN | 327 HE_TXOP_KNOWN | 328 HE_MIDABLE_PERIODICITY_KNOWN; 329 330 /* data3 */ 331 ppdu_info->he_data3 = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_BSS_COLOR); 332 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_UL_FLAG); 333 value = value << HE_DL_UL_SHIFT; 334 ppdu_info->he_data3 |= value; 335 336 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_LDPC_EXTRA); 337 value = value << HE_LDPC_EXTRA_SYMBOL_SHIFT; 338 ppdu_info->he_data3 |= value; 339 340 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC); 341 value = value << HE_STBC_SHIFT; 342 ppdu_info->he_data3 |= value; 343 344 /* data4 */ 345 ppdu_info->he_data4 = u32_get_bits(info0, 346 HAL_RX_HE_SIG_A_MU_DL_INFO0_SPATIAL_REUSE); 347 ppdu_info->he_data4 = value; 348 349 /* data5 */ 350 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW); 351 ppdu_info->he_data5 = value; 352 ppdu_info->bw = value; 353 354 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_CP_LTF_SIZE); 355 switch (value) { 356 case 0: 357 he_gi = HE_GI_0_8; 358 he_ltf = HE_LTF_4_X; 359 break; 360 case 1: 361 he_gi = HE_GI_0_8; 362 he_ltf = HE_LTF_2_X; 363 break; 364 case 2: 365 he_gi = HE_GI_1_6; 366 he_ltf = HE_LTF_2_X; 367 break; 368 case 3: 369 he_gi = HE_GI_3_2; 370 he_ltf = HE_LTF_4_X; 371 break; 372 } 373 374 ppdu_info->gi = he_gi; 375 value = he_gi << HE_GI_SHIFT; 376 ppdu_info->he_data5 |= value; 377 378 value = he_ltf << HE_LTF_SIZE_SHIFT; 379 ppdu_info->he_data5 |= value; 380 381 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_NUM_LTF_SYMB); 382 value = (value << HE_LTF_SYM_SHIFT); 383 ppdu_info->he_data5 |= value; 384 385 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_FACTOR); 386 value = value << HE_PRE_FEC_PAD_SHIFT; 387 ppdu_info->he_data5 |= value; 388 389 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_PE_DISAM); 390 value = value << HE_PE_DISAMBIGUITY_SHIFT; 391 ppdu_info->he_data5 |= value; 392 393 /*data6*/ 394 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_DOPPLER_INDICATION); 395 value = value << HE_DOPPLER_SHIFT; 396 ppdu_info->he_data6 |= value; 397 398 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_MU_DL_INFO1_TXOP_DURATION); 399 value = value << HE_TXOP_SHIFT; 400 ppdu_info->he_data6 |= value; 401 402 /* HE-MU Flags */ 403 /* HE-MU-flags1 */ 404 ppdu_info->he_flags1 = 405 HE_SIG_B_MCS_KNOWN | 406 HE_SIG_B_DCM_KNOWN | 407 HE_SIG_B_COMPRESSION_FLAG_1_KNOWN | 408 HE_SIG_B_SYM_NUM_KNOWN | 409 HE_RU_0_KNOWN; 410 411 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_MCS_OF_SIGB); 412 ppdu_info->he_flags1 |= value; 413 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_DCM_OF_SIGB); 414 value = value << HE_DCM_FLAG_1_SHIFT; 415 ppdu_info->he_flags1 |= value; 416 417 /* HE-MU-flags2 */ 418 ppdu_info->he_flags2 = HE_BW_KNOWN; 419 420 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW); 421 ppdu_info->he_flags2 |= value; 422 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_COMP_MODE_SIGB); 423 value = value << HE_SIG_B_COMPRESSION_FLAG_2_SHIFT; 424 ppdu_info->he_flags2 |= value; 425 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_MU_DL_INFO0_NUM_SIGB_SYMB); 426 value = value - 1; 427 value = value << HE_NUM_SIG_B_SYMBOLS_SHIFT; 428 ppdu_info->he_flags2 |= value; 429 430 ppdu_info->is_stbc = info1 & 431 HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC; 432 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO; 433 } 434 435 static void ath12k_dp_mon_parse_he_sig_su(u8 *tlv_data, 436 struct hal_rx_mon_ppdu_info *ppdu_info) 437 { 438 struct hal_rx_he_sig_a_su_info *he_sig_a = 439 (struct hal_rx_he_sig_a_su_info *)tlv_data; 440 u32 info0, info1, value; 441 u32 dcm; 442 u8 he_dcm = 0, he_stbc = 0; 443 u16 he_gi = 0, he_ltf = 0; 444 445 ppdu_info->he_flags = 1; 446 447 info0 = __le32_to_cpu(he_sig_a->info0); 448 info1 = __le32_to_cpu(he_sig_a->info1); 449 450 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND); 451 if (value == 0) 452 ppdu_info->he_data1 = HE_TRIG_FORMAT_TYPE; 453 else 454 ppdu_info->he_data1 = HE_SU_FORMAT_TYPE; 455 456 ppdu_info->he_data1 |= 457 HE_BSS_COLOR_KNOWN | 458 HE_BEAM_CHANGE_KNOWN | 459 HE_DL_UL_KNOWN | 460 HE_MCS_KNOWN | 461 HE_DCM_KNOWN | 462 HE_CODING_KNOWN | 463 HE_LDPC_EXTRA_SYMBOL_KNOWN | 464 HE_STBC_KNOWN | 465 HE_DATA_BW_RU_KNOWN | 466 HE_DOPPLER_KNOWN; 467 468 ppdu_info->he_data2 |= 469 HE_GI_KNOWN | 470 HE_TXBF_KNOWN | 471 HE_PE_DISAMBIGUITY_KNOWN | 472 HE_TXOP_KNOWN | 473 HE_LTF_SYMBOLS_KNOWN | 474 HE_PRE_FEC_PADDING_KNOWN | 475 HE_MIDABLE_PERIODICITY_KNOWN; 476 477 ppdu_info->he_data3 = u32_get_bits(info0, 478 HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR); 479 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE); 480 value = value << HE_BEAM_CHANGE_SHIFT; 481 ppdu_info->he_data3 |= value; 482 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG); 483 value = value << HE_DL_UL_SHIFT; 484 ppdu_info->he_data3 |= value; 485 486 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS); 487 ppdu_info->mcs = value; 488 value = value << HE_TRANSMIT_MCS_SHIFT; 489 ppdu_info->he_data3 |= value; 490 491 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM); 492 he_dcm = value; 493 value = value << HE_DCM_SHIFT; 494 ppdu_info->he_data3 |= value; 495 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING); 496 value = value << HE_CODING_SHIFT; 497 ppdu_info->he_data3 |= value; 498 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA); 499 value = value << HE_LDPC_EXTRA_SYMBOL_SHIFT; 500 ppdu_info->he_data3 |= value; 501 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC); 502 he_stbc = value; 503 value = value << HE_STBC_SHIFT; 504 ppdu_info->he_data3 |= value; 505 506 /* data4 */ 507 ppdu_info->he_data4 = u32_get_bits(info0, 508 HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE); 509 510 /* data5 */ 511 value = u32_get_bits(info0, 512 HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW); 513 ppdu_info->he_data5 = value; 514 ppdu_info->bw = value; 515 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE); 516 switch (value) { 517 case 0: 518 he_gi = HE_GI_0_8; 519 he_ltf = HE_LTF_1_X; 520 break; 521 case 1: 522 he_gi = HE_GI_0_8; 523 he_ltf = HE_LTF_2_X; 524 break; 525 case 2: 526 he_gi = HE_GI_1_6; 527 he_ltf = HE_LTF_2_X; 528 break; 529 case 3: 530 if (he_dcm && he_stbc) { 531 he_gi = HE_GI_0_8; 532 he_ltf = HE_LTF_4_X; 533 } else { 534 he_gi = HE_GI_3_2; 535 he_ltf = HE_LTF_4_X; 536 } 537 break; 538 } 539 ppdu_info->gi = he_gi; 540 value = he_gi << HE_GI_SHIFT; 541 ppdu_info->he_data5 |= value; 542 value = he_ltf << HE_LTF_SIZE_SHIFT; 543 ppdu_info->ltf_size = he_ltf; 544 ppdu_info->he_data5 |= value; 545 546 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS); 547 value = (value << HE_LTF_SYM_SHIFT); 548 ppdu_info->he_data5 |= value; 549 550 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR); 551 value = value << HE_PRE_FEC_PAD_SHIFT; 552 ppdu_info->he_data5 |= value; 553 554 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF); 555 value = value << HE_TXBF_SHIFT; 556 ppdu_info->he_data5 |= value; 557 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM); 558 value = value << HE_PE_DISAMBIGUITY_SHIFT; 559 ppdu_info->he_data5 |= value; 560 561 /* data6 */ 562 value = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS); 563 value++; 564 ppdu_info->he_data6 = value; 565 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND); 566 value = value << HE_DOPPLER_SHIFT; 567 ppdu_info->he_data6 |= value; 568 value = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION); 569 value = value << HE_TXOP_SHIFT; 570 ppdu_info->he_data6 |= value; 571 572 ppdu_info->mcs = 573 u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS); 574 ppdu_info->bw = 575 u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW); 576 ppdu_info->ldpc = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING); 577 ppdu_info->is_stbc = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC); 578 ppdu_info->beamformed = u32_get_bits(info1, HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF); 579 dcm = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM); 580 ppdu_info->nss = u32_get_bits(info0, HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS); 581 ppdu_info->dcm = dcm; 582 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 583 } 584 585 static enum hal_rx_mon_status 586 ath12k_dp_mon_rx_parse_status_tlv(struct ath12k_base *ab, 587 struct ath12k_mon_data *pmon, 588 u32 tlv_tag, u8 *tlv_data, u32 userid) 589 { 590 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info; 591 u32 info[7]; 592 593 switch (tlv_tag) { 594 case HAL_RX_PPDU_START: { 595 struct hal_rx_ppdu_start *ppdu_start = 596 (struct hal_rx_ppdu_start *)tlv_data; 597 598 info[0] = __le32_to_cpu(ppdu_start->info0); 599 600 ppdu_info->ppdu_id = 601 u32_get_bits(info[0], HAL_RX_PPDU_START_INFO0_PPDU_ID); 602 ppdu_info->chan_num = __le32_to_cpu(ppdu_start->chan_num); 603 ppdu_info->ppdu_ts = __le32_to_cpu(ppdu_start->ppdu_start_ts); 604 605 if (ppdu_info->ppdu_id != ppdu_info->last_ppdu_id) { 606 ppdu_info->last_ppdu_id = ppdu_info->ppdu_id; 607 ppdu_info->num_users = 0; 608 memset(&ppdu_info->mpdu_fcs_ok_bitmap, 0, 609 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 610 sizeof(ppdu_info->mpdu_fcs_ok_bitmap[0])); 611 } 612 break; 613 } 614 case HAL_RX_PPDU_END_USER_STATS: { 615 struct hal_rx_ppdu_end_user_stats *eu_stats = 616 (struct hal_rx_ppdu_end_user_stats *)tlv_data; 617 618 info[0] = __le32_to_cpu(eu_stats->info0); 619 info[1] = __le32_to_cpu(eu_stats->info1); 620 info[2] = __le32_to_cpu(eu_stats->info2); 621 info[4] = __le32_to_cpu(eu_stats->info4); 622 info[5] = __le32_to_cpu(eu_stats->info5); 623 info[6] = __le32_to_cpu(eu_stats->info6); 624 625 ppdu_info->ast_index = 626 u32_get_bits(info[2], HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX); 627 ppdu_info->fc_valid = 628 u32_get_bits(info[1], HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID); 629 ppdu_info->tid = 630 ffs(u32_get_bits(info[6], 631 HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP) 632 - 1); 633 ppdu_info->tcp_msdu_count = 634 u32_get_bits(info[4], 635 HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT); 636 ppdu_info->udp_msdu_count = 637 u32_get_bits(info[4], 638 HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT); 639 ppdu_info->other_msdu_count = 640 u32_get_bits(info[5], 641 HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT); 642 ppdu_info->tcp_ack_msdu_count = 643 u32_get_bits(info[5], 644 HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT); 645 ppdu_info->preamble_type = 646 u32_get_bits(info[1], 647 HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE); 648 ppdu_info->num_mpdu_fcs_ok = 649 u32_get_bits(info[1], 650 HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK); 651 ppdu_info->num_mpdu_fcs_err = 652 u32_get_bits(info[0], 653 HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR); 654 switch (ppdu_info->preamble_type) { 655 case HAL_RX_PREAMBLE_11N: 656 ppdu_info->ht_flags = 1; 657 break; 658 case HAL_RX_PREAMBLE_11AC: 659 ppdu_info->vht_flags = 1; 660 break; 661 case HAL_RX_PREAMBLE_11AX: 662 ppdu_info->he_flags = 1; 663 break; 664 default: 665 break; 666 } 667 668 if (userid < HAL_MAX_UL_MU_USERS) { 669 struct hal_rx_user_status *rxuser_stats = 670 &ppdu_info->userstats[userid]; 671 ppdu_info->num_users += 1; 672 673 ath12k_dp_mon_rx_handle_ofdma_info(tlv_data, rxuser_stats); 674 ath12k_dp_mon_rx_populate_mu_user_info(tlv_data, ppdu_info, 675 rxuser_stats); 676 } 677 ppdu_info->mpdu_fcs_ok_bitmap[0] = __le32_to_cpu(eu_stats->rsvd1[0]); 678 ppdu_info->mpdu_fcs_ok_bitmap[1] = __le32_to_cpu(eu_stats->rsvd1[1]); 679 break; 680 } 681 case HAL_RX_PPDU_END_USER_STATS_EXT: { 682 struct hal_rx_ppdu_end_user_stats_ext *eu_stats = 683 (struct hal_rx_ppdu_end_user_stats_ext *)tlv_data; 684 ppdu_info->mpdu_fcs_ok_bitmap[2] = __le32_to_cpu(eu_stats->info1); 685 ppdu_info->mpdu_fcs_ok_bitmap[3] = __le32_to_cpu(eu_stats->info2); 686 ppdu_info->mpdu_fcs_ok_bitmap[4] = __le32_to_cpu(eu_stats->info3); 687 ppdu_info->mpdu_fcs_ok_bitmap[5] = __le32_to_cpu(eu_stats->info4); 688 ppdu_info->mpdu_fcs_ok_bitmap[6] = __le32_to_cpu(eu_stats->info5); 689 ppdu_info->mpdu_fcs_ok_bitmap[7] = __le32_to_cpu(eu_stats->info6); 690 break; 691 } 692 case HAL_PHYRX_HT_SIG: 693 ath12k_dp_mon_parse_ht_sig(tlv_data, ppdu_info); 694 break; 695 696 case HAL_PHYRX_L_SIG_B: 697 ath12k_dp_mon_parse_l_sig_b(tlv_data, ppdu_info); 698 break; 699 700 case HAL_PHYRX_L_SIG_A: 701 ath12k_dp_mon_parse_l_sig_a(tlv_data, ppdu_info); 702 break; 703 704 case HAL_PHYRX_VHT_SIG_A: 705 ath12k_dp_mon_parse_vht_sig_a(tlv_data, ppdu_info); 706 break; 707 708 case HAL_PHYRX_HE_SIG_A_SU: 709 ath12k_dp_mon_parse_he_sig_su(tlv_data, ppdu_info); 710 break; 711 712 case HAL_PHYRX_HE_SIG_A_MU_DL: 713 ath12k_dp_mon_parse_he_sig_mu(tlv_data, ppdu_info); 714 break; 715 716 case HAL_PHYRX_HE_SIG_B1_MU: 717 ath12k_dp_mon_parse_he_sig_b1_mu(tlv_data, ppdu_info); 718 break; 719 720 case HAL_PHYRX_HE_SIG_B2_MU: 721 ath12k_dp_mon_parse_he_sig_b2_mu(tlv_data, ppdu_info); 722 break; 723 724 case HAL_PHYRX_HE_SIG_B2_OFDMA: 725 ath12k_dp_mon_parse_he_sig_b2_ofdma(tlv_data, ppdu_info); 726 break; 727 728 case HAL_PHYRX_RSSI_LEGACY: { 729 struct hal_rx_phyrx_rssi_legacy_info *rssi = 730 (struct hal_rx_phyrx_rssi_legacy_info *)tlv_data; 731 u32 reception_type = 0; 732 u32 rssi_legacy_info = __le32_to_cpu(rssi->rsvd[0]); 733 734 info[0] = __le32_to_cpu(rssi->info0); 735 736 /* TODO: Please note that the combined rssi will not be accurate 737 * in MU case. Rssi in MU needs to be retrieved from 738 * PHYRX_OTHER_RECEIVE_INFO TLV. 739 */ 740 ppdu_info->rssi_comb = 741 u32_get_bits(info[0], 742 HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO0_RSSI_COMB); 743 reception_type = 744 u32_get_bits(rssi_legacy_info, 745 HAL_RX_PHYRX_RSSI_LEGACY_INFO_RSVD1_RECEPTION); 746 747 switch (reception_type) { 748 case HAL_RECEPTION_TYPE_ULOFMDA: 749 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_OFDMA; 750 break; 751 case HAL_RECEPTION_TYPE_ULMIMO: 752 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_MU_MIMO; 753 break; 754 default: 755 ppdu_info->reception_type = HAL_RX_RECEPTION_TYPE_SU; 756 break; 757 } 758 break; 759 } 760 case HAL_RXPCU_PPDU_END_INFO: { 761 struct hal_rx_ppdu_end_duration *ppdu_rx_duration = 762 (struct hal_rx_ppdu_end_duration *)tlv_data; 763 764 info[0] = __le32_to_cpu(ppdu_rx_duration->info0); 765 ppdu_info->rx_duration = 766 u32_get_bits(info[0], HAL_RX_PPDU_END_DURATION); 767 ppdu_info->tsft = __le32_to_cpu(ppdu_rx_duration->rsvd0[1]); 768 ppdu_info->tsft = (ppdu_info->tsft << 32) | 769 __le32_to_cpu(ppdu_rx_duration->rsvd0[0]); 770 break; 771 } 772 case HAL_RX_MPDU_START: { 773 struct hal_rx_mpdu_start *mpdu_start = 774 (struct hal_rx_mpdu_start *)tlv_data; 775 struct dp_mon_mpdu *mon_mpdu = pmon->mon_mpdu; 776 u16 peer_id; 777 778 info[1] = __le32_to_cpu(mpdu_start->info1); 779 peer_id = u32_get_bits(info[1], HAL_RX_MPDU_START_INFO1_PEERID); 780 if (peer_id) 781 ppdu_info->peer_id = peer_id; 782 783 ppdu_info->mpdu_len += u32_get_bits(info[1], 784 HAL_RX_MPDU_START_INFO2_MPDU_LEN); 785 if (userid < HAL_MAX_UL_MU_USERS) { 786 info[0] = __le32_to_cpu(mpdu_start->info0); 787 ppdu_info->userid = userid; 788 ppdu_info->ampdu_id[userid] = 789 u32_get_bits(info[0], HAL_RX_MPDU_START_INFO1_PEERID); 790 } 791 792 mon_mpdu = kzalloc(sizeof(*mon_mpdu), GFP_ATOMIC); 793 if (!mon_mpdu) 794 return HAL_RX_MON_STATUS_PPDU_NOT_DONE; 795 796 break; 797 } 798 case HAL_RX_MSDU_START: 799 /* TODO: add msdu start parsing logic */ 800 break; 801 case HAL_MON_BUF_ADDR: { 802 struct dp_rxdma_ring *buf_ring = &ab->dp.rxdma_mon_buf_ring; 803 struct dp_mon_packet_info *packet_info = 804 (struct dp_mon_packet_info *)tlv_data; 805 int buf_id = u32_get_bits(packet_info->cookie, 806 DP_RXDMA_BUF_COOKIE_BUF_ID); 807 struct sk_buff *msdu; 808 struct dp_mon_mpdu *mon_mpdu = pmon->mon_mpdu; 809 struct ath12k_skb_rxcb *rxcb; 810 811 spin_lock_bh(&buf_ring->idr_lock); 812 msdu = idr_remove(&buf_ring->bufs_idr, buf_id); 813 spin_unlock_bh(&buf_ring->idr_lock); 814 815 if (unlikely(!msdu)) { 816 ath12k_warn(ab, "montior destination with invalid buf_id %d\n", 817 buf_id); 818 return HAL_RX_MON_STATUS_PPDU_NOT_DONE; 819 } 820 821 rxcb = ATH12K_SKB_RXCB(msdu); 822 dma_unmap_single(ab->dev, rxcb->paddr, 823 msdu->len + skb_tailroom(msdu), 824 DMA_FROM_DEVICE); 825 826 if (mon_mpdu->tail) 827 mon_mpdu->tail->next = msdu; 828 else 829 mon_mpdu->tail = msdu; 830 831 ath12k_dp_mon_buf_replenish(ab, buf_ring, 1); 832 833 break; 834 } 835 case HAL_RX_MSDU_END: { 836 struct rx_msdu_end_qcn9274 *msdu_end = 837 (struct rx_msdu_end_qcn9274 *)tlv_data; 838 bool is_first_msdu_in_mpdu; 839 u16 msdu_end_info; 840 841 msdu_end_info = __le16_to_cpu(msdu_end->info5); 842 is_first_msdu_in_mpdu = u32_get_bits(msdu_end_info, 843 RX_MSDU_END_INFO5_FIRST_MSDU); 844 if (is_first_msdu_in_mpdu) { 845 pmon->mon_mpdu->head = pmon->mon_mpdu->tail; 846 pmon->mon_mpdu->tail = NULL; 847 } 848 break; 849 } 850 case HAL_RX_MPDU_END: 851 list_add_tail(&pmon->mon_mpdu->list, &pmon->dp_rx_mon_mpdu_list); 852 break; 853 case HAL_DUMMY: 854 return HAL_RX_MON_STATUS_BUF_DONE; 855 case HAL_RX_PPDU_END_STATUS_DONE: 856 case 0: 857 return HAL_RX_MON_STATUS_PPDU_DONE; 858 default: 859 break; 860 } 861 862 return HAL_RX_MON_STATUS_PPDU_NOT_DONE; 863 } 864 865 static void ath12k_dp_mon_rx_msdus_set_payload(struct ath12k *ar, struct sk_buff *msdu) 866 { 867 u32 rx_pkt_offset, l2_hdr_offset; 868 869 rx_pkt_offset = ar->ab->hw_params->hal_desc_sz; 870 l2_hdr_offset = ath12k_dp_rx_h_l3pad(ar->ab, 871 (struct hal_rx_desc *)msdu->data); 872 skb_pull(msdu, rx_pkt_offset + l2_hdr_offset); 873 } 874 875 static struct sk_buff * 876 ath12k_dp_mon_rx_merg_msdus(struct ath12k *ar, 877 u32 mac_id, struct sk_buff *head_msdu, 878 struct ieee80211_rx_status *rxs, bool *fcs_err) 879 { 880 struct ath12k_base *ab = ar->ab; 881 struct sk_buff *msdu, *mpdu_buf, *prev_buf; 882 struct hal_rx_desc *rx_desc; 883 u8 *hdr_desc, *dest, decap_format; 884 struct ieee80211_hdr_3addr *wh; 885 u32 err_bitmap; 886 887 mpdu_buf = NULL; 888 889 if (!head_msdu) 890 goto err_merge_fail; 891 892 rx_desc = (struct hal_rx_desc *)head_msdu->data; 893 err_bitmap = ath12k_dp_rx_h_mpdu_err(ab, rx_desc); 894 895 if (err_bitmap & HAL_RX_MPDU_ERR_FCS) 896 *fcs_err = true; 897 898 decap_format = ath12k_dp_rx_h_decap_type(ab, rx_desc); 899 900 ath12k_dp_rx_h_ppdu(ar, rx_desc, rxs); 901 902 if (decap_format == DP_RX_DECAP_TYPE_RAW) { 903 ath12k_dp_mon_rx_msdus_set_payload(ar, head_msdu); 904 905 prev_buf = head_msdu; 906 msdu = head_msdu->next; 907 908 while (msdu) { 909 ath12k_dp_mon_rx_msdus_set_payload(ar, msdu); 910 911 prev_buf = msdu; 912 msdu = msdu->next; 913 } 914 915 prev_buf->next = NULL; 916 917 skb_trim(prev_buf, prev_buf->len - HAL_RX_FCS_LEN); 918 } else if (decap_format == DP_RX_DECAP_TYPE_NATIVE_WIFI) { 919 u8 qos_pkt = 0; 920 921 rx_desc = (struct hal_rx_desc *)head_msdu->data; 922 hdr_desc = ab->hw_params->hal_ops->rx_desc_get_msdu_payload(rx_desc); 923 924 /* Base size */ 925 wh = (struct ieee80211_hdr_3addr *)hdr_desc; 926 927 if (ieee80211_is_data_qos(wh->frame_control)) 928 qos_pkt = 1; 929 930 msdu = head_msdu; 931 932 while (msdu) { 933 ath12k_dp_mon_rx_msdus_set_payload(ar, msdu); 934 if (qos_pkt) { 935 dest = skb_push(msdu, sizeof(__le16)); 936 if (!dest) 937 goto err_merge_fail; 938 memcpy(dest, hdr_desc, sizeof(struct ieee80211_qos_hdr)); 939 } 940 prev_buf = msdu; 941 msdu = msdu->next; 942 } 943 dest = skb_put(prev_buf, HAL_RX_FCS_LEN); 944 if (!dest) 945 goto err_merge_fail; 946 947 ath12k_dbg(ab, ATH12K_DBG_DATA, 948 "mpdu_buf %pK mpdu_buf->len %u", 949 prev_buf, prev_buf->len); 950 } else { 951 ath12k_dbg(ab, ATH12K_DBG_DATA, 952 "decap format %d is not supported!\n", 953 decap_format); 954 goto err_merge_fail; 955 } 956 957 return head_msdu; 958 959 err_merge_fail: 960 if (mpdu_buf && decap_format != DP_RX_DECAP_TYPE_RAW) { 961 ath12k_dbg(ab, ATH12K_DBG_DATA, 962 "err_merge_fail mpdu_buf %pK", mpdu_buf); 963 /* Free the head buffer */ 964 dev_kfree_skb_any(mpdu_buf); 965 } 966 return NULL; 967 } 968 969 static void 970 ath12k_dp_mon_rx_update_radiotap_he(struct hal_rx_mon_ppdu_info *rx_status, 971 u8 *rtap_buf) 972 { 973 u32 rtap_len = 0; 974 975 put_unaligned_le16(rx_status->he_data1, &rtap_buf[rtap_len]); 976 rtap_len += 2; 977 978 put_unaligned_le16(rx_status->he_data2, &rtap_buf[rtap_len]); 979 rtap_len += 2; 980 981 put_unaligned_le16(rx_status->he_data3, &rtap_buf[rtap_len]); 982 rtap_len += 2; 983 984 put_unaligned_le16(rx_status->he_data4, &rtap_buf[rtap_len]); 985 rtap_len += 2; 986 987 put_unaligned_le16(rx_status->he_data5, &rtap_buf[rtap_len]); 988 rtap_len += 2; 989 990 put_unaligned_le16(rx_status->he_data6, &rtap_buf[rtap_len]); 991 } 992 993 static void 994 ath12k_dp_mon_rx_update_radiotap_he_mu(struct hal_rx_mon_ppdu_info *rx_status, 995 u8 *rtap_buf) 996 { 997 u32 rtap_len = 0; 998 999 put_unaligned_le16(rx_status->he_flags1, &rtap_buf[rtap_len]); 1000 rtap_len += 2; 1001 1002 put_unaligned_le16(rx_status->he_flags2, &rtap_buf[rtap_len]); 1003 rtap_len += 2; 1004 1005 rtap_buf[rtap_len] = rx_status->he_RU[0]; 1006 rtap_len += 1; 1007 1008 rtap_buf[rtap_len] = rx_status->he_RU[1]; 1009 rtap_len += 1; 1010 1011 rtap_buf[rtap_len] = rx_status->he_RU[2]; 1012 rtap_len += 1; 1013 1014 rtap_buf[rtap_len] = rx_status->he_RU[3]; 1015 } 1016 1017 static void ath12k_dp_mon_update_radiotap(struct ath12k *ar, 1018 struct hal_rx_mon_ppdu_info *ppduinfo, 1019 struct sk_buff *mon_skb, 1020 struct ieee80211_rx_status *rxs) 1021 { 1022 struct ieee80211_supported_band *sband; 1023 u8 *ptr = NULL; 1024 u16 ampdu_id = ppduinfo->ampdu_id[ppduinfo->userid]; 1025 1026 rxs->flag |= RX_FLAG_MACTIME_START; 1027 rxs->signal = ppduinfo->rssi_comb + ATH12K_DEFAULT_NOISE_FLOOR; 1028 rxs->nss = ppduinfo->nss + 1; 1029 1030 if (ampdu_id) { 1031 rxs->flag |= RX_FLAG_AMPDU_DETAILS; 1032 rxs->ampdu_reference = ampdu_id; 1033 } 1034 1035 if (ppduinfo->he_mu_flags) { 1036 rxs->flag |= RX_FLAG_RADIOTAP_HE_MU; 1037 rxs->encoding = RX_ENC_HE; 1038 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he_mu)); 1039 ath12k_dp_mon_rx_update_radiotap_he_mu(ppduinfo, ptr); 1040 } else if (ppduinfo->he_flags) { 1041 rxs->flag |= RX_FLAG_RADIOTAP_HE; 1042 rxs->encoding = RX_ENC_HE; 1043 ptr = skb_push(mon_skb, sizeof(struct ieee80211_radiotap_he)); 1044 ath12k_dp_mon_rx_update_radiotap_he(ppduinfo, ptr); 1045 rxs->rate_idx = ppduinfo->rate; 1046 } else if (ppduinfo->vht_flags) { 1047 rxs->encoding = RX_ENC_VHT; 1048 rxs->rate_idx = ppduinfo->rate; 1049 } else if (ppduinfo->ht_flags) { 1050 rxs->encoding = RX_ENC_HT; 1051 rxs->rate_idx = ppduinfo->rate; 1052 } else { 1053 rxs->encoding = RX_ENC_LEGACY; 1054 sband = &ar->mac.sbands[rxs->band]; 1055 rxs->rate_idx = ath12k_mac_hw_rate_to_idx(sband, ppduinfo->rate, 1056 ppduinfo->cck_flag); 1057 } 1058 1059 rxs->mactime = ppduinfo->tsft; 1060 } 1061 1062 static void ath12k_dp_mon_rx_deliver_msdu(struct ath12k *ar, struct napi_struct *napi, 1063 struct sk_buff *msdu, 1064 struct ieee80211_rx_status *status) 1065 { 1066 static const struct ieee80211_radiotap_he known = { 1067 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN | 1068 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN), 1069 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN), 1070 }; 1071 struct ieee80211_rx_status *rx_status; 1072 struct ieee80211_radiotap_he *he = NULL; 1073 struct ieee80211_sta *pubsta = NULL; 1074 struct ath12k_peer *peer; 1075 struct ath12k_skb_rxcb *rxcb = ATH12K_SKB_RXCB(msdu); 1076 u8 decap = DP_RX_DECAP_TYPE_RAW; 1077 bool is_mcbc = rxcb->is_mcbc; 1078 bool is_eapol_tkip = rxcb->is_eapol; 1079 1080 if ((status->encoding == RX_ENC_HE) && !(status->flag & RX_FLAG_RADIOTAP_HE) && 1081 !(status->flag & RX_FLAG_SKIP_MONITOR)) { 1082 he = skb_push(msdu, sizeof(known)); 1083 memcpy(he, &known, sizeof(known)); 1084 status->flag |= RX_FLAG_RADIOTAP_HE; 1085 } 1086 1087 if (!(status->flag & RX_FLAG_ONLY_MONITOR)) 1088 decap = ath12k_dp_rx_h_decap_type(ar->ab, rxcb->rx_desc); 1089 spin_lock_bh(&ar->ab->base_lock); 1090 peer = ath12k_dp_rx_h_find_peer(ar->ab, msdu); 1091 if (peer && peer->sta) 1092 pubsta = peer->sta; 1093 spin_unlock_bh(&ar->ab->base_lock); 1094 1095 ath12k_dbg(ar->ab, ATH12K_DBG_DATA, 1096 "rx skb %pK len %u peer %pM %u %s %s%s%s%s%s%s%s %srate_idx %u vht_nss %u freq %u band %u flag 0x%x fcs-err %i mic-err %i amsdu-more %i\n", 1097 msdu, 1098 msdu->len, 1099 peer ? peer->addr : NULL, 1100 rxcb->tid, 1101 (is_mcbc) ? "mcast" : "ucast", 1102 (status->encoding == RX_ENC_LEGACY) ? "legacy" : "", 1103 (status->encoding == RX_ENC_HT) ? "ht" : "", 1104 (status->encoding == RX_ENC_VHT) ? "vht" : "", 1105 (status->encoding == RX_ENC_HE) ? "he" : "", 1106 (status->bw == RATE_INFO_BW_40) ? "40" : "", 1107 (status->bw == RATE_INFO_BW_80) ? "80" : "", 1108 (status->bw == RATE_INFO_BW_160) ? "160" : "", 1109 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? "sgi " : "", 1110 status->rate_idx, 1111 status->nss, 1112 status->freq, 1113 status->band, status->flag, 1114 !!(status->flag & RX_FLAG_FAILED_FCS_CRC), 1115 !!(status->flag & RX_FLAG_MMIC_ERROR), 1116 !!(status->flag & RX_FLAG_AMSDU_MORE)); 1117 1118 ath12k_dbg_dump(ar->ab, ATH12K_DBG_DP_RX, NULL, "dp rx msdu: ", 1119 msdu->data, msdu->len); 1120 rx_status = IEEE80211_SKB_RXCB(msdu); 1121 *rx_status = *status; 1122 1123 /* TODO: trace rx packet */ 1124 1125 /* PN for multicast packets are not validate in HW, 1126 * so skip 802.3 rx path 1127 * Also, fast_rx expectes the STA to be authorized, hence 1128 * eapol packets are sent in slow path. 1129 */ 1130 if (decap == DP_RX_DECAP_TYPE_ETHERNET2_DIX && !is_eapol_tkip && 1131 !(is_mcbc && rx_status->flag & RX_FLAG_DECRYPTED)) 1132 rx_status->flag |= RX_FLAG_8023; 1133 1134 ieee80211_rx_napi(ar->hw, pubsta, msdu, napi); 1135 } 1136 1137 static int ath12k_dp_mon_rx_deliver(struct ath12k *ar, u32 mac_id, 1138 struct sk_buff *head_msdu, 1139 struct hal_rx_mon_ppdu_info *ppduinfo, 1140 struct napi_struct *napi) 1141 { 1142 struct ath12k_pdev_dp *dp = &ar->dp; 1143 struct sk_buff *mon_skb, *skb_next, *header; 1144 struct ieee80211_rx_status *rxs = &dp->rx_status; 1145 bool fcs_err = false; 1146 1147 mon_skb = ath12k_dp_mon_rx_merg_msdus(ar, mac_id, head_msdu, 1148 rxs, &fcs_err); 1149 if (!mon_skb) 1150 goto mon_deliver_fail; 1151 1152 header = mon_skb; 1153 rxs->flag = 0; 1154 1155 if (fcs_err) 1156 rxs->flag = RX_FLAG_FAILED_FCS_CRC; 1157 1158 do { 1159 skb_next = mon_skb->next; 1160 if (!skb_next) 1161 rxs->flag &= ~RX_FLAG_AMSDU_MORE; 1162 else 1163 rxs->flag |= RX_FLAG_AMSDU_MORE; 1164 1165 if (mon_skb == header) { 1166 header = NULL; 1167 rxs->flag &= ~RX_FLAG_ALLOW_SAME_PN; 1168 } else { 1169 rxs->flag |= RX_FLAG_ALLOW_SAME_PN; 1170 } 1171 rxs->flag |= RX_FLAG_ONLY_MONITOR; 1172 ath12k_dp_mon_update_radiotap(ar, ppduinfo, mon_skb, rxs); 1173 ath12k_dp_mon_rx_deliver_msdu(ar, napi, mon_skb, rxs); 1174 mon_skb = skb_next; 1175 } while (mon_skb); 1176 rxs->flag = 0; 1177 1178 return 0; 1179 1180 mon_deliver_fail: 1181 mon_skb = head_msdu; 1182 while (mon_skb) { 1183 skb_next = mon_skb->next; 1184 dev_kfree_skb_any(mon_skb); 1185 mon_skb = skb_next; 1186 } 1187 return -EINVAL; 1188 } 1189 1190 static enum hal_rx_mon_status 1191 ath12k_dp_mon_parse_rx_dest(struct ath12k_base *ab, struct ath12k_mon_data *pmon, 1192 struct sk_buff *skb) 1193 { 1194 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info; 1195 struct hal_tlv_hdr *tlv; 1196 enum hal_rx_mon_status hal_status; 1197 u32 tlv_userid = 0; 1198 u16 tlv_tag, tlv_len; 1199 u8 *ptr = skb->data; 1200 1201 memset(ppdu_info, 0, sizeof(struct hal_rx_mon_ppdu_info)); 1202 1203 do { 1204 tlv = (struct hal_tlv_hdr *)ptr; 1205 tlv_tag = le32_get_bits(tlv->tl, HAL_TLV_HDR_TAG); 1206 tlv_len = le32_get_bits(tlv->tl, HAL_TLV_HDR_LEN); 1207 tlv_userid = le32_get_bits(tlv->tl, HAL_TLV_USR_ID); 1208 ptr += sizeof(*tlv); 1209 1210 /* The actual length of PPDU_END is the combined length of many PHY 1211 * TLVs that follow. Skip the TLV header and 1212 * rx_rxpcu_classification_overview that follows the header to get to 1213 * next TLV. 1214 */ 1215 1216 if (tlv_tag == HAL_RX_PPDU_END) 1217 tlv_len = sizeof(struct hal_rx_rxpcu_classification_overview); 1218 1219 hal_status = ath12k_dp_mon_rx_parse_status_tlv(ab, pmon, 1220 tlv_tag, ptr, tlv_userid); 1221 ptr += tlv_len; 1222 ptr = PTR_ALIGN(ptr, HAL_TLV_ALIGN); 1223 1224 if ((ptr - skb->data) >= DP_RX_BUFFER_SIZE) 1225 break; 1226 1227 } while (hal_status == HAL_RX_MON_STATUS_PPDU_NOT_DONE); 1228 1229 return hal_status; 1230 } 1231 1232 enum hal_rx_mon_status 1233 ath12k_dp_mon_rx_parse_mon_status(struct ath12k *ar, 1234 struct ath12k_mon_data *pmon, 1235 int mac_id, 1236 struct sk_buff *skb, 1237 struct napi_struct *napi) 1238 { 1239 struct ath12k_base *ab = ar->ab; 1240 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info; 1241 struct dp_mon_mpdu *tmp; 1242 struct dp_mon_mpdu *mon_mpdu = pmon->mon_mpdu; 1243 struct sk_buff *head_msdu, *tail_msdu; 1244 enum hal_rx_mon_status hal_status = HAL_RX_MON_STATUS_BUF_DONE; 1245 1246 ath12k_dp_mon_parse_rx_dest(ab, pmon, skb); 1247 1248 list_for_each_entry_safe(mon_mpdu, tmp, &pmon->dp_rx_mon_mpdu_list, list) { 1249 list_del(&mon_mpdu->list); 1250 head_msdu = mon_mpdu->head; 1251 tail_msdu = mon_mpdu->tail; 1252 1253 if (head_msdu && tail_msdu) { 1254 ath12k_dp_mon_rx_deliver(ar, mac_id, head_msdu, 1255 ppdu_info, napi); 1256 } 1257 1258 kfree(mon_mpdu); 1259 } 1260 return hal_status; 1261 } 1262 1263 int ath12k_dp_mon_buf_replenish(struct ath12k_base *ab, 1264 struct dp_rxdma_ring *buf_ring, 1265 int req_entries) 1266 { 1267 struct hal_mon_buf_ring *mon_buf; 1268 struct sk_buff *skb; 1269 struct hal_srng *srng; 1270 dma_addr_t paddr; 1271 u32 cookie, buf_id; 1272 1273 srng = &ab->hal.srng_list[buf_ring->refill_buf_ring.ring_id]; 1274 spin_lock_bh(&srng->lock); 1275 ath12k_hal_srng_access_begin(ab, srng); 1276 1277 while (req_entries > 0) { 1278 skb = dev_alloc_skb(DP_RX_BUFFER_SIZE + DP_RX_BUFFER_ALIGN_SIZE); 1279 if (unlikely(!skb)) 1280 goto fail_alloc_skb; 1281 1282 if (!IS_ALIGNED((unsigned long)skb->data, DP_RX_BUFFER_ALIGN_SIZE)) { 1283 skb_pull(skb, 1284 PTR_ALIGN(skb->data, DP_RX_BUFFER_ALIGN_SIZE) - 1285 skb->data); 1286 } 1287 1288 paddr = dma_map_single(ab->dev, skb->data, 1289 skb->len + skb_tailroom(skb), 1290 DMA_FROM_DEVICE); 1291 1292 if (unlikely(dma_mapping_error(ab->dev, paddr))) 1293 goto fail_free_skb; 1294 1295 spin_lock_bh(&buf_ring->idr_lock); 1296 buf_id = idr_alloc(&buf_ring->bufs_idr, skb, 0, 1297 buf_ring->bufs_max * 3, GFP_ATOMIC); 1298 spin_unlock_bh(&buf_ring->idr_lock); 1299 1300 if (unlikely(buf_id < 0)) 1301 goto fail_dma_unmap; 1302 1303 mon_buf = ath12k_hal_srng_src_get_next_entry(ab, srng); 1304 if (unlikely(!mon_buf)) 1305 goto fail_idr_remove; 1306 1307 ATH12K_SKB_RXCB(skb)->paddr = paddr; 1308 1309 cookie = u32_encode_bits(buf_id, DP_RXDMA_BUF_COOKIE_BUF_ID); 1310 1311 mon_buf->paddr_lo = cpu_to_le32(lower_32_bits(paddr)); 1312 mon_buf->paddr_hi = cpu_to_le32(upper_32_bits(paddr)); 1313 mon_buf->cookie = cpu_to_le64(cookie); 1314 1315 req_entries--; 1316 } 1317 1318 ath12k_hal_srng_access_end(ab, srng); 1319 spin_unlock_bh(&srng->lock); 1320 return 0; 1321 1322 fail_idr_remove: 1323 spin_lock_bh(&buf_ring->idr_lock); 1324 idr_remove(&buf_ring->bufs_idr, buf_id); 1325 spin_unlock_bh(&buf_ring->idr_lock); 1326 fail_dma_unmap: 1327 dma_unmap_single(ab->dev, paddr, skb->len + skb_tailroom(skb), 1328 DMA_FROM_DEVICE); 1329 fail_free_skb: 1330 dev_kfree_skb_any(skb); 1331 fail_alloc_skb: 1332 ath12k_hal_srng_access_end(ab, srng); 1333 spin_unlock_bh(&srng->lock); 1334 return -ENOMEM; 1335 } 1336 1337 static struct dp_mon_tx_ppdu_info * 1338 ath12k_dp_mon_tx_get_ppdu_info(struct ath12k_mon_data *pmon, 1339 unsigned int ppdu_id, 1340 enum dp_mon_tx_ppdu_info_type type) 1341 { 1342 struct dp_mon_tx_ppdu_info *tx_ppdu_info; 1343 1344 if (type == DP_MON_TX_PROT_PPDU_INFO) { 1345 tx_ppdu_info = pmon->tx_prot_ppdu_info; 1346 1347 if (tx_ppdu_info && !tx_ppdu_info->is_used) 1348 return tx_ppdu_info; 1349 kfree(tx_ppdu_info); 1350 } else { 1351 tx_ppdu_info = pmon->tx_data_ppdu_info; 1352 1353 if (tx_ppdu_info && !tx_ppdu_info->is_used) 1354 return tx_ppdu_info; 1355 kfree(tx_ppdu_info); 1356 } 1357 1358 /* allocate new tx_ppdu_info */ 1359 tx_ppdu_info = kzalloc(sizeof(*tx_ppdu_info), GFP_ATOMIC); 1360 if (!tx_ppdu_info) 1361 return NULL; 1362 1363 tx_ppdu_info->is_used = 0; 1364 tx_ppdu_info->ppdu_id = ppdu_id; 1365 1366 if (type == DP_MON_TX_PROT_PPDU_INFO) 1367 pmon->tx_prot_ppdu_info = tx_ppdu_info; 1368 else 1369 pmon->tx_data_ppdu_info = tx_ppdu_info; 1370 1371 return tx_ppdu_info; 1372 } 1373 1374 static struct dp_mon_tx_ppdu_info * 1375 ath12k_dp_mon_hal_tx_ppdu_info(struct ath12k_mon_data *pmon, 1376 u16 tlv_tag) 1377 { 1378 switch (tlv_tag) { 1379 case HAL_TX_FES_SETUP: 1380 case HAL_TX_FLUSH: 1381 case HAL_PCU_PPDU_SETUP_INIT: 1382 case HAL_TX_PEER_ENTRY: 1383 case HAL_TX_QUEUE_EXTENSION: 1384 case HAL_TX_MPDU_START: 1385 case HAL_TX_MSDU_START: 1386 case HAL_TX_DATA: 1387 case HAL_MON_BUF_ADDR: 1388 case HAL_TX_MPDU_END: 1389 case HAL_TX_LAST_MPDU_FETCHED: 1390 case HAL_TX_LAST_MPDU_END: 1391 case HAL_COEX_TX_REQ: 1392 case HAL_TX_RAW_OR_NATIVE_FRAME_SETUP: 1393 case HAL_SCH_CRITICAL_TLV_REFERENCE: 1394 case HAL_TX_FES_SETUP_COMPLETE: 1395 case HAL_TQM_MPDU_GLOBAL_START: 1396 case HAL_SCHEDULER_END: 1397 case HAL_TX_FES_STATUS_USER_PPDU: 1398 break; 1399 case HAL_TX_FES_STATUS_PROT: { 1400 if (!pmon->tx_prot_ppdu_info->is_used) 1401 pmon->tx_prot_ppdu_info->is_used = true; 1402 1403 return pmon->tx_prot_ppdu_info; 1404 } 1405 } 1406 1407 if (!pmon->tx_data_ppdu_info->is_used) 1408 pmon->tx_data_ppdu_info->is_used = true; 1409 1410 return pmon->tx_data_ppdu_info; 1411 } 1412 1413 #define MAX_MONITOR_HEADER 512 1414 #define MAX_DUMMY_FRM_BODY 128 1415 1416 struct sk_buff *ath12k_dp_mon_tx_alloc_skb(void) 1417 { 1418 struct sk_buff *skb; 1419 1420 skb = dev_alloc_skb(MAX_MONITOR_HEADER + MAX_DUMMY_FRM_BODY); 1421 if (!skb) 1422 return NULL; 1423 1424 skb_reserve(skb, MAX_MONITOR_HEADER); 1425 1426 if (!IS_ALIGNED((unsigned long)skb->data, 4)) 1427 skb_pull(skb, PTR_ALIGN(skb->data, 4) - skb->data); 1428 1429 return skb; 1430 } 1431 1432 static int 1433 ath12k_dp_mon_tx_gen_cts2self_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info) 1434 { 1435 struct sk_buff *skb; 1436 struct ieee80211_cts *cts; 1437 1438 skb = ath12k_dp_mon_tx_alloc_skb(); 1439 if (!skb) 1440 return -ENOMEM; 1441 1442 cts = (struct ieee80211_cts *)skb->data; 1443 memset(cts, 0, MAX_DUMMY_FRM_BODY); 1444 cts->frame_control = 1445 cpu_to_le16(IEEE80211_FTYPE_CTL | IEEE80211_STYPE_CTS); 1446 cts->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration); 1447 memcpy(cts->ra, tx_ppdu_info->rx_status.addr1, sizeof(cts->ra)); 1448 1449 skb_put(skb, sizeof(*cts)); 1450 tx_ppdu_info->tx_mon_mpdu->head = skb; 1451 tx_ppdu_info->tx_mon_mpdu->tail = NULL; 1452 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list, 1453 &tx_ppdu_info->dp_tx_mon_mpdu_list); 1454 1455 return 0; 1456 } 1457 1458 static int 1459 ath12k_dp_mon_tx_gen_rts_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info) 1460 { 1461 struct sk_buff *skb; 1462 struct ieee80211_rts *rts; 1463 1464 skb = ath12k_dp_mon_tx_alloc_skb(); 1465 if (!skb) 1466 return -ENOMEM; 1467 1468 rts = (struct ieee80211_rts *)skb->data; 1469 memset(rts, 0, MAX_DUMMY_FRM_BODY); 1470 rts->frame_control = 1471 cpu_to_le16(IEEE80211_FTYPE_CTL | IEEE80211_STYPE_RTS); 1472 rts->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration); 1473 memcpy(rts->ra, tx_ppdu_info->rx_status.addr1, sizeof(rts->ra)); 1474 memcpy(rts->ta, tx_ppdu_info->rx_status.addr2, sizeof(rts->ta)); 1475 1476 skb_put(skb, sizeof(*rts)); 1477 tx_ppdu_info->tx_mon_mpdu->head = skb; 1478 tx_ppdu_info->tx_mon_mpdu->tail = NULL; 1479 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list, 1480 &tx_ppdu_info->dp_tx_mon_mpdu_list); 1481 1482 return 0; 1483 } 1484 1485 static int 1486 ath12k_dp_mon_tx_gen_3addr_qos_null_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info) 1487 { 1488 struct sk_buff *skb; 1489 struct ieee80211_qos_hdr *qhdr; 1490 1491 skb = ath12k_dp_mon_tx_alloc_skb(); 1492 if (!skb) 1493 return -ENOMEM; 1494 1495 qhdr = (struct ieee80211_qos_hdr *)skb->data; 1496 memset(qhdr, 0, MAX_DUMMY_FRM_BODY); 1497 qhdr->frame_control = 1498 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_NULLFUNC); 1499 qhdr->duration_id = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration); 1500 memcpy(qhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN); 1501 memcpy(qhdr->addr2, tx_ppdu_info->rx_status.addr2, ETH_ALEN); 1502 memcpy(qhdr->addr3, tx_ppdu_info->rx_status.addr3, ETH_ALEN); 1503 1504 skb_put(skb, sizeof(*qhdr)); 1505 tx_ppdu_info->tx_mon_mpdu->head = skb; 1506 tx_ppdu_info->tx_mon_mpdu->tail = NULL; 1507 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list, 1508 &tx_ppdu_info->dp_tx_mon_mpdu_list); 1509 1510 return 0; 1511 } 1512 1513 static int 1514 ath12k_dp_mon_tx_gen_4addr_qos_null_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info) 1515 { 1516 struct sk_buff *skb; 1517 struct dp_mon_qosframe_addr4 *qhdr; 1518 1519 skb = ath12k_dp_mon_tx_alloc_skb(); 1520 if (!skb) 1521 return -ENOMEM; 1522 1523 qhdr = (struct dp_mon_qosframe_addr4 *)skb->data; 1524 memset(qhdr, 0, MAX_DUMMY_FRM_BODY); 1525 qhdr->frame_control = 1526 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_NULLFUNC); 1527 qhdr->duration = cpu_to_le16(tx_ppdu_info->rx_status.rx_duration); 1528 memcpy(qhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN); 1529 memcpy(qhdr->addr2, tx_ppdu_info->rx_status.addr2, ETH_ALEN); 1530 memcpy(qhdr->addr3, tx_ppdu_info->rx_status.addr3, ETH_ALEN); 1531 memcpy(qhdr->addr4, tx_ppdu_info->rx_status.addr4, ETH_ALEN); 1532 1533 skb_put(skb, sizeof(*qhdr)); 1534 tx_ppdu_info->tx_mon_mpdu->head = skb; 1535 tx_ppdu_info->tx_mon_mpdu->tail = NULL; 1536 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list, 1537 &tx_ppdu_info->dp_tx_mon_mpdu_list); 1538 1539 return 0; 1540 } 1541 1542 static int 1543 ath12k_dp_mon_tx_gen_ack_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info) 1544 { 1545 struct sk_buff *skb; 1546 struct dp_mon_frame_min_one *fbmhdr; 1547 1548 skb = ath12k_dp_mon_tx_alloc_skb(); 1549 if (!skb) 1550 return -ENOMEM; 1551 1552 fbmhdr = (struct dp_mon_frame_min_one *)skb->data; 1553 memset(fbmhdr, 0, MAX_DUMMY_FRM_BODY); 1554 fbmhdr->frame_control = 1555 cpu_to_le16(IEEE80211_FTYPE_DATA | IEEE80211_STYPE_QOS_CFACK); 1556 memcpy(fbmhdr->addr1, tx_ppdu_info->rx_status.addr1, ETH_ALEN); 1557 1558 /* set duration zero for ack frame */ 1559 fbmhdr->duration = 0; 1560 1561 skb_put(skb, sizeof(*fbmhdr)); 1562 tx_ppdu_info->tx_mon_mpdu->head = skb; 1563 tx_ppdu_info->tx_mon_mpdu->tail = NULL; 1564 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list, 1565 &tx_ppdu_info->dp_tx_mon_mpdu_list); 1566 1567 return 0; 1568 } 1569 1570 static int 1571 ath12k_dp_mon_tx_gen_prot_frame(struct dp_mon_tx_ppdu_info *tx_ppdu_info) 1572 { 1573 int ret = 0; 1574 1575 switch (tx_ppdu_info->rx_status.medium_prot_type) { 1576 case DP_MON_TX_MEDIUM_RTS_LEGACY: 1577 case DP_MON_TX_MEDIUM_RTS_11AC_STATIC_BW: 1578 case DP_MON_TX_MEDIUM_RTS_11AC_DYNAMIC_BW: 1579 ret = ath12k_dp_mon_tx_gen_rts_frame(tx_ppdu_info); 1580 break; 1581 case DP_MON_TX_MEDIUM_CTS2SELF: 1582 ret = ath12k_dp_mon_tx_gen_cts2self_frame(tx_ppdu_info); 1583 break; 1584 case DP_MON_TX_MEDIUM_QOS_NULL_NO_ACK_3ADDR: 1585 ret = ath12k_dp_mon_tx_gen_3addr_qos_null_frame(tx_ppdu_info); 1586 break; 1587 case DP_MON_TX_MEDIUM_QOS_NULL_NO_ACK_4ADDR: 1588 ret = ath12k_dp_mon_tx_gen_4addr_qos_null_frame(tx_ppdu_info); 1589 break; 1590 } 1591 1592 return ret; 1593 } 1594 1595 static enum dp_mon_tx_tlv_status 1596 ath12k_dp_mon_tx_parse_status_tlv(struct ath12k_base *ab, 1597 struct ath12k_mon_data *pmon, 1598 u16 tlv_tag, u8 *tlv_data, u32 userid) 1599 { 1600 struct dp_mon_tx_ppdu_info *tx_ppdu_info; 1601 enum dp_mon_tx_tlv_status status = DP_MON_TX_STATUS_PPDU_NOT_DONE; 1602 u32 info[7]; 1603 1604 tx_ppdu_info = ath12k_dp_mon_hal_tx_ppdu_info(pmon, tlv_tag); 1605 1606 switch (tlv_tag) { 1607 case HAL_TX_FES_SETUP: { 1608 struct hal_tx_fes_setup *tx_fes_setup = 1609 (struct hal_tx_fes_setup *)tlv_data; 1610 1611 info[0] = __le32_to_cpu(tx_fes_setup->info0); 1612 tx_ppdu_info->ppdu_id = __le32_to_cpu(tx_fes_setup->schedule_id); 1613 tx_ppdu_info->num_users = 1614 u32_get_bits(info[0], HAL_TX_FES_SETUP_INFO0_NUM_OF_USERS); 1615 status = DP_MON_TX_FES_SETUP; 1616 break; 1617 } 1618 1619 case HAL_TX_FES_STATUS_END: { 1620 struct hal_tx_fes_status_end *tx_fes_status_end = 1621 (struct hal_tx_fes_status_end *)tlv_data; 1622 u32 tst_15_0, tst_31_16; 1623 1624 info[0] = __le32_to_cpu(tx_fes_status_end->info0); 1625 tst_15_0 = 1626 u32_get_bits(info[0], 1627 HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_15_0); 1628 tst_31_16 = 1629 u32_get_bits(info[0], 1630 HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_31_16); 1631 1632 tx_ppdu_info->rx_status.ppdu_ts = (tst_15_0 | (tst_31_16 << 16)); 1633 status = DP_MON_TX_FES_STATUS_END; 1634 break; 1635 } 1636 1637 case HAL_RX_RESPONSE_REQUIRED_INFO: { 1638 struct hal_rx_resp_req_info *rx_resp_req_info = 1639 (struct hal_rx_resp_req_info *)tlv_data; 1640 u32 addr_32; 1641 u16 addr_16; 1642 1643 info[0] = __le32_to_cpu(rx_resp_req_info->info0); 1644 info[1] = __le32_to_cpu(rx_resp_req_info->info1); 1645 info[2] = __le32_to_cpu(rx_resp_req_info->info2); 1646 info[3] = __le32_to_cpu(rx_resp_req_info->info3); 1647 info[4] = __le32_to_cpu(rx_resp_req_info->info4); 1648 info[5] = __le32_to_cpu(rx_resp_req_info->info5); 1649 1650 tx_ppdu_info->rx_status.ppdu_id = 1651 u32_get_bits(info[0], HAL_RX_RESP_REQ_INFO0_PPDU_ID); 1652 tx_ppdu_info->rx_status.reception_type = 1653 u32_get_bits(info[0], HAL_RX_RESP_REQ_INFO0_RECEPTION_TYPE); 1654 tx_ppdu_info->rx_status.rx_duration = 1655 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_DURATION); 1656 tx_ppdu_info->rx_status.mcs = 1657 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_RATE_MCS); 1658 tx_ppdu_info->rx_status.sgi = 1659 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_SGI); 1660 tx_ppdu_info->rx_status.is_stbc = 1661 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_STBC); 1662 tx_ppdu_info->rx_status.ldpc = 1663 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_LDPC); 1664 tx_ppdu_info->rx_status.is_ampdu = 1665 u32_get_bits(info[1], HAL_RX_RESP_REQ_INFO1_IS_AMPDU); 1666 tx_ppdu_info->rx_status.num_users = 1667 u32_get_bits(info[2], HAL_RX_RESP_REQ_INFO2_NUM_USER); 1668 1669 addr_32 = u32_get_bits(info[3], HAL_RX_RESP_REQ_INFO3_ADDR1_31_0); 1670 addr_16 = u32_get_bits(info[3], HAL_RX_RESP_REQ_INFO4_ADDR1_47_32); 1671 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1); 1672 1673 addr_16 = u32_get_bits(info[4], HAL_RX_RESP_REQ_INFO4_ADDR1_15_0); 1674 addr_32 = u32_get_bits(info[5], HAL_RX_RESP_REQ_INFO5_ADDR1_47_16); 1675 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr2); 1676 1677 if (tx_ppdu_info->rx_status.reception_type == 0) 1678 ath12k_dp_mon_tx_gen_cts2self_frame(tx_ppdu_info); 1679 status = DP_MON_RX_RESPONSE_REQUIRED_INFO; 1680 break; 1681 } 1682 1683 case HAL_PCU_PPDU_SETUP_INIT: { 1684 struct hal_tx_pcu_ppdu_setup_init *ppdu_setup = 1685 (struct hal_tx_pcu_ppdu_setup_init *)tlv_data; 1686 u32 addr_32; 1687 u16 addr_16; 1688 1689 info[0] = __le32_to_cpu(ppdu_setup->info0); 1690 info[1] = __le32_to_cpu(ppdu_setup->info1); 1691 info[2] = __le32_to_cpu(ppdu_setup->info2); 1692 info[3] = __le32_to_cpu(ppdu_setup->info3); 1693 info[4] = __le32_to_cpu(ppdu_setup->info4); 1694 info[5] = __le32_to_cpu(ppdu_setup->info5); 1695 info[6] = __le32_to_cpu(ppdu_setup->info6); 1696 1697 /* protection frame address 1 */ 1698 addr_32 = u32_get_bits(info[1], 1699 HAL_TX_PPDU_SETUP_INFO1_PROT_FRAME_ADDR1_31_0); 1700 addr_16 = u32_get_bits(info[2], 1701 HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR1_47_32); 1702 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1); 1703 1704 /* protection frame address 2 */ 1705 addr_16 = u32_get_bits(info[2], 1706 HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR2_15_0); 1707 addr_32 = u32_get_bits(info[3], 1708 HAL_TX_PPDU_SETUP_INFO3_PROT_FRAME_ADDR2_47_16); 1709 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr2); 1710 1711 /* protection frame address 3 */ 1712 addr_32 = u32_get_bits(info[4], 1713 HAL_TX_PPDU_SETUP_INFO4_PROT_FRAME_ADDR3_31_0); 1714 addr_16 = u32_get_bits(info[5], 1715 HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR3_47_32); 1716 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr3); 1717 1718 /* protection frame address 4 */ 1719 addr_16 = u32_get_bits(info[5], 1720 HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR4_15_0); 1721 addr_32 = u32_get_bits(info[6], 1722 HAL_TX_PPDU_SETUP_INFO6_PROT_FRAME_ADDR4_47_16); 1723 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr4); 1724 1725 status = u32_get_bits(info[0], 1726 HAL_TX_PPDU_SETUP_INFO0_MEDIUM_PROT_TYPE); 1727 break; 1728 } 1729 1730 case HAL_TX_QUEUE_EXTENSION: { 1731 struct hal_tx_queue_exten *tx_q_exten = 1732 (struct hal_tx_queue_exten *)tlv_data; 1733 1734 info[0] = __le32_to_cpu(tx_q_exten->info0); 1735 1736 tx_ppdu_info->rx_status.frame_control = 1737 u32_get_bits(info[0], 1738 HAL_TX_Q_EXT_INFO0_FRAME_CTRL); 1739 tx_ppdu_info->rx_status.fc_valid = true; 1740 break; 1741 } 1742 1743 case HAL_TX_FES_STATUS_START: { 1744 struct hal_tx_fes_status_start *tx_fes_start = 1745 (struct hal_tx_fes_status_start *)tlv_data; 1746 1747 info[0] = __le32_to_cpu(tx_fes_start->info0); 1748 1749 tx_ppdu_info->rx_status.medium_prot_type = 1750 u32_get_bits(info[0], 1751 HAL_TX_FES_STATUS_START_INFO0_MEDIUM_PROT_TYPE); 1752 break; 1753 } 1754 1755 case HAL_TX_FES_STATUS_PROT: { 1756 struct hal_tx_fes_status_prot *tx_fes_status = 1757 (struct hal_tx_fes_status_prot *)tlv_data; 1758 u32 start_timestamp; 1759 u32 end_timestamp; 1760 1761 info[0] = __le32_to_cpu(tx_fes_status->info0); 1762 info[1] = __le32_to_cpu(tx_fes_status->info1); 1763 1764 start_timestamp = 1765 u32_get_bits(info[0], 1766 HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_15_0); 1767 start_timestamp |= 1768 u32_get_bits(info[0], 1769 HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_31_16) << 15; 1770 end_timestamp = 1771 u32_get_bits(info[1], 1772 HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_15_0); 1773 end_timestamp |= 1774 u32_get_bits(info[1], 1775 HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_31_16) << 15; 1776 tx_ppdu_info->rx_status.rx_duration = end_timestamp - start_timestamp; 1777 1778 ath12k_dp_mon_tx_gen_prot_frame(tx_ppdu_info); 1779 break; 1780 } 1781 1782 case HAL_TX_FES_STATUS_START_PPDU: 1783 case HAL_TX_FES_STATUS_START_PROT: { 1784 struct hal_tx_fes_status_start_prot *tx_fes_stat_start = 1785 (struct hal_tx_fes_status_start_prot *)tlv_data; 1786 u64 ppdu_ts; 1787 1788 info[0] = __le32_to_cpu(tx_fes_stat_start->info0); 1789 1790 tx_ppdu_info->rx_status.ppdu_ts = 1791 u32_get_bits(info[0], 1792 HAL_TX_FES_STAT_STRT_INFO0_PROT_TS_LOWER_32); 1793 ppdu_ts = (u32_get_bits(info[1], 1794 HAL_TX_FES_STAT_STRT_INFO1_PROT_TS_UPPER_32)); 1795 tx_ppdu_info->rx_status.ppdu_ts |= ppdu_ts << 32; 1796 break; 1797 } 1798 1799 case HAL_TX_FES_STATUS_USER_PPDU: { 1800 struct hal_tx_fes_status_user_ppdu *tx_fes_usr_ppdu = 1801 (struct hal_tx_fes_status_user_ppdu *)tlv_data; 1802 1803 info[0] = __le32_to_cpu(tx_fes_usr_ppdu->info0); 1804 1805 tx_ppdu_info->rx_status.rx_duration = 1806 u32_get_bits(info[0], 1807 HAL_TX_FES_STAT_USR_PPDU_INFO0_DURATION); 1808 break; 1809 } 1810 1811 case HAL_MACTX_HE_SIG_A_SU: 1812 ath12k_dp_mon_parse_he_sig_su(tlv_data, &tx_ppdu_info->rx_status); 1813 break; 1814 1815 case HAL_MACTX_HE_SIG_A_MU_DL: 1816 ath12k_dp_mon_parse_he_sig_mu(tlv_data, &tx_ppdu_info->rx_status); 1817 break; 1818 1819 case HAL_MACTX_HE_SIG_B1_MU: 1820 ath12k_dp_mon_parse_he_sig_b1_mu(tlv_data, &tx_ppdu_info->rx_status); 1821 break; 1822 1823 case HAL_MACTX_HE_SIG_B2_MU: 1824 ath12k_dp_mon_parse_he_sig_b2_mu(tlv_data, &tx_ppdu_info->rx_status); 1825 break; 1826 1827 case HAL_MACTX_HE_SIG_B2_OFDMA: 1828 ath12k_dp_mon_parse_he_sig_b2_ofdma(tlv_data, &tx_ppdu_info->rx_status); 1829 break; 1830 1831 case HAL_MACTX_VHT_SIG_A: 1832 ath12k_dp_mon_parse_vht_sig_a(tlv_data, &tx_ppdu_info->rx_status); 1833 break; 1834 1835 case HAL_MACTX_L_SIG_A: 1836 ath12k_dp_mon_parse_l_sig_a(tlv_data, &tx_ppdu_info->rx_status); 1837 break; 1838 1839 case HAL_MACTX_L_SIG_B: 1840 ath12k_dp_mon_parse_l_sig_b(tlv_data, &tx_ppdu_info->rx_status); 1841 break; 1842 1843 case HAL_RX_FRAME_BITMAP_ACK: { 1844 struct hal_rx_frame_bitmap_ack *fbm_ack = 1845 (struct hal_rx_frame_bitmap_ack *)tlv_data; 1846 u32 addr_32; 1847 u16 addr_16; 1848 1849 info[0] = __le32_to_cpu(fbm_ack->info0); 1850 info[1] = __le32_to_cpu(fbm_ack->info1); 1851 1852 addr_32 = u32_get_bits(info[0], 1853 HAL_RX_FBM_ACK_INFO0_ADDR1_31_0); 1854 addr_16 = u32_get_bits(info[1], 1855 HAL_RX_FBM_ACK_INFO1_ADDR1_47_32); 1856 ath12k_dp_get_mac_addr(addr_32, addr_16, tx_ppdu_info->rx_status.addr1); 1857 1858 ath12k_dp_mon_tx_gen_ack_frame(tx_ppdu_info); 1859 break; 1860 } 1861 1862 case HAL_MACTX_PHY_DESC: { 1863 struct hal_tx_phy_desc *tx_phy_desc = 1864 (struct hal_tx_phy_desc *)tlv_data; 1865 1866 info[0] = __le32_to_cpu(tx_phy_desc->info0); 1867 info[1] = __le32_to_cpu(tx_phy_desc->info1); 1868 info[2] = __le32_to_cpu(tx_phy_desc->info2); 1869 info[3] = __le32_to_cpu(tx_phy_desc->info3); 1870 1871 tx_ppdu_info->rx_status.beamformed = 1872 u32_get_bits(info[0], 1873 HAL_TX_PHY_DESC_INFO0_BF_TYPE); 1874 tx_ppdu_info->rx_status.preamble_type = 1875 u32_get_bits(info[0], 1876 HAL_TX_PHY_DESC_INFO0_PREAMBLE_11B); 1877 tx_ppdu_info->rx_status.mcs = 1878 u32_get_bits(info[1], 1879 HAL_TX_PHY_DESC_INFO1_MCS); 1880 tx_ppdu_info->rx_status.ltf_size = 1881 u32_get_bits(info[3], 1882 HAL_TX_PHY_DESC_INFO3_LTF_SIZE); 1883 tx_ppdu_info->rx_status.nss = 1884 u32_get_bits(info[2], 1885 HAL_TX_PHY_DESC_INFO2_NSS); 1886 tx_ppdu_info->rx_status.chan_num = 1887 u32_get_bits(info[3], 1888 HAL_TX_PHY_DESC_INFO3_ACTIVE_CHANNEL); 1889 tx_ppdu_info->rx_status.bw = 1890 u32_get_bits(info[0], 1891 HAL_TX_PHY_DESC_INFO0_BANDWIDTH); 1892 break; 1893 } 1894 1895 case HAL_TX_MPDU_START: { 1896 struct dp_mon_mpdu *mon_mpdu = tx_ppdu_info->tx_mon_mpdu; 1897 1898 mon_mpdu = kzalloc(sizeof(*mon_mpdu), GFP_ATOMIC); 1899 if (!mon_mpdu) 1900 return DP_MON_TX_STATUS_PPDU_NOT_DONE; 1901 status = DP_MON_TX_MPDU_START; 1902 break; 1903 } 1904 1905 case HAL_MON_BUF_ADDR: { 1906 struct dp_rxdma_ring *buf_ring = &ab->dp.tx_mon_buf_ring; 1907 struct dp_mon_packet_info *packet_info = 1908 (struct dp_mon_packet_info *)tlv_data; 1909 int buf_id = u32_get_bits(packet_info->cookie, 1910 DP_RXDMA_BUF_COOKIE_BUF_ID); 1911 struct sk_buff *msdu; 1912 struct dp_mon_mpdu *mon_mpdu = tx_ppdu_info->tx_mon_mpdu; 1913 struct ath12k_skb_rxcb *rxcb; 1914 1915 spin_lock_bh(&buf_ring->idr_lock); 1916 msdu = idr_remove(&buf_ring->bufs_idr, buf_id); 1917 spin_unlock_bh(&buf_ring->idr_lock); 1918 1919 if (unlikely(!msdu)) { 1920 ath12k_warn(ab, "montior destination with invalid buf_id %d\n", 1921 buf_id); 1922 return DP_MON_TX_STATUS_PPDU_NOT_DONE; 1923 } 1924 1925 rxcb = ATH12K_SKB_RXCB(msdu); 1926 dma_unmap_single(ab->dev, rxcb->paddr, 1927 msdu->len + skb_tailroom(msdu), 1928 DMA_FROM_DEVICE); 1929 1930 if (!mon_mpdu->head) 1931 mon_mpdu->head = msdu; 1932 else if (mon_mpdu->tail) 1933 mon_mpdu->tail->next = msdu; 1934 1935 mon_mpdu->tail = msdu; 1936 1937 ath12k_dp_mon_buf_replenish(ab, buf_ring, 1); 1938 status = DP_MON_TX_BUFFER_ADDR; 1939 break; 1940 } 1941 1942 case HAL_TX_MPDU_END: 1943 list_add_tail(&tx_ppdu_info->tx_mon_mpdu->list, 1944 &tx_ppdu_info->dp_tx_mon_mpdu_list); 1945 break; 1946 } 1947 1948 return status; 1949 } 1950 1951 enum dp_mon_tx_tlv_status 1952 ath12k_dp_mon_tx_status_get_num_user(u16 tlv_tag, 1953 struct hal_tlv_hdr *tx_tlv, 1954 u8 *num_users) 1955 { 1956 u32 tlv_status = DP_MON_TX_STATUS_PPDU_NOT_DONE; 1957 u32 info0; 1958 1959 switch (tlv_tag) { 1960 case HAL_TX_FES_SETUP: { 1961 struct hal_tx_fes_setup *tx_fes_setup = 1962 (struct hal_tx_fes_setup *)tx_tlv; 1963 1964 info0 = __le32_to_cpu(tx_fes_setup->info0); 1965 1966 *num_users = u32_get_bits(info0, HAL_TX_FES_SETUP_INFO0_NUM_OF_USERS); 1967 tlv_status = DP_MON_TX_FES_SETUP; 1968 break; 1969 } 1970 1971 case HAL_RX_RESPONSE_REQUIRED_INFO: { 1972 /* TODO: need to update *num_users */ 1973 tlv_status = DP_MON_RX_RESPONSE_REQUIRED_INFO; 1974 break; 1975 } 1976 } 1977 1978 return tlv_status; 1979 } 1980 1981 static void 1982 ath12k_dp_mon_tx_process_ppdu_info(struct ath12k *ar, int mac_id, 1983 struct napi_struct *napi, 1984 struct dp_mon_tx_ppdu_info *tx_ppdu_info) 1985 { 1986 struct dp_mon_mpdu *tmp, *mon_mpdu; 1987 struct sk_buff *head_msdu; 1988 1989 list_for_each_entry_safe(mon_mpdu, tmp, 1990 &tx_ppdu_info->dp_tx_mon_mpdu_list, list) { 1991 list_del(&mon_mpdu->list); 1992 head_msdu = mon_mpdu->head; 1993 1994 if (head_msdu) 1995 ath12k_dp_mon_rx_deliver(ar, mac_id, head_msdu, 1996 &tx_ppdu_info->rx_status, napi); 1997 1998 kfree(mon_mpdu); 1999 } 2000 } 2001 2002 enum hal_rx_mon_status 2003 ath12k_dp_mon_tx_parse_mon_status(struct ath12k *ar, 2004 struct ath12k_mon_data *pmon, 2005 int mac_id, 2006 struct sk_buff *skb, 2007 struct napi_struct *napi, 2008 u32 ppdu_id) 2009 { 2010 struct ath12k_base *ab = ar->ab; 2011 struct dp_mon_tx_ppdu_info *tx_prot_ppdu_info, *tx_data_ppdu_info; 2012 struct hal_tlv_hdr *tlv; 2013 u8 *ptr = skb->data; 2014 u16 tlv_tag; 2015 u16 tlv_len; 2016 u32 tlv_userid = 0; 2017 u8 num_user; 2018 u32 tlv_status = DP_MON_TX_STATUS_PPDU_NOT_DONE; 2019 2020 tx_prot_ppdu_info = ath12k_dp_mon_tx_get_ppdu_info(pmon, ppdu_id, 2021 DP_MON_TX_PROT_PPDU_INFO); 2022 if (!tx_prot_ppdu_info) 2023 return -ENOMEM; 2024 2025 tlv = (struct hal_tlv_hdr *)ptr; 2026 tlv_tag = le32_get_bits(tlv->tl, HAL_TLV_HDR_TAG); 2027 2028 tlv_status = ath12k_dp_mon_tx_status_get_num_user(tlv_tag, tlv, &num_user); 2029 if (tlv_status == DP_MON_TX_STATUS_PPDU_NOT_DONE || !num_user) 2030 return -EINVAL; 2031 2032 tx_data_ppdu_info = ath12k_dp_mon_tx_get_ppdu_info(pmon, ppdu_id, 2033 DP_MON_TX_DATA_PPDU_INFO); 2034 if (!tx_data_ppdu_info) 2035 return -ENOMEM; 2036 2037 do { 2038 tlv = (struct hal_tlv_hdr *)ptr; 2039 tlv_tag = le32_get_bits(tlv->tl, HAL_TLV_HDR_TAG); 2040 tlv_len = le32_get_bits(tlv->tl, HAL_TLV_HDR_LEN); 2041 tlv_userid = le32_get_bits(tlv->tl, HAL_TLV_USR_ID); 2042 2043 tlv_status = ath12k_dp_mon_tx_parse_status_tlv(ab, pmon, 2044 tlv_tag, ptr, 2045 tlv_userid); 2046 ptr += tlv_len; 2047 ptr = PTR_ALIGN(ptr, HAL_TLV_ALIGN); 2048 if ((ptr - skb->data) >= DP_TX_MONITOR_BUF_SIZE) 2049 break; 2050 } while (tlv_status != DP_MON_TX_FES_STATUS_END); 2051 2052 ath12k_dp_mon_tx_process_ppdu_info(ar, mac_id, napi, tx_data_ppdu_info); 2053 ath12k_dp_mon_tx_process_ppdu_info(ar, mac_id, napi, tx_prot_ppdu_info); 2054 2055 return tlv_status; 2056 } 2057 2058 int ath12k_dp_mon_srng_process(struct ath12k *ar, int mac_id, int *budget, 2059 enum dp_monitor_mode monitor_mode, 2060 struct napi_struct *napi) 2061 { 2062 struct hal_mon_dest_desc *mon_dst_desc; 2063 struct ath12k_pdev_dp *pdev_dp = &ar->dp; 2064 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&pdev_dp->mon_data; 2065 struct ath12k_base *ab = ar->ab; 2066 struct ath12k_dp *dp = &ab->dp; 2067 struct sk_buff *skb; 2068 struct ath12k_skb_rxcb *rxcb; 2069 struct dp_srng *mon_dst_ring; 2070 struct hal_srng *srng; 2071 struct dp_rxdma_ring *buf_ring; 2072 u64 cookie; 2073 u32 ppdu_id; 2074 int num_buffs_reaped = 0, srng_id, buf_id; 2075 u8 dest_idx = 0, i; 2076 bool end_of_ppdu; 2077 struct hal_rx_mon_ppdu_info *ppdu_info; 2078 struct ath12k_peer *peer = NULL; 2079 2080 ppdu_info = &pmon->mon_ppdu_info; 2081 memset(ppdu_info, 0, sizeof(*ppdu_info)); 2082 ppdu_info->peer_id = HAL_INVALID_PEERID; 2083 2084 srng_id = ath12k_hw_mac_id_to_srng_id(ab->hw_params, mac_id); 2085 2086 if (monitor_mode == ATH12K_DP_RX_MONITOR_MODE) { 2087 mon_dst_ring = &pdev_dp->rxdma_mon_dst_ring[srng_id]; 2088 buf_ring = &dp->rxdma_mon_buf_ring; 2089 } else { 2090 mon_dst_ring = &pdev_dp->tx_mon_dst_ring[srng_id]; 2091 buf_ring = &dp->tx_mon_buf_ring; 2092 } 2093 2094 srng = &ab->hal.srng_list[mon_dst_ring->ring_id]; 2095 2096 spin_lock_bh(&srng->lock); 2097 ath12k_hal_srng_access_begin(ab, srng); 2098 2099 while (likely(*budget)) { 2100 *budget -= 1; 2101 mon_dst_desc = ath12k_hal_srng_dst_peek(ab, srng); 2102 if (unlikely(!mon_dst_desc)) 2103 break; 2104 2105 cookie = le32_to_cpu(mon_dst_desc->cookie); 2106 buf_id = u32_get_bits(cookie, DP_RXDMA_BUF_COOKIE_BUF_ID); 2107 2108 spin_lock_bh(&buf_ring->idr_lock); 2109 skb = idr_remove(&buf_ring->bufs_idr, buf_id); 2110 spin_unlock_bh(&buf_ring->idr_lock); 2111 2112 if (unlikely(!skb)) { 2113 ath12k_warn(ab, "montior destination with invalid buf_id %d\n", 2114 buf_id); 2115 goto move_next; 2116 } 2117 2118 rxcb = ATH12K_SKB_RXCB(skb); 2119 dma_unmap_single(ab->dev, rxcb->paddr, 2120 skb->len + skb_tailroom(skb), 2121 DMA_FROM_DEVICE); 2122 2123 pmon->dest_skb_q[dest_idx] = skb; 2124 dest_idx++; 2125 ppdu_id = le32_to_cpu(mon_dst_desc->ppdu_id); 2126 end_of_ppdu = le32_get_bits(mon_dst_desc->info0, 2127 HAL_MON_DEST_INFO0_END_OF_PPDU); 2128 if (!end_of_ppdu) 2129 continue; 2130 2131 for (i = 0; i < dest_idx; i++) { 2132 skb = pmon->dest_skb_q[i]; 2133 2134 if (monitor_mode == ATH12K_DP_RX_MONITOR_MODE) 2135 ath12k_dp_mon_rx_parse_mon_status(ar, pmon, mac_id, 2136 skb, napi); 2137 else 2138 ath12k_dp_mon_tx_parse_mon_status(ar, pmon, mac_id, 2139 skb, napi, ppdu_id); 2140 2141 peer = ath12k_peer_find_by_id(ab, ppdu_info->peer_id); 2142 2143 if (!peer || !peer->sta) { 2144 ath12k_dbg(ab, ATH12K_DBG_DATA, 2145 "failed to find the peer with peer_id %d\n", 2146 ppdu_info->peer_id); 2147 dev_kfree_skb_any(skb); 2148 continue; 2149 } 2150 2151 dev_kfree_skb_any(skb); 2152 pmon->dest_skb_q[i] = NULL; 2153 } 2154 2155 dest_idx = 0; 2156 move_next: 2157 ath12k_dp_mon_buf_replenish(ab, buf_ring, 1); 2158 ath12k_hal_srng_src_get_next_entry(ab, srng); 2159 num_buffs_reaped++; 2160 } 2161 2162 ath12k_hal_srng_access_end(ab, srng); 2163 spin_unlock_bh(&srng->lock); 2164 2165 return num_buffs_reaped; 2166 } 2167 2168 static void 2169 ath12k_dp_mon_rx_update_peer_rate_table_stats(struct ath12k_rx_peer_stats *rx_stats, 2170 struct hal_rx_mon_ppdu_info *ppdu_info, 2171 struct hal_rx_user_status *user_stats, 2172 u32 num_msdu) 2173 { 2174 u32 rate_idx = 0; 2175 u32 mcs_idx = (user_stats) ? user_stats->mcs : ppdu_info->mcs; 2176 u32 nss_idx = (user_stats) ? user_stats->nss - 1 : ppdu_info->nss - 1; 2177 u32 bw_idx = ppdu_info->bw; 2178 u32 gi_idx = ppdu_info->gi; 2179 2180 if ((mcs_idx > HAL_RX_MAX_MCS_HE) || (nss_idx >= HAL_RX_MAX_NSS) || 2181 (bw_idx >= HAL_RX_BW_MAX) || (gi_idx >= HAL_RX_GI_MAX)) { 2182 return; 2183 } 2184 2185 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11N || 2186 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AC) { 2187 rate_idx = mcs_idx * 8 + 8 * 10 * nss_idx; 2188 rate_idx += bw_idx * 2 + gi_idx; 2189 } else if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AX) { 2190 gi_idx = ath12k_he_gi_to_nl80211_he_gi(ppdu_info->gi); 2191 rate_idx = mcs_idx * 12 + 12 * 12 * nss_idx; 2192 rate_idx += bw_idx * 3 + gi_idx; 2193 } else { 2194 return; 2195 } 2196 2197 rx_stats->pkt_stats.rx_rate[rate_idx] += num_msdu; 2198 if (user_stats) 2199 rx_stats->byte_stats.rx_rate[rate_idx] += user_stats->mpdu_ok_byte_count; 2200 else 2201 rx_stats->byte_stats.rx_rate[rate_idx] += ppdu_info->mpdu_len; 2202 } 2203 2204 static void ath12k_dp_mon_rx_update_peer_su_stats(struct ath12k *ar, 2205 struct ath12k_sta *arsta, 2206 struct hal_rx_mon_ppdu_info *ppdu_info) 2207 { 2208 struct ath12k_rx_peer_stats *rx_stats = arsta->rx_stats; 2209 u32 num_msdu; 2210 2211 if (!rx_stats) 2212 return; 2213 2214 arsta->rssi_comb = ppdu_info->rssi_comb; 2215 2216 num_msdu = ppdu_info->tcp_msdu_count + ppdu_info->tcp_ack_msdu_count + 2217 ppdu_info->udp_msdu_count + ppdu_info->other_msdu_count; 2218 2219 rx_stats->num_msdu += num_msdu; 2220 rx_stats->tcp_msdu_count += ppdu_info->tcp_msdu_count + 2221 ppdu_info->tcp_ack_msdu_count; 2222 rx_stats->udp_msdu_count += ppdu_info->udp_msdu_count; 2223 rx_stats->other_msdu_count += ppdu_info->other_msdu_count; 2224 2225 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A || 2226 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) { 2227 ppdu_info->nss = 1; 2228 ppdu_info->mcs = HAL_RX_MAX_MCS; 2229 ppdu_info->tid = IEEE80211_NUM_TIDS; 2230 } 2231 2232 if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX) 2233 rx_stats->coding_count[ppdu_info->ldpc] += num_msdu; 2234 2235 if (ppdu_info->tid <= IEEE80211_NUM_TIDS) 2236 rx_stats->tid_count[ppdu_info->tid] += num_msdu; 2237 2238 if (ppdu_info->preamble_type < HAL_RX_PREAMBLE_MAX) 2239 rx_stats->pream_cnt[ppdu_info->preamble_type] += num_msdu; 2240 2241 if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX) 2242 rx_stats->reception_type[ppdu_info->reception_type] += num_msdu; 2243 2244 if (ppdu_info->is_stbc) 2245 rx_stats->stbc_count += num_msdu; 2246 2247 if (ppdu_info->beamformed) 2248 rx_stats->beamformed_count += num_msdu; 2249 2250 if (ppdu_info->num_mpdu_fcs_ok > 1) 2251 rx_stats->ampdu_msdu_count += num_msdu; 2252 else 2253 rx_stats->non_ampdu_msdu_count += num_msdu; 2254 2255 rx_stats->num_mpdu_fcs_ok += ppdu_info->num_mpdu_fcs_ok; 2256 rx_stats->num_mpdu_fcs_err += ppdu_info->num_mpdu_fcs_err; 2257 rx_stats->dcm_count += ppdu_info->dcm; 2258 2259 rx_stats->rx_duration += ppdu_info->rx_duration; 2260 arsta->rx_duration = rx_stats->rx_duration; 2261 2262 if (ppdu_info->nss > 0 && ppdu_info->nss <= HAL_RX_MAX_NSS) { 2263 rx_stats->pkt_stats.nss_count[ppdu_info->nss - 1] += num_msdu; 2264 rx_stats->byte_stats.nss_count[ppdu_info->nss - 1] += ppdu_info->mpdu_len; 2265 } 2266 2267 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11N && 2268 ppdu_info->mcs <= HAL_RX_MAX_MCS_HT) { 2269 rx_stats->pkt_stats.ht_mcs_count[ppdu_info->mcs] += num_msdu; 2270 rx_stats->byte_stats.ht_mcs_count[ppdu_info->mcs] += ppdu_info->mpdu_len; 2271 /* To fit into rate table for HT packets */ 2272 ppdu_info->mcs = ppdu_info->mcs % 8; 2273 } 2274 2275 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AC && 2276 ppdu_info->mcs <= HAL_RX_MAX_MCS_VHT) { 2277 rx_stats->pkt_stats.vht_mcs_count[ppdu_info->mcs] += num_msdu; 2278 rx_stats->byte_stats.vht_mcs_count[ppdu_info->mcs] += ppdu_info->mpdu_len; 2279 } 2280 2281 if (ppdu_info->preamble_type == HAL_RX_PREAMBLE_11AX && 2282 ppdu_info->mcs <= HAL_RX_MAX_MCS_HE) { 2283 rx_stats->pkt_stats.he_mcs_count[ppdu_info->mcs] += num_msdu; 2284 rx_stats->byte_stats.he_mcs_count[ppdu_info->mcs] += ppdu_info->mpdu_len; 2285 } 2286 2287 if ((ppdu_info->preamble_type == HAL_RX_PREAMBLE_11A || 2288 ppdu_info->preamble_type == HAL_RX_PREAMBLE_11B) && 2289 ppdu_info->rate < HAL_RX_LEGACY_RATE_INVALID) { 2290 rx_stats->pkt_stats.legacy_count[ppdu_info->rate] += num_msdu; 2291 rx_stats->byte_stats.legacy_count[ppdu_info->rate] += ppdu_info->mpdu_len; 2292 } 2293 2294 if (ppdu_info->gi < HAL_RX_GI_MAX) { 2295 rx_stats->pkt_stats.gi_count[ppdu_info->gi] += num_msdu; 2296 rx_stats->byte_stats.gi_count[ppdu_info->gi] += ppdu_info->mpdu_len; 2297 } 2298 2299 if (ppdu_info->bw < HAL_RX_BW_MAX) { 2300 rx_stats->pkt_stats.bw_count[ppdu_info->bw] += num_msdu; 2301 rx_stats->byte_stats.bw_count[ppdu_info->bw] += ppdu_info->mpdu_len; 2302 } 2303 2304 ath12k_dp_mon_rx_update_peer_rate_table_stats(rx_stats, ppdu_info, 2305 NULL, num_msdu); 2306 } 2307 2308 void ath12k_dp_mon_rx_process_ulofdma(struct hal_rx_mon_ppdu_info *ppdu_info) 2309 { 2310 struct hal_rx_user_status *rx_user_status; 2311 u32 num_users, i, mu_ul_user_v0_word0, mu_ul_user_v0_word1, ru_size; 2312 2313 if (!(ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_MIMO || 2314 ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA || 2315 ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO)) 2316 return; 2317 2318 num_users = ppdu_info->num_users; 2319 if (num_users > HAL_MAX_UL_MU_USERS) 2320 num_users = HAL_MAX_UL_MU_USERS; 2321 2322 for (i = 0; i < num_users; i++) { 2323 rx_user_status = &ppdu_info->userstats[i]; 2324 mu_ul_user_v0_word0 = 2325 rx_user_status->ul_ofdma_user_v0_word0; 2326 mu_ul_user_v0_word1 = 2327 rx_user_status->ul_ofdma_user_v0_word1; 2328 2329 if (u32_get_bits(mu_ul_user_v0_word0, 2330 HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VALID) && 2331 !u32_get_bits(mu_ul_user_v0_word0, 2332 HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VER)) { 2333 rx_user_status->mcs = 2334 u32_get_bits(mu_ul_user_v0_word1, 2335 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_MCS); 2336 rx_user_status->nss = 2337 u32_get_bits(mu_ul_user_v0_word1, 2338 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_NSS) + 1; 2339 2340 rx_user_status->ofdma_info_valid = 1; 2341 rx_user_status->ul_ofdma_ru_start_index = 2342 u32_get_bits(mu_ul_user_v0_word1, 2343 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_START); 2344 2345 ru_size = u32_get_bits(mu_ul_user_v0_word1, 2346 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE); 2347 rx_user_status->ul_ofdma_ru_width = ru_size; 2348 rx_user_status->ul_ofdma_ru_size = ru_size; 2349 } 2350 rx_user_status->ldpc = u32_get_bits(mu_ul_user_v0_word1, 2351 HAL_RX_UL_OFDMA_USER_INFO_V0_W1_LDPC); 2352 } 2353 ppdu_info->ldpc = 1; 2354 } 2355 2356 static void 2357 ath12k_dp_mon_rx_update_user_stats(struct ath12k *ar, 2358 struct hal_rx_mon_ppdu_info *ppdu_info, 2359 u32 uid) 2360 { 2361 struct ath12k_sta *arsta = NULL; 2362 struct ath12k_rx_peer_stats *rx_stats = NULL; 2363 struct hal_rx_user_status *user_stats = &ppdu_info->userstats[uid]; 2364 struct ath12k_peer *peer; 2365 u32 num_msdu; 2366 2367 if (user_stats->ast_index == 0 || user_stats->ast_index == 0xFFFF) 2368 return; 2369 2370 peer = ath12k_peer_find_by_ast(ar->ab, user_stats->ast_index); 2371 2372 if (!peer) { 2373 ath12k_warn(ar->ab, "peer ast idx %d can't be found\n", 2374 user_stats->ast_index); 2375 return; 2376 } 2377 2378 arsta = (struct ath12k_sta *)peer->sta->drv_priv; 2379 rx_stats = arsta->rx_stats; 2380 2381 if (!rx_stats) 2382 return; 2383 2384 arsta->rssi_comb = ppdu_info->rssi_comb; 2385 2386 num_msdu = user_stats->tcp_msdu_count + user_stats->tcp_ack_msdu_count + 2387 user_stats->udp_msdu_count + user_stats->other_msdu_count; 2388 2389 rx_stats->num_msdu += num_msdu; 2390 rx_stats->tcp_msdu_count += user_stats->tcp_msdu_count + 2391 user_stats->tcp_ack_msdu_count; 2392 rx_stats->udp_msdu_count += user_stats->udp_msdu_count; 2393 rx_stats->other_msdu_count += user_stats->other_msdu_count; 2394 2395 if (ppdu_info->ldpc < HAL_RX_SU_MU_CODING_MAX) 2396 rx_stats->coding_count[ppdu_info->ldpc] += num_msdu; 2397 2398 if (user_stats->tid <= IEEE80211_NUM_TIDS) 2399 rx_stats->tid_count[user_stats->tid] += num_msdu; 2400 2401 if (user_stats->preamble_type < HAL_RX_PREAMBLE_MAX) 2402 rx_stats->pream_cnt[user_stats->preamble_type] += num_msdu; 2403 2404 if (ppdu_info->reception_type < HAL_RX_RECEPTION_TYPE_MAX) 2405 rx_stats->reception_type[ppdu_info->reception_type] += num_msdu; 2406 2407 if (ppdu_info->is_stbc) 2408 rx_stats->stbc_count += num_msdu; 2409 2410 if (ppdu_info->beamformed) 2411 rx_stats->beamformed_count += num_msdu; 2412 2413 if (user_stats->mpdu_cnt_fcs_ok > 1) 2414 rx_stats->ampdu_msdu_count += num_msdu; 2415 else 2416 rx_stats->non_ampdu_msdu_count += num_msdu; 2417 2418 rx_stats->num_mpdu_fcs_ok += user_stats->mpdu_cnt_fcs_ok; 2419 rx_stats->num_mpdu_fcs_err += user_stats->mpdu_cnt_fcs_err; 2420 rx_stats->dcm_count += ppdu_info->dcm; 2421 if (ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA || 2422 ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO) 2423 rx_stats->ru_alloc_cnt[user_stats->ul_ofdma_ru_size] += num_msdu; 2424 2425 rx_stats->rx_duration += ppdu_info->rx_duration; 2426 arsta->rx_duration = rx_stats->rx_duration; 2427 2428 if (user_stats->nss > 0 && user_stats->nss <= HAL_RX_MAX_NSS) { 2429 rx_stats->pkt_stats.nss_count[user_stats->nss - 1] += num_msdu; 2430 rx_stats->byte_stats.nss_count[user_stats->nss - 1] += 2431 user_stats->mpdu_ok_byte_count; 2432 } 2433 2434 if (user_stats->preamble_type == HAL_RX_PREAMBLE_11AX && 2435 user_stats->mcs <= HAL_RX_MAX_MCS_HE) { 2436 rx_stats->pkt_stats.he_mcs_count[user_stats->mcs] += num_msdu; 2437 rx_stats->byte_stats.he_mcs_count[user_stats->mcs] += 2438 user_stats->mpdu_ok_byte_count; 2439 } 2440 2441 if (ppdu_info->gi < HAL_RX_GI_MAX) { 2442 rx_stats->pkt_stats.gi_count[ppdu_info->gi] += num_msdu; 2443 rx_stats->byte_stats.gi_count[ppdu_info->gi] += 2444 user_stats->mpdu_ok_byte_count; 2445 } 2446 2447 if (ppdu_info->bw < HAL_RX_BW_MAX) { 2448 rx_stats->pkt_stats.bw_count[ppdu_info->bw] += num_msdu; 2449 rx_stats->byte_stats.bw_count[ppdu_info->bw] += 2450 user_stats->mpdu_ok_byte_count; 2451 } 2452 2453 ath12k_dp_mon_rx_update_peer_rate_table_stats(rx_stats, ppdu_info, 2454 user_stats, num_msdu); 2455 } 2456 2457 static void 2458 ath12k_dp_mon_rx_update_peer_mu_stats(struct ath12k *ar, 2459 struct hal_rx_mon_ppdu_info *ppdu_info) 2460 { 2461 u32 num_users, i; 2462 2463 num_users = ppdu_info->num_users; 2464 if (num_users > HAL_MAX_UL_MU_USERS) 2465 num_users = HAL_MAX_UL_MU_USERS; 2466 2467 for (i = 0; i < num_users; i++) 2468 ath12k_dp_mon_rx_update_user_stats(ar, ppdu_info, i); 2469 } 2470 2471 int ath12k_dp_mon_rx_process_stats(struct ath12k *ar, int mac_id, 2472 struct napi_struct *napi, int *budget) 2473 { 2474 struct ath12k_base *ab = ar->ab; 2475 struct ath12k_pdev_dp *pdev_dp = &ar->dp; 2476 struct ath12k_mon_data *pmon = (struct ath12k_mon_data *)&pdev_dp->mon_data; 2477 struct hal_rx_mon_ppdu_info *ppdu_info = &pmon->mon_ppdu_info; 2478 struct ath12k_dp *dp = &ab->dp; 2479 struct hal_mon_dest_desc *mon_dst_desc; 2480 struct sk_buff *skb; 2481 struct ath12k_skb_rxcb *rxcb; 2482 struct dp_srng *mon_dst_ring; 2483 struct hal_srng *srng; 2484 struct dp_rxdma_ring *buf_ring; 2485 struct ath12k_sta *arsta = NULL; 2486 struct ath12k_peer *peer; 2487 u64 cookie; 2488 int num_buffs_reaped = 0, srng_id, buf_id; 2489 u8 dest_idx = 0, i; 2490 bool end_of_ppdu; 2491 u32 hal_status; 2492 2493 srng_id = ath12k_hw_mac_id_to_srng_id(ab->hw_params, mac_id); 2494 mon_dst_ring = &pdev_dp->rxdma_mon_dst_ring[srng_id]; 2495 buf_ring = &dp->rxdma_mon_buf_ring; 2496 2497 srng = &ab->hal.srng_list[mon_dst_ring->ring_id]; 2498 spin_lock_bh(&srng->lock); 2499 ath12k_hal_srng_access_begin(ab, srng); 2500 2501 while (likely(*budget)) { 2502 *budget -= 1; 2503 mon_dst_desc = ath12k_hal_srng_dst_peek(ab, srng); 2504 if (unlikely(!mon_dst_desc)) 2505 break; 2506 cookie = le32_to_cpu(mon_dst_desc->cookie); 2507 buf_id = u32_get_bits(cookie, DP_RXDMA_BUF_COOKIE_BUF_ID); 2508 2509 spin_lock_bh(&buf_ring->idr_lock); 2510 skb = idr_remove(&buf_ring->bufs_idr, buf_id); 2511 spin_unlock_bh(&buf_ring->idr_lock); 2512 2513 if (unlikely(!skb)) { 2514 ath12k_warn(ab, "montior destination with invalid buf_id %d\n", 2515 buf_id); 2516 goto move_next; 2517 } 2518 2519 rxcb = ATH12K_SKB_RXCB(skb); 2520 dma_unmap_single(ab->dev, rxcb->paddr, 2521 skb->len + skb_tailroom(skb), 2522 DMA_FROM_DEVICE); 2523 pmon->dest_skb_q[dest_idx] = skb; 2524 dest_idx++; 2525 end_of_ppdu = le32_get_bits(mon_dst_desc->info0, 2526 HAL_MON_DEST_INFO0_END_OF_PPDU); 2527 if (!end_of_ppdu) 2528 continue; 2529 2530 for (i = 0; i < dest_idx; i++) { 2531 skb = pmon->dest_skb_q[i]; 2532 hal_status = ath12k_dp_mon_parse_rx_dest(ab, pmon, skb); 2533 2534 if (ppdu_info->peer_id == HAL_INVALID_PEERID || 2535 hal_status != HAL_RX_MON_STATUS_PPDU_DONE) { 2536 dev_kfree_skb_any(skb); 2537 continue; 2538 } 2539 2540 rcu_read_lock(); 2541 spin_lock_bh(&ab->base_lock); 2542 peer = ath12k_peer_find_by_id(ab, ppdu_info->peer_id); 2543 if (!peer || !peer->sta) { 2544 ath12k_dbg(ab, ATH12K_DBG_DATA, 2545 "failed to find the peer with peer_id %d\n", 2546 ppdu_info->peer_id); 2547 spin_unlock_bh(&ab->base_lock); 2548 rcu_read_unlock(); 2549 dev_kfree_skb_any(skb); 2550 continue; 2551 } 2552 2553 if (ppdu_info->reception_type == HAL_RX_RECEPTION_TYPE_SU) { 2554 arsta = (struct ath12k_sta *)peer->sta->drv_priv; 2555 ath12k_dp_mon_rx_update_peer_su_stats(ar, arsta, 2556 ppdu_info); 2557 } else if ((ppdu_info->fc_valid) && 2558 (ppdu_info->ast_index != HAL_AST_IDX_INVALID)) { 2559 ath12k_dp_mon_rx_process_ulofdma(ppdu_info); 2560 ath12k_dp_mon_rx_update_peer_mu_stats(ar, ppdu_info); 2561 } 2562 2563 spin_unlock_bh(&ab->base_lock); 2564 rcu_read_unlock(); 2565 dev_kfree_skb_any(skb); 2566 memset(ppdu_info, 0, sizeof(*ppdu_info)); 2567 ppdu_info->peer_id = HAL_INVALID_PEERID; 2568 } 2569 2570 dest_idx = 0; 2571 move_next: 2572 ath12k_dp_mon_buf_replenish(ab, buf_ring, 1); 2573 ath12k_hal_srng_src_get_next_entry(ab, srng); 2574 num_buffs_reaped++; 2575 } 2576 2577 ath12k_hal_srng_access_end(ab, srng); 2578 spin_unlock_bh(&srng->lock); 2579 return num_buffs_reaped; 2580 } 2581 2582 int ath12k_dp_mon_process_ring(struct ath12k_base *ab, int mac_id, 2583 struct napi_struct *napi, int budget, 2584 enum dp_monitor_mode monitor_mode) 2585 { 2586 struct ath12k *ar = ath12k_ab_to_ar(ab, mac_id); 2587 int num_buffs_reaped = 0; 2588 2589 if (!ar->monitor_started) 2590 ath12k_dp_mon_rx_process_stats(ar, mac_id, napi, &budget); 2591 else 2592 num_buffs_reaped = ath12k_dp_mon_srng_process(ar, mac_id, &budget, 2593 monitor_mode, napi); 2594 2595 return num_buffs_reaped; 2596 } 2597