1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_CORE_H 8 #define ATH12K_CORE_H 9 10 #include <linux/types.h> 11 #include <linux/interrupt.h> 12 #include <linux/irq.h> 13 #include <linux/bitfield.h> 14 #include "qmi.h" 15 #include "htc.h" 16 #include "wmi.h" 17 #include "hal.h" 18 #include "dp.h" 19 #include "ce.h" 20 #include "mac.h" 21 #include "hw.h" 22 #include "hal_rx.h" 23 #include "reg.h" 24 #include "dbring.h" 25 26 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK) 27 28 #define ATH12K_TX_MGMT_NUM_PENDING_MAX 512 29 30 #define ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64 31 32 /* Pending management packets threshold for dropping probe responses */ 33 #define ATH12K_PRB_RSP_DROP_THRESHOLD ((ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4) 34 35 #define ATH12K_INVALID_HW_MAC_ID 0xFF 36 #define ATH12K_RX_RATE_TABLE_NUM 320 37 #define ATH12K_RX_RATE_TABLE_11AX_NUM 576 38 39 #define ATH12K_MON_TIMER_INTERVAL 10 40 #define ATH12K_RESET_TIMEOUT_HZ (20 * HZ) 41 #define ATH12K_RESET_MAX_FAIL_COUNT_FIRST 3 42 #define ATH12K_RESET_MAX_FAIL_COUNT_FINAL 5 43 #define ATH12K_RESET_FAIL_TIMEOUT_HZ (20 * HZ) 44 #define ATH12K_RECONFIGURE_TIMEOUT_HZ (10 * HZ) 45 #define ATH12K_RECOVER_START_TIMEOUT_HZ (20 * HZ) 46 47 enum wme_ac { 48 WME_AC_BE, 49 WME_AC_BK, 50 WME_AC_VI, 51 WME_AC_VO, 52 WME_NUM_AC 53 }; 54 55 #define ATH12K_HT_MCS_MAX 7 56 #define ATH12K_VHT_MCS_MAX 9 57 #define ATH12K_HE_MCS_MAX 11 58 59 enum ath12k_crypt_mode { 60 /* Only use hardware crypto engine */ 61 ATH12K_CRYPT_MODE_HW, 62 /* Only use software crypto */ 63 ATH12K_CRYPT_MODE_SW, 64 }; 65 66 static inline enum wme_ac ath12k_tid_to_ac(u32 tid) 67 { 68 return (((tid == 0) || (tid == 3)) ? WME_AC_BE : 69 ((tid == 1) || (tid == 2)) ? WME_AC_BK : 70 ((tid == 4) || (tid == 5)) ? WME_AC_VI : 71 WME_AC_VO); 72 } 73 74 enum ath12k_skb_flags { 75 ATH12K_SKB_HW_80211_ENCAP = BIT(0), 76 ATH12K_SKB_CIPHER_SET = BIT(1), 77 }; 78 79 struct ath12k_skb_cb { 80 dma_addr_t paddr; 81 struct ath12k *ar; 82 struct ieee80211_vif *vif; 83 dma_addr_t paddr_ext_desc; 84 u32 cipher; 85 u8 flags; 86 }; 87 88 struct ath12k_skb_rxcb { 89 dma_addr_t paddr; 90 bool is_first_msdu; 91 bool is_last_msdu; 92 bool is_continuation; 93 bool is_mcbc; 94 bool is_eapol; 95 struct hal_rx_desc *rx_desc; 96 u8 err_rel_src; 97 u8 err_code; 98 u8 mac_id; 99 u8 unmapped; 100 u8 is_frag; 101 u8 tid; 102 u16 peer_id; 103 }; 104 105 enum ath12k_hw_rev { 106 ATH12K_HW_QCN9274_HW10, 107 ATH12K_HW_QCN9274_HW20, 108 ATH12K_HW_WCN7850_HW20 109 }; 110 111 enum ath12k_firmware_mode { 112 /* the default mode, standard 802.11 functionality */ 113 ATH12K_FIRMWARE_MODE_NORMAL, 114 115 /* factory tests etc */ 116 ATH12K_FIRMWARE_MODE_FTM, 117 }; 118 119 #define ATH12K_IRQ_NUM_MAX 57 120 #define ATH12K_EXT_IRQ_NUM_MAX 16 121 122 struct ath12k_ext_irq_grp { 123 struct ath12k_base *ab; 124 u32 irqs[ATH12K_EXT_IRQ_NUM_MAX]; 125 u32 num_irq; 126 u32 grp_id; 127 u64 timestamp; 128 struct napi_struct napi; 129 struct net_device napi_ndev; 130 }; 131 132 #define HEHANDLE_CAP_PHYINFO_SIZE 3 133 #define HECAP_PHYINFO_SIZE 9 134 #define HECAP_MACINFO_SIZE 5 135 #define HECAP_TXRX_MCS_NSS_SIZE 2 136 #define HECAP_PPET16_PPET8_MAX_SIZE 25 137 138 #define HE_PPET16_PPET8_SIZE 8 139 140 /* 802.11ax PPE (PPDU packet Extension) threshold */ 141 struct he_ppe_threshold { 142 u32 numss_m1; 143 u32 ru_mask; 144 u32 ppet16_ppet8_ru3_ru0[HE_PPET16_PPET8_SIZE]; 145 }; 146 147 struct ath12k_he { 148 u8 hecap_macinfo[HECAP_MACINFO_SIZE]; 149 u32 hecap_rxmcsnssmap; 150 u32 hecap_txmcsnssmap; 151 u32 hecap_phyinfo[HEHANDLE_CAP_PHYINFO_SIZE]; 152 struct he_ppe_threshold hecap_ppet; 153 u32 heop_param; 154 }; 155 156 #define MAX_RADIOS 3 157 158 enum { 159 WMI_HOST_TP_SCALE_MAX = 0, 160 WMI_HOST_TP_SCALE_50 = 1, 161 WMI_HOST_TP_SCALE_25 = 2, 162 WMI_HOST_TP_SCALE_12 = 3, 163 WMI_HOST_TP_SCALE_MIN = 4, 164 WMI_HOST_TP_SCALE_SIZE = 5, 165 }; 166 167 enum ath12k_scan_state { 168 ATH12K_SCAN_IDLE, 169 ATH12K_SCAN_STARTING, 170 ATH12K_SCAN_RUNNING, 171 ATH12K_SCAN_ABORTING, 172 }; 173 174 enum ath12k_dev_flags { 175 ATH12K_CAC_RUNNING, 176 ATH12K_FLAG_CRASH_FLUSH, 177 ATH12K_FLAG_RAW_MODE, 178 ATH12K_FLAG_HW_CRYPTO_DISABLED, 179 ATH12K_FLAG_RECOVERY, 180 ATH12K_FLAG_UNREGISTERING, 181 ATH12K_FLAG_REGISTERED, 182 ATH12K_FLAG_QMI_FAIL, 183 ATH12K_FLAG_HTC_SUSPEND_COMPLETE, 184 ATH12K_FLAG_CE_IRQ_ENABLED, 185 ATH12K_FLAG_EXT_IRQ_ENABLED, 186 }; 187 188 enum ath12k_monitor_flags { 189 ATH12K_FLAG_MONITOR_ENABLED, 190 }; 191 192 struct ath12k_vif { 193 u32 vdev_id; 194 enum wmi_vdev_type vdev_type; 195 enum wmi_vdev_subtype vdev_subtype; 196 u32 beacon_interval; 197 u32 dtim_period; 198 u16 ast_hash; 199 u16 ast_idx; 200 u16 tcl_metadata; 201 u8 hal_addr_search_flags; 202 u8 search_type; 203 204 struct ath12k *ar; 205 struct ieee80211_vif *vif; 206 207 int bank_id; 208 u8 vdev_id_check_en; 209 210 struct wmi_wmm_params_all_arg wmm_params; 211 struct list_head list; 212 union { 213 struct { 214 u32 uapsd; 215 } sta; 216 struct { 217 /* 127 stations; wmi limit */ 218 u8 tim_bitmap[16]; 219 u8 tim_len; 220 u32 ssid_len; 221 u8 ssid[IEEE80211_MAX_SSID_LEN]; 222 bool hidden_ssid; 223 /* P2P_IE with NoA attribute for P2P_GO case */ 224 u32 noa_len; 225 u8 *noa_data; 226 } ap; 227 } u; 228 229 bool is_started; 230 bool is_up; 231 u32 aid; 232 u8 bssid[ETH_ALEN]; 233 struct cfg80211_bitrate_mask bitrate_mask; 234 int num_legacy_stations; 235 int rtscts_prot_mode; 236 int txpower; 237 bool rsnie_present; 238 bool wpaie_present; 239 struct ieee80211_chanctx_conf chanctx; 240 u32 key_cipher; 241 u8 tx_encap_type; 242 u8 vdev_stats_id; 243 u32 punct_bitmap; 244 }; 245 246 struct ath12k_vif_iter { 247 u32 vdev_id; 248 struct ath12k_vif *arvif; 249 }; 250 251 #define HAL_AST_IDX_INVALID 0xFFFF 252 #define HAL_RX_MAX_MCS 12 253 #define HAL_RX_MAX_MCS_HT 31 254 #define HAL_RX_MAX_MCS_VHT 9 255 #define HAL_RX_MAX_MCS_HE 11 256 #define HAL_RX_MAX_NSS 8 257 #define HAL_RX_MAX_NUM_LEGACY_RATES 12 258 #define ATH12K_RX_RATE_TABLE_11AX_NUM 576 259 #define ATH12K_RX_RATE_TABLE_NUM 320 260 261 struct ath12k_rx_peer_rate_stats { 262 u64 ht_mcs_count[HAL_RX_MAX_MCS_HT + 1]; 263 u64 vht_mcs_count[HAL_RX_MAX_MCS_VHT + 1]; 264 u64 he_mcs_count[HAL_RX_MAX_MCS_HE + 1]; 265 u64 nss_count[HAL_RX_MAX_NSS]; 266 u64 bw_count[HAL_RX_BW_MAX]; 267 u64 gi_count[HAL_RX_GI_MAX]; 268 u64 legacy_count[HAL_RX_MAX_NUM_LEGACY_RATES]; 269 u64 rx_rate[ATH12K_RX_RATE_TABLE_11AX_NUM]; 270 }; 271 272 struct ath12k_rx_peer_stats { 273 u64 num_msdu; 274 u64 num_mpdu_fcs_ok; 275 u64 num_mpdu_fcs_err; 276 u64 tcp_msdu_count; 277 u64 udp_msdu_count; 278 u64 other_msdu_count; 279 u64 ampdu_msdu_count; 280 u64 non_ampdu_msdu_count; 281 u64 stbc_count; 282 u64 beamformed_count; 283 u64 mcs_count[HAL_RX_MAX_MCS + 1]; 284 u64 nss_count[HAL_RX_MAX_NSS]; 285 u64 bw_count[HAL_RX_BW_MAX]; 286 u64 gi_count[HAL_RX_GI_MAX]; 287 u64 coding_count[HAL_RX_SU_MU_CODING_MAX]; 288 u64 tid_count[IEEE80211_NUM_TIDS + 1]; 289 u64 pream_cnt[HAL_RX_PREAMBLE_MAX]; 290 u64 reception_type[HAL_RX_RECEPTION_TYPE_MAX]; 291 u64 rx_duration; 292 u64 dcm_count; 293 u64 ru_alloc_cnt[HAL_RX_RU_ALLOC_TYPE_MAX]; 294 struct ath12k_rx_peer_rate_stats pkt_stats; 295 struct ath12k_rx_peer_rate_stats byte_stats; 296 }; 297 298 #define ATH12K_HE_MCS_NUM 12 299 #define ATH12K_VHT_MCS_NUM 10 300 #define ATH12K_BW_NUM 5 301 #define ATH12K_NSS_NUM 4 302 #define ATH12K_LEGACY_NUM 12 303 #define ATH12K_GI_NUM 4 304 #define ATH12K_HT_MCS_NUM 32 305 306 enum ath12k_pkt_rx_err { 307 ATH12K_PKT_RX_ERR_FCS, 308 ATH12K_PKT_RX_ERR_TKIP, 309 ATH12K_PKT_RX_ERR_CRYPT, 310 ATH12K_PKT_RX_ERR_PEER_IDX_INVAL, 311 ATH12K_PKT_RX_ERR_MAX, 312 }; 313 314 enum ath12k_ampdu_subfrm_num { 315 ATH12K_AMPDU_SUBFRM_NUM_10, 316 ATH12K_AMPDU_SUBFRM_NUM_20, 317 ATH12K_AMPDU_SUBFRM_NUM_30, 318 ATH12K_AMPDU_SUBFRM_NUM_40, 319 ATH12K_AMPDU_SUBFRM_NUM_50, 320 ATH12K_AMPDU_SUBFRM_NUM_60, 321 ATH12K_AMPDU_SUBFRM_NUM_MORE, 322 ATH12K_AMPDU_SUBFRM_NUM_MAX, 323 }; 324 325 enum ath12k_amsdu_subfrm_num { 326 ATH12K_AMSDU_SUBFRM_NUM_1, 327 ATH12K_AMSDU_SUBFRM_NUM_2, 328 ATH12K_AMSDU_SUBFRM_NUM_3, 329 ATH12K_AMSDU_SUBFRM_NUM_4, 330 ATH12K_AMSDU_SUBFRM_NUM_MORE, 331 ATH12K_AMSDU_SUBFRM_NUM_MAX, 332 }; 333 334 enum ath12k_counter_type { 335 ATH12K_COUNTER_TYPE_BYTES, 336 ATH12K_COUNTER_TYPE_PKTS, 337 ATH12K_COUNTER_TYPE_MAX, 338 }; 339 340 enum ath12k_stats_type { 341 ATH12K_STATS_TYPE_SUCC, 342 ATH12K_STATS_TYPE_FAIL, 343 ATH12K_STATS_TYPE_RETRY, 344 ATH12K_STATS_TYPE_AMPDU, 345 ATH12K_STATS_TYPE_MAX, 346 }; 347 348 struct ath12k_htt_data_stats { 349 u64 legacy[ATH12K_COUNTER_TYPE_MAX][ATH12K_LEGACY_NUM]; 350 u64 ht[ATH12K_COUNTER_TYPE_MAX][ATH12K_HT_MCS_NUM]; 351 u64 vht[ATH12K_COUNTER_TYPE_MAX][ATH12K_VHT_MCS_NUM]; 352 u64 he[ATH12K_COUNTER_TYPE_MAX][ATH12K_HE_MCS_NUM]; 353 u64 bw[ATH12K_COUNTER_TYPE_MAX][ATH12K_BW_NUM]; 354 u64 nss[ATH12K_COUNTER_TYPE_MAX][ATH12K_NSS_NUM]; 355 u64 gi[ATH12K_COUNTER_TYPE_MAX][ATH12K_GI_NUM]; 356 u64 transmit_type[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RECEPTION_TYPE_MAX]; 357 u64 ru_loc[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RU_ALLOC_TYPE_MAX]; 358 }; 359 360 struct ath12k_htt_tx_stats { 361 struct ath12k_htt_data_stats stats[ATH12K_STATS_TYPE_MAX]; 362 u64 tx_duration; 363 u64 ba_fails; 364 u64 ack_fails; 365 u16 ru_start; 366 u16 ru_tones; 367 u32 mu_group[MAX_MU_GROUP_ID]; 368 }; 369 370 struct ath12k_per_ppdu_tx_stats { 371 u16 succ_pkts; 372 u16 failed_pkts; 373 u16 retry_pkts; 374 u32 succ_bytes; 375 u32 failed_bytes; 376 u32 retry_bytes; 377 }; 378 379 struct ath12k_wbm_tx_stats { 380 u64 wbm_tx_comp_stats[HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX]; 381 }; 382 383 struct ath12k_sta { 384 struct ath12k_vif *arvif; 385 386 /* the following are protected by ar->data_lock */ 387 u32 changed; /* IEEE80211_RC_* */ 388 u32 bw; 389 u32 nss; 390 u32 smps; 391 enum hal_pn_type pn_type; 392 393 struct work_struct update_wk; 394 struct rate_info txrate; 395 struct rate_info last_txrate; 396 u64 rx_duration; 397 u64 tx_duration; 398 u8 rssi_comb; 399 struct ath12k_rx_peer_stats *rx_stats; 400 struct ath12k_wbm_tx_stats *wbm_tx_stats; 401 u32 bw_prev; 402 }; 403 404 #define ATH12K_MIN_5G_FREQ 4150 405 #define ATH12K_MIN_6G_FREQ 5925 406 #define ATH12K_MAX_6G_FREQ 7115 407 #define ATH12K_NUM_CHANS 100 408 #define ATH12K_MAX_5G_CHAN 173 409 410 enum ath12k_state { 411 ATH12K_STATE_OFF, 412 ATH12K_STATE_ON, 413 ATH12K_STATE_RESTARTING, 414 ATH12K_STATE_RESTARTED, 415 ATH12K_STATE_WEDGED, 416 /* Add other states as required */ 417 }; 418 419 /* Antenna noise floor */ 420 #define ATH12K_DEFAULT_NOISE_FLOOR -95 421 422 struct ath12k_fw_stats { 423 u32 pdev_id; 424 u32 stats_id; 425 struct list_head pdevs; 426 struct list_head vdevs; 427 struct list_head bcn; 428 }; 429 430 struct ath12k_per_peer_tx_stats { 431 u32 succ_bytes; 432 u32 retry_bytes; 433 u32 failed_bytes; 434 u32 duration; 435 u16 succ_pkts; 436 u16 retry_pkts; 437 u16 failed_pkts; 438 u16 ru_start; 439 u16 ru_tones; 440 u8 ba_fails; 441 u8 ppdu_type; 442 u32 mu_grpid; 443 u32 mu_pos; 444 bool is_ampdu; 445 }; 446 447 #define ATH12K_FLUSH_TIMEOUT (5 * HZ) 448 #define ATH12K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ) 449 450 struct ath12k { 451 struct ath12k_base *ab; 452 struct ath12k_pdev *pdev; 453 struct ieee80211_hw *hw; 454 struct ieee80211_ops *ops; 455 struct ath12k_wmi_pdev *wmi; 456 struct ath12k_pdev_dp dp; 457 u8 mac_addr[ETH_ALEN]; 458 u32 ht_cap_info; 459 u32 vht_cap_info; 460 struct ath12k_he ar_he; 461 enum ath12k_state state; 462 bool supports_6ghz; 463 struct { 464 struct completion started; 465 struct completion completed; 466 struct completion on_channel; 467 struct delayed_work timeout; 468 enum ath12k_scan_state state; 469 bool is_roc; 470 int vdev_id; 471 int roc_freq; 472 bool roc_notify; 473 } scan; 474 475 struct { 476 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS]; 477 struct ieee80211_sband_iftype_data 478 iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES]; 479 } mac; 480 481 unsigned long dev_flags; 482 unsigned int filter_flags; 483 unsigned long monitor_flags; 484 u32 min_tx_power; 485 u32 max_tx_power; 486 u32 txpower_limit_2g; 487 u32 txpower_limit_5g; 488 u32 txpower_scale; 489 u32 power_scale; 490 u32 chan_tx_pwr; 491 u32 num_stations; 492 u32 max_num_stations; 493 bool monitor_present; 494 /* To synchronize concurrent synchronous mac80211 callback operations, 495 * concurrent debugfs configuration and concurrent FW statistics events. 496 */ 497 struct mutex conf_mutex; 498 /* protects the radio specific data like debug stats, ppdu_stats_info stats, 499 * vdev_stop_status info, scan data, ath12k_sta info, ath12k_vif info, 500 * channel context data, survey info, test mode data. 501 */ 502 spinlock_t data_lock; 503 504 struct list_head arvifs; 505 /* should never be NULL; needed for regular htt rx */ 506 struct ieee80211_channel *rx_channel; 507 508 /* valid during scan; needed for mgmt rx during scan */ 509 struct ieee80211_channel *scan_channel; 510 511 u8 cfg_tx_chainmask; 512 u8 cfg_rx_chainmask; 513 u8 num_rx_chains; 514 u8 num_tx_chains; 515 /* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */ 516 u8 pdev_idx; 517 u8 lmac_id; 518 519 struct completion peer_assoc_done; 520 struct completion peer_delete_done; 521 522 int install_key_status; 523 struct completion install_key_done; 524 525 int last_wmi_vdev_start_status; 526 struct completion vdev_setup_done; 527 struct completion vdev_delete_done; 528 529 int num_peers; 530 int max_num_peers; 531 u32 num_started_vdevs; 532 u32 num_created_vdevs; 533 unsigned long long allocated_vdev_map; 534 535 struct idr txmgmt_idr; 536 /* protects txmgmt_idr data */ 537 spinlock_t txmgmt_idr_lock; 538 atomic_t num_pending_mgmt_tx; 539 wait_queue_head_t txmgmt_empty_waitq; 540 541 /* cycle count is reported twice for each visited channel during scan. 542 * access protected by data_lock 543 */ 544 u32 survey_last_rx_clear_count; 545 u32 survey_last_cycle_count; 546 547 /* Channel info events are expected to come in pairs without and with 548 * COMPLETE flag set respectively for each channel visit during scan. 549 * 550 * However there are deviations from this rule. This flag is used to 551 * avoid reporting garbage data. 552 */ 553 bool ch_info_can_report_survey; 554 struct survey_info survey[ATH12K_NUM_CHANS]; 555 struct completion bss_survey_done; 556 557 struct work_struct regd_update_work; 558 559 struct work_struct wmi_mgmt_tx_work; 560 struct sk_buff_head wmi_mgmt_tx_queue; 561 562 struct ath12k_per_peer_tx_stats peer_tx_stats; 563 struct list_head ppdu_stats_info; 564 u32 ppdu_stat_list_depth; 565 566 struct ath12k_per_peer_tx_stats cached_stats; 567 u32 last_ppdu_id; 568 u32 cached_ppdu_id; 569 570 bool dfs_block_radar_events; 571 bool monitor_conf_enabled; 572 bool monitor_vdev_created; 573 bool monitor_started; 574 int monitor_vdev_id; 575 }; 576 577 struct ath12k_band_cap { 578 u32 phy_id; 579 u32 max_bw_supported; 580 u32 ht_cap_info; 581 u32 he_cap_info[2]; 582 u32 he_mcs; 583 u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE]; 584 struct ath12k_wmi_ppe_threshold_arg he_ppet; 585 u16 he_6ghz_capa; 586 u32 eht_cap_mac_info[WMI_MAX_EHTCAP_MAC_SIZE]; 587 u32 eht_cap_phy_info[WMI_MAX_EHTCAP_PHY_SIZE]; 588 u32 eht_mcs_20_only; 589 u32 eht_mcs_80; 590 u32 eht_mcs_160; 591 u32 eht_mcs_320; 592 struct ath12k_wmi_ppe_threshold_arg eht_ppet; 593 u32 eht_cap_info_internal; 594 }; 595 596 struct ath12k_pdev_cap { 597 u32 supported_bands; 598 u32 ampdu_density; 599 u32 vht_cap; 600 u32 vht_mcs; 601 u32 he_mcs; 602 u32 tx_chain_mask; 603 u32 rx_chain_mask; 604 u32 tx_chain_mask_shift; 605 u32 rx_chain_mask_shift; 606 struct ath12k_band_cap band[NUM_NL80211_BANDS]; 607 }; 608 609 struct mlo_timestamp { 610 u32 info; 611 u32 sync_timestamp_lo_us; 612 u32 sync_timestamp_hi_us; 613 u32 mlo_offset_lo; 614 u32 mlo_offset_hi; 615 u32 mlo_offset_clks; 616 u32 mlo_comp_clks; 617 u32 mlo_comp_timer; 618 }; 619 620 struct ath12k_pdev { 621 struct ath12k *ar; 622 u32 pdev_id; 623 struct ath12k_pdev_cap cap; 624 u8 mac_addr[ETH_ALEN]; 625 struct mlo_timestamp timestamp; 626 }; 627 628 struct ath12k_fw_pdev { 629 u32 pdev_id; 630 u32 phy_id; 631 u32 supported_bands; 632 }; 633 634 struct ath12k_board_data { 635 const struct firmware *fw; 636 const void *data; 637 size_t len; 638 }; 639 640 struct ath12k_soc_dp_tx_err_stats { 641 /* TCL Ring Descriptor unavailable */ 642 u32 desc_na[DP_TCL_NUM_RING_MAX]; 643 /* Other failures during dp_tx due to mem allocation failure 644 * idr unavailable etc. 645 */ 646 atomic_t misc_fail; 647 }; 648 649 struct ath12k_soc_dp_stats { 650 u32 err_ring_pkts; 651 u32 invalid_rbm; 652 u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX]; 653 u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX]; 654 u32 hal_reo_error[DP_REO_DST_RING_MAX]; 655 struct ath12k_soc_dp_tx_err_stats tx_err; 656 }; 657 658 /* Master structure to hold the hw data which may be used in core module */ 659 struct ath12k_base { 660 enum ath12k_hw_rev hw_rev; 661 struct platform_device *pdev; 662 struct device *dev; 663 struct ath12k_qmi qmi; 664 struct ath12k_wmi_base wmi_ab; 665 struct completion fw_ready; 666 int num_radios; 667 /* HW channel counters frequency value in hertz common to all MACs */ 668 u32 cc_freq_hz; 669 670 struct ath12k_htc htc; 671 672 struct ath12k_dp dp; 673 674 void __iomem *mem; 675 unsigned long mem_len; 676 677 struct { 678 enum ath12k_bus bus; 679 const struct ath12k_hif_ops *ops; 680 } hif; 681 682 struct ath12k_ce ce; 683 struct timer_list rx_replenish_retry; 684 struct ath12k_hal hal; 685 /* To synchronize core_start/core_stop */ 686 struct mutex core_lock; 687 /* Protects data like peers */ 688 spinlock_t base_lock; 689 690 /* Single pdev device (struct ath12k_hw_params::single_pdev_only): 691 * 692 * Firmware maintains data for all bands but advertises a single 693 * phy to the host which is stored as a single element in this 694 * array. 695 * 696 * Other devices: 697 * 698 * This array will contain as many elements as the number of 699 * radios. 700 */ 701 struct ath12k_pdev pdevs[MAX_RADIOS]; 702 703 /* struct ath12k_hw_params::single_pdev_only devices use this to 704 * store phy specific data 705 */ 706 struct ath12k_fw_pdev fw_pdev[MAX_RADIOS]; 707 u8 fw_pdev_count; 708 709 struct ath12k_pdev __rcu *pdevs_active[MAX_RADIOS]; 710 struct ath12k_wmi_hal_reg_capabilities_ext_arg hal_reg_cap[MAX_RADIOS]; 711 unsigned long long free_vdev_map; 712 unsigned long long free_vdev_stats_id_map; 713 struct list_head peers; 714 wait_queue_head_t peer_mapping_wq; 715 u8 mac_addr[ETH_ALEN]; 716 bool wmi_ready; 717 u32 wlan_init_status; 718 int irq_num[ATH12K_IRQ_NUM_MAX]; 719 struct ath12k_ext_irq_grp ext_irq_grp[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 720 struct napi_struct *napi; 721 struct ath12k_wmi_target_cap_arg target_caps; 722 u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE]; 723 bool pdevs_macaddr_valid; 724 int bd_api; 725 726 const struct ath12k_hw_params *hw_params; 727 728 const struct firmware *cal_file; 729 730 /* Below regd's are protected by ab->data_lock */ 731 /* This is the regd set for every radio 732 * by the firmware during initialization 733 */ 734 struct ieee80211_regdomain *default_regd[MAX_RADIOS]; 735 /* This regd is set during dynamic country setting 736 * This may or may not be used during the runtime 737 */ 738 struct ieee80211_regdomain *new_regd[MAX_RADIOS]; 739 740 /* Current DFS Regulatory */ 741 enum ath12k_dfs_region dfs_region; 742 struct ath12k_soc_dp_stats soc_stats; 743 744 unsigned long dev_flags; 745 struct completion driver_recovery; 746 struct workqueue_struct *workqueue; 747 struct work_struct restart_work; 748 struct workqueue_struct *workqueue_aux; 749 struct work_struct reset_work; 750 atomic_t reset_count; 751 atomic_t recovery_count; 752 atomic_t recovery_start_count; 753 bool is_reset; 754 struct completion reset_complete; 755 struct completion reconfigure_complete; 756 struct completion recovery_start; 757 /* continuous recovery fail count */ 758 atomic_t fail_cont_count; 759 unsigned long reset_fail_timeout; 760 struct { 761 /* protected by data_lock */ 762 u32 fw_crash_counter; 763 } stats; 764 u32 pktlog_defs_checksum; 765 766 struct ath12k_dbring_cap *db_caps; 767 u32 num_db_cap; 768 769 struct timer_list mon_reap_timer; 770 771 struct completion htc_suspend; 772 773 u64 fw_soc_drop_count; 774 bool static_window_map; 775 776 /* must be last */ 777 u8 drv_priv[] __aligned(sizeof(void *)); 778 }; 779 780 int ath12k_core_qmi_firmware_ready(struct ath12k_base *ab); 781 int ath12k_core_pre_init(struct ath12k_base *ab); 782 int ath12k_core_init(struct ath12k_base *ath12k); 783 void ath12k_core_deinit(struct ath12k_base *ath12k); 784 struct ath12k_base *ath12k_core_alloc(struct device *dev, size_t priv_size, 785 enum ath12k_bus bus); 786 void ath12k_core_free(struct ath12k_base *ath12k); 787 int ath12k_core_fetch_board_data_api_1(struct ath12k_base *ab, 788 struct ath12k_board_data *bd, 789 char *filename); 790 int ath12k_core_fetch_bdf(struct ath12k_base *ath12k, 791 struct ath12k_board_data *bd); 792 void ath12k_core_free_bdf(struct ath12k_base *ab, struct ath12k_board_data *bd); 793 794 void ath12k_core_halt(struct ath12k *ar); 795 int ath12k_core_resume(struct ath12k_base *ab); 796 int ath12k_core_suspend(struct ath12k_base *ab); 797 798 const struct firmware *ath12k_core_firmware_request(struct ath12k_base *ab, 799 const char *filename); 800 801 static inline const char *ath12k_scan_state_str(enum ath12k_scan_state state) 802 { 803 switch (state) { 804 case ATH12K_SCAN_IDLE: 805 return "idle"; 806 case ATH12K_SCAN_STARTING: 807 return "starting"; 808 case ATH12K_SCAN_RUNNING: 809 return "running"; 810 case ATH12K_SCAN_ABORTING: 811 return "aborting"; 812 } 813 814 return "unknown"; 815 } 816 817 static inline struct ath12k_skb_cb *ATH12K_SKB_CB(struct sk_buff *skb) 818 { 819 BUILD_BUG_ON(sizeof(struct ath12k_skb_cb) > 820 IEEE80211_TX_INFO_DRIVER_DATA_SIZE); 821 return (struct ath12k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data; 822 } 823 824 static inline struct ath12k_skb_rxcb *ATH12K_SKB_RXCB(struct sk_buff *skb) 825 { 826 BUILD_BUG_ON(sizeof(struct ath12k_skb_rxcb) > sizeof(skb->cb)); 827 return (struct ath12k_skb_rxcb *)skb->cb; 828 } 829 830 static inline struct ath12k_vif *ath12k_vif_to_arvif(struct ieee80211_vif *vif) 831 { 832 return (struct ath12k_vif *)vif->drv_priv; 833 } 834 835 static inline struct ath12k *ath12k_ab_to_ar(struct ath12k_base *ab, 836 int mac_id) 837 { 838 return ab->pdevs[ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id)].ar; 839 } 840 841 static inline void ath12k_core_create_firmware_path(struct ath12k_base *ab, 842 const char *filename, 843 void *buf, size_t buf_len) 844 { 845 snprintf(buf, buf_len, "%s/%s/%s", ATH12K_FW_DIR, 846 ab->hw_params->fw.dir, filename); 847 } 848 849 static inline const char *ath12k_bus_str(enum ath12k_bus bus) 850 { 851 switch (bus) { 852 case ATH12K_BUS_PCI: 853 return "pci"; 854 } 855 856 return "unknown"; 857 } 858 859 #endif /* _CORE_H_ */ 860