1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH12K_CORE_H 8 #define ATH12K_CORE_H 9 10 #include <linux/types.h> 11 #include <linux/interrupt.h> 12 #include <linux/irq.h> 13 #include <linux/bitfield.h> 14 #include "qmi.h" 15 #include "htc.h" 16 #include "wmi.h" 17 #include "hal.h" 18 #include "dp.h" 19 #include "ce.h" 20 #include "mac.h" 21 #include "hw.h" 22 #include "hal_rx.h" 23 #include "reg.h" 24 #include "dbring.h" 25 26 #define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK) 27 28 #define ATH12K_TX_MGMT_NUM_PENDING_MAX 512 29 30 #define ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64 31 32 /* Pending management packets threshold for dropping probe responses */ 33 #define ATH12K_PRB_RSP_DROP_THRESHOLD ((ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4) 34 35 #define ATH12K_INVALID_HW_MAC_ID 0xFF 36 #define ATH12K_RX_RATE_TABLE_NUM 320 37 #define ATH12K_RX_RATE_TABLE_11AX_NUM 576 38 39 #define ATH12K_MON_TIMER_INTERVAL 10 40 #define ATH12K_RESET_TIMEOUT_HZ (20 * HZ) 41 #define ATH12K_RESET_MAX_FAIL_COUNT_FIRST 3 42 #define ATH12K_RESET_MAX_FAIL_COUNT_FINAL 5 43 #define ATH12K_RESET_FAIL_TIMEOUT_HZ (20 * HZ) 44 #define ATH12K_RECONFIGURE_TIMEOUT_HZ (10 * HZ) 45 #define ATH12K_RECOVER_START_TIMEOUT_HZ (20 * HZ) 46 47 enum wme_ac { 48 WME_AC_BE, 49 WME_AC_BK, 50 WME_AC_VI, 51 WME_AC_VO, 52 WME_NUM_AC 53 }; 54 55 #define ATH12K_HT_MCS_MAX 7 56 #define ATH12K_VHT_MCS_MAX 9 57 #define ATH12K_HE_MCS_MAX 11 58 59 enum ath12k_crypt_mode { 60 /* Only use hardware crypto engine */ 61 ATH12K_CRYPT_MODE_HW, 62 /* Only use software crypto */ 63 ATH12K_CRYPT_MODE_SW, 64 }; 65 66 static inline enum wme_ac ath12k_tid_to_ac(u32 tid) 67 { 68 return (((tid == 0) || (tid == 3)) ? WME_AC_BE : 69 ((tid == 1) || (tid == 2)) ? WME_AC_BK : 70 ((tid == 4) || (tid == 5)) ? WME_AC_VI : 71 WME_AC_VO); 72 } 73 74 enum ath12k_skb_flags { 75 ATH12K_SKB_HW_80211_ENCAP = BIT(0), 76 ATH12K_SKB_CIPHER_SET = BIT(1), 77 }; 78 79 struct ath12k_skb_cb { 80 dma_addr_t paddr; 81 struct ath12k *ar; 82 struct ieee80211_vif *vif; 83 dma_addr_t paddr_ext_desc; 84 u32 cipher; 85 u8 flags; 86 }; 87 88 struct ath12k_skb_rxcb { 89 dma_addr_t paddr; 90 bool is_first_msdu; 91 bool is_last_msdu; 92 bool is_continuation; 93 bool is_mcbc; 94 bool is_eapol; 95 struct hal_rx_desc *rx_desc; 96 u8 err_rel_src; 97 u8 err_code; 98 u8 mac_id; 99 u8 unmapped; 100 u8 is_frag; 101 u8 tid; 102 u16 peer_id; 103 }; 104 105 enum ath12k_hw_rev { 106 ATH12K_HW_QCN9274_HW10, 107 ATH12K_HW_QCN9274_HW20, 108 ATH12K_HW_WCN7850_HW20 109 }; 110 111 enum ath12k_firmware_mode { 112 /* the default mode, standard 802.11 functionality */ 113 ATH12K_FIRMWARE_MODE_NORMAL, 114 115 /* factory tests etc */ 116 ATH12K_FIRMWARE_MODE_FTM, 117 }; 118 119 #define ATH12K_IRQ_NUM_MAX 57 120 #define ATH12K_EXT_IRQ_NUM_MAX 16 121 122 struct ath12k_ext_irq_grp { 123 struct ath12k_base *ab; 124 u32 irqs[ATH12K_EXT_IRQ_NUM_MAX]; 125 u32 num_irq; 126 u32 grp_id; 127 u64 timestamp; 128 struct napi_struct napi; 129 struct net_device napi_ndev; 130 }; 131 132 #define HEHANDLE_CAP_PHYINFO_SIZE 3 133 #define HECAP_PHYINFO_SIZE 9 134 #define HECAP_MACINFO_SIZE 5 135 #define HECAP_TXRX_MCS_NSS_SIZE 2 136 #define HECAP_PPET16_PPET8_MAX_SIZE 25 137 138 #define HE_PPET16_PPET8_SIZE 8 139 140 /* 802.11ax PPE (PPDU packet Extension) threshold */ 141 struct he_ppe_threshold { 142 u32 numss_m1; 143 u32 ru_mask; 144 u32 ppet16_ppet8_ru3_ru0[HE_PPET16_PPET8_SIZE]; 145 }; 146 147 struct ath12k_he { 148 u8 hecap_macinfo[HECAP_MACINFO_SIZE]; 149 u32 hecap_rxmcsnssmap; 150 u32 hecap_txmcsnssmap; 151 u32 hecap_phyinfo[HEHANDLE_CAP_PHYINFO_SIZE]; 152 struct he_ppe_threshold hecap_ppet; 153 u32 heop_param; 154 }; 155 156 #define MAX_RADIOS 3 157 158 enum { 159 WMI_HOST_TP_SCALE_MAX = 0, 160 WMI_HOST_TP_SCALE_50 = 1, 161 WMI_HOST_TP_SCALE_25 = 2, 162 WMI_HOST_TP_SCALE_12 = 3, 163 WMI_HOST_TP_SCALE_MIN = 4, 164 WMI_HOST_TP_SCALE_SIZE = 5, 165 }; 166 167 enum ath12k_scan_state { 168 ATH12K_SCAN_IDLE, 169 ATH12K_SCAN_STARTING, 170 ATH12K_SCAN_RUNNING, 171 ATH12K_SCAN_ABORTING, 172 }; 173 174 enum ath12k_dev_flags { 175 ATH12K_CAC_RUNNING, 176 ATH12K_FLAG_CRASH_FLUSH, 177 ATH12K_FLAG_RAW_MODE, 178 ATH12K_FLAG_HW_CRYPTO_DISABLED, 179 ATH12K_FLAG_RECOVERY, 180 ATH12K_FLAG_UNREGISTERING, 181 ATH12K_FLAG_REGISTERED, 182 ATH12K_FLAG_QMI_FAIL, 183 ATH12K_FLAG_HTC_SUSPEND_COMPLETE, 184 }; 185 186 enum ath12k_monitor_flags { 187 ATH12K_FLAG_MONITOR_ENABLED, 188 }; 189 190 struct ath12k_vif { 191 u32 vdev_id; 192 enum wmi_vdev_type vdev_type; 193 enum wmi_vdev_subtype vdev_subtype; 194 u32 beacon_interval; 195 u32 dtim_period; 196 u16 ast_hash; 197 u16 ast_idx; 198 u16 tcl_metadata; 199 u8 hal_addr_search_flags; 200 u8 search_type; 201 202 struct ath12k *ar; 203 struct ieee80211_vif *vif; 204 205 int bank_id; 206 u8 vdev_id_check_en; 207 208 struct wmi_wmm_params_all_arg wmm_params; 209 struct list_head list; 210 union { 211 struct { 212 u32 uapsd; 213 } sta; 214 struct { 215 /* 127 stations; wmi limit */ 216 u8 tim_bitmap[16]; 217 u8 tim_len; 218 u32 ssid_len; 219 u8 ssid[IEEE80211_MAX_SSID_LEN]; 220 bool hidden_ssid; 221 /* P2P_IE with NoA attribute for P2P_GO case */ 222 u32 noa_len; 223 u8 *noa_data; 224 } ap; 225 } u; 226 227 bool is_started; 228 bool is_up; 229 u32 aid; 230 u8 bssid[ETH_ALEN]; 231 struct cfg80211_bitrate_mask bitrate_mask; 232 int num_legacy_stations; 233 int rtscts_prot_mode; 234 int txpower; 235 bool rsnie_present; 236 bool wpaie_present; 237 struct ieee80211_chanctx_conf chanctx; 238 u32 key_cipher; 239 u8 tx_encap_type; 240 u8 vdev_stats_id; 241 }; 242 243 struct ath12k_vif_iter { 244 u32 vdev_id; 245 struct ath12k_vif *arvif; 246 }; 247 248 #define HAL_AST_IDX_INVALID 0xFFFF 249 #define HAL_RX_MAX_MCS 12 250 #define HAL_RX_MAX_MCS_HT 31 251 #define HAL_RX_MAX_MCS_VHT 9 252 #define HAL_RX_MAX_MCS_HE 11 253 #define HAL_RX_MAX_NSS 8 254 #define HAL_RX_MAX_NUM_LEGACY_RATES 12 255 #define ATH12K_RX_RATE_TABLE_11AX_NUM 576 256 #define ATH12K_RX_RATE_TABLE_NUM 320 257 258 struct ath12k_rx_peer_rate_stats { 259 u64 ht_mcs_count[HAL_RX_MAX_MCS_HT + 1]; 260 u64 vht_mcs_count[HAL_RX_MAX_MCS_VHT + 1]; 261 u64 he_mcs_count[HAL_RX_MAX_MCS_HE + 1]; 262 u64 nss_count[HAL_RX_MAX_NSS]; 263 u64 bw_count[HAL_RX_BW_MAX]; 264 u64 gi_count[HAL_RX_GI_MAX]; 265 u64 legacy_count[HAL_RX_MAX_NUM_LEGACY_RATES]; 266 u64 rx_rate[ATH12K_RX_RATE_TABLE_11AX_NUM]; 267 }; 268 269 struct ath12k_rx_peer_stats { 270 u64 num_msdu; 271 u64 num_mpdu_fcs_ok; 272 u64 num_mpdu_fcs_err; 273 u64 tcp_msdu_count; 274 u64 udp_msdu_count; 275 u64 other_msdu_count; 276 u64 ampdu_msdu_count; 277 u64 non_ampdu_msdu_count; 278 u64 stbc_count; 279 u64 beamformed_count; 280 u64 mcs_count[HAL_RX_MAX_MCS + 1]; 281 u64 nss_count[HAL_RX_MAX_NSS]; 282 u64 bw_count[HAL_RX_BW_MAX]; 283 u64 gi_count[HAL_RX_GI_MAX]; 284 u64 coding_count[HAL_RX_SU_MU_CODING_MAX]; 285 u64 tid_count[IEEE80211_NUM_TIDS + 1]; 286 u64 pream_cnt[HAL_RX_PREAMBLE_MAX]; 287 u64 reception_type[HAL_RX_RECEPTION_TYPE_MAX]; 288 u64 rx_duration; 289 u64 dcm_count; 290 u64 ru_alloc_cnt[HAL_RX_RU_ALLOC_TYPE_MAX]; 291 struct ath12k_rx_peer_rate_stats pkt_stats; 292 struct ath12k_rx_peer_rate_stats byte_stats; 293 }; 294 295 #define ATH12K_HE_MCS_NUM 12 296 #define ATH12K_VHT_MCS_NUM 10 297 #define ATH12K_BW_NUM 5 298 #define ATH12K_NSS_NUM 4 299 #define ATH12K_LEGACY_NUM 12 300 #define ATH12K_GI_NUM 4 301 #define ATH12K_HT_MCS_NUM 32 302 303 enum ath12k_pkt_rx_err { 304 ATH12K_PKT_RX_ERR_FCS, 305 ATH12K_PKT_RX_ERR_TKIP, 306 ATH12K_PKT_RX_ERR_CRYPT, 307 ATH12K_PKT_RX_ERR_PEER_IDX_INVAL, 308 ATH12K_PKT_RX_ERR_MAX, 309 }; 310 311 enum ath12k_ampdu_subfrm_num { 312 ATH12K_AMPDU_SUBFRM_NUM_10, 313 ATH12K_AMPDU_SUBFRM_NUM_20, 314 ATH12K_AMPDU_SUBFRM_NUM_30, 315 ATH12K_AMPDU_SUBFRM_NUM_40, 316 ATH12K_AMPDU_SUBFRM_NUM_50, 317 ATH12K_AMPDU_SUBFRM_NUM_60, 318 ATH12K_AMPDU_SUBFRM_NUM_MORE, 319 ATH12K_AMPDU_SUBFRM_NUM_MAX, 320 }; 321 322 enum ath12k_amsdu_subfrm_num { 323 ATH12K_AMSDU_SUBFRM_NUM_1, 324 ATH12K_AMSDU_SUBFRM_NUM_2, 325 ATH12K_AMSDU_SUBFRM_NUM_3, 326 ATH12K_AMSDU_SUBFRM_NUM_4, 327 ATH12K_AMSDU_SUBFRM_NUM_MORE, 328 ATH12K_AMSDU_SUBFRM_NUM_MAX, 329 }; 330 331 enum ath12k_counter_type { 332 ATH12K_COUNTER_TYPE_BYTES, 333 ATH12K_COUNTER_TYPE_PKTS, 334 ATH12K_COUNTER_TYPE_MAX, 335 }; 336 337 enum ath12k_stats_type { 338 ATH12K_STATS_TYPE_SUCC, 339 ATH12K_STATS_TYPE_FAIL, 340 ATH12K_STATS_TYPE_RETRY, 341 ATH12K_STATS_TYPE_AMPDU, 342 ATH12K_STATS_TYPE_MAX, 343 }; 344 345 struct ath12k_htt_data_stats { 346 u64 legacy[ATH12K_COUNTER_TYPE_MAX][ATH12K_LEGACY_NUM]; 347 u64 ht[ATH12K_COUNTER_TYPE_MAX][ATH12K_HT_MCS_NUM]; 348 u64 vht[ATH12K_COUNTER_TYPE_MAX][ATH12K_VHT_MCS_NUM]; 349 u64 he[ATH12K_COUNTER_TYPE_MAX][ATH12K_HE_MCS_NUM]; 350 u64 bw[ATH12K_COUNTER_TYPE_MAX][ATH12K_BW_NUM]; 351 u64 nss[ATH12K_COUNTER_TYPE_MAX][ATH12K_NSS_NUM]; 352 u64 gi[ATH12K_COUNTER_TYPE_MAX][ATH12K_GI_NUM]; 353 u64 transmit_type[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RECEPTION_TYPE_MAX]; 354 u64 ru_loc[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RU_ALLOC_TYPE_MAX]; 355 }; 356 357 struct ath12k_htt_tx_stats { 358 struct ath12k_htt_data_stats stats[ATH12K_STATS_TYPE_MAX]; 359 u64 tx_duration; 360 u64 ba_fails; 361 u64 ack_fails; 362 u16 ru_start; 363 u16 ru_tones; 364 u32 mu_group[MAX_MU_GROUP_ID]; 365 }; 366 367 struct ath12k_per_ppdu_tx_stats { 368 u16 succ_pkts; 369 u16 failed_pkts; 370 u16 retry_pkts; 371 u32 succ_bytes; 372 u32 failed_bytes; 373 u32 retry_bytes; 374 }; 375 376 struct ath12k_wbm_tx_stats { 377 u64 wbm_tx_comp_stats[HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX]; 378 }; 379 380 struct ath12k_sta { 381 struct ath12k_vif *arvif; 382 383 /* the following are protected by ar->data_lock */ 384 u32 changed; /* IEEE80211_RC_* */ 385 u32 bw; 386 u32 nss; 387 u32 smps; 388 enum hal_pn_type pn_type; 389 390 struct work_struct update_wk; 391 struct rate_info txrate; 392 struct rate_info last_txrate; 393 u64 rx_duration; 394 u64 tx_duration; 395 u8 rssi_comb; 396 struct ath12k_rx_peer_stats *rx_stats; 397 struct ath12k_wbm_tx_stats *wbm_tx_stats; 398 }; 399 400 #define ATH12K_MIN_5G_FREQ 4150 401 #define ATH12K_MIN_6G_FREQ 5945 402 #define ATH12K_MAX_6G_FREQ 7115 403 #define ATH12K_NUM_CHANS 100 404 #define ATH12K_MAX_5G_CHAN 173 405 406 enum ath12k_state { 407 ATH12K_STATE_OFF, 408 ATH12K_STATE_ON, 409 ATH12K_STATE_RESTARTING, 410 ATH12K_STATE_RESTARTED, 411 ATH12K_STATE_WEDGED, 412 /* Add other states as required */ 413 }; 414 415 /* Antenna noise floor */ 416 #define ATH12K_DEFAULT_NOISE_FLOOR -95 417 418 struct ath12k_fw_stats { 419 u32 pdev_id; 420 u32 stats_id; 421 struct list_head pdevs; 422 struct list_head vdevs; 423 struct list_head bcn; 424 }; 425 426 struct ath12k_per_peer_tx_stats { 427 u32 succ_bytes; 428 u32 retry_bytes; 429 u32 failed_bytes; 430 u32 duration; 431 u16 succ_pkts; 432 u16 retry_pkts; 433 u16 failed_pkts; 434 u16 ru_start; 435 u16 ru_tones; 436 u8 ba_fails; 437 u8 ppdu_type; 438 u32 mu_grpid; 439 u32 mu_pos; 440 bool is_ampdu; 441 }; 442 443 #define ATH12K_FLUSH_TIMEOUT (5 * HZ) 444 #define ATH12K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ) 445 446 struct ath12k { 447 struct ath12k_base *ab; 448 struct ath12k_pdev *pdev; 449 struct ieee80211_hw *hw; 450 struct ieee80211_ops *ops; 451 struct ath12k_wmi_pdev *wmi; 452 struct ath12k_pdev_dp dp; 453 u8 mac_addr[ETH_ALEN]; 454 u32 ht_cap_info; 455 u32 vht_cap_info; 456 struct ath12k_he ar_he; 457 enum ath12k_state state; 458 bool supports_6ghz; 459 struct { 460 struct completion started; 461 struct completion completed; 462 struct completion on_channel; 463 struct delayed_work timeout; 464 enum ath12k_scan_state state; 465 bool is_roc; 466 int vdev_id; 467 int roc_freq; 468 bool roc_notify; 469 } scan; 470 471 struct { 472 struct ieee80211_supported_band sbands[NUM_NL80211_BANDS]; 473 struct ieee80211_sband_iftype_data 474 iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES]; 475 } mac; 476 477 unsigned long dev_flags; 478 unsigned int filter_flags; 479 unsigned long monitor_flags; 480 u32 min_tx_power; 481 u32 max_tx_power; 482 u32 txpower_limit_2g; 483 u32 txpower_limit_5g; 484 u32 txpower_scale; 485 u32 power_scale; 486 u32 chan_tx_pwr; 487 u32 num_stations; 488 u32 max_num_stations; 489 bool monitor_present; 490 /* To synchronize concurrent synchronous mac80211 callback operations, 491 * concurrent debugfs configuration and concurrent FW statistics events. 492 */ 493 struct mutex conf_mutex; 494 /* protects the radio specific data like debug stats, ppdu_stats_info stats, 495 * vdev_stop_status info, scan data, ath12k_sta info, ath12k_vif info, 496 * channel context data, survey info, test mode data. 497 */ 498 spinlock_t data_lock; 499 500 struct list_head arvifs; 501 /* should never be NULL; needed for regular htt rx */ 502 struct ieee80211_channel *rx_channel; 503 504 /* valid during scan; needed for mgmt rx during scan */ 505 struct ieee80211_channel *scan_channel; 506 507 u8 cfg_tx_chainmask; 508 u8 cfg_rx_chainmask; 509 u8 num_rx_chains; 510 u8 num_tx_chains; 511 /* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */ 512 u8 pdev_idx; 513 u8 lmac_id; 514 515 struct completion peer_assoc_done; 516 struct completion peer_delete_done; 517 518 int install_key_status; 519 struct completion install_key_done; 520 521 int last_wmi_vdev_start_status; 522 struct completion vdev_setup_done; 523 struct completion vdev_delete_done; 524 525 int num_peers; 526 int max_num_peers; 527 u32 num_started_vdevs; 528 u32 num_created_vdevs; 529 unsigned long long allocated_vdev_map; 530 531 struct idr txmgmt_idr; 532 /* protects txmgmt_idr data */ 533 spinlock_t txmgmt_idr_lock; 534 atomic_t num_pending_mgmt_tx; 535 536 /* cycle count is reported twice for each visited channel during scan. 537 * access protected by data_lock 538 */ 539 u32 survey_last_rx_clear_count; 540 u32 survey_last_cycle_count; 541 542 /* Channel info events are expected to come in pairs without and with 543 * COMPLETE flag set respectively for each channel visit during scan. 544 * 545 * However there are deviations from this rule. This flag is used to 546 * avoid reporting garbage data. 547 */ 548 bool ch_info_can_report_survey; 549 struct survey_info survey[ATH12K_NUM_CHANS]; 550 struct completion bss_survey_done; 551 552 struct work_struct regd_update_work; 553 554 struct work_struct wmi_mgmt_tx_work; 555 struct sk_buff_head wmi_mgmt_tx_queue; 556 557 struct ath12k_per_peer_tx_stats peer_tx_stats; 558 struct list_head ppdu_stats_info; 559 u32 ppdu_stat_list_depth; 560 561 struct ath12k_per_peer_tx_stats cached_stats; 562 u32 last_ppdu_id; 563 u32 cached_ppdu_id; 564 565 bool dfs_block_radar_events; 566 bool monitor_conf_enabled; 567 bool monitor_vdev_created; 568 bool monitor_started; 569 int monitor_vdev_id; 570 }; 571 572 struct ath12k_band_cap { 573 u32 phy_id; 574 u32 max_bw_supported; 575 u32 ht_cap_info; 576 u32 he_cap_info[2]; 577 u32 he_mcs; 578 u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE]; 579 struct ath12k_wmi_ppe_threshold_arg he_ppet; 580 u16 he_6ghz_capa; 581 }; 582 583 struct ath12k_pdev_cap { 584 u32 supported_bands; 585 u32 ampdu_density; 586 u32 vht_cap; 587 u32 vht_mcs; 588 u32 he_mcs; 589 u32 tx_chain_mask; 590 u32 rx_chain_mask; 591 u32 tx_chain_mask_shift; 592 u32 rx_chain_mask_shift; 593 struct ath12k_band_cap band[NUM_NL80211_BANDS]; 594 }; 595 596 struct mlo_timestamp { 597 u32 info; 598 u32 sync_timestamp_lo_us; 599 u32 sync_timestamp_hi_us; 600 u32 mlo_offset_lo; 601 u32 mlo_offset_hi; 602 u32 mlo_offset_clks; 603 u32 mlo_comp_clks; 604 u32 mlo_comp_timer; 605 }; 606 607 struct ath12k_pdev { 608 struct ath12k *ar; 609 u32 pdev_id; 610 struct ath12k_pdev_cap cap; 611 u8 mac_addr[ETH_ALEN]; 612 struct mlo_timestamp timestamp; 613 }; 614 615 struct ath12k_board_data { 616 const struct firmware *fw; 617 const void *data; 618 size_t len; 619 }; 620 621 struct ath12k_soc_dp_tx_err_stats { 622 /* TCL Ring Descriptor unavailable */ 623 u32 desc_na[DP_TCL_NUM_RING_MAX]; 624 /* Other failures during dp_tx due to mem allocation failure 625 * idr unavailable etc. 626 */ 627 atomic_t misc_fail; 628 }; 629 630 struct ath12k_soc_dp_stats { 631 u32 err_ring_pkts; 632 u32 invalid_rbm; 633 u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX]; 634 u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX]; 635 u32 hal_reo_error[DP_REO_DST_RING_MAX]; 636 struct ath12k_soc_dp_tx_err_stats tx_err; 637 }; 638 639 /* Master structure to hold the hw data which may be used in core module */ 640 struct ath12k_base { 641 enum ath12k_hw_rev hw_rev; 642 struct platform_device *pdev; 643 struct device *dev; 644 struct ath12k_qmi qmi; 645 struct ath12k_wmi_base wmi_ab; 646 struct completion fw_ready; 647 int num_radios; 648 /* HW channel counters frequency value in hertz common to all MACs */ 649 u32 cc_freq_hz; 650 651 struct ath12k_htc htc; 652 653 struct ath12k_dp dp; 654 655 void __iomem *mem; 656 unsigned long mem_len; 657 658 struct { 659 enum ath12k_bus bus; 660 const struct ath12k_hif_ops *ops; 661 } hif; 662 663 struct ath12k_ce ce; 664 struct timer_list rx_replenish_retry; 665 struct ath12k_hal hal; 666 /* To synchronize core_start/core_stop */ 667 struct mutex core_lock; 668 /* Protects data like peers */ 669 spinlock_t base_lock; 670 struct ath12k_pdev pdevs[MAX_RADIOS]; 671 struct ath12k_pdev __rcu *pdevs_active[MAX_RADIOS]; 672 struct ath12k_wmi_hal_reg_capabilities_ext_arg hal_reg_cap[MAX_RADIOS]; 673 unsigned long long free_vdev_map; 674 unsigned long long free_vdev_stats_id_map; 675 struct list_head peers; 676 wait_queue_head_t peer_mapping_wq; 677 u8 mac_addr[ETH_ALEN]; 678 bool wmi_ready; 679 u32 wlan_init_status; 680 int irq_num[ATH12K_IRQ_NUM_MAX]; 681 struct ath12k_ext_irq_grp ext_irq_grp[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 682 struct napi_struct *napi; 683 struct ath12k_wmi_target_cap_arg target_caps; 684 u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE]; 685 bool pdevs_macaddr_valid; 686 int bd_api; 687 688 const struct ath12k_hw_params *hw_params; 689 690 const struct firmware *cal_file; 691 692 /* Below regd's are protected by ab->data_lock */ 693 /* This is the regd set for every radio 694 * by the firmware during initialization 695 */ 696 struct ieee80211_regdomain *default_regd[MAX_RADIOS]; 697 /* This regd is set during dynamic country setting 698 * This may or may not be used during the runtime 699 */ 700 struct ieee80211_regdomain *new_regd[MAX_RADIOS]; 701 702 /* Current DFS Regulatory */ 703 enum ath12k_dfs_region dfs_region; 704 struct ath12k_soc_dp_stats soc_stats; 705 706 unsigned long dev_flags; 707 struct completion driver_recovery; 708 struct workqueue_struct *workqueue; 709 struct work_struct restart_work; 710 struct workqueue_struct *workqueue_aux; 711 struct work_struct reset_work; 712 atomic_t reset_count; 713 atomic_t recovery_count; 714 atomic_t recovery_start_count; 715 bool is_reset; 716 struct completion reset_complete; 717 struct completion reconfigure_complete; 718 struct completion recovery_start; 719 /* continuous recovery fail count */ 720 atomic_t fail_cont_count; 721 unsigned long reset_fail_timeout; 722 struct { 723 /* protected by data_lock */ 724 u32 fw_crash_counter; 725 } stats; 726 u32 pktlog_defs_checksum; 727 728 struct ath12k_dbring_cap *db_caps; 729 u32 num_db_cap; 730 731 struct timer_list mon_reap_timer; 732 733 struct completion htc_suspend; 734 735 u64 fw_soc_drop_count; 736 bool static_window_map; 737 738 /* must be last */ 739 u8 drv_priv[] __aligned(sizeof(void *)); 740 }; 741 742 int ath12k_core_qmi_firmware_ready(struct ath12k_base *ab); 743 int ath12k_core_pre_init(struct ath12k_base *ab); 744 int ath12k_core_init(struct ath12k_base *ath12k); 745 void ath12k_core_deinit(struct ath12k_base *ath12k); 746 struct ath12k_base *ath12k_core_alloc(struct device *dev, size_t priv_size, 747 enum ath12k_bus bus); 748 void ath12k_core_free(struct ath12k_base *ath12k); 749 int ath12k_core_fetch_board_data_api_1(struct ath12k_base *ab, 750 struct ath12k_board_data *bd, 751 char *filename); 752 int ath12k_core_fetch_bdf(struct ath12k_base *ath12k, 753 struct ath12k_board_data *bd); 754 void ath12k_core_free_bdf(struct ath12k_base *ab, struct ath12k_board_data *bd); 755 int ath12k_core_check_dt(struct ath12k_base *ath12k); 756 757 void ath12k_core_halt(struct ath12k *ar); 758 int ath12k_core_resume(struct ath12k_base *ab); 759 int ath12k_core_suspend(struct ath12k_base *ab); 760 761 const struct firmware *ath12k_core_firmware_request(struct ath12k_base *ab, 762 const char *filename); 763 764 static inline const char *ath12k_scan_state_str(enum ath12k_scan_state state) 765 { 766 switch (state) { 767 case ATH12K_SCAN_IDLE: 768 return "idle"; 769 case ATH12K_SCAN_STARTING: 770 return "starting"; 771 case ATH12K_SCAN_RUNNING: 772 return "running"; 773 case ATH12K_SCAN_ABORTING: 774 return "aborting"; 775 } 776 777 return "unknown"; 778 } 779 780 static inline struct ath12k_skb_cb *ATH12K_SKB_CB(struct sk_buff *skb) 781 { 782 BUILD_BUG_ON(sizeof(struct ath12k_skb_cb) > 783 IEEE80211_TX_INFO_DRIVER_DATA_SIZE); 784 return (struct ath12k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data; 785 } 786 787 static inline struct ath12k_skb_rxcb *ATH12K_SKB_RXCB(struct sk_buff *skb) 788 { 789 BUILD_BUG_ON(sizeof(struct ath12k_skb_rxcb) > sizeof(skb->cb)); 790 return (struct ath12k_skb_rxcb *)skb->cb; 791 } 792 793 static inline struct ath12k_vif *ath12k_vif_to_arvif(struct ieee80211_vif *vif) 794 { 795 return (struct ath12k_vif *)vif->drv_priv; 796 } 797 798 static inline struct ath12k *ath12k_ab_to_ar(struct ath12k_base *ab, 799 int mac_id) 800 { 801 return ab->pdevs[ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id)].ar; 802 } 803 804 static inline void ath12k_core_create_firmware_path(struct ath12k_base *ab, 805 const char *filename, 806 void *buf, size_t buf_len) 807 { 808 snprintf(buf, buf_len, "%s/%s/%s", ATH12K_FW_DIR, 809 ab->hw_params->fw.dir, filename); 810 } 811 812 static inline const char *ath12k_bus_str(enum ath12k_bus bus) 813 { 814 switch (bus) { 815 case ATH12K_BUS_PCI: 816 return "pci"; 817 } 818 819 return "unknown"; 820 } 821 822 #endif /* _CORE_H_ */ 823