1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #ifndef ATH11K_WMI_H 8 #define ATH11K_WMI_H 9 10 #include <net/mac80211.h> 11 #include "htc.h" 12 13 struct ath11k_base; 14 struct ath11k; 15 struct ath11k_fw_stats; 16 struct ath11k_fw_dbglog; 17 struct ath11k_vif; 18 19 #define PSOC_HOST_MAX_NUM_SS (8) 20 21 /* defines to set Packet extension values which can be 0 us, 8 usec or 16 usec */ 22 #define MAX_HE_NSS 8 23 #define MAX_HE_MODULATION 8 24 #define MAX_HE_RU 4 25 #define HE_MODULATION_NONE 7 26 #define HE_PET_0_USEC 0 27 #define HE_PET_8_USEC 1 28 #define HE_PET_16_USEC 2 29 30 #define WMI_MAX_CHAINS 8 31 32 #define WMI_MAX_NUM_SS MAX_HE_NSS 33 #define WMI_MAX_NUM_RU MAX_HE_RU 34 35 #define WMI_TLV_CMD(grp_id) (((grp_id) << 12) | 0x1) 36 #define WMI_TLV_EV(grp_id) (((grp_id) << 12) | 0x1) 37 #define WMI_TLV_CMD_UNSUPPORTED 0 38 #define WMI_TLV_PDEV_PARAM_UNSUPPORTED 0 39 #define WMI_TLV_VDEV_PARAM_UNSUPPORTED 0 40 41 struct wmi_cmd_hdr { 42 u32 cmd_id; 43 } __packed; 44 45 struct wmi_tlv { 46 u32 header; 47 u8 value[]; 48 } __packed; 49 50 #define WMI_TLV_LEN GENMASK(15, 0) 51 #define WMI_TLV_TAG GENMASK(31, 16) 52 #define TLV_HDR_SIZE sizeof_field(struct wmi_tlv, header) 53 54 #define WMI_CMD_HDR_CMD_ID GENMASK(23, 0) 55 #define WMI_MAX_MEM_REQS 32 56 #define ATH11K_MAX_HW_LISTEN_INTERVAL 5 57 58 #define WLAN_SCAN_MAX_HINT_S_SSID 10 59 #define WLAN_SCAN_MAX_HINT_BSSID 10 60 #define MAX_RNR_BSS 5 61 62 #define WLAN_SCAN_MAX_HINT_S_SSID 10 63 #define WLAN_SCAN_MAX_HINT_BSSID 10 64 #define MAX_RNR_BSS 5 65 66 #define WLAN_SCAN_PARAMS_MAX_SSID 16 67 #define WLAN_SCAN_PARAMS_MAX_BSSID 4 68 #define WLAN_SCAN_PARAMS_MAX_IE_LEN 256 69 70 #define WMI_APPEND_TO_EXISTING_CHAN_LIST_FLAG 1 71 72 #define MAX_WMI_UTF_LEN 252 73 #define WMI_BA_MODE_BUFFER_SIZE_256 3 74 /* 75 * HW mode config type replicated from FW header 76 * @WMI_HOST_HW_MODE_SINGLE: Only one PHY is active. 77 * @WMI_HOST_HW_MODE_DBS: Both PHYs are active in different bands, 78 * one in 2G and another in 5G. 79 * @WMI_HOST_HW_MODE_SBS_PASSIVE: Both PHYs are in passive mode (only rx) in 80 * same band; no tx allowed. 81 * @WMI_HOST_HW_MODE_SBS: Both PHYs are active in the same band. 82 * Support for both PHYs within one band is planned 83 * for 5G only(as indicated in WMI_MAC_PHY_CAPABILITIES), 84 * but could be extended to other bands in the future. 85 * The separation of the band between the two PHYs needs 86 * to be communicated separately. 87 * @WMI_HOST_HW_MODE_DBS_SBS: 3 PHYs, with 2 on the same band doing SBS 88 * as in WMI_HW_MODE_SBS, and 3rd on the other band 89 * @WMI_HOST_HW_MODE_DBS_OR_SBS: Two PHY with one PHY capabale of both 2G and 90 * 5G. It can support SBS (5G + 5G) OR DBS (5G + 2G). 91 * @WMI_HOST_HW_MODE_MAX: Max hw_mode_id. Used to indicate invalid mode. 92 */ 93 enum wmi_host_hw_mode_config_type { 94 WMI_HOST_HW_MODE_SINGLE = 0, 95 WMI_HOST_HW_MODE_DBS = 1, 96 WMI_HOST_HW_MODE_SBS_PASSIVE = 2, 97 WMI_HOST_HW_MODE_SBS = 3, 98 WMI_HOST_HW_MODE_DBS_SBS = 4, 99 WMI_HOST_HW_MODE_DBS_OR_SBS = 5, 100 101 /* keep last */ 102 WMI_HOST_HW_MODE_MAX 103 }; 104 105 /* HW mode priority values used to detect the preferred HW mode 106 * on the available modes. 107 */ 108 enum wmi_host_hw_mode_priority { 109 WMI_HOST_HW_MODE_DBS_SBS_PRI, 110 WMI_HOST_HW_MODE_DBS_PRI, 111 WMI_HOST_HW_MODE_DBS_OR_SBS_PRI, 112 WMI_HOST_HW_MODE_SBS_PRI, 113 WMI_HOST_HW_MODE_SBS_PASSIVE_PRI, 114 WMI_HOST_HW_MODE_SINGLE_PRI, 115 116 /* keep last the lowest priority */ 117 WMI_HOST_HW_MODE_MAX_PRI 118 }; 119 120 enum WMI_HOST_WLAN_BAND { 121 WMI_HOST_WLAN_2G_CAP = 0x1, 122 WMI_HOST_WLAN_5G_CAP = 0x2, 123 WMI_HOST_WLAN_2G_5G_CAP = WMI_HOST_WLAN_2G_CAP | WMI_HOST_WLAN_5G_CAP, 124 }; 125 126 /* Parameters used for WMI_VDEV_PARAM_AUTORATE_MISC_CFG command. 127 * Used only for HE auto rate mode. 128 */ 129 enum { 130 /* HE LTF related configuration */ 131 WMI_HE_AUTORATE_LTF_1X = BIT(0), 132 WMI_HE_AUTORATE_LTF_2X = BIT(1), 133 WMI_HE_AUTORATE_LTF_4X = BIT(2), 134 135 /* HE GI related configuration */ 136 WMI_AUTORATE_400NS_GI = BIT(8), 137 WMI_AUTORATE_800NS_GI = BIT(9), 138 WMI_AUTORATE_1600NS_GI = BIT(10), 139 WMI_AUTORATE_3200NS_GI = BIT(11), 140 }; 141 142 enum { 143 WMI_HOST_VDEV_FLAGS_NON_MBSSID_AP = 0x00000001, 144 WMI_HOST_VDEV_FLAGS_TRANSMIT_AP = 0x00000002, 145 WMI_HOST_VDEV_FLAGS_NON_TRANSMIT_AP = 0x00000004, 146 WMI_HOST_VDEV_FLAGS_EMA_MODE = 0x00000008, 147 WMI_HOST_VDEV_FLAGS_SCAN_MODE_VAP = 0x00000010, 148 }; 149 150 /* 151 * wmi command groups. 152 */ 153 enum wmi_cmd_group { 154 /* 0 to 2 are reserved */ 155 WMI_GRP_START = 0x3, 156 WMI_GRP_SCAN = WMI_GRP_START, 157 WMI_GRP_PDEV = 0x4, 158 WMI_GRP_VDEV = 0x5, 159 WMI_GRP_PEER = 0x6, 160 WMI_GRP_MGMT = 0x7, 161 WMI_GRP_BA_NEG = 0x8, 162 WMI_GRP_STA_PS = 0x9, 163 WMI_GRP_DFS = 0xa, 164 WMI_GRP_ROAM = 0xb, 165 WMI_GRP_OFL_SCAN = 0xc, 166 WMI_GRP_P2P = 0xd, 167 WMI_GRP_AP_PS = 0xe, 168 WMI_GRP_RATE_CTRL = 0xf, 169 WMI_GRP_PROFILE = 0x10, 170 WMI_GRP_SUSPEND = 0x11, 171 WMI_GRP_BCN_FILTER = 0x12, 172 WMI_GRP_WOW = 0x13, 173 WMI_GRP_RTT = 0x14, 174 WMI_GRP_SPECTRAL = 0x15, 175 WMI_GRP_STATS = 0x16, 176 WMI_GRP_ARP_NS_OFL = 0x17, 177 WMI_GRP_NLO_OFL = 0x18, 178 WMI_GRP_GTK_OFL = 0x19, 179 WMI_GRP_CSA_OFL = 0x1a, 180 WMI_GRP_CHATTER = 0x1b, 181 WMI_GRP_TID_ADDBA = 0x1c, 182 WMI_GRP_MISC = 0x1d, 183 WMI_GRP_GPIO = 0x1e, 184 WMI_GRP_FWTEST = 0x1f, 185 WMI_GRP_TDLS = 0x20, 186 WMI_GRP_RESMGR = 0x21, 187 WMI_GRP_STA_SMPS = 0x22, 188 WMI_GRP_WLAN_HB = 0x23, 189 WMI_GRP_RMC = 0x24, 190 WMI_GRP_MHF_OFL = 0x25, 191 WMI_GRP_LOCATION_SCAN = 0x26, 192 WMI_GRP_OEM = 0x27, 193 WMI_GRP_NAN = 0x28, 194 WMI_GRP_COEX = 0x29, 195 WMI_GRP_OBSS_OFL = 0x2a, 196 WMI_GRP_LPI = 0x2b, 197 WMI_GRP_EXTSCAN = 0x2c, 198 WMI_GRP_DHCP_OFL = 0x2d, 199 WMI_GRP_IPA = 0x2e, 200 WMI_GRP_MDNS_OFL = 0x2f, 201 WMI_GRP_SAP_OFL = 0x30, 202 WMI_GRP_OCB = 0x31, 203 WMI_GRP_SOC = 0x32, 204 WMI_GRP_PKT_FILTER = 0x33, 205 WMI_GRP_MAWC = 0x34, 206 WMI_GRP_PMF_OFFLOAD = 0x35, 207 WMI_GRP_BPF_OFFLOAD = 0x36, 208 WMI_GRP_NAN_DATA = 0x37, 209 WMI_GRP_PROTOTYPE = 0x38, 210 WMI_GRP_MONITOR = 0x39, 211 WMI_GRP_REGULATORY = 0x3a, 212 WMI_GRP_HW_DATA_FILTER = 0x3b, 213 WMI_GRP_WLM = 0x3c, 214 WMI_GRP_11K_OFFLOAD = 0x3d, 215 WMI_GRP_TWT = 0x3e, 216 WMI_GRP_MOTION_DET = 0x3f, 217 WMI_GRP_SPATIAL_REUSE = 0x40, 218 }; 219 220 #define WMI_CMD_GRP(grp_id) (((grp_id) << 12) | 0x1) 221 #define WMI_EVT_GRP_START_ID(grp_id) (((grp_id) << 12) | 0x1) 222 223 #define WMI_CMD_UNSUPPORTED 0 224 225 enum wmi_tlv_cmd_id { 226 WMI_INIT_CMDID = 0x1, 227 WMI_START_SCAN_CMDID = WMI_TLV_CMD(WMI_GRP_SCAN), 228 WMI_STOP_SCAN_CMDID, 229 WMI_SCAN_CHAN_LIST_CMDID, 230 WMI_SCAN_SCH_PRIO_TBL_CMDID, 231 WMI_SCAN_UPDATE_REQUEST_CMDID, 232 WMI_SCAN_PROB_REQ_OUI_CMDID, 233 WMI_SCAN_ADAPTIVE_DWELL_CONFIG_CMDID, 234 WMI_PDEV_SET_REGDOMAIN_CMDID = WMI_TLV_CMD(WMI_GRP_PDEV), 235 WMI_PDEV_SET_CHANNEL_CMDID, 236 WMI_PDEV_SET_PARAM_CMDID, 237 WMI_PDEV_PKTLOG_ENABLE_CMDID, 238 WMI_PDEV_PKTLOG_DISABLE_CMDID, 239 WMI_PDEV_SET_WMM_PARAMS_CMDID, 240 WMI_PDEV_SET_HT_CAP_IE_CMDID, 241 WMI_PDEV_SET_VHT_CAP_IE_CMDID, 242 WMI_PDEV_SET_DSCP_TID_MAP_CMDID, 243 WMI_PDEV_SET_QUIET_MODE_CMDID, 244 WMI_PDEV_GREEN_AP_PS_ENABLE_CMDID, 245 WMI_PDEV_GET_TPC_CONFIG_CMDID, 246 WMI_PDEV_SET_BASE_MACADDR_CMDID, 247 WMI_PDEV_DUMP_CMDID, 248 WMI_PDEV_SET_LED_CONFIG_CMDID, 249 WMI_PDEV_GET_TEMPERATURE_CMDID, 250 WMI_PDEV_SET_LED_FLASHING_CMDID, 251 WMI_PDEV_SMART_ANT_ENABLE_CMDID, 252 WMI_PDEV_SMART_ANT_SET_RX_ANTENNA_CMDID, 253 WMI_PDEV_SET_ANTENNA_SWITCH_TABLE_CMDID, 254 WMI_PDEV_SET_CTL_TABLE_CMDID, 255 WMI_PDEV_SET_MIMOGAIN_TABLE_CMDID, 256 WMI_PDEV_FIPS_CMDID, 257 WMI_PDEV_GET_ANI_CCK_CONFIG_CMDID, 258 WMI_PDEV_GET_ANI_OFDM_CONFIG_CMDID, 259 WMI_PDEV_GET_NFCAL_POWER_CMDID, 260 WMI_PDEV_GET_TPC_CMDID, 261 WMI_MIB_STATS_ENABLE_CMDID, 262 WMI_PDEV_SET_PCL_CMDID, 263 WMI_PDEV_SET_HW_MODE_CMDID, 264 WMI_PDEV_SET_MAC_CONFIG_CMDID, 265 WMI_PDEV_SET_ANTENNA_MODE_CMDID, 266 WMI_SET_PERIODIC_CHANNEL_STATS_CONFIG_CMDID, 267 WMI_PDEV_WAL_POWER_DEBUG_CMDID, 268 WMI_PDEV_SET_REORDER_TIMEOUT_VAL_CMDID, 269 WMI_PDEV_SET_WAKEUP_CONFIG_CMDID, 270 WMI_PDEV_GET_ANTDIV_STATUS_CMDID, 271 WMI_PDEV_GET_CHIP_POWER_STATS_CMDID, 272 WMI_PDEV_SET_STATS_THRESHOLD_CMDID, 273 WMI_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMDID, 274 WMI_PDEV_UPDATE_PKT_ROUTING_CMDID, 275 WMI_PDEV_CHECK_CAL_VERSION_CMDID, 276 WMI_PDEV_SET_DIVERSITY_GAIN_CMDID, 277 WMI_PDEV_DIV_GET_RSSI_ANTID_CMDID, 278 WMI_PDEV_BSS_CHAN_INFO_REQUEST_CMDID, 279 WMI_PDEV_UPDATE_PMK_CACHE_CMDID, 280 WMI_PDEV_UPDATE_FILS_HLP_PKT_CMDID, 281 WMI_PDEV_UPDATE_CTLTABLE_REQUEST_CMDID, 282 WMI_PDEV_CONFIG_VENDOR_OUI_ACTION_CMDID, 283 WMI_PDEV_SET_AC_TX_QUEUE_OPTIMIZED_CMDID, 284 WMI_PDEV_SET_RX_FILTER_PROMISCUOUS_CMDID, 285 WMI_PDEV_DMA_RING_CFG_REQ_CMDID, 286 WMI_PDEV_HE_TB_ACTION_FRM_CMDID, 287 WMI_PDEV_PKTLOG_FILTER_CMDID, 288 WMI_PDEV_SET_RAP_CONFIG_CMDID, 289 WMI_PDEV_DSM_FILTER_CMDID, 290 WMI_PDEV_FRAME_INJECT_CMDID, 291 WMI_PDEV_TBTT_OFFSET_SYNC_CMDID, 292 WMI_PDEV_SET_SRG_BSS_COLOR_BITMAP_CMDID, 293 WMI_PDEV_SET_SRG_PARTIAL_BSSID_BITMAP_CMDID, 294 WMI_PDEV_SET_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID, 295 WMI_PDEV_SET_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID, 296 WMI_PDEV_SET_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID, 297 WMI_PDEV_SET_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID, 298 WMI_PDEV_GET_TPC_STATS_CMDID, 299 WMI_PDEV_ENABLE_DURATION_BASED_TX_MODE_SELECTION_CMDID, 300 WMI_PDEV_GET_DPD_STATUS_CMDID, 301 WMI_PDEV_SET_BIOS_SAR_TABLE_CMDID, 302 WMI_PDEV_SET_BIOS_GEO_TABLE_CMDID, 303 WMI_VDEV_CREATE_CMDID = WMI_TLV_CMD(WMI_GRP_VDEV), 304 WMI_VDEV_DELETE_CMDID, 305 WMI_VDEV_START_REQUEST_CMDID, 306 WMI_VDEV_RESTART_REQUEST_CMDID, 307 WMI_VDEV_UP_CMDID, 308 WMI_VDEV_STOP_CMDID, 309 WMI_VDEV_DOWN_CMDID, 310 WMI_VDEV_SET_PARAM_CMDID, 311 WMI_VDEV_INSTALL_KEY_CMDID, 312 WMI_VDEV_WNM_SLEEPMODE_CMDID, 313 WMI_VDEV_WMM_ADDTS_CMDID, 314 WMI_VDEV_WMM_DELTS_CMDID, 315 WMI_VDEV_SET_WMM_PARAMS_CMDID, 316 WMI_VDEV_SET_GTX_PARAMS_CMDID, 317 WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMDID, 318 WMI_VDEV_PLMREQ_START_CMDID, 319 WMI_VDEV_PLMREQ_STOP_CMDID, 320 WMI_VDEV_TSF_TSTAMP_ACTION_CMDID, 321 WMI_VDEV_SET_IE_CMDID, 322 WMI_VDEV_RATEMASK_CMDID, 323 WMI_VDEV_ATF_REQUEST_CMDID, 324 WMI_VDEV_SET_DSCP_TID_MAP_CMDID, 325 WMI_VDEV_FILTER_NEIGHBOR_RX_PACKETS_CMDID, 326 WMI_VDEV_SET_QUIET_MODE_CMDID, 327 WMI_VDEV_SET_CUSTOM_AGGR_SIZE_CMDID, 328 WMI_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMDID, 329 WMI_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_CMDID, 330 WMI_PEER_CREATE_CMDID = WMI_TLV_CMD(WMI_GRP_PEER), 331 WMI_PEER_DELETE_CMDID, 332 WMI_PEER_FLUSH_TIDS_CMDID, 333 WMI_PEER_SET_PARAM_CMDID, 334 WMI_PEER_ASSOC_CMDID, 335 WMI_PEER_ADD_WDS_ENTRY_CMDID, 336 WMI_PEER_REMOVE_WDS_ENTRY_CMDID, 337 WMI_PEER_MCAST_GROUP_CMDID, 338 WMI_PEER_INFO_REQ_CMDID, 339 WMI_PEER_GET_ESTIMATED_LINKSPEED_CMDID, 340 WMI_PEER_SET_RATE_REPORT_CONDITION_CMDID, 341 WMI_PEER_UPDATE_WDS_ENTRY_CMDID, 342 WMI_PEER_ADD_PROXY_STA_ENTRY_CMDID, 343 WMI_PEER_SMART_ANT_SET_TX_ANTENNA_CMDID, 344 WMI_PEER_SMART_ANT_SET_TRAIN_INFO_CMDID, 345 WMI_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMDID, 346 WMI_PEER_ATF_REQUEST_CMDID, 347 WMI_PEER_BWF_REQUEST_CMDID, 348 WMI_PEER_REORDER_QUEUE_SETUP_CMDID, 349 WMI_PEER_REORDER_QUEUE_REMOVE_CMDID, 350 WMI_PEER_SET_RX_BLOCKSIZE_CMDID, 351 WMI_PEER_ANTDIV_INFO_REQ_CMDID, 352 WMI_BCN_TX_CMDID = WMI_TLV_CMD(WMI_GRP_MGMT), 353 WMI_PDEV_SEND_BCN_CMDID, 354 WMI_BCN_TMPL_CMDID, 355 WMI_BCN_FILTER_RX_CMDID, 356 WMI_PRB_REQ_FILTER_RX_CMDID, 357 WMI_MGMT_TX_CMDID, 358 WMI_PRB_TMPL_CMDID, 359 WMI_MGMT_TX_SEND_CMDID, 360 WMI_OFFCHAN_DATA_TX_SEND_CMDID, 361 WMI_PDEV_SEND_FD_CMDID, 362 WMI_BCN_OFFLOAD_CTRL_CMDID, 363 WMI_BSS_COLOR_CHANGE_ENABLE_CMDID, 364 WMI_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMDID, 365 WMI_FILS_DISCOVERY_TMPL_CMDID, 366 WMI_ADDBA_CLEAR_RESP_CMDID = WMI_TLV_CMD(WMI_GRP_BA_NEG), 367 WMI_ADDBA_SEND_CMDID, 368 WMI_ADDBA_STATUS_CMDID, 369 WMI_DELBA_SEND_CMDID, 370 WMI_ADDBA_SET_RESP_CMDID, 371 WMI_SEND_SINGLEAMSDU_CMDID, 372 WMI_STA_POWERSAVE_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_STA_PS), 373 WMI_STA_POWERSAVE_PARAM_CMDID, 374 WMI_STA_MIMO_PS_MODE_CMDID, 375 WMI_PDEV_DFS_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_DFS), 376 WMI_PDEV_DFS_DISABLE_CMDID, 377 WMI_DFS_PHYERR_FILTER_ENA_CMDID, 378 WMI_DFS_PHYERR_FILTER_DIS_CMDID, 379 WMI_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMDID, 380 WMI_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMDID, 381 WMI_VDEV_ADFS_CH_CFG_CMDID, 382 WMI_VDEV_ADFS_OCAC_ABORT_CMDID, 383 WMI_ROAM_SCAN_MODE = WMI_TLV_CMD(WMI_GRP_ROAM), 384 WMI_ROAM_SCAN_RSSI_THRESHOLD, 385 WMI_ROAM_SCAN_PERIOD, 386 WMI_ROAM_SCAN_RSSI_CHANGE_THRESHOLD, 387 WMI_ROAM_AP_PROFILE, 388 WMI_ROAM_CHAN_LIST, 389 WMI_ROAM_SCAN_CMD, 390 WMI_ROAM_SYNCH_COMPLETE, 391 WMI_ROAM_SET_RIC_REQUEST_CMDID, 392 WMI_ROAM_INVOKE_CMDID, 393 WMI_ROAM_FILTER_CMDID, 394 WMI_ROAM_SUBNET_CHANGE_CONFIG_CMDID, 395 WMI_ROAM_CONFIGURE_MAWC_CMDID, 396 WMI_ROAM_SET_MBO_PARAM_CMDID, 397 WMI_ROAM_PER_CONFIG_CMDID, 398 WMI_ROAM_BTM_CONFIG_CMDID, 399 WMI_ENABLE_FILS_CMDID, 400 WMI_OFL_SCAN_ADD_AP_PROFILE = WMI_TLV_CMD(WMI_GRP_OFL_SCAN), 401 WMI_OFL_SCAN_REMOVE_AP_PROFILE, 402 WMI_OFL_SCAN_PERIOD, 403 WMI_P2P_DEV_SET_DEVICE_INFO = WMI_TLV_CMD(WMI_GRP_P2P), 404 WMI_P2P_DEV_SET_DISCOVERABILITY, 405 WMI_P2P_GO_SET_BEACON_IE, 406 WMI_P2P_GO_SET_PROBE_RESP_IE, 407 WMI_P2P_SET_VENDOR_IE_DATA_CMDID, 408 WMI_P2P_DISC_OFFLOAD_CONFIG_CMDID, 409 WMI_P2P_DISC_OFFLOAD_APPIE_CMDID, 410 WMI_P2P_DISC_OFFLOAD_PATTERN_CMDID, 411 WMI_P2P_SET_OPPPS_PARAM_CMDID, 412 WMI_P2P_LISTEN_OFFLOAD_START_CMDID, 413 WMI_P2P_LISTEN_OFFLOAD_STOP_CMDID, 414 WMI_AP_PS_PEER_PARAM_CMDID = WMI_TLV_CMD(WMI_GRP_AP_PS), 415 WMI_AP_PS_PEER_UAPSD_COEX_CMDID, 416 WMI_AP_PS_EGAP_PARAM_CMDID, 417 WMI_PEER_RATE_RETRY_SCHED_CMDID = WMI_TLV_CMD(WMI_GRP_RATE_CTRL), 418 WMI_WLAN_PROFILE_TRIGGER_CMDID = WMI_TLV_CMD(WMI_GRP_PROFILE), 419 WMI_WLAN_PROFILE_SET_HIST_INTVL_CMDID, 420 WMI_WLAN_PROFILE_GET_PROFILE_DATA_CMDID, 421 WMI_WLAN_PROFILE_ENABLE_PROFILE_ID_CMDID, 422 WMI_WLAN_PROFILE_LIST_PROFILE_ID_CMDID, 423 WMI_PDEV_SUSPEND_CMDID = WMI_TLV_CMD(WMI_GRP_SUSPEND), 424 WMI_PDEV_RESUME_CMDID, 425 WMI_ADD_BCN_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_BCN_FILTER), 426 WMI_RMV_BCN_FILTER_CMDID, 427 WMI_WOW_ADD_WAKE_PATTERN_CMDID = WMI_TLV_CMD(WMI_GRP_WOW), 428 WMI_WOW_DEL_WAKE_PATTERN_CMDID, 429 WMI_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID, 430 WMI_WOW_ENABLE_CMDID, 431 WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID, 432 WMI_WOW_IOAC_ADD_KEEPALIVE_CMDID, 433 WMI_WOW_IOAC_DEL_KEEPALIVE_CMDID, 434 WMI_WOW_IOAC_ADD_WAKE_PATTERN_CMDID, 435 WMI_WOW_IOAC_DEL_WAKE_PATTERN_CMDID, 436 WMI_D0_WOW_ENABLE_DISABLE_CMDID, 437 WMI_EXTWOW_ENABLE_CMDID, 438 WMI_EXTWOW_SET_APP_TYPE1_PARAMS_CMDID, 439 WMI_EXTWOW_SET_APP_TYPE2_PARAMS_CMDID, 440 WMI_WOW_ENABLE_ICMPV6_NA_FLT_CMDID, 441 WMI_WOW_UDP_SVC_OFLD_CMDID, 442 WMI_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMDID, 443 WMI_WOW_SET_ACTION_WAKE_UP_CMDID, 444 WMI_RTT_MEASREQ_CMDID = WMI_TLV_CMD(WMI_GRP_RTT), 445 WMI_RTT_TSF_CMDID, 446 WMI_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID = WMI_TLV_CMD(WMI_GRP_SPECTRAL), 447 WMI_VDEV_SPECTRAL_SCAN_ENABLE_CMDID, 448 WMI_REQUEST_STATS_CMDID = WMI_TLV_CMD(WMI_GRP_STATS), 449 WMI_MCC_SCHED_TRAFFIC_STATS_CMDID, 450 WMI_REQUEST_STATS_EXT_CMDID, 451 WMI_REQUEST_LINK_STATS_CMDID, 452 WMI_START_LINK_STATS_CMDID, 453 WMI_CLEAR_LINK_STATS_CMDID, 454 WMI_GET_FW_MEM_DUMP_CMDID, 455 WMI_DEBUG_MESG_FLUSH_CMDID, 456 WMI_DIAG_EVENT_LOG_CONFIG_CMDID, 457 WMI_REQUEST_WLAN_STATS_CMDID, 458 WMI_REQUEST_RCPI_CMDID, 459 WMI_REQUEST_PEER_STATS_INFO_CMDID, 460 WMI_REQUEST_RADIO_CHAN_STATS_CMDID, 461 WMI_SET_ARP_NS_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_ARP_NS_OFL), 462 WMI_ADD_PROACTIVE_ARP_RSP_PATTERN_CMDID, 463 WMI_DEL_PROACTIVE_ARP_RSP_PATTERN_CMDID, 464 WMI_NETWORK_LIST_OFFLOAD_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_NLO_OFL), 465 WMI_APFIND_CMDID, 466 WMI_PASSPOINT_LIST_CONFIG_CMDID, 467 WMI_NLO_CONFIGURE_MAWC_CMDID, 468 WMI_GTK_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_GTK_OFL), 469 WMI_CSA_OFFLOAD_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_CSA_OFL), 470 WMI_CSA_OFFLOAD_CHANSWITCH_CMDID, 471 WMI_CHATTER_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_CHATTER), 472 WMI_CHATTER_ADD_COALESCING_FILTER_CMDID, 473 WMI_CHATTER_DELETE_COALESCING_FILTER_CMDID, 474 WMI_CHATTER_COALESCING_QUERY_CMDID, 475 WMI_PEER_TID_ADDBA_CMDID = WMI_TLV_CMD(WMI_GRP_TID_ADDBA), 476 WMI_PEER_TID_DELBA_CMDID, 477 WMI_STA_DTIM_PS_METHOD_CMDID, 478 WMI_STA_UAPSD_AUTO_TRIG_CMDID, 479 WMI_STA_KEEPALIVE_CMDID, 480 WMI_BA_REQ_SSN_CMDID, 481 WMI_ECHO_CMDID = WMI_TLV_CMD(WMI_GRP_MISC), 482 WMI_PDEV_UTF_CMDID, 483 WMI_DBGLOG_CFG_CMDID, 484 WMI_PDEV_QVIT_CMDID, 485 WMI_PDEV_FTM_INTG_CMDID, 486 WMI_VDEV_SET_KEEPALIVE_CMDID, 487 WMI_VDEV_GET_KEEPALIVE_CMDID, 488 WMI_FORCE_FW_HANG_CMDID, 489 WMI_SET_MCASTBCAST_FILTER_CMDID, 490 WMI_THERMAL_MGMT_CMDID, 491 WMI_HOST_AUTO_SHUTDOWN_CFG_CMDID, 492 WMI_TPC_CHAINMASK_CONFIG_CMDID, 493 WMI_SET_ANTENNA_DIVERSITY_CMDID, 494 WMI_OCB_SET_SCHED_CMDID, 495 WMI_RSSI_BREACH_MONITOR_CONFIG_CMDID, 496 WMI_LRO_CONFIG_CMDID, 497 WMI_TRANSFER_DATA_TO_FLASH_CMDID, 498 WMI_CONFIG_ENHANCED_MCAST_FILTER_CMDID, 499 WMI_VDEV_WISA_CMDID, 500 WMI_DBGLOG_TIME_STAMP_SYNC_CMDID, 501 WMI_SET_MULTIPLE_MCAST_FILTER_CMDID, 502 WMI_READ_DATA_FROM_FLASH_CMDID, 503 WMI_THERM_THROT_SET_CONF_CMDID, 504 WMI_RUNTIME_DPD_RECAL_CMDID, 505 WMI_GET_TPC_POWER_CMDID, 506 WMI_IDLE_TRIGGER_MONITOR_CMDID, 507 WMI_GPIO_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_GPIO), 508 WMI_GPIO_OUTPUT_CMDID, 509 WMI_TXBF_CMDID, 510 WMI_FWTEST_VDEV_MCC_SET_TBTT_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_FWTEST), 511 WMI_FWTEST_P2P_SET_NOA_PARAM_CMDID, 512 WMI_UNIT_TEST_CMDID, 513 WMI_FWTEST_CMDID, 514 WMI_QBOOST_CFG_CMDID, 515 WMI_TDLS_SET_STATE_CMDID = WMI_TLV_CMD(WMI_GRP_TDLS), 516 WMI_TDLS_PEER_UPDATE_CMDID, 517 WMI_TDLS_SET_OFFCHAN_MODE_CMDID, 518 WMI_RESMGR_ADAPTIVE_OCS_EN_DIS_CMDID = WMI_TLV_CMD(WMI_GRP_RESMGR), 519 WMI_RESMGR_SET_CHAN_TIME_QUOTA_CMDID, 520 WMI_RESMGR_SET_CHAN_LATENCY_CMDID, 521 WMI_STA_SMPS_FORCE_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_STA_SMPS), 522 WMI_STA_SMPS_PARAM_CMDID, 523 WMI_HB_SET_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_WLAN_HB), 524 WMI_HB_SET_TCP_PARAMS_CMDID, 525 WMI_HB_SET_TCP_PKT_FILTER_CMDID, 526 WMI_HB_SET_UDP_PARAMS_CMDID, 527 WMI_HB_SET_UDP_PKT_FILTER_CMDID, 528 WMI_RMC_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_RMC), 529 WMI_RMC_SET_ACTION_PERIOD_CMDID, 530 WMI_RMC_CONFIG_CMDID, 531 WMI_RMC_SET_MANUAL_LEADER_CMDID, 532 WMI_MHF_OFFLOAD_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_MHF_OFL), 533 WMI_MHF_OFFLOAD_PLUMB_ROUTING_TBL_CMDID, 534 WMI_BATCH_SCAN_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_LOCATION_SCAN), 535 WMI_BATCH_SCAN_DISABLE_CMDID, 536 WMI_BATCH_SCAN_TRIGGER_RESULT_CMDID, 537 WMI_OEM_REQ_CMDID = WMI_TLV_CMD(WMI_GRP_OEM), 538 WMI_OEM_REQUEST_CMDID, 539 WMI_LPI_OEM_REQ_CMDID, 540 WMI_NAN_CMDID = WMI_TLV_CMD(WMI_GRP_NAN), 541 WMI_MODEM_POWER_STATE_CMDID = WMI_TLV_CMD(WMI_GRP_COEX), 542 WMI_CHAN_AVOID_UPDATE_CMDID, 543 WMI_COEX_CONFIG_CMDID, 544 WMI_CHAN_AVOID_RPT_ALLOW_CMDID, 545 WMI_COEX_GET_ANTENNA_ISOLATION_CMDID, 546 WMI_SAR_LIMITS_CMDID, 547 WMI_OBSS_SCAN_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_OBSS_OFL), 548 WMI_OBSS_SCAN_DISABLE_CMDID, 549 WMI_OBSS_COLOR_COLLISION_DET_CONFIG_CMDID, 550 WMI_LPI_MGMT_SNOOPING_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_LPI), 551 WMI_LPI_START_SCAN_CMDID, 552 WMI_LPI_STOP_SCAN_CMDID, 553 WMI_EXTSCAN_START_CMDID = WMI_TLV_CMD(WMI_GRP_EXTSCAN), 554 WMI_EXTSCAN_STOP_CMDID, 555 WMI_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMDID, 556 WMI_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMDID, 557 WMI_EXTSCAN_GET_CACHED_RESULTS_CMDID, 558 WMI_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMDID, 559 WMI_EXTSCAN_SET_CAPABILITIES_CMDID, 560 WMI_EXTSCAN_GET_CAPABILITIES_CMDID, 561 WMI_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMDID, 562 WMI_EXTSCAN_CONFIGURE_MAWC_CMDID, 563 WMI_SET_DHCP_SERVER_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_DHCP_OFL), 564 WMI_IPA_OFFLOAD_ENABLE_DISABLE_CMDID = WMI_TLV_CMD(WMI_GRP_IPA), 565 WMI_MDNS_OFFLOAD_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_MDNS_OFL), 566 WMI_MDNS_SET_FQDN_CMDID, 567 WMI_MDNS_SET_RESPONSE_CMDID, 568 WMI_MDNS_GET_STATS_CMDID, 569 WMI_SAP_OFL_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_SAP_OFL), 570 WMI_SAP_SET_BLACKLIST_PARAM_CMDID, 571 WMI_OCB_SET_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_OCB), 572 WMI_OCB_SET_UTC_TIME_CMDID, 573 WMI_OCB_START_TIMING_ADVERT_CMDID, 574 WMI_OCB_STOP_TIMING_ADVERT_CMDID, 575 WMI_OCB_GET_TSF_TIMER_CMDID, 576 WMI_DCC_GET_STATS_CMDID, 577 WMI_DCC_CLEAR_STATS_CMDID, 578 WMI_DCC_UPDATE_NDL_CMDID, 579 WMI_SOC_SET_PCL_CMDID = WMI_TLV_CMD(WMI_GRP_SOC), 580 WMI_SOC_SET_HW_MODE_CMDID, 581 WMI_SOC_SET_DUAL_MAC_CONFIG_CMDID, 582 WMI_SOC_SET_ANTENNA_MODE_CMDID, 583 WMI_PACKET_FILTER_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_PKT_FILTER), 584 WMI_PACKET_FILTER_ENABLE_CMDID, 585 WMI_MAWC_SENSOR_REPORT_IND_CMDID = WMI_TLV_CMD(WMI_GRP_MAWC), 586 WMI_PMF_OFFLOAD_SET_SA_QUERY_CMDID = WMI_TLV_CMD(WMI_GRP_PMF_OFFLOAD), 587 WMI_BPF_GET_CAPABILITY_CMDID = WMI_TLV_CMD(WMI_GRP_BPF_OFFLOAD), 588 WMI_BPF_GET_VDEV_STATS_CMDID, 589 WMI_BPF_SET_VDEV_INSTRUCTIONS_CMDID, 590 WMI_BPF_DEL_VDEV_INSTRUCTIONS_CMDID, 591 WMI_BPF_SET_VDEV_ACTIVE_MODE_CMDID, 592 WMI_MNT_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_MONITOR), 593 WMI_SET_CURRENT_COUNTRY_CMDID = WMI_TLV_CMD(WMI_GRP_REGULATORY), 594 WMI_11D_SCAN_START_CMDID, 595 WMI_11D_SCAN_STOP_CMDID, 596 WMI_SET_INIT_COUNTRY_CMDID, 597 WMI_NDI_GET_CAP_REQ_CMDID = WMI_TLV_CMD(WMI_GRP_PROTOTYPE), 598 WMI_NDP_INITIATOR_REQ_CMDID, 599 WMI_NDP_RESPONDER_REQ_CMDID, 600 WMI_NDP_END_REQ_CMDID, 601 WMI_HW_DATA_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_HW_DATA_FILTER), 602 WMI_TWT_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_TWT), 603 WMI_TWT_DISABLE_CMDID, 604 WMI_TWT_ADD_DIALOG_CMDID, 605 WMI_TWT_DEL_DIALOG_CMDID, 606 WMI_TWT_PAUSE_DIALOG_CMDID, 607 WMI_TWT_RESUME_DIALOG_CMDID, 608 WMI_PDEV_OBSS_PD_SPATIAL_REUSE_CMDID = 609 WMI_TLV_CMD(WMI_GRP_SPATIAL_REUSE), 610 WMI_PDEV_OBSS_PD_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMDID, 611 }; 612 613 enum wmi_tlv_event_id { 614 WMI_SERVICE_READY_EVENTID = 0x1, 615 WMI_READY_EVENTID, 616 WMI_SERVICE_AVAILABLE_EVENTID, 617 WMI_SCAN_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SCAN), 618 WMI_PDEV_TPC_CONFIG_EVENTID = WMI_TLV_CMD(WMI_GRP_PDEV), 619 WMI_CHAN_INFO_EVENTID, 620 WMI_PHYERR_EVENTID, 621 WMI_PDEV_DUMP_EVENTID, 622 WMI_TX_PAUSE_EVENTID, 623 WMI_DFS_RADAR_EVENTID, 624 WMI_PDEV_L1SS_TRACK_EVENTID, 625 WMI_PDEV_TEMPERATURE_EVENTID, 626 WMI_SERVICE_READY_EXT_EVENTID, 627 WMI_PDEV_FIPS_EVENTID, 628 WMI_PDEV_CHANNEL_HOPPING_EVENTID, 629 WMI_PDEV_ANI_CCK_LEVEL_EVENTID, 630 WMI_PDEV_ANI_OFDM_LEVEL_EVENTID, 631 WMI_PDEV_TPC_EVENTID, 632 WMI_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID, 633 WMI_PDEV_SET_HW_MODE_RESP_EVENTID, 634 WMI_PDEV_HW_MODE_TRANSITION_EVENTID, 635 WMI_PDEV_SET_MAC_CONFIG_RESP_EVENTID, 636 WMI_PDEV_ANTDIV_STATUS_EVENTID, 637 WMI_PDEV_CHIP_POWER_STATS_EVENTID, 638 WMI_PDEV_CHIP_POWER_SAVE_FAILURE_DETECTED_EVENTID, 639 WMI_PDEV_CSA_SWITCH_COUNT_STATUS_EVENTID, 640 WMI_PDEV_CHECK_CAL_VERSION_EVENTID, 641 WMI_PDEV_DIV_RSSI_ANTID_EVENTID, 642 WMI_PDEV_BSS_CHAN_INFO_EVENTID, 643 WMI_PDEV_UPDATE_CTLTABLE_EVENTID, 644 WMI_PDEV_DMA_RING_CFG_RSP_EVENTID, 645 WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID, 646 WMI_PDEV_CTL_FAILSAFE_CHECK_EVENTID, 647 WMI_PDEV_CSC_SWITCH_COUNT_STATUS_EVENTID, 648 WMI_PDEV_COLD_BOOT_CAL_DATA_EVENTID, 649 WMI_PDEV_RAP_INFO_EVENTID, 650 WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENTID, 651 WMI_SERVICE_READY_EXT2_EVENTID, 652 WMI_VDEV_START_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_VDEV), 653 WMI_VDEV_STOPPED_EVENTID, 654 WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID, 655 WMI_VDEV_MCC_BCN_INTERVAL_CHANGE_REQ_EVENTID, 656 WMI_VDEV_TSF_REPORT_EVENTID, 657 WMI_VDEV_DELETE_RESP_EVENTID, 658 WMI_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENTID, 659 WMI_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_STATUS_EVENTID, 660 WMI_PEER_STA_KICKOUT_EVENTID = WMI_TLV_CMD(WMI_GRP_PEER), 661 WMI_PEER_INFO_EVENTID, 662 WMI_PEER_TX_FAIL_CNT_THR_EVENTID, 663 WMI_PEER_ESTIMATED_LINKSPEED_EVENTID, 664 WMI_PEER_STATE_EVENTID, 665 WMI_PEER_ASSOC_CONF_EVENTID, 666 WMI_PEER_DELETE_RESP_EVENTID, 667 WMI_PEER_RATECODE_LIST_EVENTID, 668 WMI_WDS_PEER_EVENTID, 669 WMI_PEER_STA_PS_STATECHG_EVENTID, 670 WMI_PEER_ANTDIV_INFO_EVENTID, 671 WMI_PEER_RESERVED0_EVENTID, 672 WMI_PEER_RESERVED1_EVENTID, 673 WMI_PEER_RESERVED2_EVENTID, 674 WMI_PEER_RESERVED3_EVENTID, 675 WMI_PEER_RESERVED4_EVENTID, 676 WMI_PEER_RESERVED5_EVENTID, 677 WMI_PEER_RESERVED6_EVENTID, 678 WMI_PEER_RESERVED7_EVENTID, 679 WMI_PEER_RESERVED8_EVENTID, 680 WMI_PEER_RESERVED9_EVENTID, 681 WMI_PEER_RESERVED10_EVENTID, 682 WMI_PEER_OPER_MODE_CHANGE_EVENTID, 683 WMI_PEER_TX_PN_RESPONSE_EVENTID, 684 WMI_PEER_CFR_CAPTURE_EVENTID, 685 WMI_PEER_CREATE_CONF_EVENTID, 686 WMI_MGMT_RX_EVENTID = WMI_TLV_CMD(WMI_GRP_MGMT), 687 WMI_HOST_SWBA_EVENTID, 688 WMI_TBTTOFFSET_UPDATE_EVENTID, 689 WMI_OFFLOAD_BCN_TX_STATUS_EVENTID, 690 WMI_OFFLOAD_PROB_RESP_TX_STATUS_EVENTID, 691 WMI_MGMT_TX_COMPLETION_EVENTID, 692 WMI_MGMT_TX_BUNDLE_COMPLETION_EVENTID, 693 WMI_TBTTOFFSET_EXT_UPDATE_EVENTID, 694 WMI_OFFCHAN_DATA_TX_COMPLETION_EVENTID, 695 WMI_HOST_FILS_DISCOVERY_EVENTID, 696 WMI_TX_DELBA_COMPLETE_EVENTID = WMI_TLV_CMD(WMI_GRP_BA_NEG), 697 WMI_TX_ADDBA_COMPLETE_EVENTID, 698 WMI_BA_RSP_SSN_EVENTID, 699 WMI_AGGR_STATE_TRIG_EVENTID, 700 WMI_ROAM_EVENTID = WMI_TLV_CMD(WMI_GRP_ROAM), 701 WMI_PROFILE_MATCH, 702 WMI_ROAM_SYNCH_EVENTID, 703 WMI_P2P_DISC_EVENTID = WMI_TLV_CMD(WMI_GRP_P2P), 704 WMI_P2P_NOA_EVENTID, 705 WMI_P2P_LISTEN_OFFLOAD_STOPPED_EVENTID, 706 WMI_AP_PS_EGAP_INFO_EVENTID = WMI_TLV_CMD(WMI_GRP_AP_PS), 707 WMI_PDEV_RESUME_EVENTID = WMI_TLV_CMD(WMI_GRP_SUSPEND), 708 WMI_WOW_WAKEUP_HOST_EVENTID = WMI_TLV_CMD(WMI_GRP_WOW), 709 WMI_D0_WOW_DISABLE_ACK_EVENTID, 710 WMI_WOW_INITIAL_WAKEUP_EVENTID, 711 WMI_RTT_MEASUREMENT_REPORT_EVENTID = WMI_TLV_CMD(WMI_GRP_RTT), 712 WMI_TSF_MEASUREMENT_REPORT_EVENTID, 713 WMI_RTT_ERROR_REPORT_EVENTID, 714 WMI_STATS_EXT_EVENTID = WMI_TLV_CMD(WMI_GRP_STATS), 715 WMI_IFACE_LINK_STATS_EVENTID, 716 WMI_PEER_LINK_STATS_EVENTID, 717 WMI_RADIO_LINK_STATS_EVENTID, 718 WMI_UPDATE_FW_MEM_DUMP_EVENTID, 719 WMI_DIAG_EVENT_LOG_SUPPORTED_EVENTID, 720 WMI_INST_RSSI_STATS_EVENTID, 721 WMI_RADIO_TX_POWER_LEVEL_STATS_EVENTID, 722 WMI_REPORT_STATS_EVENTID, 723 WMI_UPDATE_RCPI_EVENTID, 724 WMI_PEER_STATS_INFO_EVENTID, 725 WMI_RADIO_CHAN_STATS_EVENTID, 726 WMI_NLO_MATCH_EVENTID = WMI_TLV_CMD(WMI_GRP_NLO_OFL), 727 WMI_NLO_SCAN_COMPLETE_EVENTID, 728 WMI_APFIND_EVENTID, 729 WMI_PASSPOINT_MATCH_EVENTID, 730 WMI_GTK_OFFLOAD_STATUS_EVENTID = WMI_TLV_CMD(WMI_GRP_GTK_OFL), 731 WMI_GTK_REKEY_FAIL_EVENTID, 732 WMI_CSA_HANDLING_EVENTID = WMI_TLV_CMD(WMI_GRP_CSA_OFL), 733 WMI_CHATTER_PC_QUERY_EVENTID = WMI_TLV_CMD(WMI_GRP_CHATTER), 734 WMI_PDEV_DFS_RADAR_DETECTION_EVENTID = WMI_TLV_CMD(WMI_GRP_DFS), 735 WMI_VDEV_DFS_CAC_COMPLETE_EVENTID, 736 WMI_VDEV_ADFS_OCAC_COMPLETE_EVENTID, 737 WMI_ECHO_EVENTID = WMI_TLV_CMD(WMI_GRP_MISC), 738 WMI_PDEV_UTF_EVENTID, 739 WMI_DEBUG_MESG_EVENTID, 740 WMI_UPDATE_STATS_EVENTID, 741 WMI_DEBUG_PRINT_EVENTID, 742 WMI_DCS_INTERFERENCE_EVENTID, 743 WMI_PDEV_QVIT_EVENTID, 744 WMI_WLAN_PROFILE_DATA_EVENTID, 745 WMI_PDEV_FTM_INTG_EVENTID, 746 WMI_WLAN_FREQ_AVOID_EVENTID, 747 WMI_VDEV_GET_KEEPALIVE_EVENTID, 748 WMI_THERMAL_MGMT_EVENTID, 749 WMI_DIAG_DATA_CONTAINER_EVENTID, 750 WMI_HOST_AUTO_SHUTDOWN_EVENTID, 751 WMI_UPDATE_WHAL_MIB_STATS_EVENTID, 752 WMI_UPDATE_VDEV_RATE_STATS_EVENTID, 753 WMI_DIAG_EVENTID, 754 WMI_OCB_SET_SCHED_EVENTID, 755 WMI_DEBUG_MESG_FLUSH_COMPLETE_EVENTID, 756 WMI_RSSI_BREACH_EVENTID, 757 WMI_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENTID, 758 WMI_PDEV_UTF_SCPC_EVENTID, 759 WMI_READ_DATA_FROM_FLASH_EVENTID, 760 WMI_REPORT_RX_AGGR_FAILURE_EVENTID, 761 WMI_PKGID_EVENTID, 762 WMI_GPIO_INPUT_EVENTID = WMI_TLV_CMD(WMI_GRP_GPIO), 763 WMI_UPLOADH_EVENTID, 764 WMI_CAPTUREH_EVENTID, 765 WMI_RFKILL_STATE_CHANGE_EVENTID, 766 WMI_TDLS_PEER_EVENTID = WMI_TLV_CMD(WMI_GRP_TDLS), 767 WMI_STA_SMPS_FORCE_MODE_COMPL_EVENTID = WMI_TLV_CMD(WMI_GRP_STA_SMPS), 768 WMI_BATCH_SCAN_ENABLED_EVENTID = WMI_TLV_CMD(WMI_GRP_LOCATION_SCAN), 769 WMI_BATCH_SCAN_RESULT_EVENTID, 770 WMI_OEM_CAPABILITY_EVENTID = WMI_TLV_CMD(WMI_GRP_OEM), 771 WMI_OEM_MEASUREMENT_REPORT_EVENTID, 772 WMI_OEM_ERROR_REPORT_EVENTID, 773 WMI_OEM_RESPONSE_EVENTID, 774 WMI_NAN_EVENTID = WMI_TLV_CMD(WMI_GRP_NAN), 775 WMI_NAN_DISC_IFACE_CREATED_EVENTID, 776 WMI_NAN_DISC_IFACE_DELETED_EVENTID, 777 WMI_NAN_STARTED_CLUSTER_EVENTID, 778 WMI_NAN_JOINED_CLUSTER_EVENTID, 779 WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID = WMI_TLV_CMD(WMI_GRP_COEX), 780 WMI_LPI_RESULT_EVENTID = WMI_TLV_CMD(WMI_GRP_LPI), 781 WMI_LPI_STATUS_EVENTID, 782 WMI_LPI_HANDOFF_EVENTID, 783 WMI_EXTSCAN_START_STOP_EVENTID = WMI_TLV_CMD(WMI_GRP_EXTSCAN), 784 WMI_EXTSCAN_OPERATION_EVENTID, 785 WMI_EXTSCAN_TABLE_USAGE_EVENTID, 786 WMI_EXTSCAN_CACHED_RESULTS_EVENTID, 787 WMI_EXTSCAN_WLAN_CHANGE_RESULTS_EVENTID, 788 WMI_EXTSCAN_HOTLIST_MATCH_EVENTID, 789 WMI_EXTSCAN_CAPABILITIES_EVENTID, 790 WMI_EXTSCAN_HOTLIST_SSID_MATCH_EVENTID, 791 WMI_MDNS_STATS_EVENTID = WMI_TLV_CMD(WMI_GRP_MDNS_OFL), 792 WMI_SAP_OFL_ADD_STA_EVENTID = WMI_TLV_CMD(WMI_GRP_SAP_OFL), 793 WMI_SAP_OFL_DEL_STA_EVENTID, 794 WMI_OBSS_COLOR_COLLISION_DETECTION_EVENTID = 795 WMI_EVT_GRP_START_ID(WMI_GRP_OBSS_OFL), 796 WMI_OCB_SET_CONFIG_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_OCB), 797 WMI_OCB_GET_TSF_TIMER_RESP_EVENTID, 798 WMI_DCC_GET_STATS_RESP_EVENTID, 799 WMI_DCC_UPDATE_NDL_RESP_EVENTID, 800 WMI_DCC_STATS_EVENTID, 801 WMI_SOC_SET_HW_MODE_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_SOC), 802 WMI_SOC_HW_MODE_TRANSITION_EVENTID, 803 WMI_SOC_SET_DUAL_MAC_CONFIG_RESP_EVENTID, 804 WMI_MAWC_ENABLE_SENSOR_EVENTID = WMI_TLV_CMD(WMI_GRP_MAWC), 805 WMI_BPF_CAPABILIY_INFO_EVENTID = WMI_TLV_CMD(WMI_GRP_BPF_OFFLOAD), 806 WMI_BPF_VDEV_STATS_INFO_EVENTID, 807 WMI_RMC_NEW_LEADER_EVENTID = WMI_TLV_CMD(WMI_GRP_RMC), 808 WMI_REG_CHAN_LIST_CC_EVENTID = WMI_TLV_CMD(WMI_GRP_REGULATORY), 809 WMI_11D_NEW_COUNTRY_EVENTID, 810 WMI_REG_CHAN_LIST_CC_EXT_EVENTID, 811 WMI_NDI_CAP_RSP_EVENTID = WMI_TLV_CMD(WMI_GRP_PROTOTYPE), 812 WMI_NDP_INITIATOR_RSP_EVENTID, 813 WMI_NDP_RESPONDER_RSP_EVENTID, 814 WMI_NDP_END_RSP_EVENTID, 815 WMI_NDP_INDICATION_EVENTID, 816 WMI_NDP_CONFIRM_EVENTID, 817 WMI_NDP_END_INDICATION_EVENTID, 818 819 WMI_TWT_ENABLE_EVENTID = WMI_TLV_CMD(WMI_GRP_TWT), 820 WMI_TWT_DISABLE_EVENTID, 821 WMI_TWT_ADD_DIALOG_EVENTID, 822 WMI_TWT_DEL_DIALOG_EVENTID, 823 WMI_TWT_PAUSE_DIALOG_EVENTID, 824 WMI_TWT_RESUME_DIALOG_EVENTID, 825 }; 826 827 enum wmi_tlv_pdev_param { 828 WMI_PDEV_PARAM_TX_CHAIN_MASK = 0x1, 829 WMI_PDEV_PARAM_RX_CHAIN_MASK, 830 WMI_PDEV_PARAM_TXPOWER_LIMIT2G, 831 WMI_PDEV_PARAM_TXPOWER_LIMIT5G, 832 WMI_PDEV_PARAM_TXPOWER_SCALE, 833 WMI_PDEV_PARAM_BEACON_GEN_MODE, 834 WMI_PDEV_PARAM_BEACON_TX_MODE, 835 WMI_PDEV_PARAM_RESMGR_OFFCHAN_MODE, 836 WMI_PDEV_PARAM_PROTECTION_MODE, 837 WMI_PDEV_PARAM_DYNAMIC_BW, 838 WMI_PDEV_PARAM_NON_AGG_SW_RETRY_TH, 839 WMI_PDEV_PARAM_AGG_SW_RETRY_TH, 840 WMI_PDEV_PARAM_STA_KICKOUT_TH, 841 WMI_PDEV_PARAM_AC_AGGRSIZE_SCALING, 842 WMI_PDEV_PARAM_LTR_ENABLE, 843 WMI_PDEV_PARAM_LTR_AC_LATENCY_BE, 844 WMI_PDEV_PARAM_LTR_AC_LATENCY_BK, 845 WMI_PDEV_PARAM_LTR_AC_LATENCY_VI, 846 WMI_PDEV_PARAM_LTR_AC_LATENCY_VO, 847 WMI_PDEV_PARAM_LTR_AC_LATENCY_TIMEOUT, 848 WMI_PDEV_PARAM_LTR_SLEEP_OVERRIDE, 849 WMI_PDEV_PARAM_LTR_RX_OVERRIDE, 850 WMI_PDEV_PARAM_LTR_TX_ACTIVITY_TIMEOUT, 851 WMI_PDEV_PARAM_L1SS_ENABLE, 852 WMI_PDEV_PARAM_DSLEEP_ENABLE, 853 WMI_PDEV_PARAM_PCIELP_TXBUF_FLUSH, 854 WMI_PDEV_PARAM_PCIELP_TXBUF_WATERMARK, 855 WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_EN, 856 WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_VALUE, 857 WMI_PDEV_PARAM_PDEV_STATS_UPDATE_PERIOD, 858 WMI_PDEV_PARAM_VDEV_STATS_UPDATE_PERIOD, 859 WMI_PDEV_PARAM_PEER_STATS_UPDATE_PERIOD, 860 WMI_PDEV_PARAM_BCNFLT_STATS_UPDATE_PERIOD, 861 WMI_PDEV_PARAM_PMF_QOS, 862 WMI_PDEV_PARAM_ARP_AC_OVERRIDE, 863 WMI_PDEV_PARAM_DCS, 864 WMI_PDEV_PARAM_ANI_ENABLE, 865 WMI_PDEV_PARAM_ANI_POLL_PERIOD, 866 WMI_PDEV_PARAM_ANI_LISTEN_PERIOD, 867 WMI_PDEV_PARAM_ANI_OFDM_LEVEL, 868 WMI_PDEV_PARAM_ANI_CCK_LEVEL, 869 WMI_PDEV_PARAM_DYNTXCHAIN, 870 WMI_PDEV_PARAM_PROXY_STA, 871 WMI_PDEV_PARAM_IDLE_PS_CONFIG, 872 WMI_PDEV_PARAM_POWER_GATING_SLEEP, 873 WMI_PDEV_PARAM_RFKILL_ENABLE, 874 WMI_PDEV_PARAM_BURST_DUR, 875 WMI_PDEV_PARAM_BURST_ENABLE, 876 WMI_PDEV_PARAM_HW_RFKILL_CONFIG, 877 WMI_PDEV_PARAM_LOW_POWER_RF_ENABLE, 878 WMI_PDEV_PARAM_L1SS_TRACK, 879 WMI_PDEV_PARAM_HYST_EN, 880 WMI_PDEV_PARAM_POWER_COLLAPSE_ENABLE, 881 WMI_PDEV_PARAM_LED_SYS_STATE, 882 WMI_PDEV_PARAM_LED_ENABLE, 883 WMI_PDEV_PARAM_AUDIO_OVER_WLAN_LATENCY, 884 WMI_PDEV_PARAM_AUDIO_OVER_WLAN_ENABLE, 885 WMI_PDEV_PARAM_WHAL_MIB_STATS_UPDATE_ENABLE, 886 WMI_PDEV_PARAM_VDEV_RATE_STATS_UPDATE_PERIOD, 887 WMI_PDEV_PARAM_CTS_CBW, 888 WMI_PDEV_PARAM_WNTS_CONFIG, 889 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_ENABLE, 890 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_MIN_SLEEP_SLOP, 891 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_INC_DEC_STEP, 892 WMI_PDEV_PARAM_EARLY_RX_FIX_SLEEP_SLOP, 893 WMI_PDEV_PARAM_BMISS_BASED_ADAPTIVE_BTO_ENABLE, 894 WMI_PDEV_PARAM_BMISS_BTO_MIN_BCN_TIMEOUT, 895 WMI_PDEV_PARAM_BMISS_BTO_INC_DEC_STEP, 896 WMI_PDEV_PARAM_BTO_FIX_BCN_TIMEOUT, 897 WMI_PDEV_PARAM_CE_BASED_ADAPTIVE_BTO_ENABLE, 898 WMI_PDEV_PARAM_CE_BTO_COMBO_CE_VALUE, 899 WMI_PDEV_PARAM_TX_CHAIN_MASK_2G, 900 WMI_PDEV_PARAM_RX_CHAIN_MASK_2G, 901 WMI_PDEV_PARAM_TX_CHAIN_MASK_5G, 902 WMI_PDEV_PARAM_RX_CHAIN_MASK_5G, 903 WMI_PDEV_PARAM_TX_CHAIN_MASK_CCK, 904 WMI_PDEV_PARAM_TX_CHAIN_MASK_1SS, 905 WMI_PDEV_PARAM_CTS2SELF_FOR_P2P_GO_CONFIG, 906 WMI_PDEV_PARAM_TXPOWER_DECR_DB, 907 WMI_PDEV_PARAM_AGGR_BURST, 908 WMI_PDEV_PARAM_RX_DECAP_MODE, 909 WMI_PDEV_PARAM_FAST_CHANNEL_RESET, 910 WMI_PDEV_PARAM_SMART_ANTENNA_DEFAULT_ANTENNA, 911 WMI_PDEV_PARAM_ANTENNA_GAIN, 912 WMI_PDEV_PARAM_RX_FILTER, 913 WMI_PDEV_SET_MCAST_TO_UCAST_TID, 914 WMI_PDEV_PARAM_PROXY_STA_MODE, 915 WMI_PDEV_PARAM_SET_MCAST2UCAST_MODE, 916 WMI_PDEV_PARAM_SET_MCAST2UCAST_BUFFER, 917 WMI_PDEV_PARAM_REMOVE_MCAST2UCAST_BUFFER, 918 WMI_PDEV_PEER_STA_PS_STATECHG_ENABLE, 919 WMI_PDEV_PARAM_IGMPMLD_AC_OVERRIDE, 920 WMI_PDEV_PARAM_BLOCK_INTERBSS, 921 WMI_PDEV_PARAM_SET_DISABLE_RESET_CMDID, 922 WMI_PDEV_PARAM_SET_MSDU_TTL_CMDID, 923 WMI_PDEV_PARAM_SET_PPDU_DURATION_CMDID, 924 WMI_PDEV_PARAM_TXBF_SOUND_PERIOD_CMDID, 925 WMI_PDEV_PARAM_SET_PROMISC_MODE_CMDID, 926 WMI_PDEV_PARAM_SET_BURST_MODE_CMDID, 927 WMI_PDEV_PARAM_EN_STATS, 928 WMI_PDEV_PARAM_MU_GROUP_POLICY, 929 WMI_PDEV_PARAM_NOISE_DETECTION, 930 WMI_PDEV_PARAM_NOISE_THRESHOLD, 931 WMI_PDEV_PARAM_DPD_ENABLE, 932 WMI_PDEV_PARAM_SET_MCAST_BCAST_ECHO, 933 WMI_PDEV_PARAM_ATF_STRICT_SCH, 934 WMI_PDEV_PARAM_ATF_SCHED_DURATION, 935 WMI_PDEV_PARAM_ANT_PLZN, 936 WMI_PDEV_PARAM_MGMT_RETRY_LIMIT, 937 WMI_PDEV_PARAM_SENSITIVITY_LEVEL, 938 WMI_PDEV_PARAM_SIGNED_TXPOWER_2G, 939 WMI_PDEV_PARAM_SIGNED_TXPOWER_5G, 940 WMI_PDEV_PARAM_ENABLE_PER_TID_AMSDU, 941 WMI_PDEV_PARAM_ENABLE_PER_TID_AMPDU, 942 WMI_PDEV_PARAM_CCA_THRESHOLD, 943 WMI_PDEV_PARAM_RTS_FIXED_RATE, 944 WMI_PDEV_PARAM_PDEV_RESET, 945 WMI_PDEV_PARAM_WAPI_MBSSID_OFFSET, 946 WMI_PDEV_PARAM_ARP_DBG_SRCADDR, 947 WMI_PDEV_PARAM_ARP_DBG_DSTADDR, 948 WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCH, 949 WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCALING_FACTOR, 950 WMI_PDEV_PARAM_CUST_TXPOWER_SCALE, 951 WMI_PDEV_PARAM_ATF_DYNAMIC_ENABLE, 952 WMI_PDEV_PARAM_CTRL_RETRY_LIMIT, 953 WMI_PDEV_PARAM_PROPAGATION_DELAY, 954 WMI_PDEV_PARAM_ENA_ANT_DIV, 955 WMI_PDEV_PARAM_FORCE_CHAIN_ANT, 956 WMI_PDEV_PARAM_ANT_DIV_SELFTEST, 957 WMI_PDEV_PARAM_ANT_DIV_SELFTEST_INTVL, 958 WMI_PDEV_PARAM_STATS_OBSERVATION_PERIOD, 959 WMI_PDEV_PARAM_TX_PPDU_DELAY_BIN_SIZE_MS, 960 WMI_PDEV_PARAM_TX_PPDU_DELAY_ARRAY_LEN, 961 WMI_PDEV_PARAM_TX_MPDU_AGGR_ARRAY_LEN, 962 WMI_PDEV_PARAM_RX_MPDU_AGGR_ARRAY_LEN, 963 WMI_PDEV_PARAM_TX_SCH_DELAY, 964 WMI_PDEV_PARAM_ENABLE_RTS_SIFS_BURSTING, 965 WMI_PDEV_PARAM_MAX_MPDUS_IN_AMPDU, 966 WMI_PDEV_PARAM_PEER_STATS_INFO_ENABLE, 967 WMI_PDEV_PARAM_FAST_PWR_TRANSITION, 968 WMI_PDEV_PARAM_RADIO_CHAN_STATS_ENABLE, 969 WMI_PDEV_PARAM_RADIO_DIAGNOSIS_ENABLE, 970 WMI_PDEV_PARAM_MESH_MCAST_ENABLE, 971 WMI_PDEV_PARAM_SET_CMD_OBSS_PD_THRESHOLD = 0xbc, 972 WMI_PDEV_PARAM_SET_CMD_OBSS_PD_PER_AC = 0xbe, 973 WMI_PDEV_PARAM_ENABLE_SR_PROHIBIT = 0xc6, 974 }; 975 976 enum wmi_tlv_vdev_param { 977 WMI_VDEV_PARAM_RTS_THRESHOLD = 0x1, 978 WMI_VDEV_PARAM_FRAGMENTATION_THRESHOLD, 979 WMI_VDEV_PARAM_BEACON_INTERVAL, 980 WMI_VDEV_PARAM_LISTEN_INTERVAL, 981 WMI_VDEV_PARAM_MULTICAST_RATE, 982 WMI_VDEV_PARAM_MGMT_TX_RATE, 983 WMI_VDEV_PARAM_SLOT_TIME, 984 WMI_VDEV_PARAM_PREAMBLE, 985 WMI_VDEV_PARAM_SWBA_TIME, 986 WMI_VDEV_STATS_UPDATE_PERIOD, 987 WMI_VDEV_PWRSAVE_AGEOUT_TIME, 988 WMI_VDEV_HOST_SWBA_INTERVAL, 989 WMI_VDEV_PARAM_DTIM_PERIOD, 990 WMI_VDEV_OC_SCHEDULER_AIR_TIME_LIMIT, 991 WMI_VDEV_PARAM_WDS, 992 WMI_VDEV_PARAM_ATIM_WINDOW, 993 WMI_VDEV_PARAM_BMISS_COUNT_MAX, 994 WMI_VDEV_PARAM_BMISS_FIRST_BCNT, 995 WMI_VDEV_PARAM_BMISS_FINAL_BCNT, 996 WMI_VDEV_PARAM_FEATURE_WMM, 997 WMI_VDEV_PARAM_CHWIDTH, 998 WMI_VDEV_PARAM_CHEXTOFFSET, 999 WMI_VDEV_PARAM_DISABLE_HTPROTECTION, 1000 WMI_VDEV_PARAM_STA_QUICKKICKOUT, 1001 WMI_VDEV_PARAM_MGMT_RATE, 1002 WMI_VDEV_PARAM_PROTECTION_MODE, 1003 WMI_VDEV_PARAM_FIXED_RATE, 1004 WMI_VDEV_PARAM_SGI, 1005 WMI_VDEV_PARAM_LDPC, 1006 WMI_VDEV_PARAM_TX_STBC, 1007 WMI_VDEV_PARAM_RX_STBC, 1008 WMI_VDEV_PARAM_INTRA_BSS_FWD, 1009 WMI_VDEV_PARAM_DEF_KEYID, 1010 WMI_VDEV_PARAM_NSS, 1011 WMI_VDEV_PARAM_BCAST_DATA_RATE, 1012 WMI_VDEV_PARAM_MCAST_DATA_RATE, 1013 WMI_VDEV_PARAM_MCAST_INDICATE, 1014 WMI_VDEV_PARAM_DHCP_INDICATE, 1015 WMI_VDEV_PARAM_UNKNOWN_DEST_INDICATE, 1016 WMI_VDEV_PARAM_AP_KEEPALIVE_MIN_IDLE_INACTIVE_TIME_SECS, 1017 WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_IDLE_INACTIVE_TIME_SECS, 1018 WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS, 1019 WMI_VDEV_PARAM_AP_ENABLE_NAWDS, 1020 WMI_VDEV_PARAM_ENABLE_RTSCTS, 1021 WMI_VDEV_PARAM_TXBF, 1022 WMI_VDEV_PARAM_PACKET_POWERSAVE, 1023 WMI_VDEV_PARAM_DROP_UNENCRY, 1024 WMI_VDEV_PARAM_TX_ENCAP_TYPE, 1025 WMI_VDEV_PARAM_AP_DETECT_OUT_OF_SYNC_SLEEPING_STA_TIME_SECS, 1026 WMI_VDEV_PARAM_EARLY_RX_ADJUST_ENABLE, 1027 WMI_VDEV_PARAM_EARLY_RX_TGT_BMISS_NUM, 1028 WMI_VDEV_PARAM_EARLY_RX_BMISS_SAMPLE_CYCLE, 1029 WMI_VDEV_PARAM_EARLY_RX_SLOP_STEP, 1030 WMI_VDEV_PARAM_EARLY_RX_INIT_SLOP, 1031 WMI_VDEV_PARAM_EARLY_RX_ADJUST_PAUSE, 1032 WMI_VDEV_PARAM_TX_PWRLIMIT, 1033 WMI_VDEV_PARAM_SNR_NUM_FOR_CAL, 1034 WMI_VDEV_PARAM_ROAM_FW_OFFLOAD, 1035 WMI_VDEV_PARAM_ENABLE_RMC, 1036 WMI_VDEV_PARAM_IBSS_MAX_BCN_LOST_MS, 1037 WMI_VDEV_PARAM_MAX_RATE, 1038 WMI_VDEV_PARAM_EARLY_RX_DRIFT_SAMPLE, 1039 WMI_VDEV_PARAM_SET_IBSS_TX_FAIL_CNT_THR, 1040 WMI_VDEV_PARAM_EBT_RESYNC_TIMEOUT, 1041 WMI_VDEV_PARAM_AGGR_TRIG_EVENT_ENABLE, 1042 WMI_VDEV_PARAM_IS_IBSS_POWER_SAVE_ALLOWED, 1043 WMI_VDEV_PARAM_IS_POWER_COLLAPSE_ALLOWED, 1044 WMI_VDEV_PARAM_IS_AWAKE_ON_TXRX_ENABLED, 1045 WMI_VDEV_PARAM_INACTIVITY_CNT, 1046 WMI_VDEV_PARAM_TXSP_END_INACTIVITY_TIME_MS, 1047 WMI_VDEV_PARAM_DTIM_POLICY, 1048 WMI_VDEV_PARAM_IBSS_PS_WARMUP_TIME_SECS, 1049 WMI_VDEV_PARAM_IBSS_PS_1RX_CHAIN_IN_ATIM_WINDOW_ENABLE, 1050 WMI_VDEV_PARAM_RX_LEAK_WINDOW, 1051 WMI_VDEV_PARAM_STATS_AVG_FACTOR, 1052 WMI_VDEV_PARAM_DISCONNECT_TH, 1053 WMI_VDEV_PARAM_RTSCTS_RATE, 1054 WMI_VDEV_PARAM_MCC_RTSCTS_PROTECTION_ENABLE, 1055 WMI_VDEV_PARAM_MCC_BROADCAST_PROBE_ENABLE, 1056 WMI_VDEV_PARAM_TXPOWER_SCALE, 1057 WMI_VDEV_PARAM_TXPOWER_SCALE_DECR_DB, 1058 WMI_VDEV_PARAM_MCAST2UCAST_SET, 1059 WMI_VDEV_PARAM_RC_NUM_RETRIES, 1060 WMI_VDEV_PARAM_CABQ_MAXDUR, 1061 WMI_VDEV_PARAM_MFPTEST_SET, 1062 WMI_VDEV_PARAM_RTS_FIXED_RATE, 1063 WMI_VDEV_PARAM_VHT_SGIMASK, 1064 WMI_VDEV_PARAM_VHT80_RATEMASK, 1065 WMI_VDEV_PARAM_PROXY_STA, 1066 WMI_VDEV_PARAM_VIRTUAL_CELL_MODE, 1067 WMI_VDEV_PARAM_RX_DECAP_TYPE, 1068 WMI_VDEV_PARAM_BW_NSS_RATEMASK, 1069 WMI_VDEV_PARAM_SENSOR_AP, 1070 WMI_VDEV_PARAM_BEACON_RATE, 1071 WMI_VDEV_PARAM_DTIM_ENABLE_CTS, 1072 WMI_VDEV_PARAM_STA_KICKOUT, 1073 WMI_VDEV_PARAM_CAPABILITIES, 1074 WMI_VDEV_PARAM_TSF_INCREMENT, 1075 WMI_VDEV_PARAM_AMPDU_PER_AC, 1076 WMI_VDEV_PARAM_RX_FILTER, 1077 WMI_VDEV_PARAM_MGMT_TX_POWER, 1078 WMI_VDEV_PARAM_NON_AGG_SW_RETRY_TH, 1079 WMI_VDEV_PARAM_AGG_SW_RETRY_TH, 1080 WMI_VDEV_PARAM_DISABLE_DYN_BW_RTS, 1081 WMI_VDEV_PARAM_ATF_SSID_SCHED_POLICY, 1082 WMI_VDEV_PARAM_HE_DCM, 1083 WMI_VDEV_PARAM_HE_RANGE_EXT, 1084 WMI_VDEV_PARAM_ENABLE_BCAST_PROBE_RESPONSE, 1085 WMI_VDEV_PARAM_FILS_MAX_CHANNEL_GUARD_TIME, 1086 WMI_VDEV_PARAM_HE_LTF = 0x74, 1087 WMI_VDEV_PARAM_ENABLE_DISABLE_RTT_RESPONDER_ROLE = 0x7d, 1088 WMI_VDEV_PARAM_BA_MODE = 0x7e, 1089 WMI_VDEV_PARAM_AUTORATE_MISC_CFG = 0x80, 1090 WMI_VDEV_PARAM_SET_HE_SOUNDING_MODE = 0x87, 1091 WMI_VDEV_PARAM_6GHZ_PARAMS = 0x99, 1092 WMI_VDEV_PARAM_PROTOTYPE = 0x8000, 1093 WMI_VDEV_PARAM_BSS_COLOR, 1094 WMI_VDEV_PARAM_SET_HEMU_MODE, 1095 WMI_VDEV_PARAM_HEOPS_0_31 = 0x8003, 1096 }; 1097 1098 enum wmi_tlv_peer_flags { 1099 WMI_TLV_PEER_AUTH = 0x00000001, 1100 WMI_TLV_PEER_QOS = 0x00000002, 1101 WMI_TLV_PEER_NEED_PTK_4_WAY = 0x00000004, 1102 WMI_TLV_PEER_NEED_GTK_2_WAY = 0x00000010, 1103 WMI_TLV_PEER_APSD = 0x00000800, 1104 WMI_TLV_PEER_HT = 0x00001000, 1105 WMI_TLV_PEER_40MHZ = 0x00002000, 1106 WMI_TLV_PEER_STBC = 0x00008000, 1107 WMI_TLV_PEER_LDPC = 0x00010000, 1108 WMI_TLV_PEER_DYN_MIMOPS = 0x00020000, 1109 WMI_TLV_PEER_STATIC_MIMOPS = 0x00040000, 1110 WMI_TLV_PEER_SPATIAL_MUX = 0x00200000, 1111 WMI_TLV_PEER_VHT = 0x02000000, 1112 WMI_TLV_PEER_80MHZ = 0x04000000, 1113 WMI_TLV_PEER_PMF = 0x08000000, 1114 WMI_PEER_IS_P2P_CAPABLE = 0x20000000, 1115 WMI_PEER_160MHZ = 0x40000000, 1116 WMI_PEER_SAFEMODE_EN = 0x80000000, 1117 1118 }; 1119 1120 /** Enum list of TLV Tags for each parameter structure type. */ 1121 enum wmi_tlv_tag { 1122 WMI_TAG_LAST_RESERVED = 15, 1123 WMI_TAG_FIRST_ARRAY_ENUM, 1124 WMI_TAG_ARRAY_UINT32 = WMI_TAG_FIRST_ARRAY_ENUM, 1125 WMI_TAG_ARRAY_BYTE, 1126 WMI_TAG_ARRAY_STRUCT, 1127 WMI_TAG_ARRAY_FIXED_STRUCT, 1128 WMI_TAG_LAST_ARRAY_ENUM = 31, 1129 WMI_TAG_SERVICE_READY_EVENT, 1130 WMI_TAG_HAL_REG_CAPABILITIES, 1131 WMI_TAG_WLAN_HOST_MEM_REQ, 1132 WMI_TAG_READY_EVENT, 1133 WMI_TAG_SCAN_EVENT, 1134 WMI_TAG_PDEV_TPC_CONFIG_EVENT, 1135 WMI_TAG_CHAN_INFO_EVENT, 1136 WMI_TAG_COMB_PHYERR_RX_HDR, 1137 WMI_TAG_VDEV_START_RESPONSE_EVENT, 1138 WMI_TAG_VDEV_STOPPED_EVENT, 1139 WMI_TAG_VDEV_INSTALL_KEY_COMPLETE_EVENT, 1140 WMI_TAG_PEER_STA_KICKOUT_EVENT, 1141 WMI_TAG_MGMT_RX_HDR, 1142 WMI_TAG_TBTT_OFFSET_EVENT, 1143 WMI_TAG_TX_DELBA_COMPLETE_EVENT, 1144 WMI_TAG_TX_ADDBA_COMPLETE_EVENT, 1145 WMI_TAG_ROAM_EVENT, 1146 WMI_TAG_WOW_EVENT_INFO, 1147 WMI_TAG_WOW_EVENT_INFO_SECTION_BITMAP, 1148 WMI_TAG_RTT_EVENT_HEADER, 1149 WMI_TAG_RTT_ERROR_REPORT_EVENT, 1150 WMI_TAG_RTT_MEAS_EVENT, 1151 WMI_TAG_ECHO_EVENT, 1152 WMI_TAG_FTM_INTG_EVENT, 1153 WMI_TAG_VDEV_GET_KEEPALIVE_EVENT, 1154 WMI_TAG_GPIO_INPUT_EVENT, 1155 WMI_TAG_CSA_EVENT, 1156 WMI_TAG_GTK_OFFLOAD_STATUS_EVENT, 1157 WMI_TAG_IGTK_INFO, 1158 WMI_TAG_DCS_INTERFERENCE_EVENT, 1159 WMI_TAG_ATH_DCS_CW_INT, 1160 WMI_TAG_WLAN_DCS_CW_INT = /* ALIAS */ 1161 WMI_TAG_ATH_DCS_CW_INT, 1162 WMI_TAG_ATH_DCS_WLAN_INT_STAT, 1163 WMI_TAG_WLAN_DCS_IM_TGT_STATS_T = /* ALIAS */ 1164 WMI_TAG_ATH_DCS_WLAN_INT_STAT, 1165 WMI_TAG_WLAN_PROFILE_CTX_T, 1166 WMI_TAG_WLAN_PROFILE_T, 1167 WMI_TAG_PDEV_QVIT_EVENT, 1168 WMI_TAG_HOST_SWBA_EVENT, 1169 WMI_TAG_TIM_INFO, 1170 WMI_TAG_P2P_NOA_INFO, 1171 WMI_TAG_STATS_EVENT, 1172 WMI_TAG_AVOID_FREQ_RANGES_EVENT, 1173 WMI_TAG_AVOID_FREQ_RANGE_DESC, 1174 WMI_TAG_GTK_REKEY_FAIL_EVENT, 1175 WMI_TAG_INIT_CMD, 1176 WMI_TAG_RESOURCE_CONFIG, 1177 WMI_TAG_WLAN_HOST_MEMORY_CHUNK, 1178 WMI_TAG_START_SCAN_CMD, 1179 WMI_TAG_STOP_SCAN_CMD, 1180 WMI_TAG_SCAN_CHAN_LIST_CMD, 1181 WMI_TAG_CHANNEL, 1182 WMI_TAG_PDEV_SET_REGDOMAIN_CMD, 1183 WMI_TAG_PDEV_SET_PARAM_CMD, 1184 WMI_TAG_PDEV_SET_WMM_PARAMS_CMD, 1185 WMI_TAG_WMM_PARAMS, 1186 WMI_TAG_PDEV_SET_QUIET_CMD, 1187 WMI_TAG_VDEV_CREATE_CMD, 1188 WMI_TAG_VDEV_DELETE_CMD, 1189 WMI_TAG_VDEV_START_REQUEST_CMD, 1190 WMI_TAG_P2P_NOA_DESCRIPTOR, 1191 WMI_TAG_P2P_GO_SET_BEACON_IE, 1192 WMI_TAG_GTK_OFFLOAD_CMD, 1193 WMI_TAG_VDEV_UP_CMD, 1194 WMI_TAG_VDEV_STOP_CMD, 1195 WMI_TAG_VDEV_DOWN_CMD, 1196 WMI_TAG_VDEV_SET_PARAM_CMD, 1197 WMI_TAG_VDEV_INSTALL_KEY_CMD, 1198 WMI_TAG_PEER_CREATE_CMD, 1199 WMI_TAG_PEER_DELETE_CMD, 1200 WMI_TAG_PEER_FLUSH_TIDS_CMD, 1201 WMI_TAG_PEER_SET_PARAM_CMD, 1202 WMI_TAG_PEER_ASSOC_COMPLETE_CMD, 1203 WMI_TAG_VHT_RATE_SET, 1204 WMI_TAG_BCN_TMPL_CMD, 1205 WMI_TAG_PRB_TMPL_CMD, 1206 WMI_TAG_BCN_PRB_INFO, 1207 WMI_TAG_PEER_TID_ADDBA_CMD, 1208 WMI_TAG_PEER_TID_DELBA_CMD, 1209 WMI_TAG_STA_POWERSAVE_MODE_CMD, 1210 WMI_TAG_STA_POWERSAVE_PARAM_CMD, 1211 WMI_TAG_STA_DTIM_PS_METHOD_CMD, 1212 WMI_TAG_ROAM_SCAN_MODE, 1213 WMI_TAG_ROAM_SCAN_RSSI_THRESHOLD, 1214 WMI_TAG_ROAM_SCAN_PERIOD, 1215 WMI_TAG_ROAM_SCAN_RSSI_CHANGE_THRESHOLD, 1216 WMI_TAG_PDEV_SUSPEND_CMD, 1217 WMI_TAG_PDEV_RESUME_CMD, 1218 WMI_TAG_ADD_BCN_FILTER_CMD, 1219 WMI_TAG_RMV_BCN_FILTER_CMD, 1220 WMI_TAG_WOW_ENABLE_CMD, 1221 WMI_TAG_WOW_HOSTWAKEUP_FROM_SLEEP_CMD, 1222 WMI_TAG_STA_UAPSD_AUTO_TRIG_CMD, 1223 WMI_TAG_STA_UAPSD_AUTO_TRIG_PARAM, 1224 WMI_TAG_SET_ARP_NS_OFFLOAD_CMD, 1225 WMI_TAG_ARP_OFFLOAD_TUPLE, 1226 WMI_TAG_NS_OFFLOAD_TUPLE, 1227 WMI_TAG_FTM_INTG_CMD, 1228 WMI_TAG_STA_KEEPALIVE_CMD, 1229 WMI_TAG_STA_KEEPALIVE_ARP_RESPONSE, 1230 WMI_TAG_P2P_SET_VENDOR_IE_DATA_CMD, 1231 WMI_TAG_AP_PS_PEER_CMD, 1232 WMI_TAG_PEER_RATE_RETRY_SCHED_CMD, 1233 WMI_TAG_WLAN_PROFILE_TRIGGER_CMD, 1234 WMI_TAG_WLAN_PROFILE_SET_HIST_INTVL_CMD, 1235 WMI_TAG_WLAN_PROFILE_GET_PROF_DATA_CMD, 1236 WMI_TAG_WLAN_PROFILE_ENABLE_PROFILE_ID_CMD, 1237 WMI_TAG_WOW_DEL_PATTERN_CMD, 1238 WMI_TAG_WOW_ADD_DEL_EVT_CMD, 1239 WMI_TAG_RTT_MEASREQ_HEAD, 1240 WMI_TAG_RTT_MEASREQ_BODY, 1241 WMI_TAG_RTT_TSF_CMD, 1242 WMI_TAG_VDEV_SPECTRAL_CONFIGURE_CMD, 1243 WMI_TAG_VDEV_SPECTRAL_ENABLE_CMD, 1244 WMI_TAG_REQUEST_STATS_CMD, 1245 WMI_TAG_NLO_CONFIG_CMD, 1246 WMI_TAG_NLO_CONFIGURED_PARAMETERS, 1247 WMI_TAG_CSA_OFFLOAD_ENABLE_CMD, 1248 WMI_TAG_CSA_OFFLOAD_CHANSWITCH_CMD, 1249 WMI_TAG_CHATTER_SET_MODE_CMD, 1250 WMI_TAG_ECHO_CMD, 1251 WMI_TAG_VDEV_SET_KEEPALIVE_CMD, 1252 WMI_TAG_VDEV_GET_KEEPALIVE_CMD, 1253 WMI_TAG_FORCE_FW_HANG_CMD, 1254 WMI_TAG_GPIO_CONFIG_CMD, 1255 WMI_TAG_GPIO_OUTPUT_CMD, 1256 WMI_TAG_PEER_ADD_WDS_ENTRY_CMD, 1257 WMI_TAG_PEER_REMOVE_WDS_ENTRY_CMD, 1258 WMI_TAG_BCN_TX_HDR, 1259 WMI_TAG_BCN_SEND_FROM_HOST_CMD, 1260 WMI_TAG_MGMT_TX_HDR, 1261 WMI_TAG_ADDBA_CLEAR_RESP_CMD, 1262 WMI_TAG_ADDBA_SEND_CMD, 1263 WMI_TAG_DELBA_SEND_CMD, 1264 WMI_TAG_ADDBA_SETRESPONSE_CMD, 1265 WMI_TAG_SEND_SINGLEAMSDU_CMD, 1266 WMI_TAG_PDEV_PKTLOG_ENABLE_CMD, 1267 WMI_TAG_PDEV_PKTLOG_DISABLE_CMD, 1268 WMI_TAG_PDEV_SET_HT_IE_CMD, 1269 WMI_TAG_PDEV_SET_VHT_IE_CMD, 1270 WMI_TAG_PDEV_SET_DSCP_TID_MAP_CMD, 1271 WMI_TAG_PDEV_GREEN_AP_PS_ENABLE_CMD, 1272 WMI_TAG_PDEV_GET_TPC_CONFIG_CMD, 1273 WMI_TAG_PDEV_SET_BASE_MACADDR_CMD, 1274 WMI_TAG_PEER_MCAST_GROUP_CMD, 1275 WMI_TAG_ROAM_AP_PROFILE, 1276 WMI_TAG_AP_PROFILE, 1277 WMI_TAG_SCAN_SCH_PRIORITY_TABLE_CMD, 1278 WMI_TAG_PDEV_DFS_ENABLE_CMD, 1279 WMI_TAG_PDEV_DFS_DISABLE_CMD, 1280 WMI_TAG_WOW_ADD_PATTERN_CMD, 1281 WMI_TAG_WOW_BITMAP_PATTERN_T, 1282 WMI_TAG_WOW_IPV4_SYNC_PATTERN_T, 1283 WMI_TAG_WOW_IPV6_SYNC_PATTERN_T, 1284 WMI_TAG_WOW_MAGIC_PATTERN_CMD, 1285 WMI_TAG_SCAN_UPDATE_REQUEST_CMD, 1286 WMI_TAG_CHATTER_PKT_COALESCING_FILTER, 1287 WMI_TAG_CHATTER_COALESCING_ADD_FILTER_CMD, 1288 WMI_TAG_CHATTER_COALESCING_DELETE_FILTER_CMD, 1289 WMI_TAG_CHATTER_COALESCING_QUERY_CMD, 1290 WMI_TAG_TXBF_CMD, 1291 WMI_TAG_DEBUG_LOG_CONFIG_CMD, 1292 WMI_TAG_NLO_EVENT, 1293 WMI_TAG_CHATTER_QUERY_REPLY_EVENT, 1294 WMI_TAG_UPLOAD_H_HDR, 1295 WMI_TAG_CAPTURE_H_EVENT_HDR, 1296 WMI_TAG_VDEV_WNM_SLEEPMODE_CMD, 1297 WMI_TAG_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMD, 1298 WMI_TAG_VDEV_WMM_ADDTS_CMD, 1299 WMI_TAG_VDEV_WMM_DELTS_CMD, 1300 WMI_TAG_VDEV_SET_WMM_PARAMS_CMD, 1301 WMI_TAG_TDLS_SET_STATE_CMD, 1302 WMI_TAG_TDLS_PEER_UPDATE_CMD, 1303 WMI_TAG_TDLS_PEER_EVENT, 1304 WMI_TAG_TDLS_PEER_CAPABILITIES, 1305 WMI_TAG_VDEV_MCC_SET_TBTT_MODE_CMD, 1306 WMI_TAG_ROAM_CHAN_LIST, 1307 WMI_TAG_VDEV_MCC_BCN_INTVL_CHANGE_EVENT, 1308 WMI_TAG_RESMGR_ADAPTIVE_OCS_ENABLE_DISABLE_CMD, 1309 WMI_TAG_RESMGR_SET_CHAN_TIME_QUOTA_CMD, 1310 WMI_TAG_RESMGR_SET_CHAN_LATENCY_CMD, 1311 WMI_TAG_BA_REQ_SSN_CMD, 1312 WMI_TAG_BA_RSP_SSN_EVENT, 1313 WMI_TAG_STA_SMPS_FORCE_MODE_CMD, 1314 WMI_TAG_SET_MCASTBCAST_FILTER_CMD, 1315 WMI_TAG_P2P_SET_OPPPS_CMD, 1316 WMI_TAG_P2P_SET_NOA_CMD, 1317 WMI_TAG_BA_REQ_SSN_CMD_SUB_STRUCT_PARAM, 1318 WMI_TAG_BA_REQ_SSN_EVENT_SUB_STRUCT_PARAM, 1319 WMI_TAG_STA_SMPS_PARAM_CMD, 1320 WMI_TAG_VDEV_SET_GTX_PARAMS_CMD, 1321 WMI_TAG_MCC_SCHED_TRAFFIC_STATS_CMD, 1322 WMI_TAG_MCC_SCHED_STA_TRAFFIC_STATS, 1323 WMI_TAG_OFFLOAD_BCN_TX_STATUS_EVENT, 1324 WMI_TAG_P2P_NOA_EVENT, 1325 WMI_TAG_HB_SET_ENABLE_CMD, 1326 WMI_TAG_HB_SET_TCP_PARAMS_CMD, 1327 WMI_TAG_HB_SET_TCP_PKT_FILTER_CMD, 1328 WMI_TAG_HB_SET_UDP_PARAMS_CMD, 1329 WMI_TAG_HB_SET_UDP_PKT_FILTER_CMD, 1330 WMI_TAG_HB_IND_EVENT, 1331 WMI_TAG_TX_PAUSE_EVENT, 1332 WMI_TAG_RFKILL_EVENT, 1333 WMI_TAG_DFS_RADAR_EVENT, 1334 WMI_TAG_DFS_PHYERR_FILTER_ENA_CMD, 1335 WMI_TAG_DFS_PHYERR_FILTER_DIS_CMD, 1336 WMI_TAG_BATCH_SCAN_RESULT_SCAN_LIST, 1337 WMI_TAG_BATCH_SCAN_RESULT_NETWORK_INFO, 1338 WMI_TAG_BATCH_SCAN_ENABLE_CMD, 1339 WMI_TAG_BATCH_SCAN_DISABLE_CMD, 1340 WMI_TAG_BATCH_SCAN_TRIGGER_RESULT_CMD, 1341 WMI_TAG_BATCH_SCAN_ENABLED_EVENT, 1342 WMI_TAG_BATCH_SCAN_RESULT_EVENT, 1343 WMI_TAG_VDEV_PLMREQ_START_CMD, 1344 WMI_TAG_VDEV_PLMREQ_STOP_CMD, 1345 WMI_TAG_THERMAL_MGMT_CMD, 1346 WMI_TAG_THERMAL_MGMT_EVENT, 1347 WMI_TAG_PEER_INFO_REQ_CMD, 1348 WMI_TAG_PEER_INFO_EVENT, 1349 WMI_TAG_PEER_INFO, 1350 WMI_TAG_PEER_TX_FAIL_CNT_THR_EVENT, 1351 WMI_TAG_RMC_SET_MODE_CMD, 1352 WMI_TAG_RMC_SET_ACTION_PERIOD_CMD, 1353 WMI_TAG_RMC_CONFIG_CMD, 1354 WMI_TAG_MHF_OFFLOAD_SET_MODE_CMD, 1355 WMI_TAG_MHF_OFFLOAD_PLUMB_ROUTING_TABLE_CMD, 1356 WMI_TAG_ADD_PROACTIVE_ARP_RSP_PATTERN_CMD, 1357 WMI_TAG_DEL_PROACTIVE_ARP_RSP_PATTERN_CMD, 1358 WMI_TAG_NAN_CMD_PARAM, 1359 WMI_TAG_NAN_EVENT_HDR, 1360 WMI_TAG_PDEV_L1SS_TRACK_EVENT, 1361 WMI_TAG_DIAG_DATA_CONTAINER_EVENT, 1362 WMI_TAG_MODEM_POWER_STATE_CMD_PARAM, 1363 WMI_TAG_PEER_GET_ESTIMATED_LINKSPEED_CMD, 1364 WMI_TAG_PEER_ESTIMATED_LINKSPEED_EVENT, 1365 WMI_TAG_AGGR_STATE_TRIG_EVENT, 1366 WMI_TAG_MHF_OFFLOAD_ROUTING_TABLE_ENTRY, 1367 WMI_TAG_ROAM_SCAN_CMD, 1368 WMI_TAG_REQ_STATS_EXT_CMD, 1369 WMI_TAG_STATS_EXT_EVENT, 1370 WMI_TAG_OBSS_SCAN_ENABLE_CMD, 1371 WMI_TAG_OBSS_SCAN_DISABLE_CMD, 1372 WMI_TAG_OFFLOAD_PRB_RSP_TX_STATUS_EVENT, 1373 WMI_TAG_PDEV_SET_LED_CONFIG_CMD, 1374 WMI_TAG_HOST_AUTO_SHUTDOWN_CFG_CMD, 1375 WMI_TAG_HOST_AUTO_SHUTDOWN_EVENT, 1376 WMI_TAG_UPDATE_WHAL_MIB_STATS_EVENT, 1377 WMI_TAG_CHAN_AVOID_UPDATE_CMD_PARAM, 1378 WMI_TAG_WOW_IOAC_PKT_PATTERN_T, 1379 WMI_TAG_WOW_IOAC_TMR_PATTERN_T, 1380 WMI_TAG_WOW_IOAC_ADD_KEEPALIVE_CMD, 1381 WMI_TAG_WOW_IOAC_DEL_KEEPALIVE_CMD, 1382 WMI_TAG_WOW_IOAC_KEEPALIVE_T, 1383 WMI_TAG_WOW_IOAC_ADD_PATTERN_CMD, 1384 WMI_TAG_WOW_IOAC_DEL_PATTERN_CMD, 1385 WMI_TAG_START_LINK_STATS_CMD, 1386 WMI_TAG_CLEAR_LINK_STATS_CMD, 1387 WMI_TAG_REQUEST_LINK_STATS_CMD, 1388 WMI_TAG_IFACE_LINK_STATS_EVENT, 1389 WMI_TAG_RADIO_LINK_STATS_EVENT, 1390 WMI_TAG_PEER_STATS_EVENT, 1391 WMI_TAG_CHANNEL_STATS, 1392 WMI_TAG_RADIO_LINK_STATS, 1393 WMI_TAG_RATE_STATS, 1394 WMI_TAG_PEER_LINK_STATS, 1395 WMI_TAG_WMM_AC_STATS, 1396 WMI_TAG_IFACE_LINK_STATS, 1397 WMI_TAG_LPI_MGMT_SNOOPING_CONFIG_CMD, 1398 WMI_TAG_LPI_START_SCAN_CMD, 1399 WMI_TAG_LPI_STOP_SCAN_CMD, 1400 WMI_TAG_LPI_RESULT_EVENT, 1401 WMI_TAG_PEER_STATE_EVENT, 1402 WMI_TAG_EXTSCAN_BUCKET_CMD, 1403 WMI_TAG_EXTSCAN_BUCKET_CHANNEL_EVENT, 1404 WMI_TAG_EXTSCAN_START_CMD, 1405 WMI_TAG_EXTSCAN_STOP_CMD, 1406 WMI_TAG_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMD, 1407 WMI_TAG_EXTSCAN_WLAN_CHANGE_BSSID_PARAM_CMD, 1408 WMI_TAG_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMD, 1409 WMI_TAG_EXTSCAN_GET_CACHED_RESULTS_CMD, 1410 WMI_TAG_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMD, 1411 WMI_TAG_EXTSCAN_SET_CAPABILITIES_CMD, 1412 WMI_TAG_EXTSCAN_GET_CAPABILITIES_CMD, 1413 WMI_TAG_EXTSCAN_OPERATION_EVENT, 1414 WMI_TAG_EXTSCAN_START_STOP_EVENT, 1415 WMI_TAG_EXTSCAN_TABLE_USAGE_EVENT, 1416 WMI_TAG_EXTSCAN_WLAN_DESCRIPTOR_EVENT, 1417 WMI_TAG_EXTSCAN_RSSI_INFO_EVENT, 1418 WMI_TAG_EXTSCAN_CACHED_RESULTS_EVENT, 1419 WMI_TAG_EXTSCAN_WLAN_CHANGE_RESULTS_EVENT, 1420 WMI_TAG_EXTSCAN_WLAN_CHANGE_RESULT_BSSID_EVENT, 1421 WMI_TAG_EXTSCAN_HOTLIST_MATCH_EVENT, 1422 WMI_TAG_EXTSCAN_CAPABILITIES_EVENT, 1423 WMI_TAG_EXTSCAN_CACHE_CAPABILITIES_EVENT, 1424 WMI_TAG_EXTSCAN_WLAN_CHANGE_MONITOR_CAPABILITIES_EVENT, 1425 WMI_TAG_EXTSCAN_HOTLIST_MONITOR_CAPABILITIES_EVENT, 1426 WMI_TAG_D0_WOW_ENABLE_DISABLE_CMD, 1427 WMI_TAG_D0_WOW_DISABLE_ACK_EVENT, 1428 WMI_TAG_UNIT_TEST_CMD, 1429 WMI_TAG_ROAM_OFFLOAD_TLV_PARAM, 1430 WMI_TAG_ROAM_11I_OFFLOAD_TLV_PARAM, 1431 WMI_TAG_ROAM_11R_OFFLOAD_TLV_PARAM, 1432 WMI_TAG_ROAM_ESE_OFFLOAD_TLV_PARAM, 1433 WMI_TAG_ROAM_SYNCH_EVENT, 1434 WMI_TAG_ROAM_SYNCH_COMPLETE, 1435 WMI_TAG_EXTWOW_ENABLE_CMD, 1436 WMI_TAG_EXTWOW_SET_APP_TYPE1_PARAMS_CMD, 1437 WMI_TAG_EXTWOW_SET_APP_TYPE2_PARAMS_CMD, 1438 WMI_TAG_LPI_STATUS_EVENT, 1439 WMI_TAG_LPI_HANDOFF_EVENT, 1440 WMI_TAG_VDEV_RATE_STATS_EVENT, 1441 WMI_TAG_VDEV_RATE_HT_INFO, 1442 WMI_TAG_RIC_REQUEST, 1443 WMI_TAG_PDEV_GET_TEMPERATURE_CMD, 1444 WMI_TAG_PDEV_TEMPERATURE_EVENT, 1445 WMI_TAG_SET_DHCP_SERVER_OFFLOAD_CMD, 1446 WMI_TAG_TPC_CHAINMASK_CONFIG_CMD, 1447 WMI_TAG_RIC_TSPEC, 1448 WMI_TAG_TPC_CHAINMASK_CONFIG, 1449 WMI_TAG_IPA_OFFLOAD_ENABLE_DISABLE_CMD, 1450 WMI_TAG_SCAN_PROB_REQ_OUI_CMD, 1451 WMI_TAG_KEY_MATERIAL, 1452 WMI_TAG_TDLS_SET_OFFCHAN_MODE_CMD, 1453 WMI_TAG_SET_LED_FLASHING_CMD, 1454 WMI_TAG_MDNS_OFFLOAD_CMD, 1455 WMI_TAG_MDNS_SET_FQDN_CMD, 1456 WMI_TAG_MDNS_SET_RESP_CMD, 1457 WMI_TAG_MDNS_GET_STATS_CMD, 1458 WMI_TAG_MDNS_STATS_EVENT, 1459 WMI_TAG_ROAM_INVOKE_CMD, 1460 WMI_TAG_PDEV_RESUME_EVENT, 1461 WMI_TAG_PDEV_SET_ANTENNA_DIVERSITY_CMD, 1462 WMI_TAG_SAP_OFL_ENABLE_CMD, 1463 WMI_TAG_SAP_OFL_ADD_STA_EVENT, 1464 WMI_TAG_SAP_OFL_DEL_STA_EVENT, 1465 WMI_TAG_APFIND_CMD_PARAM, 1466 WMI_TAG_APFIND_EVENT_HDR, 1467 WMI_TAG_OCB_SET_SCHED_CMD, 1468 WMI_TAG_OCB_SET_SCHED_EVENT, 1469 WMI_TAG_OCB_SET_CONFIG_CMD, 1470 WMI_TAG_OCB_SET_CONFIG_RESP_EVENT, 1471 WMI_TAG_OCB_SET_UTC_TIME_CMD, 1472 WMI_TAG_OCB_START_TIMING_ADVERT_CMD, 1473 WMI_TAG_OCB_STOP_TIMING_ADVERT_CMD, 1474 WMI_TAG_OCB_GET_TSF_TIMER_CMD, 1475 WMI_TAG_OCB_GET_TSF_TIMER_RESP_EVENT, 1476 WMI_TAG_DCC_GET_STATS_CMD, 1477 WMI_TAG_DCC_CHANNEL_STATS_REQUEST, 1478 WMI_TAG_DCC_GET_STATS_RESP_EVENT, 1479 WMI_TAG_DCC_CLEAR_STATS_CMD, 1480 WMI_TAG_DCC_UPDATE_NDL_CMD, 1481 WMI_TAG_DCC_UPDATE_NDL_RESP_EVENT, 1482 WMI_TAG_DCC_STATS_EVENT, 1483 WMI_TAG_OCB_CHANNEL, 1484 WMI_TAG_OCB_SCHEDULE_ELEMENT, 1485 WMI_TAG_DCC_NDL_STATS_PER_CHANNEL, 1486 WMI_TAG_DCC_NDL_CHAN, 1487 WMI_TAG_QOS_PARAMETER, 1488 WMI_TAG_DCC_NDL_ACTIVE_STATE_CONFIG, 1489 WMI_TAG_ROAM_SCAN_EXTENDED_THRESHOLD_PARAM, 1490 WMI_TAG_ROAM_FILTER, 1491 WMI_TAG_PASSPOINT_CONFIG_CMD, 1492 WMI_TAG_PASSPOINT_EVENT_HDR, 1493 WMI_TAG_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMD, 1494 WMI_TAG_EXTSCAN_HOTLIST_SSID_MATCH_EVENT, 1495 WMI_TAG_VDEV_TSF_TSTAMP_ACTION_CMD, 1496 WMI_TAG_VDEV_TSF_REPORT_EVENT, 1497 WMI_TAG_GET_FW_MEM_DUMP, 1498 WMI_TAG_UPDATE_FW_MEM_DUMP, 1499 WMI_TAG_FW_MEM_DUMP_PARAMS, 1500 WMI_TAG_DEBUG_MESG_FLUSH, 1501 WMI_TAG_DEBUG_MESG_FLUSH_COMPLETE, 1502 WMI_TAG_PEER_SET_RATE_REPORT_CONDITION, 1503 WMI_TAG_ROAM_SUBNET_CHANGE_CONFIG, 1504 WMI_TAG_VDEV_SET_IE_CMD, 1505 WMI_TAG_RSSI_BREACH_MONITOR_CONFIG, 1506 WMI_TAG_RSSI_BREACH_EVENT, 1507 WMI_TAG_WOW_EVENT_INITIAL_WAKEUP, 1508 WMI_TAG_SOC_SET_PCL_CMD, 1509 WMI_TAG_SOC_SET_HW_MODE_CMD, 1510 WMI_TAG_SOC_SET_HW_MODE_RESPONSE_EVENT, 1511 WMI_TAG_SOC_HW_MODE_TRANSITION_EVENT, 1512 WMI_TAG_VDEV_TXRX_STREAMS, 1513 WMI_TAG_SOC_SET_HW_MODE_RESPONSE_VDEV_MAC_ENTRY, 1514 WMI_TAG_SOC_SET_DUAL_MAC_CONFIG_CMD, 1515 WMI_TAG_SOC_SET_DUAL_MAC_CONFIG_RESPONSE_EVENT, 1516 WMI_TAG_WOW_IOAC_SOCK_PATTERN_T, 1517 WMI_TAG_WOW_ENABLE_ICMPV6_NA_FLT_CMD, 1518 WMI_TAG_DIAG_EVENT_LOG_CONFIG, 1519 WMI_TAG_DIAG_EVENT_LOG_SUPPORTED_EVENT_FIXED_PARAMS, 1520 WMI_TAG_PACKET_FILTER_CONFIG, 1521 WMI_TAG_PACKET_FILTER_ENABLE, 1522 WMI_TAG_SAP_SET_BLACKLIST_PARAM_CMD, 1523 WMI_TAG_MGMT_TX_SEND_CMD, 1524 WMI_TAG_MGMT_TX_COMPL_EVENT, 1525 WMI_TAG_SOC_SET_ANTENNA_MODE_CMD, 1526 WMI_TAG_WOW_UDP_SVC_OFLD_CMD, 1527 WMI_TAG_LRO_INFO_CMD, 1528 WMI_TAG_ROAM_EARLYSTOP_RSSI_THRES_PARAM, 1529 WMI_TAG_SERVICE_READY_EXT_EVENT, 1530 WMI_TAG_MAWC_SENSOR_REPORT_IND_CMD, 1531 WMI_TAG_MAWC_ENABLE_SENSOR_EVENT, 1532 WMI_TAG_ROAM_CONFIGURE_MAWC_CMD, 1533 WMI_TAG_NLO_CONFIGURE_MAWC_CMD, 1534 WMI_TAG_EXTSCAN_CONFIGURE_MAWC_CMD, 1535 WMI_TAG_PEER_ASSOC_CONF_EVENT, 1536 WMI_TAG_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMD, 1537 WMI_TAG_AP_PS_EGAP_PARAM_CMD, 1538 WMI_TAG_AP_PS_EGAP_INFO_EVENT, 1539 WMI_TAG_PMF_OFFLOAD_SET_SA_QUERY_CMD, 1540 WMI_TAG_TRANSFER_DATA_TO_FLASH_CMD, 1541 WMI_TAG_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENT, 1542 WMI_TAG_SCPC_EVENT, 1543 WMI_TAG_AP_PS_EGAP_INFO_CHAINMASK_LIST, 1544 WMI_TAG_STA_SMPS_FORCE_MODE_COMPLETE_EVENT, 1545 WMI_TAG_BPF_GET_CAPABILITY_CMD, 1546 WMI_TAG_BPF_CAPABILITY_INFO_EVT, 1547 WMI_TAG_BPF_GET_VDEV_STATS_CMD, 1548 WMI_TAG_BPF_VDEV_STATS_INFO_EVT, 1549 WMI_TAG_BPF_SET_VDEV_INSTRUCTIONS_CMD, 1550 WMI_TAG_BPF_DEL_VDEV_INSTRUCTIONS_CMD, 1551 WMI_TAG_VDEV_DELETE_RESP_EVENT, 1552 WMI_TAG_PEER_DELETE_RESP_EVENT, 1553 WMI_TAG_ROAM_DENSE_THRES_PARAM, 1554 WMI_TAG_ENLO_CANDIDATE_SCORE_PARAM, 1555 WMI_TAG_PEER_UPDATE_WDS_ENTRY_CMD, 1556 WMI_TAG_VDEV_CONFIG_RATEMASK, 1557 WMI_TAG_PDEV_FIPS_CMD, 1558 WMI_TAG_PDEV_SMART_ANT_ENABLE_CMD, 1559 WMI_TAG_PDEV_SMART_ANT_SET_RX_ANTENNA_CMD, 1560 WMI_TAG_PEER_SMART_ANT_SET_TX_ANTENNA_CMD, 1561 WMI_TAG_PEER_SMART_ANT_SET_TRAIN_ANTENNA_CMD, 1562 WMI_TAG_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMD, 1563 WMI_TAG_PDEV_SET_ANT_SWITCH_TBL_CMD, 1564 WMI_TAG_PDEV_SET_CTL_TABLE_CMD, 1565 WMI_TAG_PDEV_SET_MIMOGAIN_TABLE_CMD, 1566 WMI_TAG_FWTEST_SET_PARAM_CMD, 1567 WMI_TAG_PEER_ATF_REQUEST, 1568 WMI_TAG_VDEV_ATF_REQUEST, 1569 WMI_TAG_PDEV_GET_ANI_CCK_CONFIG_CMD, 1570 WMI_TAG_PDEV_GET_ANI_OFDM_CONFIG_CMD, 1571 WMI_TAG_INST_RSSI_STATS_RESP, 1572 WMI_TAG_MED_UTIL_REPORT_EVENT, 1573 WMI_TAG_PEER_STA_PS_STATECHANGE_EVENT, 1574 WMI_TAG_WDS_ADDR_EVENT, 1575 WMI_TAG_PEER_RATECODE_LIST_EVENT, 1576 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENT, 1577 WMI_TAG_PDEV_TPC_EVENT, 1578 WMI_TAG_ANI_OFDM_EVENT, 1579 WMI_TAG_ANI_CCK_EVENT, 1580 WMI_TAG_PDEV_CHANNEL_HOPPING_EVENT, 1581 WMI_TAG_PDEV_FIPS_EVENT, 1582 WMI_TAG_ATF_PEER_INFO, 1583 WMI_TAG_PDEV_GET_TPC_CMD, 1584 WMI_TAG_VDEV_FILTER_NRP_CONFIG_CMD, 1585 WMI_TAG_QBOOST_CFG_CMD, 1586 WMI_TAG_PDEV_SMART_ANT_GPIO_HANDLE, 1587 WMI_TAG_PEER_SMART_ANT_SET_TX_ANTENNA_SERIES, 1588 WMI_TAG_PEER_SMART_ANT_SET_TRAIN_ANTENNA_PARAM, 1589 WMI_TAG_PDEV_SET_ANT_CTRL_CHAIN, 1590 WMI_TAG_PEER_CCK_OFDM_RATE_INFO, 1591 WMI_TAG_PEER_MCS_RATE_INFO, 1592 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_NFDBR, 1593 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_NFDBM, 1594 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_FREQNUM, 1595 WMI_TAG_MU_REPORT_TOTAL_MU, 1596 WMI_TAG_VDEV_SET_DSCP_TID_MAP_CMD, 1597 WMI_TAG_ROAM_SET_MBO, 1598 WMI_TAG_MIB_STATS_ENABLE_CMD, 1599 WMI_TAG_NAN_DISC_IFACE_CREATED_EVENT, 1600 WMI_TAG_NAN_DISC_IFACE_DELETED_EVENT, 1601 WMI_TAG_NAN_STARTED_CLUSTER_EVENT, 1602 WMI_TAG_NAN_JOINED_CLUSTER_EVENT, 1603 WMI_TAG_NDI_GET_CAP_REQ, 1604 WMI_TAG_NDP_INITIATOR_REQ, 1605 WMI_TAG_NDP_RESPONDER_REQ, 1606 WMI_TAG_NDP_END_REQ, 1607 WMI_TAG_NDI_CAP_RSP_EVENT, 1608 WMI_TAG_NDP_INITIATOR_RSP_EVENT, 1609 WMI_TAG_NDP_RESPONDER_RSP_EVENT, 1610 WMI_TAG_NDP_END_RSP_EVENT, 1611 WMI_TAG_NDP_INDICATION_EVENT, 1612 WMI_TAG_NDP_CONFIRM_EVENT, 1613 WMI_TAG_NDP_END_INDICATION_EVENT, 1614 WMI_TAG_VDEV_SET_QUIET_CMD, 1615 WMI_TAG_PDEV_SET_PCL_CMD, 1616 WMI_TAG_PDEV_SET_HW_MODE_CMD, 1617 WMI_TAG_PDEV_SET_MAC_CONFIG_CMD, 1618 WMI_TAG_PDEV_SET_ANTENNA_MODE_CMD, 1619 WMI_TAG_PDEV_SET_HW_MODE_RESPONSE_EVENT, 1620 WMI_TAG_PDEV_HW_MODE_TRANSITION_EVENT, 1621 WMI_TAG_PDEV_SET_HW_MODE_RESPONSE_VDEV_MAC_ENTRY, 1622 WMI_TAG_PDEV_SET_MAC_CONFIG_RESPONSE_EVENT, 1623 WMI_TAG_COEX_CONFIG_CMD, 1624 WMI_TAG_CONFIG_ENHANCED_MCAST_FILTER, 1625 WMI_TAG_CHAN_AVOID_RPT_ALLOW_CMD, 1626 WMI_TAG_SET_PERIODIC_CHANNEL_STATS_CONFIG, 1627 WMI_TAG_VDEV_SET_CUSTOM_AGGR_SIZE_CMD, 1628 WMI_TAG_PDEV_WAL_POWER_DEBUG_CMD, 1629 WMI_TAG_MAC_PHY_CAPABILITIES, 1630 WMI_TAG_HW_MODE_CAPABILITIES, 1631 WMI_TAG_SOC_MAC_PHY_HW_MODE_CAPS, 1632 WMI_TAG_HAL_REG_CAPABILITIES_EXT, 1633 WMI_TAG_SOC_HAL_REG_CAPABILITIES, 1634 WMI_TAG_VDEV_WISA_CMD, 1635 WMI_TAG_TX_POWER_LEVEL_STATS_EVT, 1636 WMI_TAG_SCAN_ADAPTIVE_DWELL_PARAMETERS_TLV, 1637 WMI_TAG_SCAN_ADAPTIVE_DWELL_CONFIG, 1638 WMI_TAG_WOW_SET_ACTION_WAKE_UP_CMD, 1639 WMI_TAG_NDP_END_RSP_PER_NDI, 1640 WMI_TAG_PEER_BWF_REQUEST, 1641 WMI_TAG_BWF_PEER_INFO, 1642 WMI_TAG_DBGLOG_TIME_STAMP_SYNC_CMD, 1643 WMI_TAG_RMC_SET_LEADER_CMD, 1644 WMI_TAG_RMC_MANUAL_LEADER_EVENT, 1645 WMI_TAG_PER_CHAIN_RSSI_STATS, 1646 WMI_TAG_RSSI_STATS, 1647 WMI_TAG_P2P_LO_START_CMD, 1648 WMI_TAG_P2P_LO_STOP_CMD, 1649 WMI_TAG_P2P_LO_STOPPED_EVENT, 1650 WMI_TAG_REORDER_QUEUE_SETUP_CMD, 1651 WMI_TAG_REORDER_QUEUE_REMOVE_CMD, 1652 WMI_TAG_SET_MULTIPLE_MCAST_FILTER_CMD, 1653 WMI_TAG_MGMT_TX_COMPL_BUNDLE_EVENT, 1654 WMI_TAG_READ_DATA_FROM_FLASH_CMD, 1655 WMI_TAG_READ_DATA_FROM_FLASH_EVENT, 1656 WMI_TAG_PDEV_SET_REORDER_TIMEOUT_VAL_CMD, 1657 WMI_TAG_PEER_SET_RX_BLOCKSIZE_CMD, 1658 WMI_TAG_PDEV_SET_WAKEUP_CONFIG_CMDID, 1659 WMI_TAG_TLV_BUF_LEN_PARAM, 1660 WMI_TAG_SERVICE_AVAILABLE_EVENT, 1661 WMI_TAG_PEER_ANTDIV_INFO_REQ_CMD, 1662 WMI_TAG_PEER_ANTDIV_INFO_EVENT, 1663 WMI_TAG_PEER_ANTDIV_INFO, 1664 WMI_TAG_PDEV_GET_ANTDIV_STATUS_CMD, 1665 WMI_TAG_PDEV_ANTDIV_STATUS_EVENT, 1666 WMI_TAG_MNT_FILTER_CMD, 1667 WMI_TAG_GET_CHIP_POWER_STATS_CMD, 1668 WMI_TAG_PDEV_CHIP_POWER_STATS_EVENT, 1669 WMI_TAG_COEX_GET_ANTENNA_ISOLATION_CMD, 1670 WMI_TAG_COEX_REPORT_ISOLATION_EVENT, 1671 WMI_TAG_CHAN_CCA_STATS, 1672 WMI_TAG_PEER_SIGNAL_STATS, 1673 WMI_TAG_TX_STATS, 1674 WMI_TAG_PEER_AC_TX_STATS, 1675 WMI_TAG_RX_STATS, 1676 WMI_TAG_PEER_AC_RX_STATS, 1677 WMI_TAG_REPORT_STATS_EVENT, 1678 WMI_TAG_CHAN_CCA_STATS_THRESH, 1679 WMI_TAG_PEER_SIGNAL_STATS_THRESH, 1680 WMI_TAG_TX_STATS_THRESH, 1681 WMI_TAG_RX_STATS_THRESH, 1682 WMI_TAG_PDEV_SET_STATS_THRESHOLD_CMD, 1683 WMI_TAG_REQUEST_WLAN_STATS_CMD, 1684 WMI_TAG_RX_AGGR_FAILURE_EVENT, 1685 WMI_TAG_RX_AGGR_FAILURE_INFO, 1686 WMI_TAG_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMD, 1687 WMI_TAG_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENT, 1688 WMI_TAG_PDEV_BAND_TO_MAC, 1689 WMI_TAG_TBTT_OFFSET_INFO, 1690 WMI_TAG_TBTT_OFFSET_EXT_EVENT, 1691 WMI_TAG_SAR_LIMITS_CMD, 1692 WMI_TAG_SAR_LIMIT_CMD_ROW, 1693 WMI_TAG_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMD, 1694 WMI_TAG_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMD, 1695 WMI_TAG_VDEV_ADFS_CH_CFG_CMD, 1696 WMI_TAG_VDEV_ADFS_OCAC_ABORT_CMD, 1697 WMI_TAG_PDEV_DFS_RADAR_DETECTION_EVENT, 1698 WMI_TAG_VDEV_ADFS_OCAC_COMPLETE_EVENT, 1699 WMI_TAG_VDEV_DFS_CAC_COMPLETE_EVENT, 1700 WMI_TAG_VENDOR_OUI, 1701 WMI_TAG_REQUEST_RCPI_CMD, 1702 WMI_TAG_UPDATE_RCPI_EVENT, 1703 WMI_TAG_REQUEST_PEER_STATS_INFO_CMD, 1704 WMI_TAG_PEER_STATS_INFO, 1705 WMI_TAG_PEER_STATS_INFO_EVENT, 1706 WMI_TAG_PKGID_EVENT, 1707 WMI_TAG_CONNECTED_NLO_RSSI_PARAMS, 1708 WMI_TAG_SET_CURRENT_COUNTRY_CMD, 1709 WMI_TAG_REGULATORY_RULE_STRUCT, 1710 WMI_TAG_REG_CHAN_LIST_CC_EVENT, 1711 WMI_TAG_11D_SCAN_START_CMD, 1712 WMI_TAG_11D_SCAN_STOP_CMD, 1713 WMI_TAG_11D_NEW_COUNTRY_EVENT, 1714 WMI_TAG_REQUEST_RADIO_CHAN_STATS_CMD, 1715 WMI_TAG_RADIO_CHAN_STATS, 1716 WMI_TAG_RADIO_CHAN_STATS_EVENT, 1717 WMI_TAG_ROAM_PER_CONFIG, 1718 WMI_TAG_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_CMD, 1719 WMI_TAG_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_STATUS_EVENT, 1720 WMI_TAG_BPF_SET_VDEV_ACTIVE_MODE_CMD, 1721 WMI_TAG_HW_DATA_FILTER_CMD, 1722 WMI_TAG_CONNECTED_NLO_BSS_BAND_RSSI_PREF, 1723 WMI_TAG_PEER_OPER_MODE_CHANGE_EVENT, 1724 WMI_TAG_CHIP_POWER_SAVE_FAILURE_DETECTED, 1725 WMI_TAG_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMD, 1726 WMI_TAG_PDEV_CSA_SWITCH_COUNT_STATUS_EVENT, 1727 WMI_TAG_PDEV_UPDATE_PKT_ROUTING_CMD, 1728 WMI_TAG_PDEV_CHECK_CAL_VERSION_CMD, 1729 WMI_TAG_PDEV_CHECK_CAL_VERSION_EVENT, 1730 WMI_TAG_PDEV_SET_DIVERSITY_GAIN_CMD, 1731 WMI_TAG_MAC_PHY_CHAINMASK_COMBO, 1732 WMI_TAG_MAC_PHY_CHAINMASK_CAPABILITY, 1733 WMI_TAG_VDEV_SET_ARP_STATS_CMD, 1734 WMI_TAG_VDEV_GET_ARP_STATS_CMD, 1735 WMI_TAG_VDEV_GET_ARP_STATS_EVENT, 1736 WMI_TAG_IFACE_OFFLOAD_STATS, 1737 WMI_TAG_REQUEST_STATS_CMD_SUB_STRUCT_PARAM, 1738 WMI_TAG_RSSI_CTL_EXT, 1739 WMI_TAG_SINGLE_PHYERR_EXT_RX_HDR, 1740 WMI_TAG_COEX_BT_ACTIVITY_EVENT, 1741 WMI_TAG_VDEV_GET_TX_POWER_CMD, 1742 WMI_TAG_VDEV_TX_POWER_EVENT, 1743 WMI_TAG_OFFCHAN_DATA_TX_COMPL_EVENT, 1744 WMI_TAG_OFFCHAN_DATA_TX_SEND_CMD, 1745 WMI_TAG_TX_SEND_PARAMS, 1746 WMI_TAG_HE_RATE_SET, 1747 WMI_TAG_CONGESTION_STATS, 1748 WMI_TAG_SET_INIT_COUNTRY_CMD, 1749 WMI_TAG_SCAN_DBS_DUTY_CYCLE, 1750 WMI_TAG_SCAN_DBS_DUTY_CYCLE_PARAM_TLV, 1751 WMI_TAG_PDEV_DIV_GET_RSSI_ANTID, 1752 WMI_TAG_THERM_THROT_CONFIG_REQUEST, 1753 WMI_TAG_THERM_THROT_LEVEL_CONFIG_INFO, 1754 WMI_TAG_THERM_THROT_STATS_EVENT, 1755 WMI_TAG_THERM_THROT_LEVEL_STATS_INFO, 1756 WMI_TAG_PDEV_DIV_RSSI_ANTID_EVENT, 1757 WMI_TAG_OEM_DMA_RING_CAPABILITIES, 1758 WMI_TAG_OEM_DMA_RING_CFG_REQ, 1759 WMI_TAG_OEM_DMA_RING_CFG_RSP, 1760 WMI_TAG_OEM_INDIRECT_DATA, 1761 WMI_TAG_OEM_DMA_BUF_RELEASE, 1762 WMI_TAG_OEM_DMA_BUF_RELEASE_ENTRY, 1763 WMI_TAG_PDEV_BSS_CHAN_INFO_REQUEST, 1764 WMI_TAG_PDEV_BSS_CHAN_INFO_EVENT, 1765 WMI_TAG_ROAM_LCA_DISALLOW_CONFIG, 1766 WMI_TAG_VDEV_LIMIT_OFFCHAN_CMD, 1767 WMI_TAG_ROAM_RSSI_REJECTION_OCE_CONFIG, 1768 WMI_TAG_UNIT_TEST_EVENT, 1769 WMI_TAG_ROAM_FILS_OFFLOAD, 1770 WMI_TAG_PDEV_UPDATE_PMK_CACHE_CMD, 1771 WMI_TAG_PMK_CACHE, 1772 WMI_TAG_PDEV_UPDATE_FILS_HLP_PKT_CMD, 1773 WMI_TAG_ROAM_FILS_SYNCH, 1774 WMI_TAG_GTK_OFFLOAD_EXTENDED, 1775 WMI_TAG_ROAM_BG_SCAN_ROAMING, 1776 WMI_TAG_OIC_PING_OFFLOAD_PARAMS_CMD, 1777 WMI_TAG_OIC_PING_OFFLOAD_SET_ENABLE_CMD, 1778 WMI_TAG_OIC_PING_HANDOFF_EVENT, 1779 WMI_TAG_DHCP_LEASE_RENEW_OFFLOAD_CMD, 1780 WMI_TAG_DHCP_LEASE_RENEW_EVENT, 1781 WMI_TAG_BTM_CONFIG, 1782 WMI_TAG_DEBUG_MESG_FW_DATA_STALL, 1783 WMI_TAG_WLM_CONFIG_CMD, 1784 WMI_TAG_PDEV_UPDATE_CTLTABLE_REQUEST, 1785 WMI_TAG_PDEV_UPDATE_CTLTABLE_EVENT, 1786 WMI_TAG_ROAM_CND_SCORING_PARAM, 1787 WMI_TAG_PDEV_CONFIG_VENDOR_OUI_ACTION, 1788 WMI_TAG_VENDOR_OUI_EXT, 1789 WMI_TAG_ROAM_SYNCH_FRAME_EVENT, 1790 WMI_TAG_FD_SEND_FROM_HOST_CMD, 1791 WMI_TAG_ENABLE_FILS_CMD, 1792 WMI_TAG_HOST_SWFDA_EVENT, 1793 WMI_TAG_BCN_OFFLOAD_CTRL_CMD, 1794 WMI_TAG_PDEV_SET_AC_TX_QUEUE_OPTIMIZED_CMD, 1795 WMI_TAG_STATS_PERIOD, 1796 WMI_TAG_NDL_SCHEDULE_UPDATE, 1797 WMI_TAG_PEER_TID_MSDUQ_QDEPTH_THRESH_UPDATE_CMD, 1798 WMI_TAG_MSDUQ_QDEPTH_THRESH_UPDATE, 1799 WMI_TAG_PDEV_SET_RX_FILTER_PROMISCUOUS_CMD, 1800 WMI_TAG_SAR2_RESULT_EVENT, 1801 WMI_TAG_SAR_CAPABILITIES, 1802 WMI_TAG_SAP_OBSS_DETECTION_CFG_CMD, 1803 WMI_TAG_SAP_OBSS_DETECTION_INFO_EVT, 1804 WMI_TAG_DMA_RING_CAPABILITIES, 1805 WMI_TAG_DMA_RING_CFG_REQ, 1806 WMI_TAG_DMA_RING_CFG_RSP, 1807 WMI_TAG_DMA_BUF_RELEASE, 1808 WMI_TAG_DMA_BUF_RELEASE_ENTRY, 1809 WMI_TAG_SAR_GET_LIMITS_CMD, 1810 WMI_TAG_SAR_GET_LIMITS_EVENT, 1811 WMI_TAG_SAR_GET_LIMITS_EVENT_ROW, 1812 WMI_TAG_OFFLOAD_11K_REPORT, 1813 WMI_TAG_INVOKE_NEIGHBOR_REPORT, 1814 WMI_TAG_NEIGHBOR_REPORT_OFFLOAD, 1815 WMI_TAG_VDEV_SET_CONNECTIVITY_CHECK_STATS, 1816 WMI_TAG_VDEV_GET_CONNECTIVITY_CHECK_STATS, 1817 WMI_TAG_BPF_SET_VDEV_ENABLE_CMD, 1818 WMI_TAG_BPF_SET_VDEV_WORK_MEMORY_CMD, 1819 WMI_TAG_BPF_GET_VDEV_WORK_MEMORY_CMD, 1820 WMI_TAG_BPF_GET_VDEV_WORK_MEMORY_RESP_EVT, 1821 WMI_TAG_PDEV_GET_NFCAL_POWER, 1822 WMI_TAG_BSS_COLOR_CHANGE_ENABLE, 1823 WMI_TAG_OBSS_COLOR_COLLISION_DET_CONFIG, 1824 WMI_TAG_OBSS_COLOR_COLLISION_EVT, 1825 WMI_TAG_RUNTIME_DPD_RECAL_CMD, 1826 WMI_TAG_TWT_ENABLE_CMD, 1827 WMI_TAG_TWT_DISABLE_CMD, 1828 WMI_TAG_TWT_ADD_DIALOG_CMD, 1829 WMI_TAG_TWT_DEL_DIALOG_CMD, 1830 WMI_TAG_TWT_PAUSE_DIALOG_CMD, 1831 WMI_TAG_TWT_RESUME_DIALOG_CMD, 1832 WMI_TAG_TWT_ENABLE_COMPLETE_EVENT, 1833 WMI_TAG_TWT_DISABLE_COMPLETE_EVENT, 1834 WMI_TAG_TWT_ADD_DIALOG_COMPLETE_EVENT, 1835 WMI_TAG_TWT_DEL_DIALOG_COMPLETE_EVENT, 1836 WMI_TAG_TWT_PAUSE_DIALOG_COMPLETE_EVENT, 1837 WMI_TAG_TWT_RESUME_DIALOG_COMPLETE_EVENT, 1838 WMI_TAG_REQUEST_ROAM_SCAN_STATS_CMD, 1839 WMI_TAG_ROAM_SCAN_STATS_EVENT, 1840 WMI_TAG_PEER_TID_CONFIGURATIONS_CMD, 1841 WMI_TAG_VDEV_SET_CUSTOM_SW_RETRY_TH_CMD, 1842 WMI_TAG_GET_TPC_POWER_CMD, 1843 WMI_TAG_GET_TPC_POWER_EVENT, 1844 WMI_TAG_DMA_BUF_RELEASE_SPECTRAL_META_DATA, 1845 WMI_TAG_MOTION_DET_CONFIG_PARAMS_CMD, 1846 WMI_TAG_MOTION_DET_BASE_LINE_CONFIG_PARAMS_CMD, 1847 WMI_TAG_MOTION_DET_START_STOP_CMD, 1848 WMI_TAG_MOTION_DET_BASE_LINE_START_STOP_CMD, 1849 WMI_TAG_MOTION_DET_EVENT, 1850 WMI_TAG_MOTION_DET_BASE_LINE_EVENT, 1851 WMI_TAG_NDP_TRANSPORT_IP, 1852 WMI_TAG_OBSS_SPATIAL_REUSE_SET_CMD, 1853 WMI_TAG_ESP_ESTIMATE_EVENT, 1854 WMI_TAG_NAN_HOST_CONFIG, 1855 WMI_TAG_SPECTRAL_BIN_SCALING_PARAMS, 1856 WMI_TAG_PEER_CFR_CAPTURE_CMD, 1857 WMI_TAG_PEER_CHAN_WIDTH_SWITCH_CMD, 1858 WMI_TAG_CHAN_WIDTH_PEER_LIST, 1859 WMI_TAG_OBSS_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMD, 1860 WMI_TAG_PDEV_HE_TB_ACTION_FRM_CMD, 1861 WMI_TAG_PEER_EXTD2_STATS, 1862 WMI_TAG_HPCS_PULSE_START_CMD, 1863 WMI_TAG_PDEV_CTL_FAILSAFE_CHECK_EVENT, 1864 WMI_TAG_VDEV_CHAINMASK_CONFIG_CMD, 1865 WMI_TAG_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMD, 1866 WMI_TAG_NAN_EVENT_INFO, 1867 WMI_TAG_NDP_CHANNEL_INFO, 1868 WMI_TAG_NDP_CMD, 1869 WMI_TAG_NDP_EVENT, 1870 WMI_TAG_PDEV_PEER_PKTLOG_FILTER_CMD = 0x301, 1871 WMI_TAG_PDEV_PEER_PKTLOG_FILTER_INFO, 1872 WMI_TAG_FILS_DISCOVERY_TMPL_CMD = 0x344, 1873 WMI_TAG_PDEV_SRG_BSS_COLOR_BITMAP_CMD = 0x37b, 1874 WMI_TAG_PDEV_SRG_PARTIAL_BSSID_BITMAP_CMD, 1875 WMI_TAG_PDEV_SRG_OBSS_COLOR_ENABLE_BITMAP_CMD = 0x381, 1876 WMI_TAG_PDEV_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD, 1877 WMI_TAG_PDEV_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMD, 1878 WMI_TAG_PDEV_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD, 1879 WMI_TAG_REGULATORY_RULE_EXT_STRUCT = 0x3A9, 1880 WMI_TAG_REG_CHAN_LIST_CC_EXT_EVENT, 1881 WMI_TAG_PDEV_SET_BIOS_SAR_TABLE_CMD = 0x3D8, 1882 WMI_TAG_PDEV_SET_BIOS_GEO_TABLE_CMD, 1883 WMI_TAG_MAX 1884 }; 1885 1886 enum wmi_tlv_service { 1887 WMI_TLV_SERVICE_BEACON_OFFLOAD = 0, 1888 WMI_TLV_SERVICE_SCAN_OFFLOAD = 1, 1889 WMI_TLV_SERVICE_ROAM_SCAN_OFFLOAD = 2, 1890 WMI_TLV_SERVICE_BCN_MISS_OFFLOAD = 3, 1891 WMI_TLV_SERVICE_STA_PWRSAVE = 4, 1892 WMI_TLV_SERVICE_STA_ADVANCED_PWRSAVE = 5, 1893 WMI_TLV_SERVICE_AP_UAPSD = 6, 1894 WMI_TLV_SERVICE_AP_DFS = 7, 1895 WMI_TLV_SERVICE_11AC = 8, 1896 WMI_TLV_SERVICE_BLOCKACK = 9, 1897 WMI_TLV_SERVICE_PHYERR = 10, 1898 WMI_TLV_SERVICE_BCN_FILTER = 11, 1899 WMI_TLV_SERVICE_RTT = 12, 1900 WMI_TLV_SERVICE_WOW = 13, 1901 WMI_TLV_SERVICE_RATECTRL_CACHE = 14, 1902 WMI_TLV_SERVICE_IRAM_TIDS = 15, 1903 WMI_TLV_SERVICE_ARPNS_OFFLOAD = 16, 1904 WMI_TLV_SERVICE_NLO = 17, 1905 WMI_TLV_SERVICE_GTK_OFFLOAD = 18, 1906 WMI_TLV_SERVICE_SCAN_SCH = 19, 1907 WMI_TLV_SERVICE_CSA_OFFLOAD = 20, 1908 WMI_TLV_SERVICE_CHATTER = 21, 1909 WMI_TLV_SERVICE_COEX_FREQAVOID = 22, 1910 WMI_TLV_SERVICE_PACKET_POWER_SAVE = 23, 1911 WMI_TLV_SERVICE_FORCE_FW_HANG = 24, 1912 WMI_TLV_SERVICE_GPIO = 25, 1913 WMI_TLV_SERVICE_STA_DTIM_PS_MODULATED_DTIM = 26, 1914 WMI_STA_UAPSD_BASIC_AUTO_TRIG = 27, 1915 WMI_STA_UAPSD_VAR_AUTO_TRIG = 28, 1916 WMI_TLV_SERVICE_STA_KEEP_ALIVE = 29, 1917 WMI_TLV_SERVICE_TX_ENCAP = 30, 1918 WMI_TLV_SERVICE_AP_PS_DETECT_OUT_OF_SYNC = 31, 1919 WMI_TLV_SERVICE_EARLY_RX = 32, 1920 WMI_TLV_SERVICE_STA_SMPS = 33, 1921 WMI_TLV_SERVICE_FWTEST = 34, 1922 WMI_TLV_SERVICE_STA_WMMAC = 35, 1923 WMI_TLV_SERVICE_TDLS = 36, 1924 WMI_TLV_SERVICE_BURST = 37, 1925 WMI_TLV_SERVICE_MCC_BCN_INTERVAL_CHANGE = 38, 1926 WMI_TLV_SERVICE_ADAPTIVE_OCS = 39, 1927 WMI_TLV_SERVICE_BA_SSN_SUPPORT = 40, 1928 WMI_TLV_SERVICE_FILTER_IPSEC_NATKEEPALIVE = 41, 1929 WMI_TLV_SERVICE_WLAN_HB = 42, 1930 WMI_TLV_SERVICE_LTE_ANT_SHARE_SUPPORT = 43, 1931 WMI_TLV_SERVICE_BATCH_SCAN = 44, 1932 WMI_TLV_SERVICE_QPOWER = 45, 1933 WMI_TLV_SERVICE_PLMREQ = 46, 1934 WMI_TLV_SERVICE_THERMAL_MGMT = 47, 1935 WMI_TLV_SERVICE_RMC = 48, 1936 WMI_TLV_SERVICE_MHF_OFFLOAD = 49, 1937 WMI_TLV_SERVICE_COEX_SAR = 50, 1938 WMI_TLV_SERVICE_BCN_TXRATE_OVERRIDE = 51, 1939 WMI_TLV_SERVICE_NAN = 52, 1940 WMI_TLV_SERVICE_L1SS_STAT = 53, 1941 WMI_TLV_SERVICE_ESTIMATE_LINKSPEED = 54, 1942 WMI_TLV_SERVICE_OBSS_SCAN = 55, 1943 WMI_TLV_SERVICE_TDLS_OFFCHAN = 56, 1944 WMI_TLV_SERVICE_TDLS_UAPSD_BUFFER_STA = 57, 1945 WMI_TLV_SERVICE_TDLS_UAPSD_SLEEP_STA = 58, 1946 WMI_TLV_SERVICE_IBSS_PWRSAVE = 59, 1947 WMI_TLV_SERVICE_LPASS = 60, 1948 WMI_TLV_SERVICE_EXTSCAN = 61, 1949 WMI_TLV_SERVICE_D0WOW = 62, 1950 WMI_TLV_SERVICE_HSOFFLOAD = 63, 1951 WMI_TLV_SERVICE_ROAM_HO_OFFLOAD = 64, 1952 WMI_TLV_SERVICE_RX_FULL_REORDER = 65, 1953 WMI_TLV_SERVICE_DHCP_OFFLOAD = 66, 1954 WMI_TLV_SERVICE_STA_RX_IPA_OFFLOAD_SUPPORT = 67, 1955 WMI_TLV_SERVICE_MDNS_OFFLOAD = 68, 1956 WMI_TLV_SERVICE_SAP_AUTH_OFFLOAD = 69, 1957 WMI_TLV_SERVICE_DUAL_BAND_SIMULTANEOUS_SUPPORT = 70, 1958 WMI_TLV_SERVICE_OCB = 71, 1959 WMI_TLV_SERVICE_AP_ARPNS_OFFLOAD = 72, 1960 WMI_TLV_SERVICE_PER_BAND_CHAINMASK_SUPPORT = 73, 1961 WMI_TLV_SERVICE_PACKET_FILTER_OFFLOAD = 74, 1962 WMI_TLV_SERVICE_MGMT_TX_HTT = 75, 1963 WMI_TLV_SERVICE_MGMT_TX_WMI = 76, 1964 WMI_TLV_SERVICE_EXT_MSG = 77, 1965 WMI_TLV_SERVICE_MAWC = 78, 1966 WMI_TLV_SERVICE_PEER_ASSOC_CONF = 79, 1967 WMI_TLV_SERVICE_EGAP = 80, 1968 WMI_TLV_SERVICE_STA_PMF_OFFLOAD = 81, 1969 WMI_TLV_SERVICE_UNIFIED_WOW_CAPABILITY = 82, 1970 WMI_TLV_SERVICE_ENHANCED_PROXY_STA = 83, 1971 WMI_TLV_SERVICE_ATF = 84, 1972 WMI_TLV_SERVICE_COEX_GPIO = 85, 1973 WMI_TLV_SERVICE_AUX_SPECTRAL_INTF = 86, 1974 WMI_TLV_SERVICE_AUX_CHAN_LOAD_INTF = 87, 1975 WMI_TLV_SERVICE_BSS_CHANNEL_INFO_64 = 88, 1976 WMI_TLV_SERVICE_ENTERPRISE_MESH = 89, 1977 WMI_TLV_SERVICE_RESTRT_CHNL_SUPPORT = 90, 1978 WMI_TLV_SERVICE_BPF_OFFLOAD = 91, 1979 WMI_TLV_SERVICE_SYNC_DELETE_CMDS = 92, 1980 WMI_TLV_SERVICE_SMART_ANTENNA_SW_SUPPORT = 93, 1981 WMI_TLV_SERVICE_SMART_ANTENNA_HW_SUPPORT = 94, 1982 WMI_TLV_SERVICE_RATECTRL_LIMIT_MAX_MIN_RATES = 95, 1983 WMI_TLV_SERVICE_NAN_DATA = 96, 1984 WMI_TLV_SERVICE_NAN_RTT = 97, 1985 WMI_TLV_SERVICE_11AX = 98, 1986 WMI_TLV_SERVICE_DEPRECATED_REPLACE = 99, 1987 WMI_TLV_SERVICE_TDLS_CONN_TRACKER_IN_HOST_MODE = 100, 1988 WMI_TLV_SERVICE_ENHANCED_MCAST_FILTER = 101, 1989 WMI_TLV_SERVICE_PERIODIC_CHAN_STAT_SUPPORT = 102, 1990 WMI_TLV_SERVICE_MESH_11S = 103, 1991 WMI_TLV_SERVICE_HALF_RATE_QUARTER_RATE_SUPPORT = 104, 1992 WMI_TLV_SERVICE_VDEV_RX_FILTER = 105, 1993 WMI_TLV_SERVICE_P2P_LISTEN_OFFLOAD_SUPPORT = 106, 1994 WMI_TLV_SERVICE_MARK_FIRST_WAKEUP_PACKET = 107, 1995 WMI_TLV_SERVICE_MULTIPLE_MCAST_FILTER_SET = 108, 1996 WMI_TLV_SERVICE_HOST_MANAGED_RX_REORDER = 109, 1997 WMI_TLV_SERVICE_FLASH_RDWR_SUPPORT = 110, 1998 WMI_TLV_SERVICE_WLAN_STATS_REPORT = 111, 1999 WMI_TLV_SERVICE_TX_MSDU_ID_NEW_PARTITION_SUPPORT = 112, 2000 WMI_TLV_SERVICE_DFS_PHYERR_OFFLOAD = 113, 2001 WMI_TLV_SERVICE_RCPI_SUPPORT = 114, 2002 WMI_TLV_SERVICE_FW_MEM_DUMP_SUPPORT = 115, 2003 WMI_TLV_SERVICE_PEER_STATS_INFO = 116, 2004 WMI_TLV_SERVICE_REGULATORY_DB = 117, 2005 WMI_TLV_SERVICE_11D_OFFLOAD = 118, 2006 WMI_TLV_SERVICE_HW_DATA_FILTERING = 119, 2007 WMI_TLV_SERVICE_MULTIPLE_VDEV_RESTART = 120, 2008 WMI_TLV_SERVICE_PKT_ROUTING = 121, 2009 WMI_TLV_SERVICE_CHECK_CAL_VERSION = 122, 2010 WMI_TLV_SERVICE_OFFCHAN_TX_WMI = 123, 2011 WMI_TLV_SERVICE_8SS_TX_BFEE = 124, 2012 WMI_TLV_SERVICE_EXTENDED_NSS_SUPPORT = 125, 2013 WMI_TLV_SERVICE_ACK_TIMEOUT = 126, 2014 WMI_TLV_SERVICE_PDEV_BSS_CHANNEL_INFO_64 = 127, 2015 2016 /* The first 128 bits */ 2017 WMI_MAX_SERVICE = 128, 2018 2019 WMI_TLV_SERVICE_CHAN_LOAD_INFO = 128, 2020 WMI_TLV_SERVICE_TX_PPDU_INFO_STATS_SUPPORT = 129, 2021 WMI_TLV_SERVICE_VDEV_LIMIT_OFFCHAN_SUPPORT = 130, 2022 WMI_TLV_SERVICE_FILS_SUPPORT = 131, 2023 WMI_TLV_SERVICE_WLAN_OIC_PING_OFFLOAD = 132, 2024 WMI_TLV_SERVICE_WLAN_DHCP_RENEW = 133, 2025 WMI_TLV_SERVICE_MAWC_SUPPORT = 134, 2026 WMI_TLV_SERVICE_VDEV_LATENCY_CONFIG = 135, 2027 WMI_TLV_SERVICE_PDEV_UPDATE_CTLTABLE_SUPPORT = 136, 2028 WMI_TLV_SERVICE_PKTLOG_SUPPORT_OVER_HTT = 137, 2029 WMI_TLV_SERVICE_VDEV_MULTI_GROUP_KEY_SUPPORT = 138, 2030 WMI_TLV_SERVICE_SCAN_PHYMODE_SUPPORT = 139, 2031 WMI_TLV_SERVICE_THERM_THROT = 140, 2032 WMI_TLV_SERVICE_BCN_OFFLOAD_START_STOP_SUPPORT = 141, 2033 WMI_TLV_SERVICE_WOW_WAKEUP_BY_TIMER_PATTERN = 142, 2034 WMI_TLV_SERVICE_PEER_MAP_UNMAP_V2_SUPPORT = 143, 2035 WMI_TLV_SERVICE_OFFCHAN_DATA_TID_SUPPORT = 144, 2036 WMI_TLV_SERVICE_RX_PROMISC_ENABLE_SUPPORT = 145, 2037 WMI_TLV_SERVICE_SUPPORT_DIRECT_DMA = 146, 2038 WMI_TLV_SERVICE_AP_OBSS_DETECTION_OFFLOAD = 147, 2039 WMI_TLV_SERVICE_11K_NEIGHBOUR_REPORT_SUPPORT = 148, 2040 WMI_TLV_SERVICE_LISTEN_INTERVAL_OFFLOAD_SUPPORT = 149, 2041 WMI_TLV_SERVICE_BSS_COLOR_OFFLOAD = 150, 2042 WMI_TLV_SERVICE_RUNTIME_DPD_RECAL = 151, 2043 WMI_TLV_SERVICE_STA_TWT = 152, 2044 WMI_TLV_SERVICE_AP_TWT = 153, 2045 WMI_TLV_SERVICE_GMAC_OFFLOAD_SUPPORT = 154, 2046 WMI_TLV_SERVICE_SPOOF_MAC_SUPPORT = 155, 2047 WMI_TLV_SERVICE_PEER_TID_CONFIGS_SUPPORT = 156, 2048 WMI_TLV_SERVICE_VDEV_SWRETRY_PER_AC_CONFIG_SUPPORT = 157, 2049 WMI_TLV_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_SCC_SUPPORT = 158, 2050 WMI_TLV_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_MCC_SUPPORT = 159, 2051 WMI_TLV_SERVICE_MOTION_DET = 160, 2052 WMI_TLV_SERVICE_INFRA_MBSSID = 161, 2053 WMI_TLV_SERVICE_OBSS_SPATIAL_REUSE = 162, 2054 WMI_TLV_SERVICE_VDEV_DIFFERENT_BEACON_INTERVAL_SUPPORT = 163, 2055 WMI_TLV_SERVICE_NAN_DBS_SUPPORT = 164, 2056 WMI_TLV_SERVICE_NDI_DBS_SUPPORT = 165, 2057 WMI_TLV_SERVICE_NAN_SAP_SUPPORT = 166, 2058 WMI_TLV_SERVICE_NDI_SAP_SUPPORT = 167, 2059 WMI_TLV_SERVICE_CFR_CAPTURE_SUPPORT = 168, 2060 WMI_TLV_SERVICE_CFR_CAPTURE_IND_MSG_TYPE_1 = 169, 2061 WMI_TLV_SERVICE_ESP_SUPPORT = 170, 2062 WMI_TLV_SERVICE_PEER_CHWIDTH_CHANGE = 171, 2063 WMI_TLV_SERVICE_WLAN_HPCS_PULSE = 172, 2064 WMI_TLV_SERVICE_PER_VDEV_CHAINMASK_CONFIG_SUPPORT = 173, 2065 WMI_TLV_SERVICE_TX_DATA_MGMT_ACK_RSSI = 174, 2066 WMI_TLV_SERVICE_NAN_DISABLE_SUPPORT = 175, 2067 WMI_TLV_SERVICE_HTT_H2T_NO_HTC_HDR_LEN_IN_MSG_LEN = 176, 2068 WMI_TLV_SERVICE_COEX_SUPPORT_UNEQUAL_ISOLATION = 177, 2069 WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT = 178, 2070 WMI_TLV_SERVICE_SUPPORT_EXTEND_ADDRESS = 179, 2071 WMI_TLV_SERVICE_BEACON_RECEPTION_STATS = 180, 2072 WMI_TLV_SERVICE_FETCH_TX_PN = 181, 2073 WMI_TLV_SERVICE_PEER_UNMAP_RESPONSE_SUPPORT = 182, 2074 WMI_TLV_SERVICE_TX_PER_PEER_AMPDU_SIZE = 183, 2075 WMI_TLV_SERVICE_BSS_COLOR_SWITCH_COUNT = 184, 2076 WMI_TLV_SERVICE_HTT_PEER_STATS_SUPPORT = 185, 2077 WMI_TLV_SERVICE_UL_RU26_ALLOWED = 186, 2078 WMI_TLV_SERVICE_GET_MWS_COEX_STATE = 187, 2079 WMI_TLV_SERVICE_GET_MWS_DPWB_STATE = 188, 2080 WMI_TLV_SERVICE_GET_MWS_TDM_STATE = 189, 2081 WMI_TLV_SERVICE_GET_MWS_IDRX_STATE = 190, 2082 WMI_TLV_SERVICE_GET_MWS_ANTENNA_SHARING_STATE = 191, 2083 WMI_TLV_SERVICE_ENHANCED_TPC_CONFIG_EVENT = 192, 2084 WMI_TLV_SERVICE_WLM_STATS_REQUEST = 193, 2085 WMI_TLV_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT = 194, 2086 WMI_TLV_SERVICE_WPA3_FT_SAE_SUPPORT = 195, 2087 WMI_TLV_SERVICE_WPA3_FT_SUITE_B_SUPPORT = 196, 2088 WMI_TLV_SERVICE_VOW_ENABLE = 197, 2089 WMI_TLV_SERVICE_CFR_CAPTURE_IND_EVT_TYPE_1 = 198, 2090 WMI_TLV_SERVICE_BROADCAST_TWT = 199, 2091 WMI_TLV_SERVICE_RAP_DETECTION_SUPPORT = 200, 2092 WMI_TLV_SERVICE_PS_TDCC = 201, 2093 WMI_TLV_SERVICE_THREE_WAY_COEX_CONFIG_LEGACY = 202, 2094 WMI_TLV_SERVICE_THREE_WAY_COEX_CONFIG_OVERRIDE = 203, 2095 WMI_TLV_SERVICE_TX_PWR_PER_PEER = 204, 2096 WMI_TLV_SERVICE_STA_PLUS_STA_SUPPORT = 205, 2097 WMI_TLV_SERVICE_WPA3_FT_FILS = 206, 2098 WMI_TLV_SERVICE_ADAPTIVE_11R_ROAM = 207, 2099 WMI_TLV_SERVICE_CHAN_RF_CHARACTERIZATION_INFO = 208, 2100 WMI_TLV_SERVICE_FW_IFACE_COMBINATION_SUPPORT = 209, 2101 WMI_TLV_SERVICE_TX_COMPL_TSF64 = 210, 2102 WMI_TLV_SERVICE_DSM_ROAM_FILTER = 211, 2103 WMI_TLV_SERVICE_PACKET_CAPTURE_SUPPORT = 212, 2104 WMI_TLV_SERVICE_PER_PEER_HTT_STATS_RESET = 213, 2105 WMI_TLV_SERVICE_FREQINFO_IN_METADATA = 219, 2106 WMI_TLV_SERVICE_EXT2_MSG = 220, 2107 WMI_TLV_SERVICE_PEER_POWER_SAVE_DURATION_SUPPORT = 246, 2108 WMI_TLV_SERVICE_SRG_SRP_SPATIAL_REUSE_SUPPORT = 249, 2109 WMI_TLV_SERVICE_MBSS_PARAM_IN_VDEV_START_SUPPORT = 253, 2110 WMI_TLV_SERVICE_PASSIVE_SCAN_START_TIME_ENHANCE = 263, 2111 2112 /* The second 128 bits */ 2113 WMI_MAX_EXT_SERVICE = 256, 2114 WMI_TLV_SERVICE_SCAN_CONFIG_PER_CHANNEL = 265, 2115 WMI_TLV_SERVICE_REG_CC_EXT_EVENT_SUPPORT = 281, 2116 WMI_TLV_SERVICE_BIOS_SAR_SUPPORT = 326, 2117 WMI_TLV_SERVICE_SUPPORT_11D_FOR_HOST_SCAN = 357, 2118 2119 /* The third 128 bits */ 2120 WMI_MAX_EXT2_SERVICE = 384 2121 }; 2122 2123 enum { 2124 WMI_SMPS_FORCED_MODE_NONE = 0, 2125 WMI_SMPS_FORCED_MODE_DISABLED, 2126 WMI_SMPS_FORCED_MODE_STATIC, 2127 WMI_SMPS_FORCED_MODE_DYNAMIC 2128 }; 2129 2130 #define WMI_TPC_CHAINMASK_CONFIG_BAND_2G 0 2131 #define WMI_TPC_CHAINMASK_CONFIG_BAND_5G 1 2132 #define WMI_NUM_SUPPORTED_BAND_MAX 2 2133 2134 #define WMI_PEER_MIMO_PS_STATE 0x1 2135 #define WMI_PEER_AMPDU 0x2 2136 #define WMI_PEER_AUTHORIZE 0x3 2137 #define WMI_PEER_CHWIDTH 0x4 2138 #define WMI_PEER_NSS 0x5 2139 #define WMI_PEER_USE_4ADDR 0x6 2140 #define WMI_PEER_MEMBERSHIP 0x7 2141 #define WMI_PEER_USERPOS 0x8 2142 #define WMI_PEER_CRIT_PROTO_HINT_ENABLED 0x9 2143 #define WMI_PEER_TX_FAIL_CNT_THR 0xA 2144 #define WMI_PEER_SET_HW_RETRY_CTS2S 0xB 2145 #define WMI_PEER_IBSS_ATIM_WINDOW_LENGTH 0xC 2146 #define WMI_PEER_PHYMODE 0xD 2147 #define WMI_PEER_USE_FIXED_PWR 0xE 2148 #define WMI_PEER_PARAM_FIXED_RATE 0xF 2149 #define WMI_PEER_SET_MU_WHITELIST 0x10 2150 #define WMI_PEER_SET_MAX_TX_RATE 0x11 2151 #define WMI_PEER_SET_MIN_TX_RATE 0x12 2152 #define WMI_PEER_SET_DEFAULT_ROUTING 0x13 2153 2154 /* slot time long */ 2155 #define WMI_VDEV_SLOT_TIME_LONG 0x1 2156 /* slot time short */ 2157 #define WMI_VDEV_SLOT_TIME_SHORT 0x2 2158 /* preablbe long */ 2159 #define WMI_VDEV_PREAMBLE_LONG 0x1 2160 /* preablbe short */ 2161 #define WMI_VDEV_PREAMBLE_SHORT 0x2 2162 2163 enum wmi_peer_smps_state { 2164 WMI_PEER_SMPS_PS_NONE = 0x0, 2165 WMI_PEER_SMPS_STATIC = 0x1, 2166 WMI_PEER_SMPS_DYNAMIC = 0x2 2167 }; 2168 2169 enum wmi_peer_chwidth { 2170 WMI_PEER_CHWIDTH_20MHZ = 0, 2171 WMI_PEER_CHWIDTH_40MHZ = 1, 2172 WMI_PEER_CHWIDTH_80MHZ = 2, 2173 WMI_PEER_CHWIDTH_160MHZ = 3, 2174 }; 2175 2176 enum wmi_beacon_gen_mode { 2177 WMI_BEACON_STAGGERED_MODE = 0, 2178 WMI_BEACON_BURST_MODE = 1 2179 }; 2180 2181 enum wmi_direct_buffer_module { 2182 WMI_DIRECT_BUF_SPECTRAL = 0, 2183 WMI_DIRECT_BUF_CFR = 1, 2184 2185 /* keep it last */ 2186 WMI_DIRECT_BUF_MAX 2187 }; 2188 2189 /* enum wmi_nss_ratio - NSS ratio received from FW during service ready ext 2190 * event 2191 * WMI_NSS_RATIO_1BY2_NSS -Max nss of 160MHz is equals to half of the max nss 2192 * of 80MHz 2193 * WMI_NSS_RATIO_3BY4_NSS - Max nss of 160MHz is equals to 3/4 of the max nss 2194 * of 80MHz 2195 * WMI_NSS_RATIO_1_NSS - Max nss of 160MHz is equals to the max nss of 80MHz 2196 * WMI_NSS_RATIO_2_NSS - Max nss of 160MHz is equals to two times the max 2197 * nss of 80MHz 2198 */ 2199 2200 enum wmi_nss_ratio { 2201 WMI_NSS_RATIO_1BY2_NSS = 0x0, 2202 WMI_NSS_RATIO_3BY4_NSS = 0x1, 2203 WMI_NSS_RATIO_1_NSS = 0x2, 2204 WMI_NSS_RATIO_2_NSS = 0x3, 2205 }; 2206 2207 enum wmi_dtim_policy { 2208 WMI_DTIM_POLICY_IGNORE = 1, 2209 WMI_DTIM_POLICY_NORMAL = 2, 2210 WMI_DTIM_POLICY_STICK = 3, 2211 WMI_DTIM_POLICY_AUTO = 4, 2212 }; 2213 2214 struct wmi_host_pdev_band_to_mac { 2215 u32 pdev_id; 2216 u32 start_freq; 2217 u32 end_freq; 2218 }; 2219 2220 struct ath11k_ppe_threshold { 2221 u32 numss_m1; 2222 u32 ru_bit_mask; 2223 u32 ppet16_ppet8_ru3_ru0[PSOC_HOST_MAX_NUM_SS]; 2224 }; 2225 2226 struct ath11k_service_ext_param { 2227 u32 default_conc_scan_config_bits; 2228 u32 default_fw_config_bits; 2229 struct ath11k_ppe_threshold ppet; 2230 u32 he_cap_info; 2231 u32 mpdu_density; 2232 u32 max_bssid_rx_filters; 2233 u32 num_hw_modes; 2234 u32 num_phy; 2235 }; 2236 2237 struct ath11k_hw_mode_caps { 2238 u32 hw_mode_id; 2239 u32 phy_id_map; 2240 u32 hw_mode_config_type; 2241 }; 2242 2243 #define PSOC_HOST_MAX_PHY_SIZE (3) 2244 #define ATH11K_11B_SUPPORT BIT(0) 2245 #define ATH11K_11G_SUPPORT BIT(1) 2246 #define ATH11K_11A_SUPPORT BIT(2) 2247 #define ATH11K_11N_SUPPORT BIT(3) 2248 #define ATH11K_11AC_SUPPORT BIT(4) 2249 #define ATH11K_11AX_SUPPORT BIT(5) 2250 2251 struct ath11k_hal_reg_capabilities_ext { 2252 u32 phy_id; 2253 u32 eeprom_reg_domain; 2254 u32 eeprom_reg_domain_ext; 2255 u32 regcap1; 2256 u32 regcap2; 2257 u32 wireless_modes; 2258 u32 low_2ghz_chan; 2259 u32 high_2ghz_chan; 2260 u32 low_5ghz_chan; 2261 u32 high_5ghz_chan; 2262 }; 2263 2264 #define WMI_HOST_MAX_PDEV 3 2265 2266 struct wlan_host_mem_chunk { 2267 u32 tlv_header; 2268 u32 req_id; 2269 u32 ptr; 2270 u32 size; 2271 } __packed; 2272 2273 struct wmi_host_mem_chunk { 2274 void *vaddr; 2275 dma_addr_t paddr; 2276 u32 len; 2277 u32 req_id; 2278 }; 2279 2280 struct wmi_init_cmd_param { 2281 u32 tlv_header; 2282 struct target_resource_config *res_cfg; 2283 u8 num_mem_chunks; 2284 struct wmi_host_mem_chunk *mem_chunks; 2285 u32 hw_mode_id; 2286 u32 num_band_to_mac; 2287 struct wmi_host_pdev_band_to_mac band_to_mac[WMI_HOST_MAX_PDEV]; 2288 }; 2289 2290 struct wmi_pdev_band_to_mac { 2291 u32 tlv_header; 2292 u32 pdev_id; 2293 u32 start_freq; 2294 u32 end_freq; 2295 } __packed; 2296 2297 struct wmi_pdev_set_hw_mode_cmd_param { 2298 u32 tlv_header; 2299 u32 pdev_id; 2300 u32 hw_mode_index; 2301 u32 num_band_to_mac; 2302 } __packed; 2303 2304 struct wmi_ppe_threshold { 2305 u32 numss_m1; /** NSS - 1*/ 2306 union { 2307 u32 ru_count; 2308 u32 ru_mask; 2309 } __packed; 2310 u32 ppet16_ppet8_ru3_ru0[WMI_MAX_NUM_SS]; 2311 } __packed; 2312 2313 #define HW_BD_INFO_SIZE 5 2314 2315 struct wmi_abi_version { 2316 u32 abi_version_0; 2317 u32 abi_version_1; 2318 u32 abi_version_ns_0; 2319 u32 abi_version_ns_1; 2320 u32 abi_version_ns_2; 2321 u32 abi_version_ns_3; 2322 } __packed; 2323 2324 struct wmi_init_cmd { 2325 u32 tlv_header; 2326 struct wmi_abi_version host_abi_vers; 2327 u32 num_host_mem_chunks; 2328 } __packed; 2329 2330 #define WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64 BIT(5) 2331 #define WMI_RSRC_CFG_FLAG2_CALC_NEXT_DTIM_COUNT_SET BIT(9) 2332 #define WMI_RSRC_CFG_FLAG1_ACK_RSSI BIT(18) 2333 2334 #define WMI_CFG_HOST_SERVICE_FLAG_REG_CC_EXT 4 2335 2336 struct wmi_resource_config { 2337 u32 tlv_header; 2338 u32 num_vdevs; 2339 u32 num_peers; 2340 u32 num_offload_peers; 2341 u32 num_offload_reorder_buffs; 2342 u32 num_peer_keys; 2343 u32 num_tids; 2344 u32 ast_skid_limit; 2345 u32 tx_chain_mask; 2346 u32 rx_chain_mask; 2347 u32 rx_timeout_pri[4]; 2348 u32 rx_decap_mode; 2349 u32 scan_max_pending_req; 2350 u32 bmiss_offload_max_vdev; 2351 u32 roam_offload_max_vdev; 2352 u32 roam_offload_max_ap_profiles; 2353 u32 num_mcast_groups; 2354 u32 num_mcast_table_elems; 2355 u32 mcast2ucast_mode; 2356 u32 tx_dbg_log_size; 2357 u32 num_wds_entries; 2358 u32 dma_burst_size; 2359 u32 mac_aggr_delim; 2360 u32 rx_skip_defrag_timeout_dup_detection_check; 2361 u32 vow_config; 2362 u32 gtk_offload_max_vdev; 2363 u32 num_msdu_desc; 2364 u32 max_frag_entries; 2365 u32 num_tdls_vdevs; 2366 u32 num_tdls_conn_table_entries; 2367 u32 beacon_tx_offload_max_vdev; 2368 u32 num_multicast_filter_entries; 2369 u32 num_wow_filters; 2370 u32 num_keep_alive_pattern; 2371 u32 keep_alive_pattern_size; 2372 u32 max_tdls_concurrent_sleep_sta; 2373 u32 max_tdls_concurrent_buffer_sta; 2374 u32 wmi_send_separate; 2375 u32 num_ocb_vdevs; 2376 u32 num_ocb_channels; 2377 u32 num_ocb_schedules; 2378 u32 flag1; 2379 u32 smart_ant_cap; 2380 u32 bk_minfree; 2381 u32 be_minfree; 2382 u32 vi_minfree; 2383 u32 vo_minfree; 2384 u32 alloc_frag_desc_for_data_pkt; 2385 u32 num_ns_ext_tuples_cfg; 2386 u32 bpf_instruction_size; 2387 u32 max_bssid_rx_filters; 2388 u32 use_pdev_id; 2389 u32 max_num_dbs_scan_duty_cycle; 2390 u32 max_num_group_keys; 2391 u32 peer_map_unmap_v2_support; 2392 u32 sched_params; 2393 u32 twt_ap_pdev_count; 2394 u32 twt_ap_sta_count; 2395 u32 max_nlo_ssids; 2396 u32 num_pkt_filters; 2397 u32 num_max_sta_vdevs; 2398 u32 max_bssid_indicator; 2399 u32 ul_resp_config; 2400 u32 msdu_flow_override_config0; 2401 u32 msdu_flow_override_config1; 2402 u32 flags2; 2403 u32 host_service_flags; 2404 u32 max_rnr_neighbours; 2405 u32 ema_max_vap_cnt; 2406 u32 ema_max_profile_period; 2407 } __packed; 2408 2409 struct wmi_service_ready_event { 2410 u32 fw_build_vers; 2411 struct wmi_abi_version fw_abi_vers; 2412 u32 phy_capability; 2413 u32 max_frag_entry; 2414 u32 num_rf_chains; 2415 u32 ht_cap_info; 2416 u32 vht_cap_info; 2417 u32 vht_supp_mcs; 2418 u32 hw_min_tx_power; 2419 u32 hw_max_tx_power; 2420 u32 sys_cap_info; 2421 u32 min_pkt_size_enable; 2422 u32 max_bcn_ie_size; 2423 u32 num_mem_reqs; 2424 u32 max_num_scan_channels; 2425 u32 hw_bd_id; 2426 u32 hw_bd_info[HW_BD_INFO_SIZE]; 2427 u32 max_supported_macs; 2428 u32 wmi_fw_sub_feat_caps; 2429 u32 num_dbs_hw_modes; 2430 /* txrx_chainmask 2431 * [7:0] - 2G band tx chain mask 2432 * [15:8] - 2G band rx chain mask 2433 * [23:16] - 5G band tx chain mask 2434 * [31:24] - 5G band rx chain mask 2435 */ 2436 u32 txrx_chainmask; 2437 u32 default_dbs_hw_mode_index; 2438 u32 num_msdu_desc; 2439 } __packed; 2440 2441 #define WMI_SERVICE_BM_SIZE ((WMI_MAX_SERVICE + sizeof(u32) - 1) / sizeof(u32)) 2442 2443 #define WMI_SERVICE_SEGMENT_BM_SIZE32 4 /* 4x u32 = 128 bits */ 2444 #define WMI_SERVICE_EXT_BM_SIZE (WMI_SERVICE_SEGMENT_BM_SIZE32 * sizeof(u32)) 2445 #define WMI_AVAIL_SERVICE_BITS_IN_SIZE32 32 2446 #define WMI_SERVICE_BITS_IN_SIZE32 4 2447 2448 struct wmi_service_ready_ext_event { 2449 u32 default_conc_scan_config_bits; 2450 u32 default_fw_config_bits; 2451 struct wmi_ppe_threshold ppet; 2452 u32 he_cap_info; 2453 u32 mpdu_density; 2454 u32 max_bssid_rx_filters; 2455 u32 fw_build_vers_ext; 2456 u32 max_nlo_ssids; 2457 u32 max_bssid_indicator; 2458 u32 he_cap_info_ext; 2459 } __packed; 2460 2461 struct wmi_soc_mac_phy_hw_mode_caps { 2462 u32 num_hw_modes; 2463 u32 num_chainmask_tables; 2464 } __packed; 2465 2466 struct wmi_hw_mode_capabilities { 2467 u32 tlv_header; 2468 u32 hw_mode_id; 2469 u32 phy_id_map; 2470 u32 hw_mode_config_type; 2471 } __packed; 2472 2473 #define WMI_MAX_HECAP_PHY_SIZE (3) 2474 #define WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS BIT(0) 2475 #define WMI_NSS_RATIO_ENABLE_DISABLE_GET(_val) \ 2476 FIELD_GET(WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS, _val) 2477 #define WMI_NSS_RATIO_INFO_BITPOS GENMASK(4, 1) 2478 #define WMI_NSS_RATIO_INFO_GET(_val) \ 2479 FIELD_GET(WMI_NSS_RATIO_INFO_BITPOS, _val) 2480 2481 struct wmi_mac_phy_capabilities { 2482 u32 hw_mode_id; 2483 u32 pdev_id; 2484 u32 phy_id; 2485 u32 supported_flags; 2486 u32 supported_bands; 2487 u32 ampdu_density; 2488 u32 max_bw_supported_2g; 2489 u32 ht_cap_info_2g; 2490 u32 vht_cap_info_2g; 2491 u32 vht_supp_mcs_2g; 2492 u32 he_cap_info_2g; 2493 u32 he_supp_mcs_2g; 2494 u32 tx_chain_mask_2g; 2495 u32 rx_chain_mask_2g; 2496 u32 max_bw_supported_5g; 2497 u32 ht_cap_info_5g; 2498 u32 vht_cap_info_5g; 2499 u32 vht_supp_mcs_5g; 2500 u32 he_cap_info_5g; 2501 u32 he_supp_mcs_5g; 2502 u32 tx_chain_mask_5g; 2503 u32 rx_chain_mask_5g; 2504 u32 he_cap_phy_info_2g[WMI_MAX_HECAP_PHY_SIZE]; 2505 u32 he_cap_phy_info_5g[WMI_MAX_HECAP_PHY_SIZE]; 2506 struct wmi_ppe_threshold he_ppet2g; 2507 struct wmi_ppe_threshold he_ppet5g; 2508 u32 chainmask_table_id; 2509 u32 lmac_id; 2510 u32 he_cap_info_2g_ext; 2511 u32 he_cap_info_5g_ext; 2512 u32 he_cap_info_internal; 2513 u32 wireless_modes; 2514 u32 low_2ghz_chan_freq; 2515 u32 high_2ghz_chan_freq; 2516 u32 low_5ghz_chan_freq; 2517 u32 high_5ghz_chan_freq; 2518 u32 nss_ratio; 2519 } __packed; 2520 2521 struct wmi_hal_reg_capabilities_ext { 2522 u32 tlv_header; 2523 u32 phy_id; 2524 u32 eeprom_reg_domain; 2525 u32 eeprom_reg_domain_ext; 2526 u32 regcap1; 2527 u32 regcap2; 2528 u32 wireless_modes; 2529 u32 low_2ghz_chan; 2530 u32 high_2ghz_chan; 2531 u32 low_5ghz_chan; 2532 u32 high_5ghz_chan; 2533 } __packed; 2534 2535 struct wmi_soc_hal_reg_capabilities { 2536 u32 num_phy; 2537 } __packed; 2538 2539 /* 2 word representation of MAC addr */ 2540 struct wmi_mac_addr { 2541 union { 2542 u8 addr[6]; 2543 struct { 2544 u32 word0; 2545 u32 word1; 2546 } __packed; 2547 } __packed; 2548 } __packed; 2549 2550 struct wmi_dma_ring_capabilities { 2551 u32 tlv_header; 2552 u32 pdev_id; 2553 u32 module_id; 2554 u32 min_elem; 2555 u32 min_buf_sz; 2556 u32 min_buf_align; 2557 } __packed; 2558 2559 struct wmi_ready_event_min { 2560 struct wmi_abi_version fw_abi_vers; 2561 struct wmi_mac_addr mac_addr; 2562 u32 status; 2563 u32 num_dscp_table; 2564 u32 num_extra_mac_addr; 2565 u32 num_total_peers; 2566 u32 num_extra_peers; 2567 } __packed; 2568 2569 struct wmi_ready_event { 2570 struct wmi_ready_event_min ready_event_min; 2571 u32 max_ast_index; 2572 u32 pktlog_defs_checksum; 2573 } __packed; 2574 2575 struct wmi_service_available_event { 2576 u32 wmi_service_segment_offset; 2577 u32 wmi_service_segment_bitmap[WMI_SERVICE_SEGMENT_BM_SIZE32]; 2578 } __packed; 2579 2580 struct ath11k_pdev_wmi { 2581 struct ath11k_wmi_base *wmi_ab; 2582 enum ath11k_htc_ep_id eid; 2583 const struct wmi_peer_flags_map *peer_flags; 2584 u32 rx_decap_mode; 2585 wait_queue_head_t tx_ce_desc_wq; 2586 }; 2587 2588 struct vdev_create_params { 2589 u8 if_id; 2590 u32 type; 2591 u32 subtype; 2592 struct { 2593 u8 tx; 2594 u8 rx; 2595 } chains[NUM_NL80211_BANDS]; 2596 u32 pdev_id; 2597 u32 mbssid_flags; 2598 u32 mbssid_tx_vdev_id; 2599 }; 2600 2601 struct wmi_vdev_create_cmd { 2602 u32 tlv_header; 2603 u32 vdev_id; 2604 u32 vdev_type; 2605 u32 vdev_subtype; 2606 struct wmi_mac_addr vdev_macaddr; 2607 u32 num_cfg_txrx_streams; 2608 u32 pdev_id; 2609 u32 mbssid_flags; 2610 u32 mbssid_tx_vdev_id; 2611 } __packed; 2612 2613 struct wmi_vdev_txrx_streams { 2614 u32 tlv_header; 2615 u32 band; 2616 u32 supported_tx_streams; 2617 u32 supported_rx_streams; 2618 } __packed; 2619 2620 struct wmi_vdev_delete_cmd { 2621 u32 tlv_header; 2622 u32 vdev_id; 2623 } __packed; 2624 2625 struct wmi_vdev_up_cmd { 2626 u32 tlv_header; 2627 u32 vdev_id; 2628 u32 vdev_assoc_id; 2629 struct wmi_mac_addr vdev_bssid; 2630 struct wmi_mac_addr tx_vdev_bssid; 2631 u32 nontx_profile_idx; 2632 u32 nontx_profile_cnt; 2633 } __packed; 2634 2635 struct wmi_vdev_stop_cmd { 2636 u32 tlv_header; 2637 u32 vdev_id; 2638 } __packed; 2639 2640 struct wmi_vdev_down_cmd { 2641 u32 tlv_header; 2642 u32 vdev_id; 2643 } __packed; 2644 2645 #define WMI_VDEV_START_HIDDEN_SSID BIT(0) 2646 #define WMI_VDEV_START_PMF_ENABLED BIT(1) 2647 #define WMI_VDEV_START_LDPC_RX_ENABLED BIT(3) 2648 #define WMI_VDEV_START_HW_ENCRYPTION_DISABLED BIT(4) 2649 2650 struct wmi_ssid { 2651 u32 ssid_len; 2652 u32 ssid[8]; 2653 } __packed; 2654 2655 #define ATH11K_VDEV_SETUP_TIMEOUT_HZ (1 * HZ) 2656 2657 struct wmi_vdev_start_request_cmd { 2658 u32 tlv_header; 2659 u32 vdev_id; 2660 u32 requestor_id; 2661 u32 beacon_interval; 2662 u32 dtim_period; 2663 u32 flags; 2664 struct wmi_ssid ssid; 2665 u32 bcn_tx_rate; 2666 u32 bcn_txpower; 2667 u32 num_noa_descriptors; 2668 u32 disable_hw_ack; 2669 u32 preferred_tx_streams; 2670 u32 preferred_rx_streams; 2671 u32 he_ops; 2672 u32 cac_duration_ms; 2673 u32 regdomain; 2674 u32 min_data_rate; 2675 u32 mbssid_flags; 2676 u32 mbssid_tx_vdev_id; 2677 } __packed; 2678 2679 #define MGMT_TX_DL_FRM_LEN 64 2680 #define WMI_MAC_MAX_SSID_LENGTH 32 2681 struct mac_ssid { 2682 u8 length; 2683 u8 mac_ssid[WMI_MAC_MAX_SSID_LENGTH]; 2684 } __packed; 2685 2686 struct wmi_p2p_noa_descriptor { 2687 u32 type_count; 2688 u32 duration; 2689 u32 interval; 2690 u32 start_time; 2691 }; 2692 2693 struct channel_param { 2694 u8 chan_id; 2695 u8 pwr; 2696 u32 mhz; 2697 u32 half_rate:1, 2698 quarter_rate:1, 2699 dfs_set:1, 2700 dfs_set_cfreq2:1, 2701 is_chan_passive:1, 2702 allow_ht:1, 2703 allow_vht:1, 2704 allow_he:1, 2705 set_agile:1, 2706 psc_channel:1; 2707 u32 phy_mode; 2708 u32 cfreq1; 2709 u32 cfreq2; 2710 char maxpower; 2711 char minpower; 2712 char maxregpower; 2713 u8 antennamax; 2714 u8 reg_class_id; 2715 } __packed; 2716 2717 enum wmi_phy_mode { 2718 MODE_11A = 0, 2719 MODE_11G = 1, /* 11b/g Mode */ 2720 MODE_11B = 2, /* 11b Mode */ 2721 MODE_11GONLY = 3, /* 11g only Mode */ 2722 MODE_11NA_HT20 = 4, 2723 MODE_11NG_HT20 = 5, 2724 MODE_11NA_HT40 = 6, 2725 MODE_11NG_HT40 = 7, 2726 MODE_11AC_VHT20 = 8, 2727 MODE_11AC_VHT40 = 9, 2728 MODE_11AC_VHT80 = 10, 2729 MODE_11AC_VHT20_2G = 11, 2730 MODE_11AC_VHT40_2G = 12, 2731 MODE_11AC_VHT80_2G = 13, 2732 MODE_11AC_VHT80_80 = 14, 2733 MODE_11AC_VHT160 = 15, 2734 MODE_11AX_HE20 = 16, 2735 MODE_11AX_HE40 = 17, 2736 MODE_11AX_HE80 = 18, 2737 MODE_11AX_HE80_80 = 19, 2738 MODE_11AX_HE160 = 20, 2739 MODE_11AX_HE20_2G = 21, 2740 MODE_11AX_HE40_2G = 22, 2741 MODE_11AX_HE80_2G = 23, 2742 MODE_UNKNOWN = 24, 2743 MODE_MAX = 24 2744 }; 2745 2746 static inline const char *ath11k_wmi_phymode_str(enum wmi_phy_mode mode) 2747 { 2748 switch (mode) { 2749 case MODE_11A: 2750 return "11a"; 2751 case MODE_11G: 2752 return "11g"; 2753 case MODE_11B: 2754 return "11b"; 2755 case MODE_11GONLY: 2756 return "11gonly"; 2757 case MODE_11NA_HT20: 2758 return "11na-ht20"; 2759 case MODE_11NG_HT20: 2760 return "11ng-ht20"; 2761 case MODE_11NA_HT40: 2762 return "11na-ht40"; 2763 case MODE_11NG_HT40: 2764 return "11ng-ht40"; 2765 case MODE_11AC_VHT20: 2766 return "11ac-vht20"; 2767 case MODE_11AC_VHT40: 2768 return "11ac-vht40"; 2769 case MODE_11AC_VHT80: 2770 return "11ac-vht80"; 2771 case MODE_11AC_VHT160: 2772 return "11ac-vht160"; 2773 case MODE_11AC_VHT80_80: 2774 return "11ac-vht80+80"; 2775 case MODE_11AC_VHT20_2G: 2776 return "11ac-vht20-2g"; 2777 case MODE_11AC_VHT40_2G: 2778 return "11ac-vht40-2g"; 2779 case MODE_11AC_VHT80_2G: 2780 return "11ac-vht80-2g"; 2781 case MODE_11AX_HE20: 2782 return "11ax-he20"; 2783 case MODE_11AX_HE40: 2784 return "11ax-he40"; 2785 case MODE_11AX_HE80: 2786 return "11ax-he80"; 2787 case MODE_11AX_HE80_80: 2788 return "11ax-he80+80"; 2789 case MODE_11AX_HE160: 2790 return "11ax-he160"; 2791 case MODE_11AX_HE20_2G: 2792 return "11ax-he20-2g"; 2793 case MODE_11AX_HE40_2G: 2794 return "11ax-he40-2g"; 2795 case MODE_11AX_HE80_2G: 2796 return "11ax-he80-2g"; 2797 case MODE_UNKNOWN: 2798 /* skip */ 2799 break; 2800 2801 /* no default handler to allow compiler to check that the 2802 * enum is fully handled 2803 */ 2804 } 2805 2806 return "<unknown>"; 2807 } 2808 2809 struct wmi_channel_arg { 2810 u32 freq; 2811 u32 band_center_freq1; 2812 u32 band_center_freq2; 2813 bool passive; 2814 bool allow_ibss; 2815 bool allow_ht; 2816 bool allow_vht; 2817 bool ht40plus; 2818 bool chan_radar; 2819 bool freq2_radar; 2820 bool allow_he; 2821 u32 min_power; 2822 u32 max_power; 2823 u32 max_reg_power; 2824 u32 max_antenna_gain; 2825 enum wmi_phy_mode mode; 2826 }; 2827 2828 struct wmi_vdev_start_req_arg { 2829 u32 vdev_id; 2830 struct wmi_channel_arg channel; 2831 u32 bcn_intval; 2832 u32 dtim_period; 2833 u8 *ssid; 2834 u32 ssid_len; 2835 u32 bcn_tx_rate; 2836 u32 bcn_tx_power; 2837 bool disable_hw_ack; 2838 bool hidden_ssid; 2839 bool pmf_enabled; 2840 u32 he_ops; 2841 u32 cac_duration_ms; 2842 u32 regdomain; 2843 u32 pref_rx_streams; 2844 u32 pref_tx_streams; 2845 u32 num_noa_descriptors; 2846 u32 min_data_rate; 2847 u32 mbssid_flags; 2848 u32 mbssid_tx_vdev_id; 2849 }; 2850 2851 struct peer_create_params { 2852 const u8 *peer_addr; 2853 u32 peer_type; 2854 u32 vdev_id; 2855 }; 2856 2857 struct peer_delete_params { 2858 u8 vdev_id; 2859 }; 2860 2861 struct peer_flush_params { 2862 u32 peer_tid_bitmap; 2863 u8 vdev_id; 2864 }; 2865 2866 struct pdev_set_regdomain_params { 2867 u16 current_rd_in_use; 2868 u16 current_rd_2g; 2869 u16 current_rd_5g; 2870 u32 ctl_2g; 2871 u32 ctl_5g; 2872 u8 dfs_domain; 2873 u32 pdev_id; 2874 }; 2875 2876 struct rx_reorder_queue_remove_params { 2877 u8 *peer_macaddr; 2878 u16 vdev_id; 2879 u32 peer_tid_bitmap; 2880 }; 2881 2882 #define WMI_HOST_PDEV_ID_SOC 0xFF 2883 #define WMI_HOST_PDEV_ID_0 0 2884 #define WMI_HOST_PDEV_ID_1 1 2885 #define WMI_HOST_PDEV_ID_2 2 2886 2887 #define WMI_PDEV_ID_SOC 0 2888 #define WMI_PDEV_ID_1ST 1 2889 #define WMI_PDEV_ID_2ND 2 2890 #define WMI_PDEV_ID_3RD 3 2891 2892 /* Freq units in MHz */ 2893 #define REG_RULE_START_FREQ 0x0000ffff 2894 #define REG_RULE_END_FREQ 0xffff0000 2895 #define REG_RULE_FLAGS 0x0000ffff 2896 #define REG_RULE_MAX_BW 0x0000ffff 2897 #define REG_RULE_REG_PWR 0x00ff0000 2898 #define REG_RULE_ANT_GAIN 0xff000000 2899 #define REG_RULE_PSD_INFO BIT(0) 2900 #define REG_RULE_PSD_EIRP 0xff0000 2901 2902 #define WMI_VDEV_PARAM_TXBF_SU_TX_BFEE BIT(0) 2903 #define WMI_VDEV_PARAM_TXBF_MU_TX_BFEE BIT(1) 2904 #define WMI_VDEV_PARAM_TXBF_SU_TX_BFER BIT(2) 2905 #define WMI_VDEV_PARAM_TXBF_MU_TX_BFER BIT(3) 2906 2907 #define HE_PHYCAP_BYTE_0 0 2908 #define HE_PHYCAP_BYTE_1 1 2909 #define HE_PHYCAP_BYTE_2 2 2910 #define HE_PHYCAP_BYTE_3 3 2911 #define HE_PHYCAP_BYTE_4 4 2912 2913 #define HECAP_PHY_SU_BFER BIT(7) 2914 #define HECAP_PHY_SU_BFEE BIT(0) 2915 #define HECAP_PHY_MU_BFER BIT(1) 2916 #define HECAP_PHY_UL_MUMIMO BIT(6) 2917 #define HECAP_PHY_UL_MUOFDMA BIT(7) 2918 2919 #define HECAP_PHY_SUBFMR_GET(hecap_phy) \ 2920 FIELD_GET(HECAP_PHY_SU_BFER, hecap_phy[HE_PHYCAP_BYTE_3]) 2921 2922 #define HECAP_PHY_SUBFME_GET(hecap_phy) \ 2923 FIELD_GET(HECAP_PHY_SU_BFEE, hecap_phy[HE_PHYCAP_BYTE_4]) 2924 2925 #define HECAP_PHY_MUBFMR_GET(hecap_phy) \ 2926 FIELD_GET(HECAP_PHY_MU_BFER, hecap_phy[HE_PHYCAP_BYTE_4]) 2927 2928 #define HECAP_PHY_ULMUMIMO_GET(hecap_phy) \ 2929 FIELD_GET(HECAP_PHY_UL_MUMIMO, hecap_phy[HE_PHYCAP_BYTE_2]) 2930 2931 #define HECAP_PHY_ULOFDMA_GET(hecap_phy) \ 2932 FIELD_GET(HECAP_PHY_UL_MUOFDMA, hecap_phy[HE_PHYCAP_BYTE_2]) 2933 2934 #define HE_MODE_SU_TX_BFEE BIT(0) 2935 #define HE_MODE_SU_TX_BFER BIT(1) 2936 #define HE_MODE_MU_TX_BFEE BIT(2) 2937 #define HE_MODE_MU_TX_BFER BIT(3) 2938 #define HE_MODE_DL_OFDMA BIT(4) 2939 #define HE_MODE_UL_OFDMA BIT(5) 2940 #define HE_MODE_UL_MUMIMO BIT(6) 2941 2942 #define HE_DL_MUOFDMA_ENABLE 1 2943 #define HE_UL_MUOFDMA_ENABLE 1 2944 #define HE_DL_MUMIMO_ENABLE 1 2945 #define HE_UL_MUMIMO_ENABLE 1 2946 #define HE_MU_BFEE_ENABLE 1 2947 #define HE_SU_BFEE_ENABLE 1 2948 #define HE_MU_BFER_ENABLE 1 2949 #define HE_SU_BFER_ENABLE 1 2950 2951 #define HE_VHT_SOUNDING_MODE_ENABLE 1 2952 #define HE_SU_MU_SOUNDING_MODE_ENABLE 1 2953 #define HE_TRIG_NONTRIG_SOUNDING_MODE_ENABLE 1 2954 2955 /* HE or VHT Sounding */ 2956 #define HE_VHT_SOUNDING_MODE BIT(0) 2957 /* SU or MU Sounding */ 2958 #define HE_SU_MU_SOUNDING_MODE BIT(2) 2959 /* Trig or Non-Trig Sounding */ 2960 #define HE_TRIG_NONTRIG_SOUNDING_MODE BIT(3) 2961 2962 #define WMI_TXBF_STS_CAP_OFFSET_LSB 4 2963 #define WMI_TXBF_STS_CAP_OFFSET_MASK 0x70 2964 #define WMI_BF_SOUND_DIM_OFFSET_LSB 8 2965 #define WMI_BF_SOUND_DIM_OFFSET_MASK 0x700 2966 2967 struct pdev_params { 2968 u32 param_id; 2969 u32 param_value; 2970 }; 2971 2972 enum wmi_peer_type { 2973 WMI_PEER_TYPE_DEFAULT = 0, 2974 WMI_PEER_TYPE_BSS = 1, 2975 WMI_PEER_TYPE_TDLS = 2, 2976 }; 2977 2978 struct wmi_peer_create_cmd { 2979 u32 tlv_header; 2980 u32 vdev_id; 2981 struct wmi_mac_addr peer_macaddr; 2982 u32 peer_type; 2983 } __packed; 2984 2985 struct wmi_peer_delete_cmd { 2986 u32 tlv_header; 2987 u32 vdev_id; 2988 struct wmi_mac_addr peer_macaddr; 2989 } __packed; 2990 2991 struct wmi_peer_reorder_queue_setup_cmd { 2992 u32 tlv_header; 2993 u32 vdev_id; 2994 struct wmi_mac_addr peer_macaddr; 2995 u32 tid; 2996 u32 queue_ptr_lo; 2997 u32 queue_ptr_hi; 2998 u32 queue_no; 2999 u32 ba_window_size_valid; 3000 u32 ba_window_size; 3001 } __packed; 3002 3003 struct wmi_peer_reorder_queue_remove_cmd { 3004 u32 tlv_header; 3005 u32 vdev_id; 3006 struct wmi_mac_addr peer_macaddr; 3007 u32 tid_mask; 3008 } __packed; 3009 3010 struct gpio_config_params { 3011 u32 gpio_num; 3012 u32 input; 3013 u32 pull_type; 3014 u32 intr_mode; 3015 }; 3016 3017 enum wmi_gpio_type { 3018 WMI_GPIO_PULL_NONE, 3019 WMI_GPIO_PULL_UP, 3020 WMI_GPIO_PULL_DOWN 3021 }; 3022 3023 enum wmi_gpio_intr_type { 3024 WMI_GPIO_INTTYPE_DISABLE, 3025 WMI_GPIO_INTTYPE_RISING_EDGE, 3026 WMI_GPIO_INTTYPE_FALLING_EDGE, 3027 WMI_GPIO_INTTYPE_BOTH_EDGE, 3028 WMI_GPIO_INTTYPE_LEVEL_LOW, 3029 WMI_GPIO_INTTYPE_LEVEL_HIGH 3030 }; 3031 3032 enum wmi_bss_chan_info_req_type { 3033 WMI_BSS_SURVEY_REQ_TYPE_READ = 1, 3034 WMI_BSS_SURVEY_REQ_TYPE_READ_CLEAR, 3035 }; 3036 3037 struct wmi_gpio_config_cmd_param { 3038 u32 tlv_header; 3039 u32 gpio_num; 3040 u32 input; 3041 u32 pull_type; 3042 u32 intr_mode; 3043 }; 3044 3045 struct gpio_output_params { 3046 u32 gpio_num; 3047 u32 set; 3048 }; 3049 3050 struct wmi_gpio_output_cmd_param { 3051 u32 tlv_header; 3052 u32 gpio_num; 3053 u32 set; 3054 }; 3055 3056 struct set_fwtest_params { 3057 u32 arg; 3058 u32 value; 3059 }; 3060 3061 struct wmi_fwtest_set_param_cmd_param { 3062 u32 tlv_header; 3063 u32 param_id; 3064 u32 param_value; 3065 }; 3066 3067 struct wmi_pdev_set_param_cmd { 3068 u32 tlv_header; 3069 u32 pdev_id; 3070 u32 param_id; 3071 u32 param_value; 3072 } __packed; 3073 3074 struct wmi_pdev_set_ps_mode_cmd { 3075 u32 tlv_header; 3076 u32 vdev_id; 3077 u32 sta_ps_mode; 3078 } __packed; 3079 3080 struct wmi_pdev_suspend_cmd { 3081 u32 tlv_header; 3082 u32 pdev_id; 3083 u32 suspend_opt; 3084 } __packed; 3085 3086 struct wmi_pdev_resume_cmd { 3087 u32 tlv_header; 3088 u32 pdev_id; 3089 } __packed; 3090 3091 struct wmi_pdev_bss_chan_info_req_cmd { 3092 u32 tlv_header; 3093 /* ref wmi_bss_chan_info_req_type */ 3094 u32 req_type; 3095 u32 pdev_id; 3096 } __packed; 3097 3098 struct wmi_ap_ps_peer_cmd { 3099 u32 tlv_header; 3100 u32 vdev_id; 3101 struct wmi_mac_addr peer_macaddr; 3102 u32 param; 3103 u32 value; 3104 } __packed; 3105 3106 struct wmi_sta_powersave_param_cmd { 3107 u32 tlv_header; 3108 u32 vdev_id; 3109 u32 param; 3110 u32 value; 3111 } __packed; 3112 3113 struct wmi_pdev_set_regdomain_cmd { 3114 u32 tlv_header; 3115 u32 pdev_id; 3116 u32 reg_domain; 3117 u32 reg_domain_2g; 3118 u32 reg_domain_5g; 3119 u32 conformance_test_limit_2g; 3120 u32 conformance_test_limit_5g; 3121 u32 dfs_domain; 3122 } __packed; 3123 3124 struct wmi_peer_set_param_cmd { 3125 u32 tlv_header; 3126 u32 vdev_id; 3127 struct wmi_mac_addr peer_macaddr; 3128 u32 param_id; 3129 u32 param_value; 3130 } __packed; 3131 3132 struct wmi_peer_flush_tids_cmd { 3133 u32 tlv_header; 3134 u32 vdev_id; 3135 struct wmi_mac_addr peer_macaddr; 3136 u32 peer_tid_bitmap; 3137 } __packed; 3138 3139 struct wmi_dfs_phyerr_offload_cmd { 3140 u32 tlv_header; 3141 u32 pdev_id; 3142 } __packed; 3143 3144 struct wmi_bcn_offload_ctrl_cmd { 3145 u32 tlv_header; 3146 u32 vdev_id; 3147 u32 bcn_ctrl_op; 3148 } __packed; 3149 3150 enum scan_dwelltime_adaptive_mode { 3151 SCAN_DWELL_MODE_DEFAULT = 0, 3152 SCAN_DWELL_MODE_CONSERVATIVE = 1, 3153 SCAN_DWELL_MODE_MODERATE = 2, 3154 SCAN_DWELL_MODE_AGGRESSIVE = 3, 3155 SCAN_DWELL_MODE_STATIC = 4 3156 }; 3157 3158 #define WLAN_SSID_MAX_LEN 32 3159 3160 struct element_info { 3161 u32 len; 3162 u8 *ptr; 3163 }; 3164 3165 struct wlan_ssid { 3166 u8 length; 3167 u8 ssid[WLAN_SSID_MAX_LEN]; 3168 }; 3169 3170 #define WMI_IE_BITMAP_SIZE 8 3171 3172 /* prefix used by scan requestor ids on the host */ 3173 #define WMI_HOST_SCAN_REQUESTOR_ID_PREFIX 0xA000 3174 3175 /* prefix used by scan request ids generated on the host */ 3176 /* host cycles through the lower 12 bits to generate ids */ 3177 #define WMI_HOST_SCAN_REQ_ID_PREFIX 0xA000 3178 3179 /* Values lower than this may be refused by some firmware revisions with a scan 3180 * completion with a timedout reason. 3181 */ 3182 #define WMI_SCAN_CHAN_MIN_TIME_MSEC 40 3183 3184 /* Scan priority numbers must be sequential, starting with 0 */ 3185 enum wmi_scan_priority { 3186 WMI_SCAN_PRIORITY_VERY_LOW = 0, 3187 WMI_SCAN_PRIORITY_LOW, 3188 WMI_SCAN_PRIORITY_MEDIUM, 3189 WMI_SCAN_PRIORITY_HIGH, 3190 WMI_SCAN_PRIORITY_VERY_HIGH, 3191 WMI_SCAN_PRIORITY_COUNT /* number of priorities supported */ 3192 }; 3193 3194 enum wmi_scan_event_type { 3195 WMI_SCAN_EVENT_STARTED = BIT(0), 3196 WMI_SCAN_EVENT_COMPLETED = BIT(1), 3197 WMI_SCAN_EVENT_BSS_CHANNEL = BIT(2), 3198 WMI_SCAN_EVENT_FOREIGN_CHAN = BIT(3), 3199 WMI_SCAN_EVENT_DEQUEUED = BIT(4), 3200 /* possibly by high-prio scan */ 3201 WMI_SCAN_EVENT_PREEMPTED = BIT(5), 3202 WMI_SCAN_EVENT_START_FAILED = BIT(6), 3203 WMI_SCAN_EVENT_RESTARTED = BIT(7), 3204 WMI_SCAN_EVENT_FOREIGN_CHAN_EXIT = BIT(8), 3205 WMI_SCAN_EVENT_SUSPENDED = BIT(9), 3206 WMI_SCAN_EVENT_RESUMED = BIT(10), 3207 WMI_SCAN_EVENT_MAX = BIT(15), 3208 }; 3209 3210 enum wmi_scan_completion_reason { 3211 WMI_SCAN_REASON_COMPLETED, 3212 WMI_SCAN_REASON_CANCELLED, 3213 WMI_SCAN_REASON_PREEMPTED, 3214 WMI_SCAN_REASON_TIMEDOUT, 3215 WMI_SCAN_REASON_INTERNAL_FAILURE, 3216 WMI_SCAN_REASON_MAX, 3217 }; 3218 3219 struct wmi_start_scan_cmd { 3220 u32 tlv_header; 3221 u32 scan_id; 3222 u32 scan_req_id; 3223 u32 vdev_id; 3224 u32 scan_priority; 3225 u32 notify_scan_events; 3226 u32 dwell_time_active; 3227 u32 dwell_time_passive; 3228 u32 min_rest_time; 3229 u32 max_rest_time; 3230 u32 repeat_probe_time; 3231 u32 probe_spacing_time; 3232 u32 idle_time; 3233 u32 max_scan_time; 3234 u32 probe_delay; 3235 u32 scan_ctrl_flags; 3236 u32 burst_duration; 3237 u32 num_chan; 3238 u32 num_bssid; 3239 u32 num_ssids; 3240 u32 ie_len; 3241 u32 n_probes; 3242 struct wmi_mac_addr mac_addr; 3243 struct wmi_mac_addr mac_mask; 3244 u32 ie_bitmap[WMI_IE_BITMAP_SIZE]; 3245 u32 num_vendor_oui; 3246 u32 scan_ctrl_flags_ext; 3247 u32 dwell_time_active_2g; 3248 u32 dwell_time_active_6g; 3249 u32 dwell_time_passive_6g; 3250 u32 scan_start_offset; 3251 } __packed; 3252 3253 #define WMI_SCAN_FLAG_PASSIVE 0x1 3254 #define WMI_SCAN_ADD_BCAST_PROBE_REQ 0x2 3255 #define WMI_SCAN_ADD_CCK_RATES 0x4 3256 #define WMI_SCAN_ADD_OFDM_RATES 0x8 3257 #define WMI_SCAN_CHAN_STAT_EVENT 0x10 3258 #define WMI_SCAN_FILTER_PROBE_REQ 0x20 3259 #define WMI_SCAN_BYPASS_DFS_CHN 0x40 3260 #define WMI_SCAN_CONTINUE_ON_ERROR 0x80 3261 #define WMI_SCAN_FILTER_PROMISCUOS 0x100 3262 #define WMI_SCAN_FLAG_FORCE_ACTIVE_ON_DFS 0x200 3263 #define WMI_SCAN_ADD_TPC_IE_IN_PROBE_REQ 0x400 3264 #define WMI_SCAN_ADD_DS_IE_IN_PROBE_REQ 0x800 3265 #define WMI_SCAN_ADD_SPOOF_MAC_IN_PROBE_REQ 0x1000 3266 #define WMI_SCAN_OFFCHAN_MGMT_TX 0x2000 3267 #define WMI_SCAN_OFFCHAN_DATA_TX 0x4000 3268 #define WMI_SCAN_CAPTURE_PHY_ERROR 0x8000 3269 #define WMI_SCAN_FLAG_STRICT_PASSIVE_ON_PCHN 0x10000 3270 #define WMI_SCAN_FLAG_HALF_RATE_SUPPORT 0x20000 3271 #define WMI_SCAN_FLAG_QUARTER_RATE_SUPPORT 0x40000 3272 #define WMI_SCAN_RANDOM_SEQ_NO_IN_PROBE_REQ 0x80000 3273 #define WMI_SCAN_ENABLE_IE_WHTELIST_IN_PROBE_REQ 0x100000 3274 3275 #define WMI_SCAN_DWELL_MODE_MASK 0x00E00000 3276 #define WMI_SCAN_DWELL_MODE_SHIFT 21 3277 #define WMI_SCAN_FLAG_EXT_PASSIVE_SCAN_START_TIME_ENHANCE 0x00000800 3278 3279 #define WMI_SCAN_CONFIG_PER_CHANNEL_MASK GENMASK(19, 0) 3280 #define WMI_SCAN_CH_FLAG_SCAN_ONLY_IF_RNR_FOUND BIT(20) 3281 3282 enum { 3283 WMI_SCAN_DWELL_MODE_DEFAULT = 0, 3284 WMI_SCAN_DWELL_MODE_CONSERVATIVE = 1, 3285 WMI_SCAN_DWELL_MODE_MODERATE = 2, 3286 WMI_SCAN_DWELL_MODE_AGGRESSIVE = 3, 3287 WMI_SCAN_DWELL_MODE_STATIC = 4, 3288 }; 3289 3290 #define WMI_SCAN_SET_DWELL_MODE(flag, mode) \ 3291 ((flag) |= (((mode) << WMI_SCAN_DWELL_MODE_SHIFT) & \ 3292 WMI_SCAN_DWELL_MODE_MASK)) 3293 3294 struct hint_short_ssid { 3295 u32 freq_flags; 3296 u32 short_ssid; 3297 }; 3298 3299 struct hint_bssid { 3300 u32 freq_flags; 3301 struct wmi_mac_addr bssid; 3302 }; 3303 3304 struct scan_req_params { 3305 u32 scan_id; 3306 u32 scan_req_id; 3307 u32 vdev_id; 3308 u32 pdev_id; 3309 enum wmi_scan_priority scan_priority; 3310 union { 3311 struct { 3312 u32 scan_ev_started:1, 3313 scan_ev_completed:1, 3314 scan_ev_bss_chan:1, 3315 scan_ev_foreign_chan:1, 3316 scan_ev_dequeued:1, 3317 scan_ev_preempted:1, 3318 scan_ev_start_failed:1, 3319 scan_ev_restarted:1, 3320 scan_ev_foreign_chn_exit:1, 3321 scan_ev_invalid:1, 3322 scan_ev_gpio_timeout:1, 3323 scan_ev_suspended:1, 3324 scan_ev_resumed:1; 3325 }; 3326 u32 scan_events; 3327 }; 3328 u32 scan_ctrl_flags_ext; 3329 u32 dwell_time_active; 3330 u32 dwell_time_active_2g; 3331 u32 dwell_time_passive; 3332 u32 dwell_time_active_6g; 3333 u32 dwell_time_passive_6g; 3334 u32 min_rest_time; 3335 u32 max_rest_time; 3336 u32 repeat_probe_time; 3337 u32 probe_spacing_time; 3338 u32 idle_time; 3339 u32 max_scan_time; 3340 u32 probe_delay; 3341 union { 3342 struct { 3343 u32 scan_f_passive:1, 3344 scan_f_bcast_probe:1, 3345 scan_f_cck_rates:1, 3346 scan_f_ofdm_rates:1, 3347 scan_f_chan_stat_evnt:1, 3348 scan_f_filter_prb_req:1, 3349 scan_f_bypass_dfs_chn:1, 3350 scan_f_continue_on_err:1, 3351 scan_f_offchan_mgmt_tx:1, 3352 scan_f_offchan_data_tx:1, 3353 scan_f_promisc_mode:1, 3354 scan_f_capture_phy_err:1, 3355 scan_f_strict_passive_pch:1, 3356 scan_f_half_rate:1, 3357 scan_f_quarter_rate:1, 3358 scan_f_force_active_dfs_chn:1, 3359 scan_f_add_tpc_ie_in_probe:1, 3360 scan_f_add_ds_ie_in_probe:1, 3361 scan_f_add_spoofed_mac_in_probe:1, 3362 scan_f_add_rand_seq_in_probe:1, 3363 scan_f_en_ie_whitelist_in_probe:1, 3364 scan_f_forced:1, 3365 scan_f_2ghz:1, 3366 scan_f_5ghz:1, 3367 scan_f_80mhz:1; 3368 }; 3369 u32 scan_flags; 3370 }; 3371 enum scan_dwelltime_adaptive_mode adaptive_dwell_time_mode; 3372 u32 burst_duration; 3373 u32 num_chan; 3374 u32 num_bssid; 3375 u32 num_ssids; 3376 u32 n_probes; 3377 u32 *chan_list; 3378 u32 notify_scan_events; 3379 struct wlan_ssid ssid[WLAN_SCAN_PARAMS_MAX_SSID]; 3380 struct wmi_mac_addr bssid_list[WLAN_SCAN_PARAMS_MAX_BSSID]; 3381 struct element_info extraie; 3382 struct element_info htcap; 3383 struct element_info vhtcap; 3384 u32 num_hint_s_ssid; 3385 u32 num_hint_bssid; 3386 struct hint_short_ssid hint_s_ssid[WLAN_SCAN_MAX_HINT_S_SSID]; 3387 struct hint_bssid hint_bssid[WLAN_SCAN_MAX_HINT_BSSID]; 3388 struct wmi_mac_addr mac_addr; 3389 struct wmi_mac_addr mac_mask; 3390 }; 3391 3392 struct wmi_ssid_arg { 3393 int len; 3394 const u8 *ssid; 3395 }; 3396 3397 struct wmi_bssid_arg { 3398 const u8 *bssid; 3399 }; 3400 3401 struct wmi_start_scan_arg { 3402 u32 scan_id; 3403 u32 scan_req_id; 3404 u32 vdev_id; 3405 u32 scan_priority; 3406 u32 notify_scan_events; 3407 u32 dwell_time_active; 3408 u32 dwell_time_passive; 3409 u32 min_rest_time; 3410 u32 max_rest_time; 3411 u32 repeat_probe_time; 3412 u32 probe_spacing_time; 3413 u32 idle_time; 3414 u32 max_scan_time; 3415 u32 probe_delay; 3416 u32 scan_ctrl_flags; 3417 3418 u32 ie_len; 3419 u32 n_channels; 3420 u32 n_ssids; 3421 u32 n_bssids; 3422 3423 u8 ie[WLAN_SCAN_PARAMS_MAX_IE_LEN]; 3424 u32 channels[64]; 3425 struct wmi_ssid_arg ssids[WLAN_SCAN_PARAMS_MAX_SSID]; 3426 struct wmi_bssid_arg bssids[WLAN_SCAN_PARAMS_MAX_BSSID]; 3427 }; 3428 3429 #define WMI_SCAN_STOP_ONE 0x00000000 3430 #define WMI_SCN_STOP_VAP_ALL 0x01000000 3431 #define WMI_SCAN_STOP_ALL 0x04000000 3432 3433 /* Prefix 0xA000 indicates that the scan request 3434 * is trigger by HOST 3435 */ 3436 #define ATH11K_SCAN_ID 0xA000 3437 3438 enum scan_cancel_req_type { 3439 WLAN_SCAN_CANCEL_SINGLE = 1, 3440 WLAN_SCAN_CANCEL_VDEV_ALL, 3441 WLAN_SCAN_CANCEL_PDEV_ALL, 3442 }; 3443 3444 struct scan_cancel_param { 3445 u32 requester; 3446 u32 scan_id; 3447 enum scan_cancel_req_type req_type; 3448 u32 vdev_id; 3449 u32 pdev_id; 3450 }; 3451 3452 struct wmi_bcn_send_from_host_cmd { 3453 u32 tlv_header; 3454 u32 vdev_id; 3455 u32 data_len; 3456 union { 3457 u32 frag_ptr; 3458 u32 frag_ptr_lo; 3459 }; 3460 u32 frame_ctrl; 3461 u32 dtim_flag; 3462 u32 bcn_antenna; 3463 u32 frag_ptr_hi; 3464 }; 3465 3466 #define WMI_CHAN_INFO_MODE GENMASK(5, 0) 3467 #define WMI_CHAN_INFO_HT40_PLUS BIT(6) 3468 #define WMI_CHAN_INFO_PASSIVE BIT(7) 3469 #define WMI_CHAN_INFO_ADHOC_ALLOWED BIT(8) 3470 #define WMI_CHAN_INFO_AP_DISABLED BIT(9) 3471 #define WMI_CHAN_INFO_DFS BIT(10) 3472 #define WMI_CHAN_INFO_ALLOW_HT BIT(11) 3473 #define WMI_CHAN_INFO_ALLOW_VHT BIT(12) 3474 #define WMI_CHAN_INFO_CHAN_CHANGE_CAUSE_CSA BIT(13) 3475 #define WMI_CHAN_INFO_HALF_RATE BIT(14) 3476 #define WMI_CHAN_INFO_QUARTER_RATE BIT(15) 3477 #define WMI_CHAN_INFO_DFS_FREQ2 BIT(16) 3478 #define WMI_CHAN_INFO_ALLOW_HE BIT(17) 3479 #define WMI_CHAN_INFO_PSC BIT(18) 3480 3481 #define WMI_CHAN_REG_INFO1_MIN_PWR GENMASK(7, 0) 3482 #define WMI_CHAN_REG_INFO1_MAX_PWR GENMASK(15, 8) 3483 #define WMI_CHAN_REG_INFO1_MAX_REG_PWR GENMASK(23, 16) 3484 #define WMI_CHAN_REG_INFO1_REG_CLS GENMASK(31, 24) 3485 3486 #define WMI_CHAN_REG_INFO2_ANT_MAX GENMASK(7, 0) 3487 #define WMI_CHAN_REG_INFO2_MAX_TX_PWR GENMASK(15, 8) 3488 3489 struct wmi_channel { 3490 u32 tlv_header; 3491 u32 mhz; 3492 u32 band_center_freq1; 3493 u32 band_center_freq2; 3494 u32 info; 3495 u32 reg_info_1; 3496 u32 reg_info_2; 3497 } __packed; 3498 3499 struct wmi_mgmt_params { 3500 void *tx_frame; 3501 u16 frm_len; 3502 u8 vdev_id; 3503 u16 chanfreq; 3504 void *pdata; 3505 u16 desc_id; 3506 u8 *macaddr; 3507 }; 3508 3509 enum wmi_sta_ps_mode { 3510 WMI_STA_PS_MODE_DISABLED = 0, 3511 WMI_STA_PS_MODE_ENABLED = 1, 3512 }; 3513 3514 #define WMI_SMPS_MASK_LOWER_16BITS 0xFF 3515 #define WMI_SMPS_MASK_UPPER_3BITS 0x7 3516 #define WMI_SMPS_PARAM_VALUE_SHIFT 29 3517 3518 #define ATH11K_WMI_FW_HANG_ASSERT_TYPE 1 3519 #define ATH11K_WMI_FW_HANG_DELAY 0 3520 3521 /* type, 0:unused 1: ASSERT 2: not respond detect command 3522 * delay_time_ms, the simulate will delay time 3523 */ 3524 3525 struct wmi_force_fw_hang_cmd { 3526 u32 tlv_header; 3527 u32 type; 3528 u32 delay_time_ms; 3529 }; 3530 3531 struct wmi_vdev_set_param_cmd { 3532 u32 tlv_header; 3533 u32 vdev_id; 3534 u32 param_id; 3535 u32 param_value; 3536 } __packed; 3537 3538 enum wmi_stats_id { 3539 WMI_REQUEST_PEER_STAT = BIT(0), 3540 WMI_REQUEST_AP_STAT = BIT(1), 3541 WMI_REQUEST_PDEV_STAT = BIT(2), 3542 WMI_REQUEST_VDEV_STAT = BIT(3), 3543 WMI_REQUEST_BCNFLT_STAT = BIT(4), 3544 WMI_REQUEST_VDEV_RATE_STAT = BIT(5), 3545 WMI_REQUEST_INST_STAT = BIT(6), 3546 WMI_REQUEST_MIB_STAT = BIT(7), 3547 WMI_REQUEST_RSSI_PER_CHAIN_STAT = BIT(8), 3548 WMI_REQUEST_CONGESTION_STAT = BIT(9), 3549 WMI_REQUEST_PEER_EXTD_STAT = BIT(10), 3550 WMI_REQUEST_BCN_STAT = BIT(11), 3551 WMI_REQUEST_BCN_STAT_RESET = BIT(12), 3552 WMI_REQUEST_PEER_EXTD2_STAT = BIT(13), 3553 }; 3554 3555 struct wmi_request_stats_cmd { 3556 u32 tlv_header; 3557 enum wmi_stats_id stats_id; 3558 u32 vdev_id; 3559 struct wmi_mac_addr peer_macaddr; 3560 u32 pdev_id; 3561 } __packed; 3562 3563 struct wmi_get_pdev_temperature_cmd { 3564 u32 tlv_header; 3565 u32 param; 3566 u32 pdev_id; 3567 } __packed; 3568 3569 struct wmi_ftm_seg_hdr { 3570 u32 len; 3571 u32 msgref; 3572 u32 segmentinfo; 3573 u32 pdev_id; 3574 } __packed; 3575 3576 struct wmi_ftm_cmd { 3577 u32 tlv_header; 3578 struct wmi_ftm_seg_hdr seg_hdr; 3579 u8 data[]; 3580 } __packed; 3581 3582 struct wmi_ftm_event_msg { 3583 struct wmi_ftm_seg_hdr seg_hdr; 3584 u8 data[]; 3585 } __packed; 3586 3587 #define WMI_BEACON_TX_BUFFER_SIZE 512 3588 3589 #define WMI_EMA_TMPL_IDX_SHIFT 8 3590 #define WMI_EMA_FIRST_TMPL_SHIFT 16 3591 #define WMI_EMA_LAST_TMPL_SHIFT 24 3592 3593 struct wmi_bcn_tmpl_cmd { 3594 u32 tlv_header; 3595 u32 vdev_id; 3596 u32 tim_ie_offset; 3597 u32 buf_len; 3598 u32 csa_switch_count_offset; 3599 u32 ext_csa_switch_count_offset; 3600 u32 csa_event_bitmap; 3601 u32 mbssid_ie_offset; 3602 u32 esp_ie_offset; 3603 u32 csc_switch_count_offset; 3604 u32 csc_event_bitmap; 3605 u32 mu_edca_ie_offset; 3606 u32 feature_enable_bitmap; 3607 u32 ema_params; 3608 } __packed; 3609 3610 struct wmi_key_seq_counter { 3611 u32 key_seq_counter_l; 3612 u32 key_seq_counter_h; 3613 } __packed; 3614 3615 struct wmi_vdev_install_key_cmd { 3616 u32 tlv_header; 3617 u32 vdev_id; 3618 struct wmi_mac_addr peer_macaddr; 3619 u32 key_idx; 3620 u32 key_flags; 3621 u32 key_cipher; 3622 struct wmi_key_seq_counter key_rsc_counter; 3623 struct wmi_key_seq_counter key_global_rsc_counter; 3624 struct wmi_key_seq_counter key_tsc_counter; 3625 u8 wpi_key_rsc_counter[16]; 3626 u8 wpi_key_tsc_counter[16]; 3627 u32 key_len; 3628 u32 key_txmic_len; 3629 u32 key_rxmic_len; 3630 u32 is_group_key_id_valid; 3631 u32 group_key_id; 3632 3633 /* Followed by key_data containing key followed by 3634 * tx mic and then rx mic 3635 */ 3636 } __packed; 3637 3638 struct wmi_vdev_install_key_arg { 3639 u32 vdev_id; 3640 const u8 *macaddr; 3641 u32 key_idx; 3642 u32 key_flags; 3643 u32 key_cipher; 3644 u32 key_len; 3645 u32 key_txmic_len; 3646 u32 key_rxmic_len; 3647 u64 key_rsc_counter; 3648 const void *key_data; 3649 }; 3650 3651 #define WMI_MAX_SUPPORTED_RATES 128 3652 #define WMI_HOST_MAX_HECAP_PHY_SIZE 3 3653 #define WMI_HOST_MAX_HE_RATE_SET 3 3654 #define WMI_HECAP_TXRX_MCS_NSS_IDX_80 0 3655 #define WMI_HECAP_TXRX_MCS_NSS_IDX_160 1 3656 #define WMI_HECAP_TXRX_MCS_NSS_IDX_80_80 2 3657 3658 struct wmi_rate_set_arg { 3659 u32 num_rates; 3660 u8 rates[WMI_MAX_SUPPORTED_RATES]; 3661 }; 3662 3663 struct peer_assoc_params { 3664 struct wmi_mac_addr peer_macaddr; 3665 u32 vdev_id; 3666 u32 peer_new_assoc; 3667 u32 peer_associd; 3668 u32 peer_flags; 3669 u32 peer_caps; 3670 u32 peer_listen_intval; 3671 u32 peer_ht_caps; 3672 u32 peer_max_mpdu; 3673 u32 peer_mpdu_density; 3674 u32 peer_rate_caps; 3675 u32 peer_nss; 3676 u32 peer_vht_caps; 3677 u32 peer_phymode; 3678 u32 peer_ht_info[2]; 3679 struct wmi_rate_set_arg peer_legacy_rates; 3680 struct wmi_rate_set_arg peer_ht_rates; 3681 u32 rx_max_rate; 3682 u32 rx_mcs_set; 3683 u32 tx_max_rate; 3684 u32 tx_mcs_set; 3685 u8 vht_capable; 3686 u8 min_data_rate; 3687 u32 tx_max_mcs_nss; 3688 u32 peer_bw_rxnss_override; 3689 bool is_pmf_enabled; 3690 bool is_wme_set; 3691 bool qos_flag; 3692 bool apsd_flag; 3693 bool ht_flag; 3694 bool bw_40; 3695 bool bw_80; 3696 bool bw_160; 3697 bool stbc_flag; 3698 bool ldpc_flag; 3699 bool static_mimops_flag; 3700 bool dynamic_mimops_flag; 3701 bool spatial_mux_flag; 3702 bool vht_flag; 3703 bool vht_ng_flag; 3704 bool need_ptk_4_way; 3705 bool need_gtk_2_way; 3706 bool auth_flag; 3707 bool safe_mode_enabled; 3708 bool amsdu_disable; 3709 /* Use common structure */ 3710 u8 peer_mac[ETH_ALEN]; 3711 3712 bool he_flag; 3713 u32 peer_he_cap_macinfo[2]; 3714 u32 peer_he_cap_macinfo_internal; 3715 u32 peer_he_caps_6ghz; 3716 u32 peer_he_ops; 3717 u32 peer_he_cap_phyinfo[WMI_HOST_MAX_HECAP_PHY_SIZE]; 3718 u32 peer_he_mcs_count; 3719 u32 peer_he_rx_mcs_set[WMI_HOST_MAX_HE_RATE_SET]; 3720 u32 peer_he_tx_mcs_set[WMI_HOST_MAX_HE_RATE_SET]; 3721 bool twt_responder; 3722 bool twt_requester; 3723 bool is_assoc; 3724 struct ath11k_ppe_threshold peer_ppet; 3725 }; 3726 3727 struct wmi_peer_assoc_complete_cmd { 3728 u32 tlv_header; 3729 struct wmi_mac_addr peer_macaddr; 3730 u32 vdev_id; 3731 u32 peer_new_assoc; 3732 u32 peer_associd; 3733 u32 peer_flags; 3734 u32 peer_caps; 3735 u32 peer_listen_intval; 3736 u32 peer_ht_caps; 3737 u32 peer_max_mpdu; 3738 u32 peer_mpdu_density; 3739 u32 peer_rate_caps; 3740 u32 peer_nss; 3741 u32 peer_vht_caps; 3742 u32 peer_phymode; 3743 u32 peer_ht_info[2]; 3744 u32 num_peer_legacy_rates; 3745 u32 num_peer_ht_rates; 3746 u32 peer_bw_rxnss_override; 3747 struct wmi_ppe_threshold peer_ppet; 3748 u32 peer_he_cap_info; 3749 u32 peer_he_ops; 3750 u32 peer_he_cap_phy[WMI_MAX_HECAP_PHY_SIZE]; 3751 u32 peer_he_mcs; 3752 u32 peer_he_cap_info_ext; 3753 u32 peer_he_cap_info_internal; 3754 u32 min_data_rate; 3755 u32 peer_he_caps_6ghz; 3756 } __packed; 3757 3758 struct wmi_stop_scan_cmd { 3759 u32 tlv_header; 3760 u32 requestor; 3761 u32 scan_id; 3762 u32 req_type; 3763 u32 vdev_id; 3764 u32 pdev_id; 3765 }; 3766 3767 struct scan_chan_list_params { 3768 u32 pdev_id; 3769 u16 nallchans; 3770 struct channel_param ch_param[]; 3771 }; 3772 3773 struct wmi_scan_chan_list_cmd { 3774 u32 tlv_header; 3775 u32 num_scan_chans; 3776 u32 flags; 3777 u32 pdev_id; 3778 } __packed; 3779 3780 struct wmi_scan_prob_req_oui_cmd { 3781 u32 tlv_header; 3782 u32 prob_req_oui; 3783 } __packed; 3784 3785 #define WMI_MGMT_SEND_DOWNLD_LEN 64 3786 3787 #define WMI_TX_PARAMS_DWORD0_POWER GENMASK(7, 0) 3788 #define WMI_TX_PARAMS_DWORD0_MCS_MASK GENMASK(19, 8) 3789 #define WMI_TX_PARAMS_DWORD0_NSS_MASK GENMASK(27, 20) 3790 #define WMI_TX_PARAMS_DWORD0_RETRY_LIMIT GENMASK(31, 28) 3791 3792 #define WMI_TX_PARAMS_DWORD1_CHAIN_MASK GENMASK(7, 0) 3793 #define WMI_TX_PARAMS_DWORD1_BW_MASK GENMASK(14, 8) 3794 #define WMI_TX_PARAMS_DWORD1_PREAMBLE_TYPE GENMASK(19, 15) 3795 #define WMI_TX_PARAMS_DWORD1_FRAME_TYPE BIT(20) 3796 #define WMI_TX_PARAMS_DWORD1_RSVD GENMASK(31, 21) 3797 3798 struct wmi_mgmt_send_params { 3799 u32 tlv_header; 3800 u32 tx_params_dword0; 3801 u32 tx_params_dword1; 3802 }; 3803 3804 struct wmi_mgmt_send_cmd { 3805 u32 tlv_header; 3806 u32 vdev_id; 3807 u32 desc_id; 3808 u32 chanfreq; 3809 u32 paddr_lo; 3810 u32 paddr_hi; 3811 u32 frame_len; 3812 u32 buf_len; 3813 u32 tx_params_valid; 3814 3815 /* This TLV is followed by struct wmi_mgmt_frame */ 3816 3817 /* Followed by struct wmi_mgmt_send_params */ 3818 } __packed; 3819 3820 struct wmi_sta_powersave_mode_cmd { 3821 u32 tlv_header; 3822 u32 vdev_id; 3823 u32 sta_ps_mode; 3824 }; 3825 3826 struct wmi_sta_smps_force_mode_cmd { 3827 u32 tlv_header; 3828 u32 vdev_id; 3829 u32 forced_mode; 3830 }; 3831 3832 struct wmi_sta_smps_param_cmd { 3833 u32 tlv_header; 3834 u32 vdev_id; 3835 u32 param; 3836 u32 value; 3837 }; 3838 3839 struct wmi_bcn_prb_info { 3840 u32 tlv_header; 3841 u32 caps; 3842 u32 erp; 3843 } __packed; 3844 3845 enum { 3846 WMI_PDEV_SUSPEND, 3847 WMI_PDEV_SUSPEND_AND_DISABLE_INTR, 3848 }; 3849 3850 struct green_ap_ps_params { 3851 u32 value; 3852 }; 3853 3854 struct wmi_pdev_green_ap_ps_enable_cmd_param { 3855 u32 tlv_header; 3856 u32 pdev_id; 3857 u32 enable; 3858 }; 3859 3860 struct ap_ps_params { 3861 u32 vdev_id; 3862 u32 param; 3863 u32 value; 3864 }; 3865 3866 struct vdev_set_params { 3867 u32 if_id; 3868 u32 param_id; 3869 u32 param_value; 3870 }; 3871 3872 struct stats_request_params { 3873 u32 stats_id; 3874 u32 vdev_id; 3875 u32 pdev_id; 3876 }; 3877 3878 struct wmi_set_current_country_params { 3879 u8 alpha2[3]; 3880 }; 3881 3882 struct wmi_set_current_country_cmd { 3883 u32 tlv_header; 3884 u32 pdev_id; 3885 u32 new_alpha2; 3886 } __packed; 3887 3888 enum set_init_cc_type { 3889 WMI_COUNTRY_INFO_TYPE_ALPHA, 3890 WMI_COUNTRY_INFO_TYPE_COUNTRY_CODE, 3891 WMI_COUNTRY_INFO_TYPE_REGDOMAIN, 3892 }; 3893 3894 enum set_init_cc_flags { 3895 INVALID_CC, 3896 CC_IS_SET, 3897 REGDMN_IS_SET, 3898 ALPHA_IS_SET, 3899 }; 3900 3901 struct wmi_init_country_params { 3902 union { 3903 u16 country_code; 3904 u16 regdom_id; 3905 u8 alpha2[3]; 3906 } cc_info; 3907 enum set_init_cc_flags flags; 3908 }; 3909 3910 struct wmi_init_country_cmd { 3911 u32 tlv_header; 3912 u32 pdev_id; 3913 u32 init_cc_type; 3914 union { 3915 u32 country_code; 3916 u32 regdom_id; 3917 u32 alpha2; 3918 } cc_info; 3919 } __packed; 3920 3921 struct wmi_11d_scan_start_params { 3922 u32 vdev_id; 3923 u32 scan_period_msec; 3924 u32 start_interval_msec; 3925 }; 3926 3927 struct wmi_11d_scan_start_cmd { 3928 u32 tlv_header; 3929 u32 vdev_id; 3930 u32 scan_period_msec; 3931 u32 start_interval_msec; 3932 } __packed; 3933 3934 struct wmi_11d_scan_stop_cmd { 3935 u32 tlv_header; 3936 u32 vdev_id; 3937 } __packed; 3938 3939 struct wmi_11d_new_cc_ev { 3940 u32 new_alpha2; 3941 } __packed; 3942 3943 #define THERMAL_LEVELS 1 3944 struct tt_level_config { 3945 u32 tmplwm; 3946 u32 tmphwm; 3947 u32 dcoffpercent; 3948 u32 priority; 3949 }; 3950 3951 struct thermal_mitigation_params { 3952 u32 pdev_id; 3953 u32 enable; 3954 u32 dc; 3955 u32 dc_per_event; 3956 struct tt_level_config levelconf[THERMAL_LEVELS]; 3957 }; 3958 3959 struct wmi_therm_throt_config_request_cmd { 3960 u32 tlv_header; 3961 u32 pdev_id; 3962 u32 enable; 3963 u32 dc; 3964 u32 dc_per_event; 3965 u32 therm_throt_levels; 3966 } __packed; 3967 3968 struct wmi_therm_throt_level_config_info { 3969 u32 tlv_header; 3970 u32 temp_lwm; 3971 u32 temp_hwm; 3972 u32 dc_off_percent; 3973 u32 prio; 3974 } __packed; 3975 3976 struct wmi_delba_send_cmd { 3977 u32 tlv_header; 3978 u32 vdev_id; 3979 struct wmi_mac_addr peer_macaddr; 3980 u32 tid; 3981 u32 initiator; 3982 u32 reasoncode; 3983 } __packed; 3984 3985 struct wmi_addba_setresponse_cmd { 3986 u32 tlv_header; 3987 u32 vdev_id; 3988 struct wmi_mac_addr peer_macaddr; 3989 u32 tid; 3990 u32 statuscode; 3991 } __packed; 3992 3993 struct wmi_addba_send_cmd { 3994 u32 tlv_header; 3995 u32 vdev_id; 3996 struct wmi_mac_addr peer_macaddr; 3997 u32 tid; 3998 u32 buffersize; 3999 } __packed; 4000 4001 struct wmi_addba_clear_resp_cmd { 4002 u32 tlv_header; 4003 u32 vdev_id; 4004 struct wmi_mac_addr peer_macaddr; 4005 } __packed; 4006 4007 struct wmi_pdev_pktlog_filter_info { 4008 u32 tlv_header; 4009 struct wmi_mac_addr peer_macaddr; 4010 } __packed; 4011 4012 struct wmi_pdev_pktlog_filter_cmd { 4013 u32 tlv_header; 4014 u32 pdev_id; 4015 u32 enable; 4016 u32 filter_type; 4017 u32 num_mac; 4018 } __packed; 4019 4020 enum ath11k_wmi_pktlog_enable { 4021 ATH11K_WMI_PKTLOG_ENABLE_AUTO = 0, 4022 ATH11K_WMI_PKTLOG_ENABLE_FORCE = 1, 4023 }; 4024 4025 struct wmi_pktlog_enable_cmd { 4026 u32 tlv_header; 4027 u32 pdev_id; 4028 u32 evlist; /* WMI_PKTLOG_EVENT */ 4029 u32 enable; 4030 } __packed; 4031 4032 struct wmi_pktlog_disable_cmd { 4033 u32 tlv_header; 4034 u32 pdev_id; 4035 } __packed; 4036 4037 #define DFS_PHYERR_UNIT_TEST_CMD 0 4038 #define DFS_UNIT_TEST_MODULE 0x2b 4039 #define DFS_UNIT_TEST_TOKEN 0xAA 4040 4041 enum dfs_test_args_idx { 4042 DFS_TEST_CMDID = 0, 4043 DFS_TEST_PDEV_ID, 4044 DFS_TEST_RADAR_PARAM, 4045 DFS_MAX_TEST_ARGS, 4046 }; 4047 4048 struct wmi_dfs_unit_test_arg { 4049 u32 cmd_id; 4050 u32 pdev_id; 4051 u32 radar_param; 4052 }; 4053 4054 struct wmi_unit_test_cmd { 4055 u32 tlv_header; 4056 u32 vdev_id; 4057 u32 module_id; 4058 u32 num_args; 4059 u32 diag_token; 4060 /* Followed by test args*/ 4061 } __packed; 4062 4063 #define MAX_SUPPORTED_RATES 128 4064 4065 #define WMI_PEER_AUTH 0x00000001 4066 #define WMI_PEER_QOS 0x00000002 4067 #define WMI_PEER_NEED_PTK_4_WAY 0x00000004 4068 #define WMI_PEER_NEED_GTK_2_WAY 0x00000010 4069 #define WMI_PEER_HE 0x00000400 4070 #define WMI_PEER_APSD 0x00000800 4071 #define WMI_PEER_HT 0x00001000 4072 #define WMI_PEER_40MHZ 0x00002000 4073 #define WMI_PEER_STBC 0x00008000 4074 #define WMI_PEER_LDPC 0x00010000 4075 #define WMI_PEER_DYN_MIMOPS 0x00020000 4076 #define WMI_PEER_STATIC_MIMOPS 0x00040000 4077 #define WMI_PEER_SPATIAL_MUX 0x00200000 4078 #define WMI_PEER_TWT_REQ 0x00400000 4079 #define WMI_PEER_TWT_RESP 0x00800000 4080 #define WMI_PEER_VHT 0x02000000 4081 #define WMI_PEER_80MHZ 0x04000000 4082 #define WMI_PEER_PMF 0x08000000 4083 /* TODO: Place holder for WLAN_PEER_F_PS_PRESEND_REQUIRED = 0x10000000. 4084 * Need to be cleaned up 4085 */ 4086 #define WMI_PEER_IS_P2P_CAPABLE 0x20000000 4087 #define WMI_PEER_160MHZ 0x40000000 4088 #define WMI_PEER_SAFEMODE_EN 0x80000000 4089 4090 struct beacon_tmpl_params { 4091 u8 vdev_id; 4092 u32 tim_ie_offset; 4093 u32 tmpl_len; 4094 u32 tmpl_len_aligned; 4095 u32 csa_switch_count_offset; 4096 u32 ext_csa_switch_count_offset; 4097 u8 *frm; 4098 }; 4099 4100 struct wmi_rate_set { 4101 u32 num_rates; 4102 u32 rates[(MAX_SUPPORTED_RATES / 4) + 1]; 4103 }; 4104 4105 struct wmi_vht_rate_set { 4106 u32 tlv_header; 4107 u32 rx_max_rate; 4108 u32 rx_mcs_set; 4109 u32 tx_max_rate; 4110 u32 tx_mcs_set; 4111 u32 tx_max_mcs_nss; 4112 } __packed; 4113 4114 struct wmi_he_rate_set { 4115 u32 tlv_header; 4116 4117 /* MCS at which the peer can receive */ 4118 u32 rx_mcs_set; 4119 4120 /* MCS at which the peer can transmit */ 4121 u32 tx_mcs_set; 4122 } __packed; 4123 4124 #define MAX_REG_RULES 10 4125 #define REG_ALPHA2_LEN 2 4126 #define MAX_6GHZ_REG_RULES 5 4127 4128 enum wmi_start_event_param { 4129 WMI_VDEV_START_RESP_EVENT = 0, 4130 WMI_VDEV_RESTART_RESP_EVENT, 4131 }; 4132 4133 struct wmi_vdev_start_resp_event { 4134 u32 vdev_id; 4135 u32 requestor_id; 4136 enum wmi_start_event_param resp_type; 4137 u32 status; 4138 u32 chain_mask; 4139 u32 smps_mode; 4140 union { 4141 u32 mac_id; 4142 u32 pdev_id; 4143 }; 4144 u32 cfgd_tx_streams; 4145 u32 cfgd_rx_streams; 4146 } __packed; 4147 4148 /* VDEV start response status codes */ 4149 enum wmi_vdev_start_resp_status_code { 4150 WMI_VDEV_START_RESPONSE_STATUS_SUCCESS = 0, 4151 WMI_VDEV_START_RESPONSE_INVALID_VDEVID = 1, 4152 WMI_VDEV_START_RESPONSE_NOT_SUPPORTED = 2, 4153 WMI_VDEV_START_RESPONSE_DFS_VIOLATION = 3, 4154 WMI_VDEV_START_RESPONSE_INVALID_REGDOMAIN = 4, 4155 }; 4156 4157 /* Regaulatory Rule Flags Passed by FW */ 4158 #define REGULATORY_CHAN_DISABLED BIT(0) 4159 #define REGULATORY_CHAN_NO_IR BIT(1) 4160 #define REGULATORY_CHAN_RADAR BIT(3) 4161 #define REGULATORY_CHAN_NO_OFDM BIT(6) 4162 #define REGULATORY_CHAN_INDOOR_ONLY BIT(9) 4163 4164 #define REGULATORY_CHAN_NO_HT40 BIT(4) 4165 #define REGULATORY_CHAN_NO_80MHZ BIT(7) 4166 #define REGULATORY_CHAN_NO_160MHZ BIT(8) 4167 #define REGULATORY_CHAN_NO_20MHZ BIT(11) 4168 #define REGULATORY_CHAN_NO_10MHZ BIT(12) 4169 4170 enum wmi_reg_chan_list_cmd_type { 4171 WMI_REG_CHAN_LIST_CC_ID = 0, 4172 WMI_REG_CHAN_LIST_CC_EXT_ID = 1, 4173 }; 4174 4175 enum wmi_reg_cc_setting_code { 4176 WMI_REG_SET_CC_STATUS_PASS = 0, 4177 WMI_REG_CURRENT_ALPHA2_NOT_FOUND = 1, 4178 WMI_REG_INIT_ALPHA2_NOT_FOUND = 2, 4179 WMI_REG_SET_CC_CHANGE_NOT_ALLOWED = 3, 4180 WMI_REG_SET_CC_STATUS_NO_MEMORY = 4, 4181 WMI_REG_SET_CC_STATUS_FAIL = 5, 4182 4183 /* add new setting code above, update in 4184 * @enum cc_setting_code as well. 4185 * Also handle it in ath11k_wmi_cc_setting_code_to_reg() 4186 */ 4187 }; 4188 4189 enum cc_setting_code { 4190 REG_SET_CC_STATUS_PASS = 0, 4191 REG_CURRENT_ALPHA2_NOT_FOUND = 1, 4192 REG_INIT_ALPHA2_NOT_FOUND = 2, 4193 REG_SET_CC_CHANGE_NOT_ALLOWED = 3, 4194 REG_SET_CC_STATUS_NO_MEMORY = 4, 4195 REG_SET_CC_STATUS_FAIL = 5, 4196 4197 /* add new setting code above, update in 4198 * @enum wmi_reg_cc_setting_code as well. 4199 * Also handle it in ath11k_cc_status_to_str() 4200 */ 4201 }; 4202 4203 static inline enum cc_setting_code 4204 ath11k_wmi_cc_setting_code_to_reg(enum wmi_reg_cc_setting_code status_code) 4205 { 4206 switch (status_code) { 4207 case WMI_REG_SET_CC_STATUS_PASS: 4208 return REG_SET_CC_STATUS_PASS; 4209 case WMI_REG_CURRENT_ALPHA2_NOT_FOUND: 4210 return REG_CURRENT_ALPHA2_NOT_FOUND; 4211 case WMI_REG_INIT_ALPHA2_NOT_FOUND: 4212 return REG_INIT_ALPHA2_NOT_FOUND; 4213 case WMI_REG_SET_CC_CHANGE_NOT_ALLOWED: 4214 return REG_SET_CC_CHANGE_NOT_ALLOWED; 4215 case WMI_REG_SET_CC_STATUS_NO_MEMORY: 4216 return REG_SET_CC_STATUS_NO_MEMORY; 4217 case WMI_REG_SET_CC_STATUS_FAIL: 4218 return REG_SET_CC_STATUS_FAIL; 4219 } 4220 4221 return REG_SET_CC_STATUS_FAIL; 4222 } 4223 4224 static inline const char *ath11k_cc_status_to_str(enum cc_setting_code code) 4225 { 4226 switch (code) { 4227 case REG_SET_CC_STATUS_PASS: 4228 return "REG_SET_CC_STATUS_PASS"; 4229 case REG_CURRENT_ALPHA2_NOT_FOUND: 4230 return "REG_CURRENT_ALPHA2_NOT_FOUND"; 4231 case REG_INIT_ALPHA2_NOT_FOUND: 4232 return "REG_INIT_ALPHA2_NOT_FOUND"; 4233 case REG_SET_CC_CHANGE_NOT_ALLOWED: 4234 return "REG_SET_CC_CHANGE_NOT_ALLOWED"; 4235 case REG_SET_CC_STATUS_NO_MEMORY: 4236 return "REG_SET_CC_STATUS_NO_MEMORY"; 4237 case REG_SET_CC_STATUS_FAIL: 4238 return "REG_SET_CC_STATUS_FAIL"; 4239 } 4240 4241 return "Unknown CC status"; 4242 } 4243 4244 enum wmi_reg_6ghz_ap_type { 4245 WMI_REG_INDOOR_AP = 0, 4246 WMI_REG_STANDARD_POWER_AP = 1, 4247 WMI_REG_VERY_LOW_POWER_AP = 2, 4248 4249 /* add AP type above, handle in ath11k_6ghz_ap_type_to_str() 4250 */ 4251 WMI_REG_CURRENT_MAX_AP_TYPE, 4252 WMI_REG_MAX_AP_TYPE = 7, 4253 }; 4254 4255 static inline const char * 4256 ath11k_6ghz_ap_type_to_str(enum wmi_reg_6ghz_ap_type type) 4257 { 4258 switch (type) { 4259 case WMI_REG_INDOOR_AP: 4260 return "INDOOR AP"; 4261 case WMI_REG_STANDARD_POWER_AP: 4262 return "STANDARD POWER AP"; 4263 case WMI_REG_VERY_LOW_POWER_AP: 4264 return "VERY LOW POWER AP"; 4265 case WMI_REG_CURRENT_MAX_AP_TYPE: 4266 return "CURRENT_MAX_AP_TYPE"; 4267 case WMI_REG_MAX_AP_TYPE: 4268 return "MAX_AP_TYPE"; 4269 } 4270 4271 return "unknown 6 GHz AP type"; 4272 } 4273 4274 enum wmi_reg_6ghz_client_type { 4275 WMI_REG_DEFAULT_CLIENT = 0, 4276 WMI_REG_SUBORDINATE_CLIENT = 1, 4277 WMI_REG_MAX_CLIENT_TYPE = 2, 4278 4279 /* add client type above, handle it in 4280 * ath11k_6ghz_client_type_to_str() 4281 */ 4282 }; 4283 4284 static inline const char * 4285 ath11k_6ghz_client_type_to_str(enum wmi_reg_6ghz_client_type type) 4286 { 4287 switch (type) { 4288 case WMI_REG_DEFAULT_CLIENT: 4289 return "DEFAULT CLIENT"; 4290 case WMI_REG_SUBORDINATE_CLIENT: 4291 return "SUBORDINATE CLIENT"; 4292 case WMI_REG_MAX_CLIENT_TYPE: 4293 return "MAX_CLIENT_TYPE"; 4294 } 4295 4296 return "unknown 6 GHz client type"; 4297 } 4298 4299 enum reg_subdomains_6ghz { 4300 EMPTY_6GHZ = 0x0, 4301 FCC1_CLIENT_LPI_REGULAR_6GHZ = 0x01, 4302 FCC1_CLIENT_SP_6GHZ = 0x02, 4303 FCC1_AP_LPI_6GHZ = 0x03, 4304 FCC1_CLIENT_LPI_SUBORDINATE = FCC1_AP_LPI_6GHZ, 4305 FCC1_AP_SP_6GHZ = 0x04, 4306 ETSI1_LPI_6GHZ = 0x10, 4307 ETSI1_VLP_6GHZ = 0x11, 4308 ETSI2_LPI_6GHZ = 0x12, 4309 ETSI2_VLP_6GHZ = 0x13, 4310 APL1_LPI_6GHZ = 0x20, 4311 APL1_VLP_6GHZ = 0x21, 4312 4313 /* add sub-domain above, handle it in 4314 * ath11k_sub_reg_6ghz_to_str() 4315 */ 4316 }; 4317 4318 static inline const char * 4319 ath11k_sub_reg_6ghz_to_str(enum reg_subdomains_6ghz sub_id) 4320 { 4321 switch (sub_id) { 4322 case EMPTY_6GHZ: 4323 return "N/A"; 4324 case FCC1_CLIENT_LPI_REGULAR_6GHZ: 4325 return "FCC1_CLIENT_LPI_REGULAR_6GHZ"; 4326 case FCC1_CLIENT_SP_6GHZ: 4327 return "FCC1_CLIENT_SP_6GHZ"; 4328 case FCC1_AP_LPI_6GHZ: 4329 return "FCC1_AP_LPI_6GHZ/FCC1_CLIENT_LPI_SUBORDINATE"; 4330 case FCC1_AP_SP_6GHZ: 4331 return "FCC1_AP_SP_6GHZ"; 4332 case ETSI1_LPI_6GHZ: 4333 return "ETSI1_LPI_6GHZ"; 4334 case ETSI1_VLP_6GHZ: 4335 return "ETSI1_VLP_6GHZ"; 4336 case ETSI2_LPI_6GHZ: 4337 return "ETSI2_LPI_6GHZ"; 4338 case ETSI2_VLP_6GHZ: 4339 return "ETSI2_VLP_6GHZ"; 4340 case APL1_LPI_6GHZ: 4341 return "APL1_LPI_6GHZ"; 4342 case APL1_VLP_6GHZ: 4343 return "APL1_VLP_6GHZ"; 4344 } 4345 4346 return "unknown sub reg id"; 4347 } 4348 4349 enum reg_super_domain_6ghz { 4350 FCC1_6GHZ = 0x01, 4351 ETSI1_6GHZ = 0x02, 4352 ETSI2_6GHZ = 0x03, 4353 APL1_6GHZ = 0x04, 4354 FCC1_6GHZ_CL = 0x05, 4355 4356 /* add super domain above, handle it in 4357 * ath11k_super_reg_6ghz_to_str() 4358 */ 4359 }; 4360 4361 static inline const char * 4362 ath11k_super_reg_6ghz_to_str(enum reg_super_domain_6ghz domain_id) 4363 { 4364 switch (domain_id) { 4365 case FCC1_6GHZ: 4366 return "FCC1_6GHZ"; 4367 case ETSI1_6GHZ: 4368 return "ETSI1_6GHZ"; 4369 case ETSI2_6GHZ: 4370 return "ETSI2_6GHZ"; 4371 case APL1_6GHZ: 4372 return "APL1_6GHZ"; 4373 case FCC1_6GHZ_CL: 4374 return "FCC1_6GHZ_CL"; 4375 } 4376 4377 return "unknown domain id"; 4378 } 4379 4380 struct cur_reg_rule { 4381 u16 start_freq; 4382 u16 end_freq; 4383 u16 max_bw; 4384 u8 reg_power; 4385 u8 ant_gain; 4386 u16 flags; 4387 bool psd_flag; 4388 s8 psd_eirp; 4389 }; 4390 4391 struct cur_regulatory_info { 4392 enum cc_setting_code status_code; 4393 u8 num_phy; 4394 u8 phy_id; 4395 u16 reg_dmn_pair; 4396 u16 ctry_code; 4397 u8 alpha2[REG_ALPHA2_LEN + 1]; 4398 u32 dfs_region; 4399 u32 phybitmap; 4400 u32 min_bw_2ghz; 4401 u32 max_bw_2ghz; 4402 u32 min_bw_5ghz; 4403 u32 max_bw_5ghz; 4404 u32 num_2ghz_reg_rules; 4405 u32 num_5ghz_reg_rules; 4406 struct cur_reg_rule *reg_rules_2ghz_ptr; 4407 struct cur_reg_rule *reg_rules_5ghz_ptr; 4408 bool is_ext_reg_event; 4409 enum wmi_reg_6ghz_client_type client_type; 4410 bool rnr_tpe_usable; 4411 bool unspecified_ap_usable; 4412 u8 domain_code_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; 4413 u8 domain_code_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 4414 u32 domain_code_6ghz_super_id; 4415 u32 min_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; 4416 u32 max_bw_6ghz_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; 4417 u32 min_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 4418 u32 max_bw_6ghz_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 4419 u32 num_6ghz_rules_ap[WMI_REG_CURRENT_MAX_AP_TYPE]; 4420 u32 num_6ghz_rules_client[WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 4421 struct cur_reg_rule *reg_rules_6ghz_ap_ptr[WMI_REG_CURRENT_MAX_AP_TYPE]; 4422 struct cur_reg_rule *reg_rules_6ghz_client_ptr 4423 [WMI_REG_CURRENT_MAX_AP_TYPE][WMI_REG_MAX_CLIENT_TYPE]; 4424 }; 4425 4426 struct wmi_reg_chan_list_cc_event { 4427 u32 status_code; 4428 u32 phy_id; 4429 u32 alpha2; 4430 u32 num_phy; 4431 u32 country_id; 4432 u32 domain_code; 4433 u32 dfs_region; 4434 u32 phybitmap; 4435 u32 min_bw_2ghz; 4436 u32 max_bw_2ghz; 4437 u32 min_bw_5ghz; 4438 u32 max_bw_5ghz; 4439 u32 num_2ghz_reg_rules; 4440 u32 num_5ghz_reg_rules; 4441 } __packed; 4442 4443 struct wmi_regulatory_rule_struct { 4444 u32 tlv_header; 4445 u32 freq_info; 4446 u32 bw_pwr_info; 4447 u32 flag_info; 4448 }; 4449 4450 #define WMI_REG_CLIENT_MAX 4 4451 4452 struct wmi_reg_chan_list_cc_ext_event { 4453 u32 status_code; 4454 u32 phy_id; 4455 u32 alpha2; 4456 u32 num_phy; 4457 u32 country_id; 4458 u32 domain_code; 4459 u32 dfs_region; 4460 u32 phybitmap; 4461 u32 min_bw_2ghz; 4462 u32 max_bw_2ghz; 4463 u32 min_bw_5ghz; 4464 u32 max_bw_5ghz; 4465 u32 num_2ghz_reg_rules; 4466 u32 num_5ghz_reg_rules; 4467 u32 client_type; 4468 u32 rnr_tpe_usable; 4469 u32 unspecified_ap_usable; 4470 u32 domain_code_6ghz_ap_lpi; 4471 u32 domain_code_6ghz_ap_sp; 4472 u32 domain_code_6ghz_ap_vlp; 4473 u32 domain_code_6ghz_client_lpi[WMI_REG_CLIENT_MAX]; 4474 u32 domain_code_6ghz_client_sp[WMI_REG_CLIENT_MAX]; 4475 u32 domain_code_6ghz_client_vlp[WMI_REG_CLIENT_MAX]; 4476 u32 domain_code_6ghz_super_id; 4477 u32 min_bw_6ghz_ap_sp; 4478 u32 max_bw_6ghz_ap_sp; 4479 u32 min_bw_6ghz_ap_lpi; 4480 u32 max_bw_6ghz_ap_lpi; 4481 u32 min_bw_6ghz_ap_vlp; 4482 u32 max_bw_6ghz_ap_vlp; 4483 u32 min_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX]; 4484 u32 max_bw_6ghz_client_sp[WMI_REG_CLIENT_MAX]; 4485 u32 min_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX]; 4486 u32 max_bw_6ghz_client_lpi[WMI_REG_CLIENT_MAX]; 4487 u32 min_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX]; 4488 u32 max_bw_6ghz_client_vlp[WMI_REG_CLIENT_MAX]; 4489 u32 num_6ghz_reg_rules_ap_sp; 4490 u32 num_6ghz_reg_rules_ap_lpi; 4491 u32 num_6ghz_reg_rules_ap_vlp; 4492 u32 num_6ghz_reg_rules_client_sp[WMI_REG_CLIENT_MAX]; 4493 u32 num_6ghz_reg_rules_client_lpi[WMI_REG_CLIENT_MAX]; 4494 u32 num_6ghz_reg_rules_client_vlp[WMI_REG_CLIENT_MAX]; 4495 } __packed; 4496 4497 struct wmi_regulatory_ext_rule { 4498 u32 tlv_header; 4499 u32 freq_info; 4500 u32 bw_pwr_info; 4501 u32 flag_info; 4502 u32 psd_power_info; 4503 } __packed; 4504 4505 struct wmi_vdev_delete_resp_event { 4506 u32 vdev_id; 4507 } __packed; 4508 4509 struct wmi_peer_delete_resp_event { 4510 u32 vdev_id; 4511 struct wmi_mac_addr peer_macaddr; 4512 } __packed; 4513 4514 struct wmi_bcn_tx_status_event { 4515 u32 vdev_id; 4516 u32 tx_status; 4517 } __packed; 4518 4519 struct wmi_vdev_stopped_event { 4520 u32 vdev_id; 4521 } __packed; 4522 4523 struct wmi_pdev_bss_chan_info_event { 4524 u32 freq; /* Units in MHz */ 4525 u32 noise_floor; /* units are dBm */ 4526 /* rx clear - how often the channel was unused */ 4527 u32 rx_clear_count_low; 4528 u32 rx_clear_count_high; 4529 /* cycle count - elapsed time during measured period, in clock ticks */ 4530 u32 cycle_count_low; 4531 u32 cycle_count_high; 4532 /* tx cycle count - elapsed time spent in tx, in clock ticks */ 4533 u32 tx_cycle_count_low; 4534 u32 tx_cycle_count_high; 4535 /* rx cycle count - elapsed time spent in rx, in clock ticks */ 4536 u32 rx_cycle_count_low; 4537 u32 rx_cycle_count_high; 4538 /*rx_cycle cnt for my bss in 64bits format */ 4539 u32 rx_bss_cycle_count_low; 4540 u32 rx_bss_cycle_count_high; 4541 u32 pdev_id; 4542 } __packed; 4543 4544 #define WMI_VDEV_INSTALL_KEY_COMPL_STATUS_SUCCESS 0 4545 4546 struct wmi_vdev_install_key_compl_event { 4547 u32 vdev_id; 4548 struct wmi_mac_addr peer_macaddr; 4549 u32 key_idx; 4550 u32 key_flags; 4551 u32 status; 4552 } __packed; 4553 4554 struct wmi_vdev_install_key_complete_arg { 4555 u32 vdev_id; 4556 const u8 *macaddr; 4557 u32 key_idx; 4558 u32 key_flags; 4559 u32 status; 4560 }; 4561 4562 struct wmi_peer_assoc_conf_event { 4563 u32 vdev_id; 4564 struct wmi_mac_addr peer_macaddr; 4565 } __packed; 4566 4567 struct wmi_peer_assoc_conf_arg { 4568 u32 vdev_id; 4569 const u8 *macaddr; 4570 }; 4571 4572 struct wmi_fils_discovery_event { 4573 u32 vdev_id; 4574 u32 fils_tt; 4575 u32 tbtt; 4576 } __packed; 4577 4578 struct wmi_probe_resp_tx_status_event { 4579 u32 vdev_id; 4580 u32 tx_status; 4581 } __packed; 4582 4583 /* 4584 * PDEV statistics 4585 */ 4586 struct wmi_pdev_stats_base { 4587 s32 chan_nf; 4588 u32 tx_frame_count; /* Cycles spent transmitting frames */ 4589 u32 rx_frame_count; /* Cycles spent receiving frames */ 4590 u32 rx_clear_count; /* Total channel busy time, evidently */ 4591 u32 cycle_count; /* Total on-channel time */ 4592 u32 phy_err_count; 4593 u32 chan_tx_pwr; 4594 } __packed; 4595 4596 struct wmi_pdev_stats_extra { 4597 u32 ack_rx_bad; 4598 u32 rts_bad; 4599 u32 rts_good; 4600 u32 fcs_bad; 4601 u32 no_beacons; 4602 u32 mib_int_count; 4603 } __packed; 4604 4605 struct wmi_pdev_stats_tx { 4606 /* Num HTT cookies queued to dispatch list */ 4607 s32 comp_queued; 4608 4609 /* Num HTT cookies dispatched */ 4610 s32 comp_delivered; 4611 4612 /* Num MSDU queued to WAL */ 4613 s32 msdu_enqued; 4614 4615 /* Num MPDU queue to WAL */ 4616 s32 mpdu_enqued; 4617 4618 /* Num MSDUs dropped by WMM limit */ 4619 s32 wmm_drop; 4620 4621 /* Num Local frames queued */ 4622 s32 local_enqued; 4623 4624 /* Num Local frames done */ 4625 s32 local_freed; 4626 4627 /* Num queued to HW */ 4628 s32 hw_queued; 4629 4630 /* Num PPDU reaped from HW */ 4631 s32 hw_reaped; 4632 4633 /* Num underruns */ 4634 s32 underrun; 4635 4636 /* Num hw paused */ 4637 u32 hw_paused; 4638 4639 /* Num PPDUs cleaned up in TX abort */ 4640 s32 tx_abort; 4641 4642 /* Num MPDUs requeued by SW */ 4643 s32 mpdus_requeued; 4644 4645 /* excessive retries */ 4646 u32 tx_ko; 4647 4648 u32 tx_xretry; 4649 4650 /* data hw rate code */ 4651 u32 data_rc; 4652 4653 /* Scheduler self triggers */ 4654 u32 self_triggers; 4655 4656 /* frames dropped due to excessive sw retries */ 4657 u32 sw_retry_failure; 4658 4659 /* illegal rate phy errors */ 4660 u32 illgl_rate_phy_err; 4661 4662 /* wal pdev continuous xretry */ 4663 u32 pdev_cont_xretry; 4664 4665 /* wal pdev tx timeouts */ 4666 u32 pdev_tx_timeout; 4667 4668 /* wal pdev resets */ 4669 u32 pdev_resets; 4670 4671 /* frames dropped due to non-availability of stateless TIDs */ 4672 u32 stateless_tid_alloc_failure; 4673 4674 /* PhY/BB underrun */ 4675 u32 phy_underrun; 4676 4677 /* MPDU is more than txop limit */ 4678 u32 txop_ovf; 4679 4680 /* Num sequences posted */ 4681 u32 seq_posted; 4682 4683 /* Num sequences failed in queueing */ 4684 u32 seq_failed_queueing; 4685 4686 /* Num sequences completed */ 4687 u32 seq_completed; 4688 4689 /* Num sequences restarted */ 4690 u32 seq_restarted; 4691 4692 /* Num of MU sequences posted */ 4693 u32 mu_seq_posted; 4694 4695 /* Num MPDUs flushed by SW, HWPAUSED, SW TXABORT 4696 * (Reset,channel change) 4697 */ 4698 s32 mpdus_sw_flush; 4699 4700 /* Num MPDUs filtered by HW, all filter condition (TTL expired) */ 4701 s32 mpdus_hw_filter; 4702 4703 /* Num MPDUs truncated by PDG (TXOP, TBTT, 4704 * PPDU_duration based on rate, dyn_bw) 4705 */ 4706 s32 mpdus_truncated; 4707 4708 /* Num MPDUs that was tried but didn't receive ACK or BA */ 4709 s32 mpdus_ack_failed; 4710 4711 /* Num MPDUs that was dropped du to expiry. */ 4712 s32 mpdus_expired; 4713 } __packed; 4714 4715 struct wmi_pdev_stats_rx { 4716 /* Cnts any change in ring routing mid-ppdu */ 4717 s32 mid_ppdu_route_change; 4718 4719 /* Total number of statuses processed */ 4720 s32 status_rcvd; 4721 4722 /* Extra frags on rings 0-3 */ 4723 s32 r0_frags; 4724 s32 r1_frags; 4725 s32 r2_frags; 4726 s32 r3_frags; 4727 4728 /* MSDUs / MPDUs delivered to HTT */ 4729 s32 htt_msdus; 4730 s32 htt_mpdus; 4731 4732 /* MSDUs / MPDUs delivered to local stack */ 4733 s32 loc_msdus; 4734 s32 loc_mpdus; 4735 4736 /* AMSDUs that have more MSDUs than the status ring size */ 4737 s32 oversize_amsdu; 4738 4739 /* Number of PHY errors */ 4740 s32 phy_errs; 4741 4742 /* Number of PHY errors drops */ 4743 s32 phy_err_drop; 4744 4745 /* Number of mpdu errors - FCS, MIC, ENC etc. */ 4746 s32 mpdu_errs; 4747 4748 /* Num overflow errors */ 4749 s32 rx_ovfl_errs; 4750 } __packed; 4751 4752 struct wmi_pdev_stats { 4753 struct wmi_pdev_stats_base base; 4754 struct wmi_pdev_stats_tx tx; 4755 struct wmi_pdev_stats_rx rx; 4756 } __packed; 4757 4758 #define WLAN_MAX_AC 4 4759 #define MAX_TX_RATE_VALUES 10 4760 #define MAX_TX_RATE_VALUES 10 4761 4762 struct wmi_vdev_stats { 4763 u32 vdev_id; 4764 u32 beacon_snr; 4765 u32 data_snr; 4766 u32 num_tx_frames[WLAN_MAX_AC]; 4767 u32 num_rx_frames; 4768 u32 num_tx_frames_retries[WLAN_MAX_AC]; 4769 u32 num_tx_frames_failures[WLAN_MAX_AC]; 4770 u32 num_rts_fail; 4771 u32 num_rts_success; 4772 u32 num_rx_err; 4773 u32 num_rx_discard; 4774 u32 num_tx_not_acked; 4775 u32 tx_rate_history[MAX_TX_RATE_VALUES]; 4776 u32 beacon_rssi_history[MAX_TX_RATE_VALUES]; 4777 } __packed; 4778 4779 struct wmi_bcn_stats { 4780 u32 vdev_id; 4781 u32 tx_bcn_succ_cnt; 4782 u32 tx_bcn_outage_cnt; 4783 } __packed; 4784 4785 struct wmi_stats_event { 4786 u32 stats_id; 4787 u32 num_pdev_stats; 4788 u32 num_vdev_stats; 4789 u32 num_peer_stats; 4790 u32 num_bcnflt_stats; 4791 u32 num_chan_stats; 4792 u32 num_mib_stats; 4793 u32 pdev_id; 4794 u32 num_bcn_stats; 4795 u32 num_peer_extd_stats; 4796 u32 num_peer_extd2_stats; 4797 } __packed; 4798 4799 struct wmi_rssi_stats { 4800 u32 vdev_id; 4801 u32 rssi_avg_beacon[WMI_MAX_CHAINS]; 4802 u32 rssi_avg_data[WMI_MAX_CHAINS]; 4803 struct wmi_mac_addr peer_macaddr; 4804 } __packed; 4805 4806 struct wmi_per_chain_rssi_stats { 4807 u32 num_per_chain_rssi_stats; 4808 } __packed; 4809 4810 struct wmi_pdev_ctl_failsafe_chk_event { 4811 u32 pdev_id; 4812 u32 ctl_failsafe_status; 4813 } __packed; 4814 4815 struct wmi_pdev_csa_switch_ev { 4816 u32 pdev_id; 4817 u32 current_switch_count; 4818 u32 num_vdevs; 4819 } __packed; 4820 4821 struct wmi_pdev_radar_ev { 4822 u32 pdev_id; 4823 u32 detection_mode; 4824 u32 chan_freq; 4825 u32 chan_width; 4826 u32 detector_id; 4827 u32 segment_id; 4828 u32 timestamp; 4829 u32 is_chirp; 4830 s32 freq_offset; 4831 s32 sidx; 4832 } __packed; 4833 4834 struct wmi_pdev_temperature_event { 4835 /* temperature value in Celsius degree */ 4836 s32 temp; 4837 u32 pdev_id; 4838 } __packed; 4839 4840 #define WMI_RX_STATUS_OK 0x00 4841 #define WMI_RX_STATUS_ERR_CRC 0x01 4842 #define WMI_RX_STATUS_ERR_DECRYPT 0x08 4843 #define WMI_RX_STATUS_ERR_MIC 0x10 4844 #define WMI_RX_STATUS_ERR_KEY_CACHE_MISS 0x20 4845 4846 #define WLAN_MGMT_TXRX_HOST_MAX_ANTENNA 4 4847 4848 struct mgmt_rx_event_params { 4849 u32 chan_freq; 4850 u32 channel; 4851 u32 snr; 4852 u8 rssi_ctl[WLAN_MGMT_TXRX_HOST_MAX_ANTENNA]; 4853 u32 rate; 4854 enum wmi_phy_mode phy_mode; 4855 u32 buf_len; 4856 int status; 4857 u32 flags; 4858 int rssi; 4859 u32 tsf_delta; 4860 u8 pdev_id; 4861 }; 4862 4863 #define ATH_MAX_ANTENNA 4 4864 4865 struct wmi_mgmt_rx_hdr { 4866 u32 channel; 4867 u32 snr; 4868 u32 rate; 4869 u32 phy_mode; 4870 u32 buf_len; 4871 u32 status; 4872 u32 rssi_ctl[ATH_MAX_ANTENNA]; 4873 u32 flags; 4874 int rssi; 4875 u32 tsf_delta; 4876 u32 rx_tsf_l32; 4877 u32 rx_tsf_u32; 4878 u32 pdev_id; 4879 u32 chan_freq; 4880 } __packed; 4881 4882 #define MAX_ANTENNA_EIGHT 8 4883 4884 struct wmi_rssi_ctl_ext { 4885 u32 tlv_header; 4886 u32 rssi_ctl_ext[MAX_ANTENNA_EIGHT - ATH_MAX_ANTENNA]; 4887 }; 4888 4889 struct wmi_mgmt_tx_compl_event { 4890 u32 desc_id; 4891 u32 status; 4892 u32 pdev_id; 4893 u32 ppdu_id; 4894 u32 ack_rssi; 4895 } __packed; 4896 4897 struct wmi_scan_event { 4898 u32 event_type; /* %WMI_SCAN_EVENT_ */ 4899 u32 reason; /* %WMI_SCAN_REASON_ */ 4900 u32 channel_freq; /* only valid for WMI_SCAN_EVENT_FOREIGN_CHANNEL */ 4901 u32 scan_req_id; 4902 u32 scan_id; 4903 u32 vdev_id; 4904 /* TSF Timestamp when the scan event (%WMI_SCAN_EVENT_) is completed 4905 * In case of AP it is TSF of the AP vdev 4906 * In case of STA connected state, this is the TSF of the AP 4907 * In case of STA not connected, it will be the free running HW timer 4908 */ 4909 u32 tsf_timestamp; 4910 } __packed; 4911 4912 struct wmi_peer_sta_kickout_arg { 4913 const u8 *mac_addr; 4914 }; 4915 4916 struct wmi_peer_sta_kickout_event { 4917 struct wmi_mac_addr peer_macaddr; 4918 } __packed; 4919 4920 enum wmi_roam_reason { 4921 WMI_ROAM_REASON_BETTER_AP = 1, 4922 WMI_ROAM_REASON_BEACON_MISS = 2, 4923 WMI_ROAM_REASON_LOW_RSSI = 3, 4924 WMI_ROAM_REASON_SUITABLE_AP_FOUND = 4, 4925 WMI_ROAM_REASON_HO_FAILED = 5, 4926 4927 /* keep last */ 4928 WMI_ROAM_REASON_MAX, 4929 }; 4930 4931 struct wmi_roam_event { 4932 u32 vdev_id; 4933 u32 reason; 4934 u32 rssi; 4935 } __packed; 4936 4937 #define WMI_CHAN_INFO_START_RESP 0 4938 #define WMI_CHAN_INFO_END_RESP 1 4939 4940 struct wmi_chan_info_event { 4941 u32 err_code; 4942 u32 freq; 4943 u32 cmd_flags; 4944 u32 noise_floor; 4945 u32 rx_clear_count; 4946 u32 cycle_count; 4947 u32 chan_tx_pwr_range; 4948 u32 chan_tx_pwr_tp; 4949 u32 rx_frame_count; 4950 u32 my_bss_rx_cycle_count; 4951 u32 rx_11b_mode_data_duration; 4952 u32 tx_frame_cnt; 4953 u32 mac_clk_mhz; 4954 u32 vdev_id; 4955 } __packed; 4956 4957 struct ath11k_targ_cap { 4958 u32 phy_capability; 4959 u32 max_frag_entry; 4960 u32 num_rf_chains; 4961 u32 ht_cap_info; 4962 u32 vht_cap_info; 4963 u32 vht_supp_mcs; 4964 u32 hw_min_tx_power; 4965 u32 hw_max_tx_power; 4966 u32 sys_cap_info; 4967 u32 min_pkt_size_enable; 4968 u32 max_bcn_ie_size; 4969 u32 max_num_scan_channels; 4970 u32 max_supported_macs; 4971 u32 wmi_fw_sub_feat_caps; 4972 u32 txrx_chainmask; 4973 u32 default_dbs_hw_mode_index; 4974 u32 num_msdu_desc; 4975 }; 4976 4977 enum wmi_vdev_type { 4978 WMI_VDEV_TYPE_AP = 1, 4979 WMI_VDEV_TYPE_STA = 2, 4980 WMI_VDEV_TYPE_IBSS = 3, 4981 WMI_VDEV_TYPE_MONITOR = 4, 4982 }; 4983 4984 enum wmi_vdev_subtype { 4985 WMI_VDEV_SUBTYPE_NONE, 4986 WMI_VDEV_SUBTYPE_P2P_DEVICE, 4987 WMI_VDEV_SUBTYPE_P2P_CLIENT, 4988 WMI_VDEV_SUBTYPE_P2P_GO, 4989 WMI_VDEV_SUBTYPE_PROXY_STA, 4990 WMI_VDEV_SUBTYPE_MESH_NON_11S, 4991 WMI_VDEV_SUBTYPE_MESH_11S, 4992 }; 4993 4994 enum wmi_sta_powersave_param { 4995 WMI_STA_PS_PARAM_RX_WAKE_POLICY = 0, 4996 WMI_STA_PS_PARAM_TX_WAKE_THRESHOLD = 1, 4997 WMI_STA_PS_PARAM_PSPOLL_COUNT = 2, 4998 WMI_STA_PS_PARAM_INACTIVITY_TIME = 3, 4999 WMI_STA_PS_PARAM_UAPSD = 4, 5000 }; 5001 5002 #define WMI_UAPSD_AC_TYPE_DELI 0 5003 #define WMI_UAPSD_AC_TYPE_TRIG 1 5004 5005 #define WMI_UAPSD_AC_BIT_MASK(ac, type) \ 5006 ((type == WMI_UAPSD_AC_TYPE_DELI) ? \ 5007 (1 << (ac << 1)) : (1 << ((ac << 1) + 1))) 5008 5009 enum wmi_sta_ps_param_uapsd { 5010 WMI_STA_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0), 5011 WMI_STA_PS_UAPSD_AC0_TRIGGER_EN = (1 << 1), 5012 WMI_STA_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2), 5013 WMI_STA_PS_UAPSD_AC1_TRIGGER_EN = (1 << 3), 5014 WMI_STA_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4), 5015 WMI_STA_PS_UAPSD_AC2_TRIGGER_EN = (1 << 5), 5016 WMI_STA_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6), 5017 WMI_STA_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7), 5018 }; 5019 5020 #define WMI_STA_UAPSD_MAX_INTERVAL_MSEC UINT_MAX 5021 5022 struct wmi_sta_uapsd_auto_trig_param { 5023 u32 wmm_ac; 5024 u32 user_priority; 5025 u32 service_interval; 5026 u32 suspend_interval; 5027 u32 delay_interval; 5028 }; 5029 5030 struct wmi_sta_uapsd_auto_trig_cmd_fixed_param { 5031 u32 vdev_id; 5032 struct wmi_mac_addr peer_macaddr; 5033 u32 num_ac; 5034 }; 5035 5036 struct wmi_sta_uapsd_auto_trig_arg { 5037 u32 wmm_ac; 5038 u32 user_priority; 5039 u32 service_interval; 5040 u32 suspend_interval; 5041 u32 delay_interval; 5042 }; 5043 5044 enum wmi_sta_ps_param_tx_wake_threshold { 5045 WMI_STA_PS_TX_WAKE_THRESHOLD_NEVER = 0, 5046 WMI_STA_PS_TX_WAKE_THRESHOLD_ALWAYS = 1, 5047 5048 /* Values greater than one indicate that many TX attempts per beacon 5049 * interval before the STA will wake up 5050 */ 5051 }; 5052 5053 /* The maximum number of PS-Poll frames the FW will send in response to 5054 * traffic advertised in TIM before waking up (by sending a null frame with PS 5055 * = 0). Value 0 has a special meaning: there is no maximum count and the FW 5056 * will send as many PS-Poll as are necessary to retrieve buffered BU. This 5057 * parameter is used when the RX wake policy is 5058 * WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD and ignored when the RX wake 5059 * policy is WMI_STA_PS_RX_WAKE_POLICY_WAKE. 5060 */ 5061 enum wmi_sta_ps_param_pspoll_count { 5062 WMI_STA_PS_PSPOLL_COUNT_NO_MAX = 0, 5063 /* Values greater than 0 indicate the maximum number of PS-Poll frames 5064 * FW will send before waking up. 5065 */ 5066 }; 5067 5068 /* U-APSD configuration of peer station from (re)assoc request and TSPECs */ 5069 enum wmi_ap_ps_param_uapsd { 5070 WMI_AP_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0), 5071 WMI_AP_PS_UAPSD_AC0_TRIGGER_EN = (1 << 1), 5072 WMI_AP_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2), 5073 WMI_AP_PS_UAPSD_AC1_TRIGGER_EN = (1 << 3), 5074 WMI_AP_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4), 5075 WMI_AP_PS_UAPSD_AC2_TRIGGER_EN = (1 << 5), 5076 WMI_AP_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6), 5077 WMI_AP_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7), 5078 }; 5079 5080 /* U-APSD maximum service period of peer station */ 5081 enum wmi_ap_ps_peer_param_max_sp { 5082 WMI_AP_PS_PEER_PARAM_MAX_SP_UNLIMITED = 0, 5083 WMI_AP_PS_PEER_PARAM_MAX_SP_2 = 1, 5084 WMI_AP_PS_PEER_PARAM_MAX_SP_4 = 2, 5085 WMI_AP_PS_PEER_PARAM_MAX_SP_6 = 3, 5086 MAX_WMI_AP_PS_PEER_PARAM_MAX_SP, 5087 }; 5088 5089 enum wmi_ap_ps_peer_param { 5090 /** Set uapsd configuration for a given peer. 5091 * 5092 * This include the delivery and trigger enabled state for each AC. 5093 * The host MLME needs to set this based on AP capability and stations 5094 * request Set in the association request received from the station. 5095 * 5096 * Lower 8 bits of the value specify the UAPSD configuration. 5097 * 5098 * (see enum wmi_ap_ps_param_uapsd) 5099 * The default value is 0. 5100 */ 5101 WMI_AP_PS_PEER_PARAM_UAPSD = 0, 5102 5103 /** 5104 * Set the service period for a UAPSD capable station 5105 * 5106 * The service period from wme ie in the (re)assoc request frame. 5107 * 5108 * (see enum wmi_ap_ps_peer_param_max_sp) 5109 */ 5110 WMI_AP_PS_PEER_PARAM_MAX_SP = 1, 5111 5112 /** Time in seconds for aging out buffered frames 5113 * for STA in power save 5114 */ 5115 WMI_AP_PS_PEER_PARAM_AGEOUT_TIME = 2, 5116 5117 /** Specify frame types that are considered SIFS 5118 * RESP trigger frame 5119 */ 5120 WMI_AP_PS_PEER_PARAM_SIFS_RESP_FRMTYPE = 3, 5121 5122 /** Specifies the trigger state of TID. 5123 * Valid only for UAPSD frame type 5124 */ 5125 WMI_AP_PS_PEER_PARAM_SIFS_RESP_UAPSD = 4, 5126 5127 /* Specifies the WNM sleep state of a STA */ 5128 WMI_AP_PS_PEER_PARAM_WNM_SLEEP = 5, 5129 }; 5130 5131 #define DISABLE_SIFS_RESPONSE_TRIGGER 0 5132 5133 #define WMI_MAX_KEY_INDEX 3 5134 #define WMI_MAX_KEY_LEN 32 5135 5136 #define WMI_KEY_PAIRWISE 0x00 5137 #define WMI_KEY_GROUP 0x01 5138 5139 #define WMI_CIPHER_NONE 0x0 /* clear key */ 5140 #define WMI_CIPHER_WEP 0x1 5141 #define WMI_CIPHER_TKIP 0x2 5142 #define WMI_CIPHER_AES_OCB 0x3 5143 #define WMI_CIPHER_AES_CCM 0x4 5144 #define WMI_CIPHER_WAPI 0x5 5145 #define WMI_CIPHER_CKIP 0x6 5146 #define WMI_CIPHER_AES_CMAC 0x7 5147 #define WMI_CIPHER_ANY 0x8 5148 #define WMI_CIPHER_AES_GCM 0x9 5149 #define WMI_CIPHER_AES_GMAC 0xa 5150 5151 /* Value to disable fixed rate setting */ 5152 #define WMI_FIXED_RATE_NONE (0xffff) 5153 5154 #define ATH11K_RC_VERSION_OFFSET 28 5155 #define ATH11K_RC_PREAMBLE_OFFSET 8 5156 #define ATH11K_RC_NSS_OFFSET 5 5157 5158 #define ATH11K_HW_RATE_CODE(rate, nss, preamble) \ 5159 ((1 << ATH11K_RC_VERSION_OFFSET) | \ 5160 ((nss) << ATH11K_RC_NSS_OFFSET) | \ 5161 ((preamble) << ATH11K_RC_PREAMBLE_OFFSET) | \ 5162 (rate)) 5163 5164 /* Preamble types to be used with VDEV fixed rate configuration */ 5165 enum wmi_rate_preamble { 5166 WMI_RATE_PREAMBLE_OFDM, 5167 WMI_RATE_PREAMBLE_CCK, 5168 WMI_RATE_PREAMBLE_HT, 5169 WMI_RATE_PREAMBLE_VHT, 5170 WMI_RATE_PREAMBLE_HE, 5171 }; 5172 5173 /** 5174 * enum wmi_rtscts_prot_mode - Enable/Disable RTS/CTS and CTS2Self Protection. 5175 * @WMI_RTS_CTS_DISABLED: RTS/CTS protection is disabled. 5176 * @WMI_USE_RTS_CTS: RTS/CTS Enabled. 5177 * @WMI_USE_CTS2SELF: CTS to self protection Enabled. 5178 */ 5179 enum wmi_rtscts_prot_mode { 5180 WMI_RTS_CTS_DISABLED = 0, 5181 WMI_USE_RTS_CTS = 1, 5182 WMI_USE_CTS2SELF = 2, 5183 }; 5184 5185 /** 5186 * enum wmi_rtscts_profile - Selection of RTS CTS profile along with enabling 5187 * protection mode. 5188 * @WMI_RTSCTS_FOR_NO_RATESERIES: Neither of rate-series should use RTS-CTS 5189 * @WMI_RTSCTS_FOR_SECOND_RATESERIES: Only second rate-series will use RTS-CTS 5190 * @WMI_RTSCTS_ACROSS_SW_RETRIES: Only the second rate-series will use RTS-CTS, 5191 * but if there's a sw retry, both the rate 5192 * series will use RTS-CTS. 5193 * @WMI_RTSCTS_ERP: RTS/CTS used for ERP protection for every PPDU. 5194 * @WMI_RTSCTS_FOR_ALL_RATESERIES: Enable RTS-CTS for all rate series. 5195 */ 5196 enum wmi_rtscts_profile { 5197 WMI_RTSCTS_FOR_NO_RATESERIES = 0, 5198 WMI_RTSCTS_FOR_SECOND_RATESERIES = 1, 5199 WMI_RTSCTS_ACROSS_SW_RETRIES = 2, 5200 WMI_RTSCTS_ERP = 3, 5201 WMI_RTSCTS_FOR_ALL_RATESERIES = 4, 5202 }; 5203 5204 struct ath11k_hal_reg_cap { 5205 u32 eeprom_rd; 5206 u32 eeprom_rd_ext; 5207 u32 regcap1; 5208 u32 regcap2; 5209 u32 wireless_modes; 5210 u32 low_2ghz_chan; 5211 u32 high_2ghz_chan; 5212 u32 low_5ghz_chan; 5213 u32 high_5ghz_chan; 5214 }; 5215 5216 struct ath11k_mem_chunk { 5217 void *vaddr; 5218 dma_addr_t paddr; 5219 u32 len; 5220 u32 req_id; 5221 }; 5222 5223 #define WMI_SKB_HEADROOM sizeof(struct wmi_cmd_hdr) 5224 5225 enum wmi_sta_ps_param_rx_wake_policy { 5226 WMI_STA_PS_RX_WAKE_POLICY_WAKE = 0, 5227 WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD = 1, 5228 }; 5229 5230 /* Do not change existing values! Used by ath11k_frame_mode parameter 5231 * module parameter. 5232 */ 5233 enum ath11k_hw_txrx_mode { 5234 ATH11K_HW_TXRX_RAW = 0, 5235 ATH11K_HW_TXRX_NATIVE_WIFI = 1, 5236 ATH11K_HW_TXRX_ETHERNET = 2, 5237 }; 5238 5239 struct wmi_wmm_params { 5240 u32 tlv_header; 5241 u32 cwmin; 5242 u32 cwmax; 5243 u32 aifs; 5244 u32 txoplimit; 5245 u32 acm; 5246 u32 no_ack; 5247 } __packed; 5248 5249 struct wmi_wmm_params_arg { 5250 u8 acm; 5251 u8 aifs; 5252 u16 cwmin; 5253 u16 cwmax; 5254 u16 txop; 5255 u8 no_ack; 5256 }; 5257 5258 struct wmi_vdev_set_wmm_params_cmd { 5259 u32 tlv_header; 5260 u32 vdev_id; 5261 struct wmi_wmm_params wmm_params[4]; 5262 u32 wmm_param_type; 5263 } __packed; 5264 5265 struct wmi_wmm_params_all_arg { 5266 struct wmi_wmm_params_arg ac_be; 5267 struct wmi_wmm_params_arg ac_bk; 5268 struct wmi_wmm_params_arg ac_vi; 5269 struct wmi_wmm_params_arg ac_vo; 5270 }; 5271 5272 #define ATH11K_TWT_DEF_STA_CONG_TIMER_MS 5000 5273 #define ATH11K_TWT_DEF_DEFAULT_SLOT_SIZE 10 5274 #define ATH11K_TWT_DEF_CONGESTION_THRESH_SETUP 50 5275 #define ATH11K_TWT_DEF_CONGESTION_THRESH_TEARDOWN 20 5276 #define ATH11K_TWT_DEF_CONGESTION_THRESH_CRITICAL 100 5277 #define ATH11K_TWT_DEF_INTERFERENCE_THRESH_TEARDOWN 80 5278 #define ATH11K_TWT_DEF_INTERFERENCE_THRESH_SETUP 50 5279 #define ATH11K_TWT_DEF_MIN_NO_STA_SETUP 10 5280 #define ATH11K_TWT_DEF_MIN_NO_STA_TEARDOWN 2 5281 #define ATH11K_TWT_DEF_NO_OF_BCAST_MCAST_SLOTS 2 5282 #define ATH11K_TWT_DEF_MIN_NO_TWT_SLOTS 2 5283 #define ATH11K_TWT_DEF_MAX_NO_STA_TWT 500 5284 #define ATH11K_TWT_DEF_MODE_CHECK_INTERVAL 10000 5285 #define ATH11K_TWT_DEF_ADD_STA_SLOT_INTERVAL 1000 5286 #define ATH11K_TWT_DEF_REMOVE_STA_SLOT_INTERVAL 5000 5287 5288 struct wmi_twt_enable_params { 5289 u32 sta_cong_timer_ms; 5290 u32 mbss_support; 5291 u32 default_slot_size; 5292 u32 congestion_thresh_setup; 5293 u32 congestion_thresh_teardown; 5294 u32 congestion_thresh_critical; 5295 u32 interference_thresh_teardown; 5296 u32 interference_thresh_setup; 5297 u32 min_no_sta_setup; 5298 u32 min_no_sta_teardown; 5299 u32 no_of_bcast_mcast_slots; 5300 u32 min_no_twt_slots; 5301 u32 max_no_sta_twt; 5302 u32 mode_check_interval; 5303 u32 add_sta_slot_interval; 5304 u32 remove_sta_slot_interval; 5305 }; 5306 5307 struct wmi_twt_enable_params_cmd { 5308 u32 tlv_header; 5309 u32 pdev_id; 5310 u32 sta_cong_timer_ms; 5311 u32 mbss_support; 5312 u32 default_slot_size; 5313 u32 congestion_thresh_setup; 5314 u32 congestion_thresh_teardown; 5315 u32 congestion_thresh_critical; 5316 u32 interference_thresh_teardown; 5317 u32 interference_thresh_setup; 5318 u32 min_no_sta_setup; 5319 u32 min_no_sta_teardown; 5320 u32 no_of_bcast_mcast_slots; 5321 u32 min_no_twt_slots; 5322 u32 max_no_sta_twt; 5323 u32 mode_check_interval; 5324 u32 add_sta_slot_interval; 5325 u32 remove_sta_slot_interval; 5326 } __packed; 5327 5328 struct wmi_twt_disable_params_cmd { 5329 u32 tlv_header; 5330 u32 pdev_id; 5331 } __packed; 5332 5333 enum WMI_HOST_TWT_COMMAND { 5334 WMI_HOST_TWT_COMMAND_REQUEST_TWT = 0, 5335 WMI_HOST_TWT_COMMAND_SUGGEST_TWT, 5336 WMI_HOST_TWT_COMMAND_DEMAND_TWT, 5337 WMI_HOST_TWT_COMMAND_TWT_GROUPING, 5338 WMI_HOST_TWT_COMMAND_ACCEPT_TWT, 5339 WMI_HOST_TWT_COMMAND_ALTERNATE_TWT, 5340 WMI_HOST_TWT_COMMAND_DICTATE_TWT, 5341 WMI_HOST_TWT_COMMAND_REJECT_TWT, 5342 }; 5343 5344 #define WMI_TWT_ADD_DIALOG_FLAG_BCAST BIT(8) 5345 #define WMI_TWT_ADD_DIALOG_FLAG_TRIGGER BIT(9) 5346 #define WMI_TWT_ADD_DIALOG_FLAG_FLOW_TYPE BIT(10) 5347 #define WMI_TWT_ADD_DIALOG_FLAG_PROTECTION BIT(11) 5348 5349 struct wmi_twt_add_dialog_params_cmd { 5350 u32 tlv_header; 5351 u32 vdev_id; 5352 struct wmi_mac_addr peer_macaddr; 5353 u32 dialog_id; 5354 u32 wake_intvl_us; 5355 u32 wake_intvl_mantis; 5356 u32 wake_dura_us; 5357 u32 sp_offset_us; 5358 u32 flags; 5359 } __packed; 5360 5361 struct wmi_twt_add_dialog_params { 5362 u32 vdev_id; 5363 u8 peer_macaddr[ETH_ALEN]; 5364 u32 dialog_id; 5365 u32 wake_intvl_us; 5366 u32 wake_intvl_mantis; 5367 u32 wake_dura_us; 5368 u32 sp_offset_us; 5369 u8 twt_cmd; 5370 u8 flag_bcast; 5371 u8 flag_trigger; 5372 u8 flag_flow_type; 5373 u8 flag_protection; 5374 } __packed; 5375 5376 enum wmi_twt_add_dialog_status { 5377 WMI_ADD_TWT_STATUS_OK, 5378 WMI_ADD_TWT_STATUS_TWT_NOT_ENABLED, 5379 WMI_ADD_TWT_STATUS_USED_DIALOG_ID, 5380 WMI_ADD_TWT_STATUS_INVALID_PARAM, 5381 WMI_ADD_TWT_STATUS_NOT_READY, 5382 WMI_ADD_TWT_STATUS_NO_RESOURCE, 5383 WMI_ADD_TWT_STATUS_NO_ACK, 5384 WMI_ADD_TWT_STATUS_NO_RESPONSE, 5385 WMI_ADD_TWT_STATUS_DENIED, 5386 WMI_ADD_TWT_STATUS_UNKNOWN_ERROR, 5387 }; 5388 5389 struct wmi_twt_add_dialog_event { 5390 u32 vdev_id; 5391 struct wmi_mac_addr peer_macaddr; 5392 u32 dialog_id; 5393 u32 status; 5394 } __packed; 5395 5396 struct wmi_twt_del_dialog_params { 5397 u32 vdev_id; 5398 u8 peer_macaddr[ETH_ALEN]; 5399 u32 dialog_id; 5400 } __packed; 5401 5402 struct wmi_twt_del_dialog_params_cmd { 5403 u32 tlv_header; 5404 u32 vdev_id; 5405 struct wmi_mac_addr peer_macaddr; 5406 u32 dialog_id; 5407 } __packed; 5408 5409 struct wmi_twt_pause_dialog_params { 5410 u32 vdev_id; 5411 u8 peer_macaddr[ETH_ALEN]; 5412 u32 dialog_id; 5413 } __packed; 5414 5415 struct wmi_twt_pause_dialog_params_cmd { 5416 u32 tlv_header; 5417 u32 vdev_id; 5418 struct wmi_mac_addr peer_macaddr; 5419 u32 dialog_id; 5420 } __packed; 5421 5422 struct wmi_twt_resume_dialog_params { 5423 u32 vdev_id; 5424 u8 peer_macaddr[ETH_ALEN]; 5425 u32 dialog_id; 5426 u32 sp_offset_us; 5427 u32 next_twt_size; 5428 } __packed; 5429 5430 struct wmi_twt_resume_dialog_params_cmd { 5431 u32 tlv_header; 5432 u32 vdev_id; 5433 struct wmi_mac_addr peer_macaddr; 5434 u32 dialog_id; 5435 u32 sp_offset_us; 5436 u32 next_twt_size; 5437 } __packed; 5438 5439 struct wmi_obss_spatial_reuse_params_cmd { 5440 u32 tlv_header; 5441 u32 pdev_id; 5442 u32 enable; 5443 s32 obss_min; 5444 s32 obss_max; 5445 u32 vdev_id; 5446 } __packed; 5447 5448 struct wmi_pdev_obss_pd_bitmap_cmd { 5449 u32 tlv_header; 5450 u32 pdev_id; 5451 u32 bitmap[2]; 5452 } __packed; 5453 5454 #define ATH11K_BSS_COLOR_COLLISION_SCAN_PERIOD_MS 200 5455 #define ATH11K_OBSS_COLOR_COLLISION_DETECTION_DISABLE 0 5456 #define ATH11K_OBSS_COLOR_COLLISION_DETECTION 1 5457 5458 #define ATH11K_BSS_COLOR_COLLISION_DETECTION_STA_PERIOD_MS 10000 5459 #define ATH11K_BSS_COLOR_COLLISION_DETECTION_AP_PERIOD_MS 5000 5460 5461 enum wmi_bss_color_collision { 5462 WMI_BSS_COLOR_COLLISION_DISABLE = 0, 5463 WMI_BSS_COLOR_COLLISION_DETECTION, 5464 WMI_BSS_COLOR_FREE_SLOT_TIMER_EXPIRY, 5465 WMI_BSS_COLOR_FREE_SLOT_AVAILABLE, 5466 }; 5467 5468 struct wmi_obss_color_collision_cfg_params_cmd { 5469 u32 tlv_header; 5470 u32 vdev_id; 5471 u32 flags; 5472 u32 evt_type; 5473 u32 current_bss_color; 5474 u32 detection_period_ms; 5475 u32 scan_period_ms; 5476 u32 free_slot_expiry_time_ms; 5477 } __packed; 5478 5479 struct wmi_bss_color_change_enable_params_cmd { 5480 u32 tlv_header; 5481 u32 vdev_id; 5482 u32 enable; 5483 } __packed; 5484 5485 struct wmi_obss_color_collision_event { 5486 u32 vdev_id; 5487 u32 evt_type; 5488 u64 obss_color_bitmap; 5489 } __packed; 5490 5491 #define ATH11K_IPV4_TH_SEED_SIZE 5 5492 #define ATH11K_IPV6_TH_SEED_SIZE 11 5493 5494 struct ath11k_wmi_pdev_lro_config_cmd { 5495 u32 tlv_header; 5496 u32 lro_enable; 5497 u32 res; 5498 u32 th_4[ATH11K_IPV4_TH_SEED_SIZE]; 5499 u32 th_6[ATH11K_IPV6_TH_SEED_SIZE]; 5500 u32 pdev_id; 5501 } __packed; 5502 5503 #define ATH11K_WMI_SPECTRAL_COUNT_DEFAULT 0 5504 #define ATH11K_WMI_SPECTRAL_PERIOD_DEFAULT 224 5505 #define ATH11K_WMI_SPECTRAL_PRIORITY_DEFAULT 1 5506 #define ATH11K_WMI_SPECTRAL_FFT_SIZE_DEFAULT 7 5507 #define ATH11K_WMI_SPECTRAL_GC_ENA_DEFAULT 1 5508 #define ATH11K_WMI_SPECTRAL_RESTART_ENA_DEFAULT 0 5509 #define ATH11K_WMI_SPECTRAL_NOISE_FLOOR_REF_DEFAULT -96 5510 #define ATH11K_WMI_SPECTRAL_INIT_DELAY_DEFAULT 80 5511 #define ATH11K_WMI_SPECTRAL_NB_TONE_THR_DEFAULT 12 5512 #define ATH11K_WMI_SPECTRAL_STR_BIN_THR_DEFAULT 8 5513 #define ATH11K_WMI_SPECTRAL_WB_RPT_MODE_DEFAULT 0 5514 #define ATH11K_WMI_SPECTRAL_RSSI_RPT_MODE_DEFAULT 0 5515 #define ATH11K_WMI_SPECTRAL_RSSI_THR_DEFAULT 0xf0 5516 #define ATH11K_WMI_SPECTRAL_PWR_FORMAT_DEFAULT 0 5517 #define ATH11K_WMI_SPECTRAL_RPT_MODE_DEFAULT 2 5518 #define ATH11K_WMI_SPECTRAL_BIN_SCALE_DEFAULT 1 5519 #define ATH11K_WMI_SPECTRAL_DBM_ADJ_DEFAULT 1 5520 #define ATH11K_WMI_SPECTRAL_CHN_MASK_DEFAULT 1 5521 5522 struct ath11k_wmi_vdev_spectral_conf_param { 5523 u32 vdev_id; 5524 u32 scan_count; 5525 u32 scan_period; 5526 u32 scan_priority; 5527 u32 scan_fft_size; 5528 u32 scan_gc_ena; 5529 u32 scan_restart_ena; 5530 u32 scan_noise_floor_ref; 5531 u32 scan_init_delay; 5532 u32 scan_nb_tone_thr; 5533 u32 scan_str_bin_thr; 5534 u32 scan_wb_rpt_mode; 5535 u32 scan_rssi_rpt_mode; 5536 u32 scan_rssi_thr; 5537 u32 scan_pwr_format; 5538 u32 scan_rpt_mode; 5539 u32 scan_bin_scale; 5540 u32 scan_dbm_adj; 5541 u32 scan_chn_mask; 5542 } __packed; 5543 5544 struct ath11k_wmi_vdev_spectral_conf_cmd { 5545 u32 tlv_header; 5546 struct ath11k_wmi_vdev_spectral_conf_param param; 5547 } __packed; 5548 5549 #define ATH11K_WMI_SPECTRAL_TRIGGER_CMD_TRIGGER 1 5550 #define ATH11K_WMI_SPECTRAL_TRIGGER_CMD_CLEAR 2 5551 #define ATH11K_WMI_SPECTRAL_ENABLE_CMD_ENABLE 1 5552 #define ATH11K_WMI_SPECTRAL_ENABLE_CMD_DISABLE 2 5553 5554 struct ath11k_wmi_vdev_spectral_enable_cmd { 5555 u32 tlv_header; 5556 u32 vdev_id; 5557 u32 trigger_cmd; 5558 u32 enable_cmd; 5559 } __packed; 5560 5561 struct ath11k_wmi_pdev_dma_ring_cfg_req_cmd { 5562 u32 tlv_header; 5563 u32 pdev_id; 5564 u32 module_id; /* see enum wmi_direct_buffer_module */ 5565 u32 base_paddr_lo; 5566 u32 base_paddr_hi; 5567 u32 head_idx_paddr_lo; 5568 u32 head_idx_paddr_hi; 5569 u32 tail_idx_paddr_lo; 5570 u32 tail_idx_paddr_hi; 5571 u32 num_elems; /* Number of elems in the ring */ 5572 u32 buf_size; /* size of allocated buffer in bytes */ 5573 5574 /* Number of wmi_dma_buf_release_entry packed together */ 5575 u32 num_resp_per_event; 5576 5577 /* Target should timeout and send whatever resp 5578 * it has if this time expires, units in milliseconds 5579 */ 5580 u32 event_timeout_ms; 5581 } __packed; 5582 5583 struct ath11k_wmi_dma_buf_release_fixed_param { 5584 u32 pdev_id; 5585 u32 module_id; 5586 u32 num_buf_release_entry; 5587 u32 num_meta_data_entry; 5588 } __packed; 5589 5590 struct wmi_dma_buf_release_entry { 5591 u32 tlv_header; 5592 u32 paddr_lo; 5593 5594 /* Bits 11:0: address of data 5595 * Bits 31:12: host context data 5596 */ 5597 u32 paddr_hi; 5598 } __packed; 5599 5600 #define WMI_SPECTRAL_META_INFO1_FREQ1 GENMASK(15, 0) 5601 #define WMI_SPECTRAL_META_INFO1_FREQ2 GENMASK(31, 16) 5602 5603 #define WMI_SPECTRAL_META_INFO2_CHN_WIDTH GENMASK(7, 0) 5604 5605 struct wmi_dma_buf_release_meta_data { 5606 u32 tlv_header; 5607 s32 noise_floor[WMI_MAX_CHAINS]; 5608 u32 reset_delay; 5609 u32 freq1; 5610 u32 freq2; 5611 u32 ch_width; 5612 } __packed; 5613 5614 enum wmi_fils_discovery_cmd_type { 5615 WMI_FILS_DISCOVERY_CMD, 5616 WMI_UNSOL_BCAST_PROBE_RESP, 5617 }; 5618 5619 struct wmi_fils_discovery_cmd { 5620 u32 tlv_header; 5621 u32 vdev_id; 5622 u32 interval; 5623 u32 config; /* enum wmi_fils_discovery_cmd_type */ 5624 } __packed; 5625 5626 struct wmi_fils_discovery_tmpl_cmd { 5627 u32 tlv_header; 5628 u32 vdev_id; 5629 u32 buf_len; 5630 } __packed; 5631 5632 struct wmi_probe_tmpl_cmd { 5633 u32 tlv_header; 5634 u32 vdev_id; 5635 u32 buf_len; 5636 } __packed; 5637 5638 struct target_resource_config { 5639 u32 num_vdevs; 5640 u32 num_peers; 5641 u32 num_active_peers; 5642 u32 num_offload_peers; 5643 u32 num_offload_reorder_buffs; 5644 u32 num_peer_keys; 5645 u32 num_tids; 5646 u32 ast_skid_limit; 5647 u32 tx_chain_mask; 5648 u32 rx_chain_mask; 5649 u32 rx_timeout_pri[4]; 5650 u32 rx_decap_mode; 5651 u32 scan_max_pending_req; 5652 u32 bmiss_offload_max_vdev; 5653 u32 roam_offload_max_vdev; 5654 u32 roam_offload_max_ap_profiles; 5655 u32 num_mcast_groups; 5656 u32 num_mcast_table_elems; 5657 u32 mcast2ucast_mode; 5658 u32 tx_dbg_log_size; 5659 u32 num_wds_entries; 5660 u32 dma_burst_size; 5661 u32 mac_aggr_delim; 5662 u32 rx_skip_defrag_timeout_dup_detection_check; 5663 u32 vow_config; 5664 u32 gtk_offload_max_vdev; 5665 u32 num_msdu_desc; 5666 u32 max_frag_entries; 5667 u32 max_peer_ext_stats; 5668 u32 smart_ant_cap; 5669 u32 bk_minfree; 5670 u32 be_minfree; 5671 u32 vi_minfree; 5672 u32 vo_minfree; 5673 u32 rx_batchmode; 5674 u32 tt_support; 5675 u32 flag1; 5676 u32 iphdr_pad_config; 5677 u32 qwrap_config:16, 5678 alloc_frag_desc_for_data_pkt:16; 5679 u32 num_tdls_vdevs; 5680 u32 num_tdls_conn_table_entries; 5681 u32 beacon_tx_offload_max_vdev; 5682 u32 num_multicast_filter_entries; 5683 u32 num_wow_filters; 5684 u32 num_keep_alive_pattern; 5685 u32 keep_alive_pattern_size; 5686 u32 max_tdls_concurrent_sleep_sta; 5687 u32 max_tdls_concurrent_buffer_sta; 5688 u32 wmi_send_separate; 5689 u32 num_ocb_vdevs; 5690 u32 num_ocb_channels; 5691 u32 num_ocb_schedules; 5692 u32 num_ns_ext_tuples_cfg; 5693 u32 bpf_instruction_size; 5694 u32 max_bssid_rx_filters; 5695 u32 use_pdev_id; 5696 u32 peer_map_unmap_v2_support; 5697 u32 sched_params; 5698 u32 twt_ap_pdev_count; 5699 u32 twt_ap_sta_count; 5700 u8 is_reg_cc_ext_event_supported; 5701 u32 ema_max_vap_cnt; 5702 u32 ema_max_profile_period; 5703 }; 5704 5705 enum wmi_debug_log_param { 5706 WMI_DEBUG_LOG_PARAM_LOG_LEVEL = 0x1, 5707 WMI_DEBUG_LOG_PARAM_VDEV_ENABLE, 5708 WMI_DEBUG_LOG_PARAM_VDEV_DISABLE, 5709 WMI_DEBUG_LOG_PARAM_VDEV_ENABLE_BITMAP, 5710 WMI_DEBUG_LOG_PARAM_MOD_ENABLE_BITMAP, 5711 WMI_DEBUG_LOG_PARAM_WOW_MOD_ENABLE_BITMAP, 5712 }; 5713 5714 struct wmi_debug_log_config_cmd_fixed_param { 5715 u32 tlv_header; 5716 u32 dbg_log_param; 5717 u32 value; 5718 } __packed; 5719 5720 #define WMI_MAX_MEM_REQS 32 5721 5722 #define MAX_RADIOS 3 5723 5724 #define WMI_SERVICE_READY_TIMEOUT_HZ (5 * HZ) 5725 #define WMI_SEND_TIMEOUT_HZ (3 * HZ) 5726 5727 enum ath11k_wmi_peer_ps_state { 5728 WMI_PEER_PS_STATE_OFF, 5729 WMI_PEER_PS_STATE_ON, 5730 WMI_PEER_PS_STATE_DISABLED, 5731 }; 5732 5733 enum wmi_peer_ps_supported_bitmap { 5734 /* Used to indicate that power save state change is valid */ 5735 WMI_PEER_PS_VALID = 0x1, 5736 WMI_PEER_PS_STATE_TIMESTAMP = 0x2, 5737 }; 5738 5739 struct wmi_peer_sta_ps_state_chg_event { 5740 struct wmi_mac_addr peer_macaddr; 5741 u32 peer_ps_state; 5742 u32 ps_supported_bitmap; 5743 u32 peer_ps_valid; 5744 u32 peer_ps_timestamp; 5745 } __packed; 5746 5747 struct ath11k_wmi_base { 5748 struct ath11k_base *ab; 5749 struct ath11k_pdev_wmi wmi[MAX_RADIOS]; 5750 enum ath11k_htc_ep_id wmi_endpoint_id[MAX_RADIOS]; 5751 u32 max_msg_len[MAX_RADIOS]; 5752 5753 struct completion service_ready; 5754 struct completion unified_ready; 5755 DECLARE_BITMAP(svc_map, WMI_MAX_EXT2_SERVICE); 5756 wait_queue_head_t tx_credits_wq; 5757 const struct wmi_peer_flags_map *peer_flags; 5758 u32 num_mem_chunks; 5759 u32 rx_decap_mode; 5760 struct wmi_host_mem_chunk mem_chunks[WMI_MAX_MEM_REQS]; 5761 5762 enum wmi_host_hw_mode_config_type preferred_hw_mode; 5763 struct target_resource_config wlan_resource_config; 5764 5765 struct ath11k_targ_cap *targ_cap; 5766 }; 5767 5768 /* Definition of HW data filtering */ 5769 enum hw_data_filter_type { 5770 WMI_HW_DATA_FILTER_DROP_NON_ARP_BC = BIT(0), 5771 WMI_HW_DATA_FILTER_DROP_NON_ICMPV6_MC = BIT(1), 5772 }; 5773 5774 struct wmi_hw_data_filter_cmd { 5775 u32 tlv_header; 5776 u32 vdev_id; 5777 u32 enable; 5778 u32 hw_filter_bitmap; 5779 } __packed; 5780 5781 /* WOW structures */ 5782 enum wmi_wow_wakeup_event { 5783 WOW_BMISS_EVENT = 0, 5784 WOW_BETTER_AP_EVENT, 5785 WOW_DEAUTH_RECVD_EVENT, 5786 WOW_MAGIC_PKT_RECVD_EVENT, 5787 WOW_GTK_ERR_EVENT, 5788 WOW_FOURWAY_HSHAKE_EVENT, 5789 WOW_EAPOL_RECVD_EVENT, 5790 WOW_NLO_DETECTED_EVENT, 5791 WOW_DISASSOC_RECVD_EVENT, 5792 WOW_PATTERN_MATCH_EVENT, 5793 WOW_CSA_IE_EVENT, 5794 WOW_PROBE_REQ_WPS_IE_EVENT, 5795 WOW_AUTH_REQ_EVENT, 5796 WOW_ASSOC_REQ_EVENT, 5797 WOW_HTT_EVENT, 5798 WOW_RA_MATCH_EVENT, 5799 WOW_HOST_AUTO_SHUTDOWN_EVENT, 5800 WOW_IOAC_MAGIC_EVENT, 5801 WOW_IOAC_SHORT_EVENT, 5802 WOW_IOAC_EXTEND_EVENT, 5803 WOW_IOAC_TIMER_EVENT, 5804 WOW_DFS_PHYERR_RADAR_EVENT, 5805 WOW_BEACON_EVENT, 5806 WOW_CLIENT_KICKOUT_EVENT, 5807 WOW_EVENT_MAX, 5808 }; 5809 5810 enum wmi_wow_interface_cfg { 5811 WOW_IFACE_PAUSE_ENABLED, 5812 WOW_IFACE_PAUSE_DISABLED 5813 }; 5814 5815 #define C2S(x) case x: return #x 5816 5817 static inline const char *wow_wakeup_event(enum wmi_wow_wakeup_event ev) 5818 { 5819 switch (ev) { 5820 C2S(WOW_BMISS_EVENT); 5821 C2S(WOW_BETTER_AP_EVENT); 5822 C2S(WOW_DEAUTH_RECVD_EVENT); 5823 C2S(WOW_MAGIC_PKT_RECVD_EVENT); 5824 C2S(WOW_GTK_ERR_EVENT); 5825 C2S(WOW_FOURWAY_HSHAKE_EVENT); 5826 C2S(WOW_EAPOL_RECVD_EVENT); 5827 C2S(WOW_NLO_DETECTED_EVENT); 5828 C2S(WOW_DISASSOC_RECVD_EVENT); 5829 C2S(WOW_PATTERN_MATCH_EVENT); 5830 C2S(WOW_CSA_IE_EVENT); 5831 C2S(WOW_PROBE_REQ_WPS_IE_EVENT); 5832 C2S(WOW_AUTH_REQ_EVENT); 5833 C2S(WOW_ASSOC_REQ_EVENT); 5834 C2S(WOW_HTT_EVENT); 5835 C2S(WOW_RA_MATCH_EVENT); 5836 C2S(WOW_HOST_AUTO_SHUTDOWN_EVENT); 5837 C2S(WOW_IOAC_MAGIC_EVENT); 5838 C2S(WOW_IOAC_SHORT_EVENT); 5839 C2S(WOW_IOAC_EXTEND_EVENT); 5840 C2S(WOW_IOAC_TIMER_EVENT); 5841 C2S(WOW_DFS_PHYERR_RADAR_EVENT); 5842 C2S(WOW_BEACON_EVENT); 5843 C2S(WOW_CLIENT_KICKOUT_EVENT); 5844 C2S(WOW_EVENT_MAX); 5845 default: 5846 return NULL; 5847 } 5848 } 5849 5850 enum wmi_wow_wake_reason { 5851 WOW_REASON_UNSPECIFIED = -1, 5852 WOW_REASON_NLOD = 0, 5853 WOW_REASON_AP_ASSOC_LOST, 5854 WOW_REASON_LOW_RSSI, 5855 WOW_REASON_DEAUTH_RECVD, 5856 WOW_REASON_DISASSOC_RECVD, 5857 WOW_REASON_GTK_HS_ERR, 5858 WOW_REASON_EAP_REQ, 5859 WOW_REASON_FOURWAY_HS_RECV, 5860 WOW_REASON_TIMER_INTR_RECV, 5861 WOW_REASON_PATTERN_MATCH_FOUND, 5862 WOW_REASON_RECV_MAGIC_PATTERN, 5863 WOW_REASON_P2P_DISC, 5864 WOW_REASON_WLAN_HB, 5865 WOW_REASON_CSA_EVENT, 5866 WOW_REASON_PROBE_REQ_WPS_IE_RECV, 5867 WOW_REASON_AUTH_REQ_RECV, 5868 WOW_REASON_ASSOC_REQ_RECV, 5869 WOW_REASON_HTT_EVENT, 5870 WOW_REASON_RA_MATCH, 5871 WOW_REASON_HOST_AUTO_SHUTDOWN, 5872 WOW_REASON_IOAC_MAGIC_EVENT, 5873 WOW_REASON_IOAC_SHORT_EVENT, 5874 WOW_REASON_IOAC_EXTEND_EVENT, 5875 WOW_REASON_IOAC_TIMER_EVENT, 5876 WOW_REASON_ROAM_HO, 5877 WOW_REASON_DFS_PHYERR_RADADR_EVENT, 5878 WOW_REASON_BEACON_RECV, 5879 WOW_REASON_CLIENT_KICKOUT_EVENT, 5880 WOW_REASON_PAGE_FAULT = 0x3a, 5881 WOW_REASON_DEBUG_TEST = 0xFF, 5882 }; 5883 5884 static inline const char *wow_reason(enum wmi_wow_wake_reason reason) 5885 { 5886 switch (reason) { 5887 C2S(WOW_REASON_UNSPECIFIED); 5888 C2S(WOW_REASON_NLOD); 5889 C2S(WOW_REASON_AP_ASSOC_LOST); 5890 C2S(WOW_REASON_LOW_RSSI); 5891 C2S(WOW_REASON_DEAUTH_RECVD); 5892 C2S(WOW_REASON_DISASSOC_RECVD); 5893 C2S(WOW_REASON_GTK_HS_ERR); 5894 C2S(WOW_REASON_EAP_REQ); 5895 C2S(WOW_REASON_FOURWAY_HS_RECV); 5896 C2S(WOW_REASON_TIMER_INTR_RECV); 5897 C2S(WOW_REASON_PATTERN_MATCH_FOUND); 5898 C2S(WOW_REASON_RECV_MAGIC_PATTERN); 5899 C2S(WOW_REASON_P2P_DISC); 5900 C2S(WOW_REASON_WLAN_HB); 5901 C2S(WOW_REASON_CSA_EVENT); 5902 C2S(WOW_REASON_PROBE_REQ_WPS_IE_RECV); 5903 C2S(WOW_REASON_AUTH_REQ_RECV); 5904 C2S(WOW_REASON_ASSOC_REQ_RECV); 5905 C2S(WOW_REASON_HTT_EVENT); 5906 C2S(WOW_REASON_RA_MATCH); 5907 C2S(WOW_REASON_HOST_AUTO_SHUTDOWN); 5908 C2S(WOW_REASON_IOAC_MAGIC_EVENT); 5909 C2S(WOW_REASON_IOAC_SHORT_EVENT); 5910 C2S(WOW_REASON_IOAC_EXTEND_EVENT); 5911 C2S(WOW_REASON_IOAC_TIMER_EVENT); 5912 C2S(WOW_REASON_ROAM_HO); 5913 C2S(WOW_REASON_DFS_PHYERR_RADADR_EVENT); 5914 C2S(WOW_REASON_BEACON_RECV); 5915 C2S(WOW_REASON_CLIENT_KICKOUT_EVENT); 5916 C2S(WOW_REASON_PAGE_FAULT); 5917 C2S(WOW_REASON_DEBUG_TEST); 5918 default: 5919 return NULL; 5920 } 5921 } 5922 5923 #undef C2S 5924 5925 struct wmi_wow_ev_arg { 5926 u32 vdev_id; 5927 u32 flag; 5928 enum wmi_wow_wake_reason wake_reason; 5929 u32 data_len; 5930 }; 5931 5932 enum wmi_tlv_pattern_type { 5933 WOW_PATTERN_MIN = 0, 5934 WOW_BITMAP_PATTERN = WOW_PATTERN_MIN, 5935 WOW_IPV4_SYNC_PATTERN, 5936 WOW_IPV6_SYNC_PATTERN, 5937 WOW_WILD_CARD_PATTERN, 5938 WOW_TIMER_PATTERN, 5939 WOW_MAGIC_PATTERN, 5940 WOW_IPV6_RA_PATTERN, 5941 WOW_IOAC_PKT_PATTERN, 5942 WOW_IOAC_TMR_PATTERN, 5943 WOW_PATTERN_MAX 5944 }; 5945 5946 #define WOW_DEFAULT_BITMAP_PATTERN_SIZE 148 5947 #define WOW_DEFAULT_BITMASK_SIZE 148 5948 5949 #define WOW_MIN_PATTERN_SIZE 1 5950 #define WOW_MAX_PATTERN_SIZE 148 5951 #define WOW_MAX_PKT_OFFSET 128 5952 #define WOW_HDR_LEN (sizeof(struct ieee80211_hdr_3addr) + \ 5953 sizeof(struct rfc1042_hdr)) 5954 #define WOW_MAX_REDUCE (WOW_HDR_LEN - sizeof(struct ethhdr) - \ 5955 offsetof(struct ieee80211_hdr_3addr, addr1)) 5956 5957 struct wmi_wow_add_del_event_cmd { 5958 u32 tlv_header; 5959 u32 vdev_id; 5960 u32 is_add; 5961 u32 event_bitmap; 5962 } __packed; 5963 5964 struct wmi_wow_enable_cmd { 5965 u32 tlv_header; 5966 u32 enable; 5967 u32 pause_iface_config; 5968 u32 flags; 5969 } __packed; 5970 5971 struct wmi_wow_host_wakeup_ind { 5972 u32 tlv_header; 5973 u32 reserved; 5974 } __packed; 5975 5976 struct wmi_tlv_wow_event_info { 5977 u32 vdev_id; 5978 u32 flag; 5979 u32 wake_reason; 5980 u32 data_len; 5981 } __packed; 5982 5983 struct wmi_wow_bitmap_pattern { 5984 u32 tlv_header; 5985 u8 patternbuf[WOW_DEFAULT_BITMAP_PATTERN_SIZE]; 5986 u8 bitmaskbuf[WOW_DEFAULT_BITMASK_SIZE]; 5987 u32 pattern_offset; 5988 u32 pattern_len; 5989 u32 bitmask_len; 5990 u32 pattern_id; 5991 } __packed; 5992 5993 struct wmi_wow_add_pattern_cmd { 5994 u32 tlv_header; 5995 u32 vdev_id; 5996 u32 pattern_id; 5997 u32 pattern_type; 5998 } __packed; 5999 6000 struct wmi_wow_del_pattern_cmd { 6001 u32 tlv_header; 6002 u32 vdev_id; 6003 u32 pattern_id; 6004 u32 pattern_type; 6005 } __packed; 6006 6007 #define WMI_PNO_MAX_SCHED_SCAN_PLANS 2 6008 #define WMI_PNO_MAX_SCHED_SCAN_PLAN_INT 7200 6009 #define WMI_PNO_MAX_SCHED_SCAN_PLAN_ITRNS 100 6010 #define WMI_PNO_MAX_NETW_CHANNELS 26 6011 #define WMI_PNO_MAX_NETW_CHANNELS_EX 60 6012 #define WMI_PNO_MAX_SUPP_NETWORKS WLAN_SCAN_PARAMS_MAX_SSID 6013 #define WMI_PNO_MAX_IE_LENGTH WLAN_SCAN_PARAMS_MAX_IE_LEN 6014 6015 /* size based of dot11 declaration without extra IEs as we will not carry those for PNO */ 6016 #define WMI_PNO_MAX_PB_REQ_SIZE 450 6017 6018 #define WMI_PNO_24G_DEFAULT_CH 1 6019 #define WMI_PNO_5G_DEFAULT_CH 36 6020 6021 #define WMI_ACTIVE_MAX_CHANNEL_TIME 40 6022 #define WMI_PASSIVE_MAX_CHANNEL_TIME 110 6023 6024 /* SSID broadcast type */ 6025 enum wmi_ssid_bcast_type { 6026 BCAST_UNKNOWN = 0, 6027 BCAST_NORMAL = 1, 6028 BCAST_HIDDEN = 2, 6029 }; 6030 6031 #define WMI_NLO_MAX_SSIDS 16 6032 #define WMI_NLO_MAX_CHAN 48 6033 6034 #define WMI_NLO_CONFIG_STOP BIT(0) 6035 #define WMI_NLO_CONFIG_START BIT(1) 6036 #define WMI_NLO_CONFIG_RESET BIT(2) 6037 #define WMI_NLO_CONFIG_SLOW_SCAN BIT(4) 6038 #define WMI_NLO_CONFIG_FAST_SCAN BIT(5) 6039 #define WMI_NLO_CONFIG_SSID_HIDE_EN BIT(6) 6040 6041 /* This bit is used to indicate if EPNO or supplicant PNO is enabled. 6042 * Only one of them can be enabled at a given time 6043 */ 6044 #define WMI_NLO_CONFIG_ENLO BIT(7) 6045 #define WMI_NLO_CONFIG_SCAN_PASSIVE BIT(8) 6046 #define WMI_NLO_CONFIG_ENLO_RESET BIT(9) 6047 #define WMI_NLO_CONFIG_SPOOFED_MAC_IN_PROBE_REQ BIT(10) 6048 #define WMI_NLO_CONFIG_RANDOM_SEQ_NO_IN_PROBE_REQ BIT(11) 6049 #define WMI_NLO_CONFIG_ENABLE_IE_WHITELIST_IN_PROBE_REQ BIT(12) 6050 #define WMI_NLO_CONFIG_ENABLE_CNLO_RSSI_CONFIG BIT(13) 6051 6052 struct wmi_nlo_ssid_param { 6053 u32 valid; 6054 struct wmi_ssid ssid; 6055 } __packed; 6056 6057 struct wmi_nlo_enc_param { 6058 u32 valid; 6059 u32 enc_type; 6060 } __packed; 6061 6062 struct wmi_nlo_auth_param { 6063 u32 valid; 6064 u32 auth_type; 6065 } __packed; 6066 6067 struct wmi_nlo_bcast_nw_param { 6068 u32 valid; 6069 u32 bcast_nw_type; 6070 } __packed; 6071 6072 struct wmi_nlo_rssi_param { 6073 u32 valid; 6074 s32 rssi; 6075 } __packed; 6076 6077 struct nlo_configured_parameters { 6078 /* TLV tag and len;*/ 6079 u32 tlv_header; 6080 struct wmi_nlo_ssid_param ssid; 6081 struct wmi_nlo_enc_param enc_type; 6082 struct wmi_nlo_auth_param auth_type; 6083 struct wmi_nlo_rssi_param rssi_cond; 6084 6085 /* indicates if the SSID is hidden or not */ 6086 struct wmi_nlo_bcast_nw_param bcast_nw_type; 6087 } __packed; 6088 6089 struct wmi_network_type { 6090 struct wmi_ssid ssid; 6091 u32 authentication; 6092 u32 encryption; 6093 u32 bcast_nw_type; 6094 u8 channel_count; 6095 u16 channels[WMI_PNO_MAX_NETW_CHANNELS_EX]; 6096 s32 rssi_threshold; 6097 }; 6098 6099 struct wmi_pno_scan_req { 6100 u8 enable; 6101 u8 vdev_id; 6102 u8 uc_networks_count; 6103 struct wmi_network_type a_networks[WMI_PNO_MAX_SUPP_NETWORKS]; 6104 u32 fast_scan_period; 6105 u32 slow_scan_period; 6106 u8 fast_scan_max_cycles; 6107 6108 bool do_passive_scan; 6109 6110 u32 delay_start_time; 6111 u32 active_min_time; 6112 u32 active_max_time; 6113 u32 passive_min_time; 6114 u32 passive_max_time; 6115 6116 /* mac address randomization attributes */ 6117 u32 enable_pno_scan_randomization; 6118 u8 mac_addr[ETH_ALEN]; 6119 u8 mac_addr_mask[ETH_ALEN]; 6120 }; 6121 6122 struct wmi_wow_nlo_config_cmd { 6123 u32 tlv_header; 6124 u32 flags; 6125 u32 vdev_id; 6126 u32 fast_scan_max_cycles; 6127 u32 active_dwell_time; 6128 u32 passive_dwell_time; 6129 u32 probe_bundle_size; 6130 6131 /* ART = IRT */ 6132 u32 rest_time; 6133 6134 /* Max value that can be reached after SBM */ 6135 u32 max_rest_time; 6136 6137 /* SBM */ 6138 u32 scan_backoff_multiplier; 6139 6140 /* SCBM */ 6141 u32 fast_scan_period; 6142 6143 /* specific to windows */ 6144 u32 slow_scan_period; 6145 6146 u32 no_of_ssids; 6147 6148 u32 num_of_channels; 6149 6150 /* NLO scan start delay time in milliseconds */ 6151 u32 delay_start_time; 6152 6153 /* MAC Address to use in Probe Req as SA */ 6154 struct wmi_mac_addr mac_addr; 6155 6156 /* Mask on which MAC has to be randomized */ 6157 struct wmi_mac_addr mac_mask; 6158 6159 /* IE bitmap to use in Probe Req */ 6160 u32 ie_bitmap[8]; 6161 6162 /* Number of vendor OUIs. In the TLV vendor_oui[] */ 6163 u32 num_vendor_oui; 6164 6165 /* Number of connected NLO band preferences */ 6166 u32 num_cnlo_band_pref; 6167 6168 /* The TLVs will follow. 6169 * nlo_configured_parameters nlo_list[]; 6170 * u32 channel_list[num_of_channels]; 6171 */ 6172 } __packed; 6173 6174 #define WMI_MAX_NS_OFFLOADS 2 6175 #define WMI_MAX_ARP_OFFLOADS 2 6176 6177 #define WMI_ARPOL_FLAGS_VALID BIT(0) 6178 #define WMI_ARPOL_FLAGS_MAC_VALID BIT(1) 6179 #define WMI_ARPOL_FLAGS_REMOTE_IP_VALID BIT(2) 6180 6181 struct wmi_arp_offload_tuple { 6182 u32 tlv_header; 6183 u32 flags; 6184 u8 target_ipaddr[4]; 6185 u8 remote_ipaddr[4]; 6186 struct wmi_mac_addr target_mac; 6187 } __packed; 6188 6189 #define WMI_NSOL_FLAGS_VALID BIT(0) 6190 #define WMI_NSOL_FLAGS_MAC_VALID BIT(1) 6191 #define WMI_NSOL_FLAGS_REMOTE_IP_VALID BIT(2) 6192 #define WMI_NSOL_FLAGS_IS_IPV6_ANYCAST BIT(3) 6193 6194 #define WMI_NSOL_MAX_TARGET_IPS 2 6195 6196 struct wmi_ns_offload_tuple { 6197 u32 tlv_header; 6198 u32 flags; 6199 u8 target_ipaddr[WMI_NSOL_MAX_TARGET_IPS][16]; 6200 u8 solicitation_ipaddr[16]; 6201 u8 remote_ipaddr[16]; 6202 struct wmi_mac_addr target_mac; 6203 } __packed; 6204 6205 struct wmi_set_arp_ns_offload_cmd { 6206 u32 tlv_header; 6207 u32 flags; 6208 u32 vdev_id; 6209 u32 num_ns_ext_tuples; 6210 /* The TLVs follow: 6211 * wmi_ns_offload_tuple ns_tuples[WMI_MAX_NS_OFFLOADS]; 6212 * wmi_arp_offload_tuple arp_tuples[WMI_MAX_ARP_OFFLOADS]; 6213 * wmi_ns_offload_tuple ns_ext_tuples[num_ns_ext_tuples]; 6214 */ 6215 } __packed; 6216 6217 #define GTK_OFFLOAD_OPCODE_MASK 0xFF000000 6218 #define GTK_OFFLOAD_ENABLE_OPCODE 0x01000000 6219 #define GTK_OFFLOAD_DISABLE_OPCODE 0x02000000 6220 #define GTK_OFFLOAD_REQUEST_STATUS_OPCODE 0x04000000 6221 6222 #define GTK_OFFLOAD_KEK_BYTES 16 6223 #define GTK_OFFLOAD_KCK_BYTES 16 6224 #define GTK_REPLAY_COUNTER_BYTES 8 6225 #define WMI_MAX_KEY_LEN 32 6226 #define IGTK_PN_SIZE 6 6227 6228 struct wmi_replayc_cnt { 6229 union { 6230 u8 counter[GTK_REPLAY_COUNTER_BYTES]; 6231 struct { 6232 u32 word0; 6233 u32 word1; 6234 } __packed; 6235 } __packed; 6236 } __packed; 6237 6238 struct wmi_gtk_offload_status_event { 6239 u32 vdev_id; 6240 u32 flags; 6241 u32 refresh_cnt; 6242 struct wmi_replayc_cnt replay_ctr; 6243 u8 igtk_key_index; 6244 u8 igtk_key_length; 6245 u8 igtk_key_rsc[IGTK_PN_SIZE]; 6246 u8 igtk_key[WMI_MAX_KEY_LEN]; 6247 u8 gtk_key_index; 6248 u8 gtk_key_length; 6249 u8 gtk_key_rsc[GTK_REPLAY_COUNTER_BYTES]; 6250 u8 gtk_key[WMI_MAX_KEY_LEN]; 6251 } __packed; 6252 6253 struct wmi_gtk_rekey_offload_cmd { 6254 u32 tlv_header; 6255 u32 vdev_id; 6256 u32 flags; 6257 u8 kek[GTK_OFFLOAD_KEK_BYTES]; 6258 u8 kck[GTK_OFFLOAD_KCK_BYTES]; 6259 u8 replay_ctr[GTK_REPLAY_COUNTER_BYTES]; 6260 } __packed; 6261 6262 #define BIOS_SAR_TABLE_LEN (22) 6263 #define BIOS_SAR_RSVD1_LEN (6) 6264 #define BIOS_SAR_RSVD2_LEN (18) 6265 6266 struct wmi_pdev_set_sar_table_cmd { 6267 u32 tlv_header; 6268 u32 pdev_id; 6269 u32 sar_len; 6270 u32 rsvd_len; 6271 } __packed; 6272 6273 struct wmi_pdev_set_geo_table_cmd { 6274 u32 tlv_header; 6275 u32 pdev_id; 6276 u32 rsvd_len; 6277 } __packed; 6278 6279 struct wmi_sta_keepalive_cmd { 6280 u32 tlv_header; 6281 u32 vdev_id; 6282 u32 enabled; 6283 6284 /* WMI_STA_KEEPALIVE_METHOD_ */ 6285 u32 method; 6286 6287 /* in seconds */ 6288 u32 interval; 6289 6290 /* following this structure is the TLV for struct 6291 * wmi_sta_keepalive_arp_resp 6292 */ 6293 } __packed; 6294 6295 struct wmi_sta_keepalive_arp_resp { 6296 u32 tlv_header; 6297 u32 src_ip4_addr; 6298 u32 dest_ip4_addr; 6299 struct wmi_mac_addr dest_mac_addr; 6300 } __packed; 6301 6302 struct wmi_sta_keepalive_arg { 6303 u32 vdev_id; 6304 u32 enabled; 6305 u32 method; 6306 u32 interval; 6307 u32 src_ip4_addr; 6308 u32 dest_ip4_addr; 6309 const u8 dest_mac_addr[ETH_ALEN]; 6310 }; 6311 6312 enum wmi_sta_keepalive_method { 6313 WMI_STA_KEEPALIVE_METHOD_NULL_FRAME = 1, 6314 WMI_STA_KEEPALIVE_METHOD_UNSOLICITED_ARP_RESPONSE = 2, 6315 WMI_STA_KEEPALIVE_METHOD_ETHERNET_LOOPBACK = 3, 6316 WMI_STA_KEEPALIVE_METHOD_GRATUITOUS_ARP_REQUEST = 4, 6317 WMI_STA_KEEPALIVE_METHOD_MGMT_VENDOR_ACTION = 5, 6318 }; 6319 6320 #define WMI_STA_KEEPALIVE_INTERVAL_DEFAULT 30 6321 #define WMI_STA_KEEPALIVE_INTERVAL_DISABLE 0 6322 6323 const void **ath11k_wmi_tlv_parse_alloc(struct ath11k_base *ab, const void *ptr, 6324 size_t len, gfp_t gfp); 6325 int ath11k_wmi_cmd_send(struct ath11k_pdev_wmi *wmi, struct sk_buff *skb, 6326 u32 cmd_id); 6327 struct sk_buff *ath11k_wmi_alloc_skb(struct ath11k_wmi_base *wmi_sc, u32 len); 6328 int ath11k_wmi_mgmt_send(struct ath11k *ar, u32 vdev_id, u32 buf_id, 6329 struct sk_buff *frame); 6330 int ath11k_wmi_bcn_tmpl(struct ath11k *ar, u32 vdev_id, 6331 struct ieee80211_mutable_offsets *offs, 6332 struct sk_buff *bcn, u32 ema_param); 6333 int ath11k_wmi_vdev_down(struct ath11k *ar, u8 vdev_id); 6334 int ath11k_wmi_vdev_up(struct ath11k *ar, u32 vdev_id, u32 aid, 6335 const u8 *bssid, u8 *tx_bssid, u32 nontx_profile_idx, 6336 u32 nontx_profile_cnt); 6337 int ath11k_wmi_vdev_stop(struct ath11k *ar, u8 vdev_id); 6338 int ath11k_wmi_vdev_start(struct ath11k *ar, struct wmi_vdev_start_req_arg *arg, 6339 bool restart); 6340 int ath11k_wmi_set_peer_param(struct ath11k *ar, const u8 *peer_addr, 6341 u32 vdev_id, u32 param_id, u32 param_val); 6342 int ath11k_wmi_pdev_set_param(struct ath11k *ar, u32 param_id, 6343 u32 param_value, u8 pdev_id); 6344 int ath11k_wmi_pdev_set_ps_mode(struct ath11k *ar, int vdev_id, 6345 enum wmi_sta_ps_mode psmode); 6346 int ath11k_wmi_wait_for_unified_ready(struct ath11k_base *ab); 6347 int ath11k_wmi_cmd_init(struct ath11k_base *ab); 6348 int ath11k_wmi_wait_for_service_ready(struct ath11k_base *ab); 6349 int ath11k_wmi_connect(struct ath11k_base *ab); 6350 int ath11k_wmi_pdev_attach(struct ath11k_base *ab, 6351 u8 pdev_id); 6352 int ath11k_wmi_attach(struct ath11k_base *ab); 6353 void ath11k_wmi_detach(struct ath11k_base *ab); 6354 int ath11k_wmi_vdev_create(struct ath11k *ar, u8 *macaddr, 6355 struct vdev_create_params *param); 6356 int ath11k_wmi_peer_rx_reorder_queue_setup(struct ath11k *ar, int vdev_id, 6357 const u8 *addr, dma_addr_t paddr, 6358 u8 tid, u8 ba_window_size_valid, 6359 u32 ba_window_size); 6360 int ath11k_wmi_send_peer_create_cmd(struct ath11k *ar, 6361 struct peer_create_params *param); 6362 int ath11k_wmi_vdev_set_param_cmd(struct ath11k *ar, u32 vdev_id, 6363 u32 param_id, u32 param_value); 6364 6365 int ath11k_wmi_set_sta_ps_param(struct ath11k *ar, u32 vdev_id, 6366 u32 param, u32 param_value); 6367 int ath11k_wmi_force_fw_hang_cmd(struct ath11k *ar, u32 type, u32 delay_time_ms); 6368 int ath11k_wmi_send_peer_delete_cmd(struct ath11k *ar, 6369 const u8 *peer_addr, u8 vdev_id); 6370 int ath11k_wmi_vdev_delete(struct ath11k *ar, u8 vdev_id); 6371 void ath11k_wmi_start_scan_init(struct ath11k *ar, struct scan_req_params *arg); 6372 int ath11k_wmi_send_scan_start_cmd(struct ath11k *ar, 6373 struct scan_req_params *params); 6374 int ath11k_wmi_send_scan_stop_cmd(struct ath11k *ar, 6375 struct scan_cancel_param *param); 6376 int ath11k_wmi_send_wmm_update_cmd_tlv(struct ath11k *ar, u32 vdev_id, 6377 struct wmi_wmm_params_all_arg *param); 6378 int ath11k_wmi_pdev_suspend(struct ath11k *ar, u32 suspend_opt, 6379 u32 pdev_id); 6380 int ath11k_wmi_pdev_resume(struct ath11k *ar, u32 pdev_id); 6381 6382 int ath11k_wmi_send_peer_assoc_cmd(struct ath11k *ar, 6383 struct peer_assoc_params *param); 6384 int ath11k_wmi_vdev_install_key(struct ath11k *ar, 6385 struct wmi_vdev_install_key_arg *arg); 6386 int ath11k_wmi_pdev_bss_chan_info_request(struct ath11k *ar, 6387 enum wmi_bss_chan_info_req_type type); 6388 int ath11k_wmi_send_stats_request_cmd(struct ath11k *ar, 6389 struct stats_request_params *param); 6390 int ath11k_wmi_send_pdev_temperature_cmd(struct ath11k *ar); 6391 int ath11k_wmi_send_peer_flush_tids_cmd(struct ath11k *ar, 6392 u8 peer_addr[ETH_ALEN], 6393 struct peer_flush_params *param); 6394 int ath11k_wmi_send_set_ap_ps_param_cmd(struct ath11k *ar, u8 *peer_addr, 6395 struct ap_ps_params *param); 6396 int ath11k_wmi_send_scan_chan_list_cmd(struct ath11k *ar, 6397 struct scan_chan_list_params *chan_list); 6398 int ath11k_wmi_send_dfs_phyerr_offload_enable_cmd(struct ath11k *ar, 6399 u32 pdev_id); 6400 int ath11k_wmi_addba_clear_resp(struct ath11k *ar, u32 vdev_id, const u8 *mac); 6401 int ath11k_wmi_addba_send(struct ath11k *ar, u32 vdev_id, const u8 *mac, 6402 u32 tid, u32 buf_size); 6403 int ath11k_wmi_addba_set_resp(struct ath11k *ar, u32 vdev_id, const u8 *mac, 6404 u32 tid, u32 status); 6405 int ath11k_wmi_delba_send(struct ath11k *ar, u32 vdev_id, const u8 *mac, 6406 u32 tid, u32 initiator, u32 reason); 6407 int ath11k_wmi_send_bcn_offload_control_cmd(struct ath11k *ar, 6408 u32 vdev_id, u32 bcn_ctrl_op); 6409 int ath11k_wmi_send_set_current_country_cmd(struct ath11k *ar, 6410 struct wmi_set_current_country_params *param); 6411 int 6412 ath11k_wmi_send_init_country_cmd(struct ath11k *ar, 6413 struct wmi_init_country_params init_cc_param); 6414 6415 int ath11k_wmi_send_11d_scan_start_cmd(struct ath11k *ar, 6416 struct wmi_11d_scan_start_params *param); 6417 int ath11k_wmi_send_11d_scan_stop_cmd(struct ath11k *ar, u32 vdev_id); 6418 6419 int 6420 ath11k_wmi_send_thermal_mitigation_param_cmd(struct ath11k *ar, 6421 struct thermal_mitigation_params *param); 6422 int ath11k_wmi_pdev_pktlog_enable(struct ath11k *ar, u32 pktlog_filter); 6423 int ath11k_wmi_pdev_pktlog_disable(struct ath11k *ar); 6424 int ath11k_wmi_pdev_peer_pktlog_filter(struct ath11k *ar, u8 *addr, u8 enable); 6425 int 6426 ath11k_wmi_rx_reord_queue_remove(struct ath11k *ar, 6427 struct rx_reorder_queue_remove_params *param); 6428 int ath11k_wmi_send_pdev_set_regdomain(struct ath11k *ar, 6429 struct pdev_set_regdomain_params *param); 6430 int ath11k_wmi_pull_fw_stats(struct ath11k_base *ab, struct sk_buff *skb, 6431 struct ath11k_fw_stats *stats); 6432 void ath11k_wmi_fw_stats_fill(struct ath11k *ar, 6433 struct ath11k_fw_stats *fw_stats, u32 stats_id, 6434 char *buf); 6435 int ath11k_wmi_simulate_radar(struct ath11k *ar); 6436 void ath11k_wmi_fill_default_twt_params(struct wmi_twt_enable_params *twt_params); 6437 int ath11k_wmi_send_twt_enable_cmd(struct ath11k *ar, u32 pdev_id, 6438 struct wmi_twt_enable_params *params); 6439 int ath11k_wmi_send_twt_disable_cmd(struct ath11k *ar, u32 pdev_id); 6440 int ath11k_wmi_send_twt_add_dialog_cmd(struct ath11k *ar, 6441 struct wmi_twt_add_dialog_params *params); 6442 int ath11k_wmi_send_twt_del_dialog_cmd(struct ath11k *ar, 6443 struct wmi_twt_del_dialog_params *params); 6444 int ath11k_wmi_send_twt_pause_dialog_cmd(struct ath11k *ar, 6445 struct wmi_twt_pause_dialog_params *params); 6446 int ath11k_wmi_send_twt_resume_dialog_cmd(struct ath11k *ar, 6447 struct wmi_twt_resume_dialog_params *params); 6448 int ath11k_wmi_send_obss_spr_cmd(struct ath11k *ar, u32 vdev_id, 6449 struct ieee80211_he_obss_pd *he_obss_pd); 6450 int ath11k_wmi_pdev_set_srg_bss_color_bitmap(struct ath11k *ar, u32 *bitmap); 6451 int ath11k_wmi_pdev_set_srg_patial_bssid_bitmap(struct ath11k *ar, u32 *bitmap); 6452 int ath11k_wmi_pdev_srg_obss_color_enable_bitmap(struct ath11k *ar, 6453 u32 *bitmap); 6454 int ath11k_wmi_pdev_srg_obss_bssid_enable_bitmap(struct ath11k *ar, 6455 u32 *bitmap); 6456 int ath11k_wmi_pdev_non_srg_obss_color_enable_bitmap(struct ath11k *ar, 6457 u32 *bitmap); 6458 int ath11k_wmi_pdev_non_srg_obss_bssid_enable_bitmap(struct ath11k *ar, 6459 u32 *bitmap); 6460 int ath11k_wmi_send_obss_color_collision_cfg_cmd(struct ath11k *ar, u32 vdev_id, 6461 u8 bss_color, u32 period, 6462 bool enable); 6463 int ath11k_wmi_send_bss_color_change_enable_cmd(struct ath11k *ar, u32 vdev_id, 6464 bool enable); 6465 int ath11k_wmi_pdev_lro_cfg(struct ath11k *ar, int pdev_id); 6466 int ath11k_wmi_pdev_dma_ring_cfg(struct ath11k *ar, 6467 struct ath11k_wmi_pdev_dma_ring_cfg_req_cmd *param); 6468 int ath11k_wmi_vdev_spectral_enable(struct ath11k *ar, u32 vdev_id, 6469 u32 trigger, u32 enable); 6470 int ath11k_wmi_vdev_spectral_conf(struct ath11k *ar, 6471 struct ath11k_wmi_vdev_spectral_conf_param *param); 6472 int ath11k_wmi_fils_discovery_tmpl(struct ath11k *ar, u32 vdev_id, 6473 struct sk_buff *tmpl); 6474 int ath11k_wmi_fils_discovery(struct ath11k *ar, u32 vdev_id, u32 interval, 6475 bool unsol_bcast_probe_resp_enabled); 6476 int ath11k_wmi_probe_resp_tmpl(struct ath11k *ar, u32 vdev_id, 6477 struct sk_buff *tmpl); 6478 int ath11k_wmi_set_hw_mode(struct ath11k_base *ab, 6479 enum wmi_host_hw_mode_config_type mode); 6480 int ath11k_wmi_wow_host_wakeup_ind(struct ath11k *ar); 6481 int ath11k_wmi_wow_enable(struct ath11k *ar); 6482 int ath11k_wmi_scan_prob_req_oui(struct ath11k *ar, 6483 const u8 mac_addr[ETH_ALEN]); 6484 int ath11k_wmi_fw_dbglog_cfg(struct ath11k *ar, u32 *module_id_bitmap, 6485 struct ath11k_fw_dbglog *dbglog); 6486 int ath11k_wmi_wow_config_pno(struct ath11k *ar, u32 vdev_id, 6487 struct wmi_pno_scan_req *pno_scan); 6488 int ath11k_wmi_wow_del_pattern(struct ath11k *ar, u32 vdev_id, u32 pattern_id); 6489 int ath11k_wmi_wow_add_pattern(struct ath11k *ar, u32 vdev_id, u32 pattern_id, 6490 const u8 *pattern, const u8 *mask, 6491 int pattern_len, int pattern_offset); 6492 int ath11k_wmi_wow_add_wakeup_event(struct ath11k *ar, u32 vdev_id, 6493 enum wmi_wow_wakeup_event event, 6494 u32 enable); 6495 int ath11k_wmi_hw_data_filter_cmd(struct ath11k *ar, u32 vdev_id, 6496 u32 filter_bitmap, bool enable); 6497 int ath11k_wmi_arp_ns_offload(struct ath11k *ar, 6498 struct ath11k_vif *arvif, bool enable); 6499 int ath11k_wmi_gtk_rekey_offload(struct ath11k *ar, 6500 struct ath11k_vif *arvif, bool enable); 6501 int ath11k_wmi_gtk_rekey_getinfo(struct ath11k *ar, 6502 struct ath11k_vif *arvif); 6503 int ath11k_wmi_pdev_set_bios_sar_table_param(struct ath11k *ar, const u8 *sar_val); 6504 int ath11k_wmi_pdev_set_bios_geo_table_param(struct ath11k *ar); 6505 int ath11k_wmi_sta_keepalive(struct ath11k *ar, 6506 const struct wmi_sta_keepalive_arg *arg); 6507 6508 #endif 6509