1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef ATH11K_WMI_H 7 #define ATH11K_WMI_H 8 9 #include <net/mac80211.h> 10 #include "htc.h" 11 12 struct ath11k_base; 13 struct ath11k; 14 struct ath11k_fw_stats; 15 struct ath11k_fw_dbglog; 16 struct ath11k_vif; 17 18 #define PSOC_HOST_MAX_NUM_SS (8) 19 20 /* defines to set Packet extension values which can be 0 us, 8 usec or 16 usec */ 21 #define MAX_HE_NSS 8 22 #define MAX_HE_MODULATION 8 23 #define MAX_HE_RU 4 24 #define HE_MODULATION_NONE 7 25 #define HE_PET_0_USEC 0 26 #define HE_PET_8_USEC 1 27 #define HE_PET_16_USEC 2 28 29 #define WMI_MAX_CHAINS 8 30 31 #define WMI_MAX_NUM_SS MAX_HE_NSS 32 #define WMI_MAX_NUM_RU MAX_HE_RU 33 34 #define WMI_TLV_CMD(grp_id) (((grp_id) << 12) | 0x1) 35 #define WMI_TLV_EV(grp_id) (((grp_id) << 12) | 0x1) 36 #define WMI_TLV_CMD_UNSUPPORTED 0 37 #define WMI_TLV_PDEV_PARAM_UNSUPPORTED 0 38 #define WMI_TLV_VDEV_PARAM_UNSUPPORTED 0 39 40 struct wmi_cmd_hdr { 41 u32 cmd_id; 42 } __packed; 43 44 struct wmi_tlv { 45 u32 header; 46 u8 value[]; 47 } __packed; 48 49 #define WMI_TLV_LEN GENMASK(15, 0) 50 #define WMI_TLV_TAG GENMASK(31, 16) 51 #define TLV_HDR_SIZE sizeof_field(struct wmi_tlv, header) 52 53 #define WMI_CMD_HDR_CMD_ID GENMASK(23, 0) 54 #define WMI_MAX_MEM_REQS 32 55 #define ATH11K_MAX_HW_LISTEN_INTERVAL 5 56 57 #define WLAN_SCAN_MAX_HINT_S_SSID 10 58 #define WLAN_SCAN_MAX_HINT_BSSID 10 59 #define MAX_RNR_BSS 5 60 61 #define WLAN_SCAN_MAX_HINT_S_SSID 10 62 #define WLAN_SCAN_MAX_HINT_BSSID 10 63 #define MAX_RNR_BSS 5 64 65 #define WLAN_SCAN_PARAMS_MAX_SSID 16 66 #define WLAN_SCAN_PARAMS_MAX_BSSID 4 67 #define WLAN_SCAN_PARAMS_MAX_IE_LEN 256 68 69 #define WMI_APPEND_TO_EXISTING_CHAN_LIST_FLAG 1 70 71 #define WMI_BA_MODE_BUFFER_SIZE_256 3 72 /* 73 * HW mode config type replicated from FW header 74 * @WMI_HOST_HW_MODE_SINGLE: Only one PHY is active. 75 * @WMI_HOST_HW_MODE_DBS: Both PHYs are active in different bands, 76 * one in 2G and another in 5G. 77 * @WMI_HOST_HW_MODE_SBS_PASSIVE: Both PHYs are in passive mode (only rx) in 78 * same band; no tx allowed. 79 * @WMI_HOST_HW_MODE_SBS: Both PHYs are active in the same band. 80 * Support for both PHYs within one band is planned 81 * for 5G only(as indicated in WMI_MAC_PHY_CAPABILITIES), 82 * but could be extended to other bands in the future. 83 * The separation of the band between the two PHYs needs 84 * to be communicated separately. 85 * @WMI_HOST_HW_MODE_DBS_SBS: 3 PHYs, with 2 on the same band doing SBS 86 * as in WMI_HW_MODE_SBS, and 3rd on the other band 87 * @WMI_HOST_HW_MODE_DBS_OR_SBS: Two PHY with one PHY capabale of both 2G and 88 * 5G. It can support SBS (5G + 5G) OR DBS (5G + 2G). 89 * @WMI_HOST_HW_MODE_MAX: Max hw_mode_id. Used to indicate invalid mode. 90 */ 91 enum wmi_host_hw_mode_config_type { 92 WMI_HOST_HW_MODE_SINGLE = 0, 93 WMI_HOST_HW_MODE_DBS = 1, 94 WMI_HOST_HW_MODE_SBS_PASSIVE = 2, 95 WMI_HOST_HW_MODE_SBS = 3, 96 WMI_HOST_HW_MODE_DBS_SBS = 4, 97 WMI_HOST_HW_MODE_DBS_OR_SBS = 5, 98 99 /* keep last */ 100 WMI_HOST_HW_MODE_MAX 101 }; 102 103 /* HW mode priority values used to detect the preferred HW mode 104 * on the available modes. 105 */ 106 enum wmi_host_hw_mode_priority { 107 WMI_HOST_HW_MODE_DBS_SBS_PRI, 108 WMI_HOST_HW_MODE_DBS_PRI, 109 WMI_HOST_HW_MODE_DBS_OR_SBS_PRI, 110 WMI_HOST_HW_MODE_SBS_PRI, 111 WMI_HOST_HW_MODE_SBS_PASSIVE_PRI, 112 WMI_HOST_HW_MODE_SINGLE_PRI, 113 114 /* keep last the lowest priority */ 115 WMI_HOST_HW_MODE_MAX_PRI 116 }; 117 118 enum WMI_HOST_WLAN_BAND { 119 WMI_HOST_WLAN_2G_CAP = 0x1, 120 WMI_HOST_WLAN_5G_CAP = 0x2, 121 WMI_HOST_WLAN_2G_5G_CAP = WMI_HOST_WLAN_2G_CAP | WMI_HOST_WLAN_5G_CAP, 122 }; 123 124 /* Parameters used for WMI_VDEV_PARAM_AUTORATE_MISC_CFG command. 125 * Used only for HE auto rate mode. 126 */ 127 enum { 128 /* HE LTF related configuration */ 129 WMI_HE_AUTORATE_LTF_1X = BIT(0), 130 WMI_HE_AUTORATE_LTF_2X = BIT(1), 131 WMI_HE_AUTORATE_LTF_4X = BIT(2), 132 133 /* HE GI related configuration */ 134 WMI_AUTORATE_400NS_GI = BIT(8), 135 WMI_AUTORATE_800NS_GI = BIT(9), 136 WMI_AUTORATE_1600NS_GI = BIT(10), 137 WMI_AUTORATE_3200NS_GI = BIT(11), 138 }; 139 140 /* 141 * wmi command groups. 142 */ 143 enum wmi_cmd_group { 144 /* 0 to 2 are reserved */ 145 WMI_GRP_START = 0x3, 146 WMI_GRP_SCAN = WMI_GRP_START, 147 WMI_GRP_PDEV = 0x4, 148 WMI_GRP_VDEV = 0x5, 149 WMI_GRP_PEER = 0x6, 150 WMI_GRP_MGMT = 0x7, 151 WMI_GRP_BA_NEG = 0x8, 152 WMI_GRP_STA_PS = 0x9, 153 WMI_GRP_DFS = 0xa, 154 WMI_GRP_ROAM = 0xb, 155 WMI_GRP_OFL_SCAN = 0xc, 156 WMI_GRP_P2P = 0xd, 157 WMI_GRP_AP_PS = 0xe, 158 WMI_GRP_RATE_CTRL = 0xf, 159 WMI_GRP_PROFILE = 0x10, 160 WMI_GRP_SUSPEND = 0x11, 161 WMI_GRP_BCN_FILTER = 0x12, 162 WMI_GRP_WOW = 0x13, 163 WMI_GRP_RTT = 0x14, 164 WMI_GRP_SPECTRAL = 0x15, 165 WMI_GRP_STATS = 0x16, 166 WMI_GRP_ARP_NS_OFL = 0x17, 167 WMI_GRP_NLO_OFL = 0x18, 168 WMI_GRP_GTK_OFL = 0x19, 169 WMI_GRP_CSA_OFL = 0x1a, 170 WMI_GRP_CHATTER = 0x1b, 171 WMI_GRP_TID_ADDBA = 0x1c, 172 WMI_GRP_MISC = 0x1d, 173 WMI_GRP_GPIO = 0x1e, 174 WMI_GRP_FWTEST = 0x1f, 175 WMI_GRP_TDLS = 0x20, 176 WMI_GRP_RESMGR = 0x21, 177 WMI_GRP_STA_SMPS = 0x22, 178 WMI_GRP_WLAN_HB = 0x23, 179 WMI_GRP_RMC = 0x24, 180 WMI_GRP_MHF_OFL = 0x25, 181 WMI_GRP_LOCATION_SCAN = 0x26, 182 WMI_GRP_OEM = 0x27, 183 WMI_GRP_NAN = 0x28, 184 WMI_GRP_COEX = 0x29, 185 WMI_GRP_OBSS_OFL = 0x2a, 186 WMI_GRP_LPI = 0x2b, 187 WMI_GRP_EXTSCAN = 0x2c, 188 WMI_GRP_DHCP_OFL = 0x2d, 189 WMI_GRP_IPA = 0x2e, 190 WMI_GRP_MDNS_OFL = 0x2f, 191 WMI_GRP_SAP_OFL = 0x30, 192 WMI_GRP_OCB = 0x31, 193 WMI_GRP_SOC = 0x32, 194 WMI_GRP_PKT_FILTER = 0x33, 195 WMI_GRP_MAWC = 0x34, 196 WMI_GRP_PMF_OFFLOAD = 0x35, 197 WMI_GRP_BPF_OFFLOAD = 0x36, 198 WMI_GRP_NAN_DATA = 0x37, 199 WMI_GRP_PROTOTYPE = 0x38, 200 WMI_GRP_MONITOR = 0x39, 201 WMI_GRP_REGULATORY = 0x3a, 202 WMI_GRP_HW_DATA_FILTER = 0x3b, 203 WMI_GRP_WLM = 0x3c, 204 WMI_GRP_11K_OFFLOAD = 0x3d, 205 WMI_GRP_TWT = 0x3e, 206 WMI_GRP_MOTION_DET = 0x3f, 207 WMI_GRP_SPATIAL_REUSE = 0x40, 208 }; 209 210 #define WMI_CMD_GRP(grp_id) (((grp_id) << 12) | 0x1) 211 #define WMI_EVT_GRP_START_ID(grp_id) (((grp_id) << 12) | 0x1) 212 213 #define WMI_CMD_UNSUPPORTED 0 214 215 enum wmi_tlv_cmd_id { 216 WMI_INIT_CMDID = 0x1, 217 WMI_START_SCAN_CMDID = WMI_TLV_CMD(WMI_GRP_SCAN), 218 WMI_STOP_SCAN_CMDID, 219 WMI_SCAN_CHAN_LIST_CMDID, 220 WMI_SCAN_SCH_PRIO_TBL_CMDID, 221 WMI_SCAN_UPDATE_REQUEST_CMDID, 222 WMI_SCAN_PROB_REQ_OUI_CMDID, 223 WMI_SCAN_ADAPTIVE_DWELL_CONFIG_CMDID, 224 WMI_PDEV_SET_REGDOMAIN_CMDID = WMI_TLV_CMD(WMI_GRP_PDEV), 225 WMI_PDEV_SET_CHANNEL_CMDID, 226 WMI_PDEV_SET_PARAM_CMDID, 227 WMI_PDEV_PKTLOG_ENABLE_CMDID, 228 WMI_PDEV_PKTLOG_DISABLE_CMDID, 229 WMI_PDEV_SET_WMM_PARAMS_CMDID, 230 WMI_PDEV_SET_HT_CAP_IE_CMDID, 231 WMI_PDEV_SET_VHT_CAP_IE_CMDID, 232 WMI_PDEV_SET_DSCP_TID_MAP_CMDID, 233 WMI_PDEV_SET_QUIET_MODE_CMDID, 234 WMI_PDEV_GREEN_AP_PS_ENABLE_CMDID, 235 WMI_PDEV_GET_TPC_CONFIG_CMDID, 236 WMI_PDEV_SET_BASE_MACADDR_CMDID, 237 WMI_PDEV_DUMP_CMDID, 238 WMI_PDEV_SET_LED_CONFIG_CMDID, 239 WMI_PDEV_GET_TEMPERATURE_CMDID, 240 WMI_PDEV_SET_LED_FLASHING_CMDID, 241 WMI_PDEV_SMART_ANT_ENABLE_CMDID, 242 WMI_PDEV_SMART_ANT_SET_RX_ANTENNA_CMDID, 243 WMI_PDEV_SET_ANTENNA_SWITCH_TABLE_CMDID, 244 WMI_PDEV_SET_CTL_TABLE_CMDID, 245 WMI_PDEV_SET_MIMOGAIN_TABLE_CMDID, 246 WMI_PDEV_FIPS_CMDID, 247 WMI_PDEV_GET_ANI_CCK_CONFIG_CMDID, 248 WMI_PDEV_GET_ANI_OFDM_CONFIG_CMDID, 249 WMI_PDEV_GET_NFCAL_POWER_CMDID, 250 WMI_PDEV_GET_TPC_CMDID, 251 WMI_MIB_STATS_ENABLE_CMDID, 252 WMI_PDEV_SET_PCL_CMDID, 253 WMI_PDEV_SET_HW_MODE_CMDID, 254 WMI_PDEV_SET_MAC_CONFIG_CMDID, 255 WMI_PDEV_SET_ANTENNA_MODE_CMDID, 256 WMI_SET_PERIODIC_CHANNEL_STATS_CONFIG_CMDID, 257 WMI_PDEV_WAL_POWER_DEBUG_CMDID, 258 WMI_PDEV_SET_REORDER_TIMEOUT_VAL_CMDID, 259 WMI_PDEV_SET_WAKEUP_CONFIG_CMDID, 260 WMI_PDEV_GET_ANTDIV_STATUS_CMDID, 261 WMI_PDEV_GET_CHIP_POWER_STATS_CMDID, 262 WMI_PDEV_SET_STATS_THRESHOLD_CMDID, 263 WMI_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMDID, 264 WMI_PDEV_UPDATE_PKT_ROUTING_CMDID, 265 WMI_PDEV_CHECK_CAL_VERSION_CMDID, 266 WMI_PDEV_SET_DIVERSITY_GAIN_CMDID, 267 WMI_PDEV_DIV_GET_RSSI_ANTID_CMDID, 268 WMI_PDEV_BSS_CHAN_INFO_REQUEST_CMDID, 269 WMI_PDEV_UPDATE_PMK_CACHE_CMDID, 270 WMI_PDEV_UPDATE_FILS_HLP_PKT_CMDID, 271 WMI_PDEV_UPDATE_CTLTABLE_REQUEST_CMDID, 272 WMI_PDEV_CONFIG_VENDOR_OUI_ACTION_CMDID, 273 WMI_PDEV_SET_AC_TX_QUEUE_OPTIMIZED_CMDID, 274 WMI_PDEV_SET_RX_FILTER_PROMISCUOUS_CMDID, 275 WMI_PDEV_DMA_RING_CFG_REQ_CMDID, 276 WMI_PDEV_HE_TB_ACTION_FRM_CMDID, 277 WMI_PDEV_PKTLOG_FILTER_CMDID, 278 WMI_PDEV_SET_RAP_CONFIG_CMDID, 279 WMI_PDEV_DSM_FILTER_CMDID, 280 WMI_PDEV_FRAME_INJECT_CMDID, 281 WMI_PDEV_TBTT_OFFSET_SYNC_CMDID, 282 WMI_PDEV_SET_SRG_BSS_COLOR_BITMAP_CMDID, 283 WMI_PDEV_SET_SRG_PARTIAL_BSSID_BITMAP_CMDID, 284 WMI_PDEV_SET_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID, 285 WMI_PDEV_SET_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID, 286 WMI_PDEV_SET_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMDID, 287 WMI_PDEV_SET_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMDID, 288 WMI_PDEV_GET_TPC_STATS_CMDID, 289 WMI_PDEV_ENABLE_DURATION_BASED_TX_MODE_SELECTION_CMDID, 290 WMI_PDEV_GET_DPD_STATUS_CMDID, 291 WMI_PDEV_SET_BIOS_SAR_TABLE_CMDID, 292 WMI_PDEV_SET_BIOS_GEO_TABLE_CMDID, 293 WMI_VDEV_CREATE_CMDID = WMI_TLV_CMD(WMI_GRP_VDEV), 294 WMI_VDEV_DELETE_CMDID, 295 WMI_VDEV_START_REQUEST_CMDID, 296 WMI_VDEV_RESTART_REQUEST_CMDID, 297 WMI_VDEV_UP_CMDID, 298 WMI_VDEV_STOP_CMDID, 299 WMI_VDEV_DOWN_CMDID, 300 WMI_VDEV_SET_PARAM_CMDID, 301 WMI_VDEV_INSTALL_KEY_CMDID, 302 WMI_VDEV_WNM_SLEEPMODE_CMDID, 303 WMI_VDEV_WMM_ADDTS_CMDID, 304 WMI_VDEV_WMM_DELTS_CMDID, 305 WMI_VDEV_SET_WMM_PARAMS_CMDID, 306 WMI_VDEV_SET_GTX_PARAMS_CMDID, 307 WMI_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMDID, 308 WMI_VDEV_PLMREQ_START_CMDID, 309 WMI_VDEV_PLMREQ_STOP_CMDID, 310 WMI_VDEV_TSF_TSTAMP_ACTION_CMDID, 311 WMI_VDEV_SET_IE_CMDID, 312 WMI_VDEV_RATEMASK_CMDID, 313 WMI_VDEV_ATF_REQUEST_CMDID, 314 WMI_VDEV_SET_DSCP_TID_MAP_CMDID, 315 WMI_VDEV_FILTER_NEIGHBOR_RX_PACKETS_CMDID, 316 WMI_VDEV_SET_QUIET_MODE_CMDID, 317 WMI_VDEV_SET_CUSTOM_AGGR_SIZE_CMDID, 318 WMI_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMDID, 319 WMI_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_CMDID, 320 WMI_PEER_CREATE_CMDID = WMI_TLV_CMD(WMI_GRP_PEER), 321 WMI_PEER_DELETE_CMDID, 322 WMI_PEER_FLUSH_TIDS_CMDID, 323 WMI_PEER_SET_PARAM_CMDID, 324 WMI_PEER_ASSOC_CMDID, 325 WMI_PEER_ADD_WDS_ENTRY_CMDID, 326 WMI_PEER_REMOVE_WDS_ENTRY_CMDID, 327 WMI_PEER_MCAST_GROUP_CMDID, 328 WMI_PEER_INFO_REQ_CMDID, 329 WMI_PEER_GET_ESTIMATED_LINKSPEED_CMDID, 330 WMI_PEER_SET_RATE_REPORT_CONDITION_CMDID, 331 WMI_PEER_UPDATE_WDS_ENTRY_CMDID, 332 WMI_PEER_ADD_PROXY_STA_ENTRY_CMDID, 333 WMI_PEER_SMART_ANT_SET_TX_ANTENNA_CMDID, 334 WMI_PEER_SMART_ANT_SET_TRAIN_INFO_CMDID, 335 WMI_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMDID, 336 WMI_PEER_ATF_REQUEST_CMDID, 337 WMI_PEER_BWF_REQUEST_CMDID, 338 WMI_PEER_REORDER_QUEUE_SETUP_CMDID, 339 WMI_PEER_REORDER_QUEUE_REMOVE_CMDID, 340 WMI_PEER_SET_RX_BLOCKSIZE_CMDID, 341 WMI_PEER_ANTDIV_INFO_REQ_CMDID, 342 WMI_BCN_TX_CMDID = WMI_TLV_CMD(WMI_GRP_MGMT), 343 WMI_PDEV_SEND_BCN_CMDID, 344 WMI_BCN_TMPL_CMDID, 345 WMI_BCN_FILTER_RX_CMDID, 346 WMI_PRB_REQ_FILTER_RX_CMDID, 347 WMI_MGMT_TX_CMDID, 348 WMI_PRB_TMPL_CMDID, 349 WMI_MGMT_TX_SEND_CMDID, 350 WMI_OFFCHAN_DATA_TX_SEND_CMDID, 351 WMI_PDEV_SEND_FD_CMDID, 352 WMI_BCN_OFFLOAD_CTRL_CMDID, 353 WMI_BSS_COLOR_CHANGE_ENABLE_CMDID, 354 WMI_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMDID, 355 WMI_FILS_DISCOVERY_TMPL_CMDID, 356 WMI_ADDBA_CLEAR_RESP_CMDID = WMI_TLV_CMD(WMI_GRP_BA_NEG), 357 WMI_ADDBA_SEND_CMDID, 358 WMI_ADDBA_STATUS_CMDID, 359 WMI_DELBA_SEND_CMDID, 360 WMI_ADDBA_SET_RESP_CMDID, 361 WMI_SEND_SINGLEAMSDU_CMDID, 362 WMI_STA_POWERSAVE_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_STA_PS), 363 WMI_STA_POWERSAVE_PARAM_CMDID, 364 WMI_STA_MIMO_PS_MODE_CMDID, 365 WMI_PDEV_DFS_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_DFS), 366 WMI_PDEV_DFS_DISABLE_CMDID, 367 WMI_DFS_PHYERR_FILTER_ENA_CMDID, 368 WMI_DFS_PHYERR_FILTER_DIS_CMDID, 369 WMI_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMDID, 370 WMI_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMDID, 371 WMI_VDEV_ADFS_CH_CFG_CMDID, 372 WMI_VDEV_ADFS_OCAC_ABORT_CMDID, 373 WMI_ROAM_SCAN_MODE = WMI_TLV_CMD(WMI_GRP_ROAM), 374 WMI_ROAM_SCAN_RSSI_THRESHOLD, 375 WMI_ROAM_SCAN_PERIOD, 376 WMI_ROAM_SCAN_RSSI_CHANGE_THRESHOLD, 377 WMI_ROAM_AP_PROFILE, 378 WMI_ROAM_CHAN_LIST, 379 WMI_ROAM_SCAN_CMD, 380 WMI_ROAM_SYNCH_COMPLETE, 381 WMI_ROAM_SET_RIC_REQUEST_CMDID, 382 WMI_ROAM_INVOKE_CMDID, 383 WMI_ROAM_FILTER_CMDID, 384 WMI_ROAM_SUBNET_CHANGE_CONFIG_CMDID, 385 WMI_ROAM_CONFIGURE_MAWC_CMDID, 386 WMI_ROAM_SET_MBO_PARAM_CMDID, 387 WMI_ROAM_PER_CONFIG_CMDID, 388 WMI_ROAM_BTM_CONFIG_CMDID, 389 WMI_ENABLE_FILS_CMDID, 390 WMI_OFL_SCAN_ADD_AP_PROFILE = WMI_TLV_CMD(WMI_GRP_OFL_SCAN), 391 WMI_OFL_SCAN_REMOVE_AP_PROFILE, 392 WMI_OFL_SCAN_PERIOD, 393 WMI_P2P_DEV_SET_DEVICE_INFO = WMI_TLV_CMD(WMI_GRP_P2P), 394 WMI_P2P_DEV_SET_DISCOVERABILITY, 395 WMI_P2P_GO_SET_BEACON_IE, 396 WMI_P2P_GO_SET_PROBE_RESP_IE, 397 WMI_P2P_SET_VENDOR_IE_DATA_CMDID, 398 WMI_P2P_DISC_OFFLOAD_CONFIG_CMDID, 399 WMI_P2P_DISC_OFFLOAD_APPIE_CMDID, 400 WMI_P2P_DISC_OFFLOAD_PATTERN_CMDID, 401 WMI_P2P_SET_OPPPS_PARAM_CMDID, 402 WMI_P2P_LISTEN_OFFLOAD_START_CMDID, 403 WMI_P2P_LISTEN_OFFLOAD_STOP_CMDID, 404 WMI_AP_PS_PEER_PARAM_CMDID = WMI_TLV_CMD(WMI_GRP_AP_PS), 405 WMI_AP_PS_PEER_UAPSD_COEX_CMDID, 406 WMI_AP_PS_EGAP_PARAM_CMDID, 407 WMI_PEER_RATE_RETRY_SCHED_CMDID = WMI_TLV_CMD(WMI_GRP_RATE_CTRL), 408 WMI_WLAN_PROFILE_TRIGGER_CMDID = WMI_TLV_CMD(WMI_GRP_PROFILE), 409 WMI_WLAN_PROFILE_SET_HIST_INTVL_CMDID, 410 WMI_WLAN_PROFILE_GET_PROFILE_DATA_CMDID, 411 WMI_WLAN_PROFILE_ENABLE_PROFILE_ID_CMDID, 412 WMI_WLAN_PROFILE_LIST_PROFILE_ID_CMDID, 413 WMI_PDEV_SUSPEND_CMDID = WMI_TLV_CMD(WMI_GRP_SUSPEND), 414 WMI_PDEV_RESUME_CMDID, 415 WMI_ADD_BCN_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_BCN_FILTER), 416 WMI_RMV_BCN_FILTER_CMDID, 417 WMI_WOW_ADD_WAKE_PATTERN_CMDID = WMI_TLV_CMD(WMI_GRP_WOW), 418 WMI_WOW_DEL_WAKE_PATTERN_CMDID, 419 WMI_WOW_ENABLE_DISABLE_WAKE_EVENT_CMDID, 420 WMI_WOW_ENABLE_CMDID, 421 WMI_WOW_HOSTWAKEUP_FROM_SLEEP_CMDID, 422 WMI_WOW_IOAC_ADD_KEEPALIVE_CMDID, 423 WMI_WOW_IOAC_DEL_KEEPALIVE_CMDID, 424 WMI_WOW_IOAC_ADD_WAKE_PATTERN_CMDID, 425 WMI_WOW_IOAC_DEL_WAKE_PATTERN_CMDID, 426 WMI_D0_WOW_ENABLE_DISABLE_CMDID, 427 WMI_EXTWOW_ENABLE_CMDID, 428 WMI_EXTWOW_SET_APP_TYPE1_PARAMS_CMDID, 429 WMI_EXTWOW_SET_APP_TYPE2_PARAMS_CMDID, 430 WMI_WOW_ENABLE_ICMPV6_NA_FLT_CMDID, 431 WMI_WOW_UDP_SVC_OFLD_CMDID, 432 WMI_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMDID, 433 WMI_WOW_SET_ACTION_WAKE_UP_CMDID, 434 WMI_RTT_MEASREQ_CMDID = WMI_TLV_CMD(WMI_GRP_RTT), 435 WMI_RTT_TSF_CMDID, 436 WMI_VDEV_SPECTRAL_SCAN_CONFIGURE_CMDID = WMI_TLV_CMD(WMI_GRP_SPECTRAL), 437 WMI_VDEV_SPECTRAL_SCAN_ENABLE_CMDID, 438 WMI_REQUEST_STATS_CMDID = WMI_TLV_CMD(WMI_GRP_STATS), 439 WMI_MCC_SCHED_TRAFFIC_STATS_CMDID, 440 WMI_REQUEST_STATS_EXT_CMDID, 441 WMI_REQUEST_LINK_STATS_CMDID, 442 WMI_START_LINK_STATS_CMDID, 443 WMI_CLEAR_LINK_STATS_CMDID, 444 WMI_GET_FW_MEM_DUMP_CMDID, 445 WMI_DEBUG_MESG_FLUSH_CMDID, 446 WMI_DIAG_EVENT_LOG_CONFIG_CMDID, 447 WMI_REQUEST_WLAN_STATS_CMDID, 448 WMI_REQUEST_RCPI_CMDID, 449 WMI_REQUEST_PEER_STATS_INFO_CMDID, 450 WMI_REQUEST_RADIO_CHAN_STATS_CMDID, 451 WMI_SET_ARP_NS_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_ARP_NS_OFL), 452 WMI_ADD_PROACTIVE_ARP_RSP_PATTERN_CMDID, 453 WMI_DEL_PROACTIVE_ARP_RSP_PATTERN_CMDID, 454 WMI_NETWORK_LIST_OFFLOAD_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_NLO_OFL), 455 WMI_APFIND_CMDID, 456 WMI_PASSPOINT_LIST_CONFIG_CMDID, 457 WMI_NLO_CONFIGURE_MAWC_CMDID, 458 WMI_GTK_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_GTK_OFL), 459 WMI_CSA_OFFLOAD_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_CSA_OFL), 460 WMI_CSA_OFFLOAD_CHANSWITCH_CMDID, 461 WMI_CHATTER_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_CHATTER), 462 WMI_CHATTER_ADD_COALESCING_FILTER_CMDID, 463 WMI_CHATTER_DELETE_COALESCING_FILTER_CMDID, 464 WMI_CHATTER_COALESCING_QUERY_CMDID, 465 WMI_PEER_TID_ADDBA_CMDID = WMI_TLV_CMD(WMI_GRP_TID_ADDBA), 466 WMI_PEER_TID_DELBA_CMDID, 467 WMI_STA_DTIM_PS_METHOD_CMDID, 468 WMI_STA_UAPSD_AUTO_TRIG_CMDID, 469 WMI_STA_KEEPALIVE_CMDID, 470 WMI_BA_REQ_SSN_CMDID, 471 WMI_ECHO_CMDID = WMI_TLV_CMD(WMI_GRP_MISC), 472 WMI_PDEV_UTF_CMDID, 473 WMI_DBGLOG_CFG_CMDID, 474 WMI_PDEV_QVIT_CMDID, 475 WMI_PDEV_FTM_INTG_CMDID, 476 WMI_VDEV_SET_KEEPALIVE_CMDID, 477 WMI_VDEV_GET_KEEPALIVE_CMDID, 478 WMI_FORCE_FW_HANG_CMDID, 479 WMI_SET_MCASTBCAST_FILTER_CMDID, 480 WMI_THERMAL_MGMT_CMDID, 481 WMI_HOST_AUTO_SHUTDOWN_CFG_CMDID, 482 WMI_TPC_CHAINMASK_CONFIG_CMDID, 483 WMI_SET_ANTENNA_DIVERSITY_CMDID, 484 WMI_OCB_SET_SCHED_CMDID, 485 WMI_RSSI_BREACH_MONITOR_CONFIG_CMDID, 486 WMI_LRO_CONFIG_CMDID, 487 WMI_TRANSFER_DATA_TO_FLASH_CMDID, 488 WMI_CONFIG_ENHANCED_MCAST_FILTER_CMDID, 489 WMI_VDEV_WISA_CMDID, 490 WMI_DBGLOG_TIME_STAMP_SYNC_CMDID, 491 WMI_SET_MULTIPLE_MCAST_FILTER_CMDID, 492 WMI_READ_DATA_FROM_FLASH_CMDID, 493 WMI_THERM_THROT_SET_CONF_CMDID, 494 WMI_RUNTIME_DPD_RECAL_CMDID, 495 WMI_GET_TPC_POWER_CMDID, 496 WMI_IDLE_TRIGGER_MONITOR_CMDID, 497 WMI_GPIO_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_GPIO), 498 WMI_GPIO_OUTPUT_CMDID, 499 WMI_TXBF_CMDID, 500 WMI_FWTEST_VDEV_MCC_SET_TBTT_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_FWTEST), 501 WMI_FWTEST_P2P_SET_NOA_PARAM_CMDID, 502 WMI_UNIT_TEST_CMDID, 503 WMI_FWTEST_CMDID, 504 WMI_QBOOST_CFG_CMDID, 505 WMI_TDLS_SET_STATE_CMDID = WMI_TLV_CMD(WMI_GRP_TDLS), 506 WMI_TDLS_PEER_UPDATE_CMDID, 507 WMI_TDLS_SET_OFFCHAN_MODE_CMDID, 508 WMI_RESMGR_ADAPTIVE_OCS_EN_DIS_CMDID = WMI_TLV_CMD(WMI_GRP_RESMGR), 509 WMI_RESMGR_SET_CHAN_TIME_QUOTA_CMDID, 510 WMI_RESMGR_SET_CHAN_LATENCY_CMDID, 511 WMI_STA_SMPS_FORCE_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_STA_SMPS), 512 WMI_STA_SMPS_PARAM_CMDID, 513 WMI_HB_SET_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_WLAN_HB), 514 WMI_HB_SET_TCP_PARAMS_CMDID, 515 WMI_HB_SET_TCP_PKT_FILTER_CMDID, 516 WMI_HB_SET_UDP_PARAMS_CMDID, 517 WMI_HB_SET_UDP_PKT_FILTER_CMDID, 518 WMI_RMC_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_RMC), 519 WMI_RMC_SET_ACTION_PERIOD_CMDID, 520 WMI_RMC_CONFIG_CMDID, 521 WMI_RMC_SET_MANUAL_LEADER_CMDID, 522 WMI_MHF_OFFLOAD_SET_MODE_CMDID = WMI_TLV_CMD(WMI_GRP_MHF_OFL), 523 WMI_MHF_OFFLOAD_PLUMB_ROUTING_TBL_CMDID, 524 WMI_BATCH_SCAN_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_LOCATION_SCAN), 525 WMI_BATCH_SCAN_DISABLE_CMDID, 526 WMI_BATCH_SCAN_TRIGGER_RESULT_CMDID, 527 WMI_OEM_REQ_CMDID = WMI_TLV_CMD(WMI_GRP_OEM), 528 WMI_OEM_REQUEST_CMDID, 529 WMI_LPI_OEM_REQ_CMDID, 530 WMI_NAN_CMDID = WMI_TLV_CMD(WMI_GRP_NAN), 531 WMI_MODEM_POWER_STATE_CMDID = WMI_TLV_CMD(WMI_GRP_COEX), 532 WMI_CHAN_AVOID_UPDATE_CMDID, 533 WMI_COEX_CONFIG_CMDID, 534 WMI_CHAN_AVOID_RPT_ALLOW_CMDID, 535 WMI_COEX_GET_ANTENNA_ISOLATION_CMDID, 536 WMI_SAR_LIMITS_CMDID, 537 WMI_OBSS_SCAN_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_OBSS_OFL), 538 WMI_OBSS_SCAN_DISABLE_CMDID, 539 WMI_OBSS_COLOR_COLLISION_DET_CONFIG_CMDID, 540 WMI_LPI_MGMT_SNOOPING_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_LPI), 541 WMI_LPI_START_SCAN_CMDID, 542 WMI_LPI_STOP_SCAN_CMDID, 543 WMI_EXTSCAN_START_CMDID = WMI_TLV_CMD(WMI_GRP_EXTSCAN), 544 WMI_EXTSCAN_STOP_CMDID, 545 WMI_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMDID, 546 WMI_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMDID, 547 WMI_EXTSCAN_GET_CACHED_RESULTS_CMDID, 548 WMI_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMDID, 549 WMI_EXTSCAN_SET_CAPABILITIES_CMDID, 550 WMI_EXTSCAN_GET_CAPABILITIES_CMDID, 551 WMI_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMDID, 552 WMI_EXTSCAN_CONFIGURE_MAWC_CMDID, 553 WMI_SET_DHCP_SERVER_OFFLOAD_CMDID = WMI_TLV_CMD(WMI_GRP_DHCP_OFL), 554 WMI_IPA_OFFLOAD_ENABLE_DISABLE_CMDID = WMI_TLV_CMD(WMI_GRP_IPA), 555 WMI_MDNS_OFFLOAD_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_MDNS_OFL), 556 WMI_MDNS_SET_FQDN_CMDID, 557 WMI_MDNS_SET_RESPONSE_CMDID, 558 WMI_MDNS_GET_STATS_CMDID, 559 WMI_SAP_OFL_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_SAP_OFL), 560 WMI_SAP_SET_BLACKLIST_PARAM_CMDID, 561 WMI_OCB_SET_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_OCB), 562 WMI_OCB_SET_UTC_TIME_CMDID, 563 WMI_OCB_START_TIMING_ADVERT_CMDID, 564 WMI_OCB_STOP_TIMING_ADVERT_CMDID, 565 WMI_OCB_GET_TSF_TIMER_CMDID, 566 WMI_DCC_GET_STATS_CMDID, 567 WMI_DCC_CLEAR_STATS_CMDID, 568 WMI_DCC_UPDATE_NDL_CMDID, 569 WMI_SOC_SET_PCL_CMDID = WMI_TLV_CMD(WMI_GRP_SOC), 570 WMI_SOC_SET_HW_MODE_CMDID, 571 WMI_SOC_SET_DUAL_MAC_CONFIG_CMDID, 572 WMI_SOC_SET_ANTENNA_MODE_CMDID, 573 WMI_PACKET_FILTER_CONFIG_CMDID = WMI_TLV_CMD(WMI_GRP_PKT_FILTER), 574 WMI_PACKET_FILTER_ENABLE_CMDID, 575 WMI_MAWC_SENSOR_REPORT_IND_CMDID = WMI_TLV_CMD(WMI_GRP_MAWC), 576 WMI_PMF_OFFLOAD_SET_SA_QUERY_CMDID = WMI_TLV_CMD(WMI_GRP_PMF_OFFLOAD), 577 WMI_BPF_GET_CAPABILITY_CMDID = WMI_TLV_CMD(WMI_GRP_BPF_OFFLOAD), 578 WMI_BPF_GET_VDEV_STATS_CMDID, 579 WMI_BPF_SET_VDEV_INSTRUCTIONS_CMDID, 580 WMI_BPF_DEL_VDEV_INSTRUCTIONS_CMDID, 581 WMI_BPF_SET_VDEV_ACTIVE_MODE_CMDID, 582 WMI_MNT_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_MONITOR), 583 WMI_SET_CURRENT_COUNTRY_CMDID = WMI_TLV_CMD(WMI_GRP_REGULATORY), 584 WMI_11D_SCAN_START_CMDID, 585 WMI_11D_SCAN_STOP_CMDID, 586 WMI_SET_INIT_COUNTRY_CMDID, 587 WMI_NDI_GET_CAP_REQ_CMDID = WMI_TLV_CMD(WMI_GRP_PROTOTYPE), 588 WMI_NDP_INITIATOR_REQ_CMDID, 589 WMI_NDP_RESPONDER_REQ_CMDID, 590 WMI_NDP_END_REQ_CMDID, 591 WMI_HW_DATA_FILTER_CMDID = WMI_TLV_CMD(WMI_GRP_HW_DATA_FILTER), 592 WMI_TWT_ENABLE_CMDID = WMI_TLV_CMD(WMI_GRP_TWT), 593 WMI_TWT_DISABLE_CMDID, 594 WMI_TWT_ADD_DIALOG_CMDID, 595 WMI_TWT_DEL_DIALOG_CMDID, 596 WMI_TWT_PAUSE_DIALOG_CMDID, 597 WMI_TWT_RESUME_DIALOG_CMDID, 598 WMI_PDEV_OBSS_PD_SPATIAL_REUSE_CMDID = 599 WMI_TLV_CMD(WMI_GRP_SPATIAL_REUSE), 600 WMI_PDEV_OBSS_PD_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMDID, 601 }; 602 603 enum wmi_tlv_event_id { 604 WMI_SERVICE_READY_EVENTID = 0x1, 605 WMI_READY_EVENTID, 606 WMI_SERVICE_AVAILABLE_EVENTID, 607 WMI_SCAN_EVENTID = WMI_EVT_GRP_START_ID(WMI_GRP_SCAN), 608 WMI_PDEV_TPC_CONFIG_EVENTID = WMI_TLV_CMD(WMI_GRP_PDEV), 609 WMI_CHAN_INFO_EVENTID, 610 WMI_PHYERR_EVENTID, 611 WMI_PDEV_DUMP_EVENTID, 612 WMI_TX_PAUSE_EVENTID, 613 WMI_DFS_RADAR_EVENTID, 614 WMI_PDEV_L1SS_TRACK_EVENTID, 615 WMI_PDEV_TEMPERATURE_EVENTID, 616 WMI_SERVICE_READY_EXT_EVENTID, 617 WMI_PDEV_FIPS_EVENTID, 618 WMI_PDEV_CHANNEL_HOPPING_EVENTID, 619 WMI_PDEV_ANI_CCK_LEVEL_EVENTID, 620 WMI_PDEV_ANI_OFDM_LEVEL_EVENTID, 621 WMI_PDEV_TPC_EVENTID, 622 WMI_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENTID, 623 WMI_PDEV_SET_HW_MODE_RESP_EVENTID, 624 WMI_PDEV_HW_MODE_TRANSITION_EVENTID, 625 WMI_PDEV_SET_MAC_CONFIG_RESP_EVENTID, 626 WMI_PDEV_ANTDIV_STATUS_EVENTID, 627 WMI_PDEV_CHIP_POWER_STATS_EVENTID, 628 WMI_PDEV_CHIP_POWER_SAVE_FAILURE_DETECTED_EVENTID, 629 WMI_PDEV_CSA_SWITCH_COUNT_STATUS_EVENTID, 630 WMI_PDEV_CHECK_CAL_VERSION_EVENTID, 631 WMI_PDEV_DIV_RSSI_ANTID_EVENTID, 632 WMI_PDEV_BSS_CHAN_INFO_EVENTID, 633 WMI_PDEV_UPDATE_CTLTABLE_EVENTID, 634 WMI_PDEV_DMA_RING_CFG_RSP_EVENTID, 635 WMI_PDEV_DMA_RING_BUF_RELEASE_EVENTID, 636 WMI_PDEV_CTL_FAILSAFE_CHECK_EVENTID, 637 WMI_PDEV_CSC_SWITCH_COUNT_STATUS_EVENTID, 638 WMI_PDEV_COLD_BOOT_CAL_DATA_EVENTID, 639 WMI_PDEV_RAP_INFO_EVENTID, 640 WMI_CHAN_RF_CHARACTERIZATION_INFO_EVENTID, 641 WMI_SERVICE_READY_EXT2_EVENTID, 642 WMI_VDEV_START_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_VDEV), 643 WMI_VDEV_STOPPED_EVENTID, 644 WMI_VDEV_INSTALL_KEY_COMPLETE_EVENTID, 645 WMI_VDEV_MCC_BCN_INTERVAL_CHANGE_REQ_EVENTID, 646 WMI_VDEV_TSF_REPORT_EVENTID, 647 WMI_VDEV_DELETE_RESP_EVENTID, 648 WMI_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENTID, 649 WMI_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_STATUS_EVENTID, 650 WMI_PEER_STA_KICKOUT_EVENTID = WMI_TLV_CMD(WMI_GRP_PEER), 651 WMI_PEER_INFO_EVENTID, 652 WMI_PEER_TX_FAIL_CNT_THR_EVENTID, 653 WMI_PEER_ESTIMATED_LINKSPEED_EVENTID, 654 WMI_PEER_STATE_EVENTID, 655 WMI_PEER_ASSOC_CONF_EVENTID, 656 WMI_PEER_DELETE_RESP_EVENTID, 657 WMI_PEER_RATECODE_LIST_EVENTID, 658 WMI_WDS_PEER_EVENTID, 659 WMI_PEER_STA_PS_STATECHG_EVENTID, 660 WMI_PEER_ANTDIV_INFO_EVENTID, 661 WMI_PEER_RESERVED0_EVENTID, 662 WMI_PEER_RESERVED1_EVENTID, 663 WMI_PEER_RESERVED2_EVENTID, 664 WMI_PEER_RESERVED3_EVENTID, 665 WMI_PEER_RESERVED4_EVENTID, 666 WMI_PEER_RESERVED5_EVENTID, 667 WMI_PEER_RESERVED6_EVENTID, 668 WMI_PEER_RESERVED7_EVENTID, 669 WMI_PEER_RESERVED8_EVENTID, 670 WMI_PEER_RESERVED9_EVENTID, 671 WMI_PEER_RESERVED10_EVENTID, 672 WMI_PEER_OPER_MODE_CHANGE_EVENTID, 673 WMI_PEER_TX_PN_RESPONSE_EVENTID, 674 WMI_PEER_CFR_CAPTURE_EVENTID, 675 WMI_PEER_CREATE_CONF_EVENTID, 676 WMI_MGMT_RX_EVENTID = WMI_TLV_CMD(WMI_GRP_MGMT), 677 WMI_HOST_SWBA_EVENTID, 678 WMI_TBTTOFFSET_UPDATE_EVENTID, 679 WMI_OFFLOAD_BCN_TX_STATUS_EVENTID, 680 WMI_OFFLOAD_PROB_RESP_TX_STATUS_EVENTID, 681 WMI_MGMT_TX_COMPLETION_EVENTID, 682 WMI_MGMT_TX_BUNDLE_COMPLETION_EVENTID, 683 WMI_TBTTOFFSET_EXT_UPDATE_EVENTID, 684 WMI_OFFCHAN_DATA_TX_COMPLETION_EVENTID, 685 WMI_HOST_FILS_DISCOVERY_EVENTID, 686 WMI_TX_DELBA_COMPLETE_EVENTID = WMI_TLV_CMD(WMI_GRP_BA_NEG), 687 WMI_TX_ADDBA_COMPLETE_EVENTID, 688 WMI_BA_RSP_SSN_EVENTID, 689 WMI_AGGR_STATE_TRIG_EVENTID, 690 WMI_ROAM_EVENTID = WMI_TLV_CMD(WMI_GRP_ROAM), 691 WMI_PROFILE_MATCH, 692 WMI_ROAM_SYNCH_EVENTID, 693 WMI_P2P_DISC_EVENTID = WMI_TLV_CMD(WMI_GRP_P2P), 694 WMI_P2P_NOA_EVENTID, 695 WMI_P2P_LISTEN_OFFLOAD_STOPPED_EVENTID, 696 WMI_AP_PS_EGAP_INFO_EVENTID = WMI_TLV_CMD(WMI_GRP_AP_PS), 697 WMI_PDEV_RESUME_EVENTID = WMI_TLV_CMD(WMI_GRP_SUSPEND), 698 WMI_WOW_WAKEUP_HOST_EVENTID = WMI_TLV_CMD(WMI_GRP_WOW), 699 WMI_D0_WOW_DISABLE_ACK_EVENTID, 700 WMI_WOW_INITIAL_WAKEUP_EVENTID, 701 WMI_RTT_MEASUREMENT_REPORT_EVENTID = WMI_TLV_CMD(WMI_GRP_RTT), 702 WMI_TSF_MEASUREMENT_REPORT_EVENTID, 703 WMI_RTT_ERROR_REPORT_EVENTID, 704 WMI_STATS_EXT_EVENTID = WMI_TLV_CMD(WMI_GRP_STATS), 705 WMI_IFACE_LINK_STATS_EVENTID, 706 WMI_PEER_LINK_STATS_EVENTID, 707 WMI_RADIO_LINK_STATS_EVENTID, 708 WMI_UPDATE_FW_MEM_DUMP_EVENTID, 709 WMI_DIAG_EVENT_LOG_SUPPORTED_EVENTID, 710 WMI_INST_RSSI_STATS_EVENTID, 711 WMI_RADIO_TX_POWER_LEVEL_STATS_EVENTID, 712 WMI_REPORT_STATS_EVENTID, 713 WMI_UPDATE_RCPI_EVENTID, 714 WMI_PEER_STATS_INFO_EVENTID, 715 WMI_RADIO_CHAN_STATS_EVENTID, 716 WMI_NLO_MATCH_EVENTID = WMI_TLV_CMD(WMI_GRP_NLO_OFL), 717 WMI_NLO_SCAN_COMPLETE_EVENTID, 718 WMI_APFIND_EVENTID, 719 WMI_PASSPOINT_MATCH_EVENTID, 720 WMI_GTK_OFFLOAD_STATUS_EVENTID = WMI_TLV_CMD(WMI_GRP_GTK_OFL), 721 WMI_GTK_REKEY_FAIL_EVENTID, 722 WMI_CSA_HANDLING_EVENTID = WMI_TLV_CMD(WMI_GRP_CSA_OFL), 723 WMI_CHATTER_PC_QUERY_EVENTID = WMI_TLV_CMD(WMI_GRP_CHATTER), 724 WMI_PDEV_DFS_RADAR_DETECTION_EVENTID = WMI_TLV_CMD(WMI_GRP_DFS), 725 WMI_VDEV_DFS_CAC_COMPLETE_EVENTID, 726 WMI_VDEV_ADFS_OCAC_COMPLETE_EVENTID, 727 WMI_ECHO_EVENTID = WMI_TLV_CMD(WMI_GRP_MISC), 728 WMI_PDEV_UTF_EVENTID, 729 WMI_DEBUG_MESG_EVENTID, 730 WMI_UPDATE_STATS_EVENTID, 731 WMI_DEBUG_PRINT_EVENTID, 732 WMI_DCS_INTERFERENCE_EVENTID, 733 WMI_PDEV_QVIT_EVENTID, 734 WMI_WLAN_PROFILE_DATA_EVENTID, 735 WMI_PDEV_FTM_INTG_EVENTID, 736 WMI_WLAN_FREQ_AVOID_EVENTID, 737 WMI_VDEV_GET_KEEPALIVE_EVENTID, 738 WMI_THERMAL_MGMT_EVENTID, 739 WMI_DIAG_DATA_CONTAINER_EVENTID, 740 WMI_HOST_AUTO_SHUTDOWN_EVENTID, 741 WMI_UPDATE_WHAL_MIB_STATS_EVENTID, 742 WMI_UPDATE_VDEV_RATE_STATS_EVENTID, 743 WMI_DIAG_EVENTID, 744 WMI_OCB_SET_SCHED_EVENTID, 745 WMI_DEBUG_MESG_FLUSH_COMPLETE_EVENTID, 746 WMI_RSSI_BREACH_EVENTID, 747 WMI_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENTID, 748 WMI_PDEV_UTF_SCPC_EVENTID, 749 WMI_READ_DATA_FROM_FLASH_EVENTID, 750 WMI_REPORT_RX_AGGR_FAILURE_EVENTID, 751 WMI_PKGID_EVENTID, 752 WMI_GPIO_INPUT_EVENTID = WMI_TLV_CMD(WMI_GRP_GPIO), 753 WMI_UPLOADH_EVENTID, 754 WMI_CAPTUREH_EVENTID, 755 WMI_RFKILL_STATE_CHANGE_EVENTID, 756 WMI_TDLS_PEER_EVENTID = WMI_TLV_CMD(WMI_GRP_TDLS), 757 WMI_STA_SMPS_FORCE_MODE_COMPL_EVENTID = WMI_TLV_CMD(WMI_GRP_STA_SMPS), 758 WMI_BATCH_SCAN_ENABLED_EVENTID = WMI_TLV_CMD(WMI_GRP_LOCATION_SCAN), 759 WMI_BATCH_SCAN_RESULT_EVENTID, 760 WMI_OEM_CAPABILITY_EVENTID = WMI_TLV_CMD(WMI_GRP_OEM), 761 WMI_OEM_MEASUREMENT_REPORT_EVENTID, 762 WMI_OEM_ERROR_REPORT_EVENTID, 763 WMI_OEM_RESPONSE_EVENTID, 764 WMI_NAN_EVENTID = WMI_TLV_CMD(WMI_GRP_NAN), 765 WMI_NAN_DISC_IFACE_CREATED_EVENTID, 766 WMI_NAN_DISC_IFACE_DELETED_EVENTID, 767 WMI_NAN_STARTED_CLUSTER_EVENTID, 768 WMI_NAN_JOINED_CLUSTER_EVENTID, 769 WMI_COEX_REPORT_ANTENNA_ISOLATION_EVENTID = WMI_TLV_CMD(WMI_GRP_COEX), 770 WMI_LPI_RESULT_EVENTID = WMI_TLV_CMD(WMI_GRP_LPI), 771 WMI_LPI_STATUS_EVENTID, 772 WMI_LPI_HANDOFF_EVENTID, 773 WMI_EXTSCAN_START_STOP_EVENTID = WMI_TLV_CMD(WMI_GRP_EXTSCAN), 774 WMI_EXTSCAN_OPERATION_EVENTID, 775 WMI_EXTSCAN_TABLE_USAGE_EVENTID, 776 WMI_EXTSCAN_CACHED_RESULTS_EVENTID, 777 WMI_EXTSCAN_WLAN_CHANGE_RESULTS_EVENTID, 778 WMI_EXTSCAN_HOTLIST_MATCH_EVENTID, 779 WMI_EXTSCAN_CAPABILITIES_EVENTID, 780 WMI_EXTSCAN_HOTLIST_SSID_MATCH_EVENTID, 781 WMI_MDNS_STATS_EVENTID = WMI_TLV_CMD(WMI_GRP_MDNS_OFL), 782 WMI_SAP_OFL_ADD_STA_EVENTID = WMI_TLV_CMD(WMI_GRP_SAP_OFL), 783 WMI_SAP_OFL_DEL_STA_EVENTID, 784 WMI_OBSS_COLOR_COLLISION_DETECTION_EVENTID = 785 WMI_EVT_GRP_START_ID(WMI_GRP_OBSS_OFL), 786 WMI_OCB_SET_CONFIG_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_OCB), 787 WMI_OCB_GET_TSF_TIMER_RESP_EVENTID, 788 WMI_DCC_GET_STATS_RESP_EVENTID, 789 WMI_DCC_UPDATE_NDL_RESP_EVENTID, 790 WMI_DCC_STATS_EVENTID, 791 WMI_SOC_SET_HW_MODE_RESP_EVENTID = WMI_TLV_CMD(WMI_GRP_SOC), 792 WMI_SOC_HW_MODE_TRANSITION_EVENTID, 793 WMI_SOC_SET_DUAL_MAC_CONFIG_RESP_EVENTID, 794 WMI_MAWC_ENABLE_SENSOR_EVENTID = WMI_TLV_CMD(WMI_GRP_MAWC), 795 WMI_BPF_CAPABILIY_INFO_EVENTID = WMI_TLV_CMD(WMI_GRP_BPF_OFFLOAD), 796 WMI_BPF_VDEV_STATS_INFO_EVENTID, 797 WMI_RMC_NEW_LEADER_EVENTID = WMI_TLV_CMD(WMI_GRP_RMC), 798 WMI_REG_CHAN_LIST_CC_EVENTID = WMI_TLV_CMD(WMI_GRP_REGULATORY), 799 WMI_11D_NEW_COUNTRY_EVENTID, 800 WMI_NDI_CAP_RSP_EVENTID = WMI_TLV_CMD(WMI_GRP_PROTOTYPE), 801 WMI_NDP_INITIATOR_RSP_EVENTID, 802 WMI_NDP_RESPONDER_RSP_EVENTID, 803 WMI_NDP_END_RSP_EVENTID, 804 WMI_NDP_INDICATION_EVENTID, 805 WMI_NDP_CONFIRM_EVENTID, 806 WMI_NDP_END_INDICATION_EVENTID, 807 808 WMI_TWT_ENABLE_EVENTID = WMI_TLV_CMD(WMI_GRP_TWT), 809 WMI_TWT_DISABLE_EVENTID, 810 WMI_TWT_ADD_DIALOG_EVENTID, 811 WMI_TWT_DEL_DIALOG_EVENTID, 812 WMI_TWT_PAUSE_DIALOG_EVENTID, 813 WMI_TWT_RESUME_DIALOG_EVENTID, 814 }; 815 816 enum wmi_tlv_pdev_param { 817 WMI_PDEV_PARAM_TX_CHAIN_MASK = 0x1, 818 WMI_PDEV_PARAM_RX_CHAIN_MASK, 819 WMI_PDEV_PARAM_TXPOWER_LIMIT2G, 820 WMI_PDEV_PARAM_TXPOWER_LIMIT5G, 821 WMI_PDEV_PARAM_TXPOWER_SCALE, 822 WMI_PDEV_PARAM_BEACON_GEN_MODE, 823 WMI_PDEV_PARAM_BEACON_TX_MODE, 824 WMI_PDEV_PARAM_RESMGR_OFFCHAN_MODE, 825 WMI_PDEV_PARAM_PROTECTION_MODE, 826 WMI_PDEV_PARAM_DYNAMIC_BW, 827 WMI_PDEV_PARAM_NON_AGG_SW_RETRY_TH, 828 WMI_PDEV_PARAM_AGG_SW_RETRY_TH, 829 WMI_PDEV_PARAM_STA_KICKOUT_TH, 830 WMI_PDEV_PARAM_AC_AGGRSIZE_SCALING, 831 WMI_PDEV_PARAM_LTR_ENABLE, 832 WMI_PDEV_PARAM_LTR_AC_LATENCY_BE, 833 WMI_PDEV_PARAM_LTR_AC_LATENCY_BK, 834 WMI_PDEV_PARAM_LTR_AC_LATENCY_VI, 835 WMI_PDEV_PARAM_LTR_AC_LATENCY_VO, 836 WMI_PDEV_PARAM_LTR_AC_LATENCY_TIMEOUT, 837 WMI_PDEV_PARAM_LTR_SLEEP_OVERRIDE, 838 WMI_PDEV_PARAM_LTR_RX_OVERRIDE, 839 WMI_PDEV_PARAM_LTR_TX_ACTIVITY_TIMEOUT, 840 WMI_PDEV_PARAM_L1SS_ENABLE, 841 WMI_PDEV_PARAM_DSLEEP_ENABLE, 842 WMI_PDEV_PARAM_PCIELP_TXBUF_FLUSH, 843 WMI_PDEV_PARAM_PCIELP_TXBUF_WATERMARK, 844 WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_EN, 845 WMI_PDEV_PARAM_PCIELP_TXBUF_TMO_VALUE, 846 WMI_PDEV_PARAM_PDEV_STATS_UPDATE_PERIOD, 847 WMI_PDEV_PARAM_VDEV_STATS_UPDATE_PERIOD, 848 WMI_PDEV_PARAM_PEER_STATS_UPDATE_PERIOD, 849 WMI_PDEV_PARAM_BCNFLT_STATS_UPDATE_PERIOD, 850 WMI_PDEV_PARAM_PMF_QOS, 851 WMI_PDEV_PARAM_ARP_AC_OVERRIDE, 852 WMI_PDEV_PARAM_DCS, 853 WMI_PDEV_PARAM_ANI_ENABLE, 854 WMI_PDEV_PARAM_ANI_POLL_PERIOD, 855 WMI_PDEV_PARAM_ANI_LISTEN_PERIOD, 856 WMI_PDEV_PARAM_ANI_OFDM_LEVEL, 857 WMI_PDEV_PARAM_ANI_CCK_LEVEL, 858 WMI_PDEV_PARAM_DYNTXCHAIN, 859 WMI_PDEV_PARAM_PROXY_STA, 860 WMI_PDEV_PARAM_IDLE_PS_CONFIG, 861 WMI_PDEV_PARAM_POWER_GATING_SLEEP, 862 WMI_PDEV_PARAM_RFKILL_ENABLE, 863 WMI_PDEV_PARAM_BURST_DUR, 864 WMI_PDEV_PARAM_BURST_ENABLE, 865 WMI_PDEV_PARAM_HW_RFKILL_CONFIG, 866 WMI_PDEV_PARAM_LOW_POWER_RF_ENABLE, 867 WMI_PDEV_PARAM_L1SS_TRACK, 868 WMI_PDEV_PARAM_HYST_EN, 869 WMI_PDEV_PARAM_POWER_COLLAPSE_ENABLE, 870 WMI_PDEV_PARAM_LED_SYS_STATE, 871 WMI_PDEV_PARAM_LED_ENABLE, 872 WMI_PDEV_PARAM_AUDIO_OVER_WLAN_LATENCY, 873 WMI_PDEV_PARAM_AUDIO_OVER_WLAN_ENABLE, 874 WMI_PDEV_PARAM_WHAL_MIB_STATS_UPDATE_ENABLE, 875 WMI_PDEV_PARAM_VDEV_RATE_STATS_UPDATE_PERIOD, 876 WMI_PDEV_PARAM_CTS_CBW, 877 WMI_PDEV_PARAM_WNTS_CONFIG, 878 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_ENABLE, 879 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_MIN_SLEEP_SLOP, 880 WMI_PDEV_PARAM_ADAPTIVE_EARLY_RX_INC_DEC_STEP, 881 WMI_PDEV_PARAM_EARLY_RX_FIX_SLEEP_SLOP, 882 WMI_PDEV_PARAM_BMISS_BASED_ADAPTIVE_BTO_ENABLE, 883 WMI_PDEV_PARAM_BMISS_BTO_MIN_BCN_TIMEOUT, 884 WMI_PDEV_PARAM_BMISS_BTO_INC_DEC_STEP, 885 WMI_PDEV_PARAM_BTO_FIX_BCN_TIMEOUT, 886 WMI_PDEV_PARAM_CE_BASED_ADAPTIVE_BTO_ENABLE, 887 WMI_PDEV_PARAM_CE_BTO_COMBO_CE_VALUE, 888 WMI_PDEV_PARAM_TX_CHAIN_MASK_2G, 889 WMI_PDEV_PARAM_RX_CHAIN_MASK_2G, 890 WMI_PDEV_PARAM_TX_CHAIN_MASK_5G, 891 WMI_PDEV_PARAM_RX_CHAIN_MASK_5G, 892 WMI_PDEV_PARAM_TX_CHAIN_MASK_CCK, 893 WMI_PDEV_PARAM_TX_CHAIN_MASK_1SS, 894 WMI_PDEV_PARAM_CTS2SELF_FOR_P2P_GO_CONFIG, 895 WMI_PDEV_PARAM_TXPOWER_DECR_DB, 896 WMI_PDEV_PARAM_AGGR_BURST, 897 WMI_PDEV_PARAM_RX_DECAP_MODE, 898 WMI_PDEV_PARAM_FAST_CHANNEL_RESET, 899 WMI_PDEV_PARAM_SMART_ANTENNA_DEFAULT_ANTENNA, 900 WMI_PDEV_PARAM_ANTENNA_GAIN, 901 WMI_PDEV_PARAM_RX_FILTER, 902 WMI_PDEV_SET_MCAST_TO_UCAST_TID, 903 WMI_PDEV_PARAM_PROXY_STA_MODE, 904 WMI_PDEV_PARAM_SET_MCAST2UCAST_MODE, 905 WMI_PDEV_PARAM_SET_MCAST2UCAST_BUFFER, 906 WMI_PDEV_PARAM_REMOVE_MCAST2UCAST_BUFFER, 907 WMI_PDEV_PEER_STA_PS_STATECHG_ENABLE, 908 WMI_PDEV_PARAM_IGMPMLD_AC_OVERRIDE, 909 WMI_PDEV_PARAM_BLOCK_INTERBSS, 910 WMI_PDEV_PARAM_SET_DISABLE_RESET_CMDID, 911 WMI_PDEV_PARAM_SET_MSDU_TTL_CMDID, 912 WMI_PDEV_PARAM_SET_PPDU_DURATION_CMDID, 913 WMI_PDEV_PARAM_TXBF_SOUND_PERIOD_CMDID, 914 WMI_PDEV_PARAM_SET_PROMISC_MODE_CMDID, 915 WMI_PDEV_PARAM_SET_BURST_MODE_CMDID, 916 WMI_PDEV_PARAM_EN_STATS, 917 WMI_PDEV_PARAM_MU_GROUP_POLICY, 918 WMI_PDEV_PARAM_NOISE_DETECTION, 919 WMI_PDEV_PARAM_NOISE_THRESHOLD, 920 WMI_PDEV_PARAM_DPD_ENABLE, 921 WMI_PDEV_PARAM_SET_MCAST_BCAST_ECHO, 922 WMI_PDEV_PARAM_ATF_STRICT_SCH, 923 WMI_PDEV_PARAM_ATF_SCHED_DURATION, 924 WMI_PDEV_PARAM_ANT_PLZN, 925 WMI_PDEV_PARAM_MGMT_RETRY_LIMIT, 926 WMI_PDEV_PARAM_SENSITIVITY_LEVEL, 927 WMI_PDEV_PARAM_SIGNED_TXPOWER_2G, 928 WMI_PDEV_PARAM_SIGNED_TXPOWER_5G, 929 WMI_PDEV_PARAM_ENABLE_PER_TID_AMSDU, 930 WMI_PDEV_PARAM_ENABLE_PER_TID_AMPDU, 931 WMI_PDEV_PARAM_CCA_THRESHOLD, 932 WMI_PDEV_PARAM_RTS_FIXED_RATE, 933 WMI_PDEV_PARAM_PDEV_RESET, 934 WMI_PDEV_PARAM_WAPI_MBSSID_OFFSET, 935 WMI_PDEV_PARAM_ARP_DBG_SRCADDR, 936 WMI_PDEV_PARAM_ARP_DBG_DSTADDR, 937 WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCH, 938 WMI_PDEV_PARAM_ATF_OBSS_NOISE_SCALING_FACTOR, 939 WMI_PDEV_PARAM_CUST_TXPOWER_SCALE, 940 WMI_PDEV_PARAM_ATF_DYNAMIC_ENABLE, 941 WMI_PDEV_PARAM_CTRL_RETRY_LIMIT, 942 WMI_PDEV_PARAM_PROPAGATION_DELAY, 943 WMI_PDEV_PARAM_ENA_ANT_DIV, 944 WMI_PDEV_PARAM_FORCE_CHAIN_ANT, 945 WMI_PDEV_PARAM_ANT_DIV_SELFTEST, 946 WMI_PDEV_PARAM_ANT_DIV_SELFTEST_INTVL, 947 WMI_PDEV_PARAM_STATS_OBSERVATION_PERIOD, 948 WMI_PDEV_PARAM_TX_PPDU_DELAY_BIN_SIZE_MS, 949 WMI_PDEV_PARAM_TX_PPDU_DELAY_ARRAY_LEN, 950 WMI_PDEV_PARAM_TX_MPDU_AGGR_ARRAY_LEN, 951 WMI_PDEV_PARAM_RX_MPDU_AGGR_ARRAY_LEN, 952 WMI_PDEV_PARAM_TX_SCH_DELAY, 953 WMI_PDEV_PARAM_ENABLE_RTS_SIFS_BURSTING, 954 WMI_PDEV_PARAM_MAX_MPDUS_IN_AMPDU, 955 WMI_PDEV_PARAM_PEER_STATS_INFO_ENABLE, 956 WMI_PDEV_PARAM_FAST_PWR_TRANSITION, 957 WMI_PDEV_PARAM_RADIO_CHAN_STATS_ENABLE, 958 WMI_PDEV_PARAM_RADIO_DIAGNOSIS_ENABLE, 959 WMI_PDEV_PARAM_MESH_MCAST_ENABLE, 960 WMI_PDEV_PARAM_SET_CMD_OBSS_PD_THRESHOLD = 0xbc, 961 WMI_PDEV_PARAM_SET_CMD_OBSS_PD_PER_AC = 0xbe, 962 WMI_PDEV_PARAM_ENABLE_SR_PROHIBIT = 0xc6, 963 }; 964 965 enum wmi_tlv_vdev_param { 966 WMI_VDEV_PARAM_RTS_THRESHOLD = 0x1, 967 WMI_VDEV_PARAM_FRAGMENTATION_THRESHOLD, 968 WMI_VDEV_PARAM_BEACON_INTERVAL, 969 WMI_VDEV_PARAM_LISTEN_INTERVAL, 970 WMI_VDEV_PARAM_MULTICAST_RATE, 971 WMI_VDEV_PARAM_MGMT_TX_RATE, 972 WMI_VDEV_PARAM_SLOT_TIME, 973 WMI_VDEV_PARAM_PREAMBLE, 974 WMI_VDEV_PARAM_SWBA_TIME, 975 WMI_VDEV_STATS_UPDATE_PERIOD, 976 WMI_VDEV_PWRSAVE_AGEOUT_TIME, 977 WMI_VDEV_HOST_SWBA_INTERVAL, 978 WMI_VDEV_PARAM_DTIM_PERIOD, 979 WMI_VDEV_OC_SCHEDULER_AIR_TIME_LIMIT, 980 WMI_VDEV_PARAM_WDS, 981 WMI_VDEV_PARAM_ATIM_WINDOW, 982 WMI_VDEV_PARAM_BMISS_COUNT_MAX, 983 WMI_VDEV_PARAM_BMISS_FIRST_BCNT, 984 WMI_VDEV_PARAM_BMISS_FINAL_BCNT, 985 WMI_VDEV_PARAM_FEATURE_WMM, 986 WMI_VDEV_PARAM_CHWIDTH, 987 WMI_VDEV_PARAM_CHEXTOFFSET, 988 WMI_VDEV_PARAM_DISABLE_HTPROTECTION, 989 WMI_VDEV_PARAM_STA_QUICKKICKOUT, 990 WMI_VDEV_PARAM_MGMT_RATE, 991 WMI_VDEV_PARAM_PROTECTION_MODE, 992 WMI_VDEV_PARAM_FIXED_RATE, 993 WMI_VDEV_PARAM_SGI, 994 WMI_VDEV_PARAM_LDPC, 995 WMI_VDEV_PARAM_TX_STBC, 996 WMI_VDEV_PARAM_RX_STBC, 997 WMI_VDEV_PARAM_INTRA_BSS_FWD, 998 WMI_VDEV_PARAM_DEF_KEYID, 999 WMI_VDEV_PARAM_NSS, 1000 WMI_VDEV_PARAM_BCAST_DATA_RATE, 1001 WMI_VDEV_PARAM_MCAST_DATA_RATE, 1002 WMI_VDEV_PARAM_MCAST_INDICATE, 1003 WMI_VDEV_PARAM_DHCP_INDICATE, 1004 WMI_VDEV_PARAM_UNKNOWN_DEST_INDICATE, 1005 WMI_VDEV_PARAM_AP_KEEPALIVE_MIN_IDLE_INACTIVE_TIME_SECS, 1006 WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_IDLE_INACTIVE_TIME_SECS, 1007 WMI_VDEV_PARAM_AP_KEEPALIVE_MAX_UNRESPONSIVE_TIME_SECS, 1008 WMI_VDEV_PARAM_AP_ENABLE_NAWDS, 1009 WMI_VDEV_PARAM_ENABLE_RTSCTS, 1010 WMI_VDEV_PARAM_TXBF, 1011 WMI_VDEV_PARAM_PACKET_POWERSAVE, 1012 WMI_VDEV_PARAM_DROP_UNENCRY, 1013 WMI_VDEV_PARAM_TX_ENCAP_TYPE, 1014 WMI_VDEV_PARAM_AP_DETECT_OUT_OF_SYNC_SLEEPING_STA_TIME_SECS, 1015 WMI_VDEV_PARAM_EARLY_RX_ADJUST_ENABLE, 1016 WMI_VDEV_PARAM_EARLY_RX_TGT_BMISS_NUM, 1017 WMI_VDEV_PARAM_EARLY_RX_BMISS_SAMPLE_CYCLE, 1018 WMI_VDEV_PARAM_EARLY_RX_SLOP_STEP, 1019 WMI_VDEV_PARAM_EARLY_RX_INIT_SLOP, 1020 WMI_VDEV_PARAM_EARLY_RX_ADJUST_PAUSE, 1021 WMI_VDEV_PARAM_TX_PWRLIMIT, 1022 WMI_VDEV_PARAM_SNR_NUM_FOR_CAL, 1023 WMI_VDEV_PARAM_ROAM_FW_OFFLOAD, 1024 WMI_VDEV_PARAM_ENABLE_RMC, 1025 WMI_VDEV_PARAM_IBSS_MAX_BCN_LOST_MS, 1026 WMI_VDEV_PARAM_MAX_RATE, 1027 WMI_VDEV_PARAM_EARLY_RX_DRIFT_SAMPLE, 1028 WMI_VDEV_PARAM_SET_IBSS_TX_FAIL_CNT_THR, 1029 WMI_VDEV_PARAM_EBT_RESYNC_TIMEOUT, 1030 WMI_VDEV_PARAM_AGGR_TRIG_EVENT_ENABLE, 1031 WMI_VDEV_PARAM_IS_IBSS_POWER_SAVE_ALLOWED, 1032 WMI_VDEV_PARAM_IS_POWER_COLLAPSE_ALLOWED, 1033 WMI_VDEV_PARAM_IS_AWAKE_ON_TXRX_ENABLED, 1034 WMI_VDEV_PARAM_INACTIVITY_CNT, 1035 WMI_VDEV_PARAM_TXSP_END_INACTIVITY_TIME_MS, 1036 WMI_VDEV_PARAM_DTIM_POLICY, 1037 WMI_VDEV_PARAM_IBSS_PS_WARMUP_TIME_SECS, 1038 WMI_VDEV_PARAM_IBSS_PS_1RX_CHAIN_IN_ATIM_WINDOW_ENABLE, 1039 WMI_VDEV_PARAM_RX_LEAK_WINDOW, 1040 WMI_VDEV_PARAM_STATS_AVG_FACTOR, 1041 WMI_VDEV_PARAM_DISCONNECT_TH, 1042 WMI_VDEV_PARAM_RTSCTS_RATE, 1043 WMI_VDEV_PARAM_MCC_RTSCTS_PROTECTION_ENABLE, 1044 WMI_VDEV_PARAM_MCC_BROADCAST_PROBE_ENABLE, 1045 WMI_VDEV_PARAM_TXPOWER_SCALE, 1046 WMI_VDEV_PARAM_TXPOWER_SCALE_DECR_DB, 1047 WMI_VDEV_PARAM_MCAST2UCAST_SET, 1048 WMI_VDEV_PARAM_RC_NUM_RETRIES, 1049 WMI_VDEV_PARAM_CABQ_MAXDUR, 1050 WMI_VDEV_PARAM_MFPTEST_SET, 1051 WMI_VDEV_PARAM_RTS_FIXED_RATE, 1052 WMI_VDEV_PARAM_VHT_SGIMASK, 1053 WMI_VDEV_PARAM_VHT80_RATEMASK, 1054 WMI_VDEV_PARAM_PROXY_STA, 1055 WMI_VDEV_PARAM_VIRTUAL_CELL_MODE, 1056 WMI_VDEV_PARAM_RX_DECAP_TYPE, 1057 WMI_VDEV_PARAM_BW_NSS_RATEMASK, 1058 WMI_VDEV_PARAM_SENSOR_AP, 1059 WMI_VDEV_PARAM_BEACON_RATE, 1060 WMI_VDEV_PARAM_DTIM_ENABLE_CTS, 1061 WMI_VDEV_PARAM_STA_KICKOUT, 1062 WMI_VDEV_PARAM_CAPABILITIES, 1063 WMI_VDEV_PARAM_TSF_INCREMENT, 1064 WMI_VDEV_PARAM_AMPDU_PER_AC, 1065 WMI_VDEV_PARAM_RX_FILTER, 1066 WMI_VDEV_PARAM_MGMT_TX_POWER, 1067 WMI_VDEV_PARAM_NON_AGG_SW_RETRY_TH, 1068 WMI_VDEV_PARAM_AGG_SW_RETRY_TH, 1069 WMI_VDEV_PARAM_DISABLE_DYN_BW_RTS, 1070 WMI_VDEV_PARAM_ATF_SSID_SCHED_POLICY, 1071 WMI_VDEV_PARAM_HE_DCM, 1072 WMI_VDEV_PARAM_HE_RANGE_EXT, 1073 WMI_VDEV_PARAM_ENABLE_BCAST_PROBE_RESPONSE, 1074 WMI_VDEV_PARAM_FILS_MAX_CHANNEL_GUARD_TIME, 1075 WMI_VDEV_PARAM_HE_LTF = 0x74, 1076 WMI_VDEV_PARAM_ENABLE_DISABLE_RTT_RESPONDER_ROLE = 0x7d, 1077 WMI_VDEV_PARAM_BA_MODE = 0x7e, 1078 WMI_VDEV_PARAM_AUTORATE_MISC_CFG = 0x80, 1079 WMI_VDEV_PARAM_SET_HE_SOUNDING_MODE = 0x87, 1080 WMI_VDEV_PARAM_6GHZ_PARAMS = 0x99, 1081 WMI_VDEV_PARAM_PROTOTYPE = 0x8000, 1082 WMI_VDEV_PARAM_BSS_COLOR, 1083 WMI_VDEV_PARAM_SET_HEMU_MODE, 1084 WMI_VDEV_PARAM_HEOPS_0_31 = 0x8003, 1085 }; 1086 1087 enum wmi_tlv_peer_flags { 1088 WMI_TLV_PEER_AUTH = 0x00000001, 1089 WMI_TLV_PEER_QOS = 0x00000002, 1090 WMI_TLV_PEER_NEED_PTK_4_WAY = 0x00000004, 1091 WMI_TLV_PEER_NEED_GTK_2_WAY = 0x00000010, 1092 WMI_TLV_PEER_APSD = 0x00000800, 1093 WMI_TLV_PEER_HT = 0x00001000, 1094 WMI_TLV_PEER_40MHZ = 0x00002000, 1095 WMI_TLV_PEER_STBC = 0x00008000, 1096 WMI_TLV_PEER_LDPC = 0x00010000, 1097 WMI_TLV_PEER_DYN_MIMOPS = 0x00020000, 1098 WMI_TLV_PEER_STATIC_MIMOPS = 0x00040000, 1099 WMI_TLV_PEER_SPATIAL_MUX = 0x00200000, 1100 WMI_TLV_PEER_VHT = 0x02000000, 1101 WMI_TLV_PEER_80MHZ = 0x04000000, 1102 WMI_TLV_PEER_PMF = 0x08000000, 1103 WMI_PEER_IS_P2P_CAPABLE = 0x20000000, 1104 WMI_PEER_160MHZ = 0x40000000, 1105 WMI_PEER_SAFEMODE_EN = 0x80000000, 1106 1107 }; 1108 1109 /** Enum list of TLV Tags for each parameter structure type. */ 1110 enum wmi_tlv_tag { 1111 WMI_TAG_LAST_RESERVED = 15, 1112 WMI_TAG_FIRST_ARRAY_ENUM, 1113 WMI_TAG_ARRAY_UINT32 = WMI_TAG_FIRST_ARRAY_ENUM, 1114 WMI_TAG_ARRAY_BYTE, 1115 WMI_TAG_ARRAY_STRUCT, 1116 WMI_TAG_ARRAY_FIXED_STRUCT, 1117 WMI_TAG_LAST_ARRAY_ENUM = 31, 1118 WMI_TAG_SERVICE_READY_EVENT, 1119 WMI_TAG_HAL_REG_CAPABILITIES, 1120 WMI_TAG_WLAN_HOST_MEM_REQ, 1121 WMI_TAG_READY_EVENT, 1122 WMI_TAG_SCAN_EVENT, 1123 WMI_TAG_PDEV_TPC_CONFIG_EVENT, 1124 WMI_TAG_CHAN_INFO_EVENT, 1125 WMI_TAG_COMB_PHYERR_RX_HDR, 1126 WMI_TAG_VDEV_START_RESPONSE_EVENT, 1127 WMI_TAG_VDEV_STOPPED_EVENT, 1128 WMI_TAG_VDEV_INSTALL_KEY_COMPLETE_EVENT, 1129 WMI_TAG_PEER_STA_KICKOUT_EVENT, 1130 WMI_TAG_MGMT_RX_HDR, 1131 WMI_TAG_TBTT_OFFSET_EVENT, 1132 WMI_TAG_TX_DELBA_COMPLETE_EVENT, 1133 WMI_TAG_TX_ADDBA_COMPLETE_EVENT, 1134 WMI_TAG_ROAM_EVENT, 1135 WMI_TAG_WOW_EVENT_INFO, 1136 WMI_TAG_WOW_EVENT_INFO_SECTION_BITMAP, 1137 WMI_TAG_RTT_EVENT_HEADER, 1138 WMI_TAG_RTT_ERROR_REPORT_EVENT, 1139 WMI_TAG_RTT_MEAS_EVENT, 1140 WMI_TAG_ECHO_EVENT, 1141 WMI_TAG_FTM_INTG_EVENT, 1142 WMI_TAG_VDEV_GET_KEEPALIVE_EVENT, 1143 WMI_TAG_GPIO_INPUT_EVENT, 1144 WMI_TAG_CSA_EVENT, 1145 WMI_TAG_GTK_OFFLOAD_STATUS_EVENT, 1146 WMI_TAG_IGTK_INFO, 1147 WMI_TAG_DCS_INTERFERENCE_EVENT, 1148 WMI_TAG_ATH_DCS_CW_INT, 1149 WMI_TAG_WLAN_DCS_CW_INT = /* ALIAS */ 1150 WMI_TAG_ATH_DCS_CW_INT, 1151 WMI_TAG_ATH_DCS_WLAN_INT_STAT, 1152 WMI_TAG_WLAN_DCS_IM_TGT_STATS_T = /* ALIAS */ 1153 WMI_TAG_ATH_DCS_WLAN_INT_STAT, 1154 WMI_TAG_WLAN_PROFILE_CTX_T, 1155 WMI_TAG_WLAN_PROFILE_T, 1156 WMI_TAG_PDEV_QVIT_EVENT, 1157 WMI_TAG_HOST_SWBA_EVENT, 1158 WMI_TAG_TIM_INFO, 1159 WMI_TAG_P2P_NOA_INFO, 1160 WMI_TAG_STATS_EVENT, 1161 WMI_TAG_AVOID_FREQ_RANGES_EVENT, 1162 WMI_TAG_AVOID_FREQ_RANGE_DESC, 1163 WMI_TAG_GTK_REKEY_FAIL_EVENT, 1164 WMI_TAG_INIT_CMD, 1165 WMI_TAG_RESOURCE_CONFIG, 1166 WMI_TAG_WLAN_HOST_MEMORY_CHUNK, 1167 WMI_TAG_START_SCAN_CMD, 1168 WMI_TAG_STOP_SCAN_CMD, 1169 WMI_TAG_SCAN_CHAN_LIST_CMD, 1170 WMI_TAG_CHANNEL, 1171 WMI_TAG_PDEV_SET_REGDOMAIN_CMD, 1172 WMI_TAG_PDEV_SET_PARAM_CMD, 1173 WMI_TAG_PDEV_SET_WMM_PARAMS_CMD, 1174 WMI_TAG_WMM_PARAMS, 1175 WMI_TAG_PDEV_SET_QUIET_CMD, 1176 WMI_TAG_VDEV_CREATE_CMD, 1177 WMI_TAG_VDEV_DELETE_CMD, 1178 WMI_TAG_VDEV_START_REQUEST_CMD, 1179 WMI_TAG_P2P_NOA_DESCRIPTOR, 1180 WMI_TAG_P2P_GO_SET_BEACON_IE, 1181 WMI_TAG_GTK_OFFLOAD_CMD, 1182 WMI_TAG_VDEV_UP_CMD, 1183 WMI_TAG_VDEV_STOP_CMD, 1184 WMI_TAG_VDEV_DOWN_CMD, 1185 WMI_TAG_VDEV_SET_PARAM_CMD, 1186 WMI_TAG_VDEV_INSTALL_KEY_CMD, 1187 WMI_TAG_PEER_CREATE_CMD, 1188 WMI_TAG_PEER_DELETE_CMD, 1189 WMI_TAG_PEER_FLUSH_TIDS_CMD, 1190 WMI_TAG_PEER_SET_PARAM_CMD, 1191 WMI_TAG_PEER_ASSOC_COMPLETE_CMD, 1192 WMI_TAG_VHT_RATE_SET, 1193 WMI_TAG_BCN_TMPL_CMD, 1194 WMI_TAG_PRB_TMPL_CMD, 1195 WMI_TAG_BCN_PRB_INFO, 1196 WMI_TAG_PEER_TID_ADDBA_CMD, 1197 WMI_TAG_PEER_TID_DELBA_CMD, 1198 WMI_TAG_STA_POWERSAVE_MODE_CMD, 1199 WMI_TAG_STA_POWERSAVE_PARAM_CMD, 1200 WMI_TAG_STA_DTIM_PS_METHOD_CMD, 1201 WMI_TAG_ROAM_SCAN_MODE, 1202 WMI_TAG_ROAM_SCAN_RSSI_THRESHOLD, 1203 WMI_TAG_ROAM_SCAN_PERIOD, 1204 WMI_TAG_ROAM_SCAN_RSSI_CHANGE_THRESHOLD, 1205 WMI_TAG_PDEV_SUSPEND_CMD, 1206 WMI_TAG_PDEV_RESUME_CMD, 1207 WMI_TAG_ADD_BCN_FILTER_CMD, 1208 WMI_TAG_RMV_BCN_FILTER_CMD, 1209 WMI_TAG_WOW_ENABLE_CMD, 1210 WMI_TAG_WOW_HOSTWAKEUP_FROM_SLEEP_CMD, 1211 WMI_TAG_STA_UAPSD_AUTO_TRIG_CMD, 1212 WMI_TAG_STA_UAPSD_AUTO_TRIG_PARAM, 1213 WMI_TAG_SET_ARP_NS_OFFLOAD_CMD, 1214 WMI_TAG_ARP_OFFLOAD_TUPLE, 1215 WMI_TAG_NS_OFFLOAD_TUPLE, 1216 WMI_TAG_FTM_INTG_CMD, 1217 WMI_TAG_STA_KEEPALIVE_CMD, 1218 WMI_TAG_STA_KEEPALIVE_ARP_RESPONSE, 1219 WMI_TAG_P2P_SET_VENDOR_IE_DATA_CMD, 1220 WMI_TAG_AP_PS_PEER_CMD, 1221 WMI_TAG_PEER_RATE_RETRY_SCHED_CMD, 1222 WMI_TAG_WLAN_PROFILE_TRIGGER_CMD, 1223 WMI_TAG_WLAN_PROFILE_SET_HIST_INTVL_CMD, 1224 WMI_TAG_WLAN_PROFILE_GET_PROF_DATA_CMD, 1225 WMI_TAG_WLAN_PROFILE_ENABLE_PROFILE_ID_CMD, 1226 WMI_TAG_WOW_DEL_PATTERN_CMD, 1227 WMI_TAG_WOW_ADD_DEL_EVT_CMD, 1228 WMI_TAG_RTT_MEASREQ_HEAD, 1229 WMI_TAG_RTT_MEASREQ_BODY, 1230 WMI_TAG_RTT_TSF_CMD, 1231 WMI_TAG_VDEV_SPECTRAL_CONFIGURE_CMD, 1232 WMI_TAG_VDEV_SPECTRAL_ENABLE_CMD, 1233 WMI_TAG_REQUEST_STATS_CMD, 1234 WMI_TAG_NLO_CONFIG_CMD, 1235 WMI_TAG_NLO_CONFIGURED_PARAMETERS, 1236 WMI_TAG_CSA_OFFLOAD_ENABLE_CMD, 1237 WMI_TAG_CSA_OFFLOAD_CHANSWITCH_CMD, 1238 WMI_TAG_CHATTER_SET_MODE_CMD, 1239 WMI_TAG_ECHO_CMD, 1240 WMI_TAG_VDEV_SET_KEEPALIVE_CMD, 1241 WMI_TAG_VDEV_GET_KEEPALIVE_CMD, 1242 WMI_TAG_FORCE_FW_HANG_CMD, 1243 WMI_TAG_GPIO_CONFIG_CMD, 1244 WMI_TAG_GPIO_OUTPUT_CMD, 1245 WMI_TAG_PEER_ADD_WDS_ENTRY_CMD, 1246 WMI_TAG_PEER_REMOVE_WDS_ENTRY_CMD, 1247 WMI_TAG_BCN_TX_HDR, 1248 WMI_TAG_BCN_SEND_FROM_HOST_CMD, 1249 WMI_TAG_MGMT_TX_HDR, 1250 WMI_TAG_ADDBA_CLEAR_RESP_CMD, 1251 WMI_TAG_ADDBA_SEND_CMD, 1252 WMI_TAG_DELBA_SEND_CMD, 1253 WMI_TAG_ADDBA_SETRESPONSE_CMD, 1254 WMI_TAG_SEND_SINGLEAMSDU_CMD, 1255 WMI_TAG_PDEV_PKTLOG_ENABLE_CMD, 1256 WMI_TAG_PDEV_PKTLOG_DISABLE_CMD, 1257 WMI_TAG_PDEV_SET_HT_IE_CMD, 1258 WMI_TAG_PDEV_SET_VHT_IE_CMD, 1259 WMI_TAG_PDEV_SET_DSCP_TID_MAP_CMD, 1260 WMI_TAG_PDEV_GREEN_AP_PS_ENABLE_CMD, 1261 WMI_TAG_PDEV_GET_TPC_CONFIG_CMD, 1262 WMI_TAG_PDEV_SET_BASE_MACADDR_CMD, 1263 WMI_TAG_PEER_MCAST_GROUP_CMD, 1264 WMI_TAG_ROAM_AP_PROFILE, 1265 WMI_TAG_AP_PROFILE, 1266 WMI_TAG_SCAN_SCH_PRIORITY_TABLE_CMD, 1267 WMI_TAG_PDEV_DFS_ENABLE_CMD, 1268 WMI_TAG_PDEV_DFS_DISABLE_CMD, 1269 WMI_TAG_WOW_ADD_PATTERN_CMD, 1270 WMI_TAG_WOW_BITMAP_PATTERN_T, 1271 WMI_TAG_WOW_IPV4_SYNC_PATTERN_T, 1272 WMI_TAG_WOW_IPV6_SYNC_PATTERN_T, 1273 WMI_TAG_WOW_MAGIC_PATTERN_CMD, 1274 WMI_TAG_SCAN_UPDATE_REQUEST_CMD, 1275 WMI_TAG_CHATTER_PKT_COALESCING_FILTER, 1276 WMI_TAG_CHATTER_COALESCING_ADD_FILTER_CMD, 1277 WMI_TAG_CHATTER_COALESCING_DELETE_FILTER_CMD, 1278 WMI_TAG_CHATTER_COALESCING_QUERY_CMD, 1279 WMI_TAG_TXBF_CMD, 1280 WMI_TAG_DEBUG_LOG_CONFIG_CMD, 1281 WMI_TAG_NLO_EVENT, 1282 WMI_TAG_CHATTER_QUERY_REPLY_EVENT, 1283 WMI_TAG_UPLOAD_H_HDR, 1284 WMI_TAG_CAPTURE_H_EVENT_HDR, 1285 WMI_TAG_VDEV_WNM_SLEEPMODE_CMD, 1286 WMI_TAG_VDEV_IPSEC_NATKEEPALIVE_FILTER_CMD, 1287 WMI_TAG_VDEV_WMM_ADDTS_CMD, 1288 WMI_TAG_VDEV_WMM_DELTS_CMD, 1289 WMI_TAG_VDEV_SET_WMM_PARAMS_CMD, 1290 WMI_TAG_TDLS_SET_STATE_CMD, 1291 WMI_TAG_TDLS_PEER_UPDATE_CMD, 1292 WMI_TAG_TDLS_PEER_EVENT, 1293 WMI_TAG_TDLS_PEER_CAPABILITIES, 1294 WMI_TAG_VDEV_MCC_SET_TBTT_MODE_CMD, 1295 WMI_TAG_ROAM_CHAN_LIST, 1296 WMI_TAG_VDEV_MCC_BCN_INTVL_CHANGE_EVENT, 1297 WMI_TAG_RESMGR_ADAPTIVE_OCS_ENABLE_DISABLE_CMD, 1298 WMI_TAG_RESMGR_SET_CHAN_TIME_QUOTA_CMD, 1299 WMI_TAG_RESMGR_SET_CHAN_LATENCY_CMD, 1300 WMI_TAG_BA_REQ_SSN_CMD, 1301 WMI_TAG_BA_RSP_SSN_EVENT, 1302 WMI_TAG_STA_SMPS_FORCE_MODE_CMD, 1303 WMI_TAG_SET_MCASTBCAST_FILTER_CMD, 1304 WMI_TAG_P2P_SET_OPPPS_CMD, 1305 WMI_TAG_P2P_SET_NOA_CMD, 1306 WMI_TAG_BA_REQ_SSN_CMD_SUB_STRUCT_PARAM, 1307 WMI_TAG_BA_REQ_SSN_EVENT_SUB_STRUCT_PARAM, 1308 WMI_TAG_STA_SMPS_PARAM_CMD, 1309 WMI_TAG_VDEV_SET_GTX_PARAMS_CMD, 1310 WMI_TAG_MCC_SCHED_TRAFFIC_STATS_CMD, 1311 WMI_TAG_MCC_SCHED_STA_TRAFFIC_STATS, 1312 WMI_TAG_OFFLOAD_BCN_TX_STATUS_EVENT, 1313 WMI_TAG_P2P_NOA_EVENT, 1314 WMI_TAG_HB_SET_ENABLE_CMD, 1315 WMI_TAG_HB_SET_TCP_PARAMS_CMD, 1316 WMI_TAG_HB_SET_TCP_PKT_FILTER_CMD, 1317 WMI_TAG_HB_SET_UDP_PARAMS_CMD, 1318 WMI_TAG_HB_SET_UDP_PKT_FILTER_CMD, 1319 WMI_TAG_HB_IND_EVENT, 1320 WMI_TAG_TX_PAUSE_EVENT, 1321 WMI_TAG_RFKILL_EVENT, 1322 WMI_TAG_DFS_RADAR_EVENT, 1323 WMI_TAG_DFS_PHYERR_FILTER_ENA_CMD, 1324 WMI_TAG_DFS_PHYERR_FILTER_DIS_CMD, 1325 WMI_TAG_BATCH_SCAN_RESULT_SCAN_LIST, 1326 WMI_TAG_BATCH_SCAN_RESULT_NETWORK_INFO, 1327 WMI_TAG_BATCH_SCAN_ENABLE_CMD, 1328 WMI_TAG_BATCH_SCAN_DISABLE_CMD, 1329 WMI_TAG_BATCH_SCAN_TRIGGER_RESULT_CMD, 1330 WMI_TAG_BATCH_SCAN_ENABLED_EVENT, 1331 WMI_TAG_BATCH_SCAN_RESULT_EVENT, 1332 WMI_TAG_VDEV_PLMREQ_START_CMD, 1333 WMI_TAG_VDEV_PLMREQ_STOP_CMD, 1334 WMI_TAG_THERMAL_MGMT_CMD, 1335 WMI_TAG_THERMAL_MGMT_EVENT, 1336 WMI_TAG_PEER_INFO_REQ_CMD, 1337 WMI_TAG_PEER_INFO_EVENT, 1338 WMI_TAG_PEER_INFO, 1339 WMI_TAG_PEER_TX_FAIL_CNT_THR_EVENT, 1340 WMI_TAG_RMC_SET_MODE_CMD, 1341 WMI_TAG_RMC_SET_ACTION_PERIOD_CMD, 1342 WMI_TAG_RMC_CONFIG_CMD, 1343 WMI_TAG_MHF_OFFLOAD_SET_MODE_CMD, 1344 WMI_TAG_MHF_OFFLOAD_PLUMB_ROUTING_TABLE_CMD, 1345 WMI_TAG_ADD_PROACTIVE_ARP_RSP_PATTERN_CMD, 1346 WMI_TAG_DEL_PROACTIVE_ARP_RSP_PATTERN_CMD, 1347 WMI_TAG_NAN_CMD_PARAM, 1348 WMI_TAG_NAN_EVENT_HDR, 1349 WMI_TAG_PDEV_L1SS_TRACK_EVENT, 1350 WMI_TAG_DIAG_DATA_CONTAINER_EVENT, 1351 WMI_TAG_MODEM_POWER_STATE_CMD_PARAM, 1352 WMI_TAG_PEER_GET_ESTIMATED_LINKSPEED_CMD, 1353 WMI_TAG_PEER_ESTIMATED_LINKSPEED_EVENT, 1354 WMI_TAG_AGGR_STATE_TRIG_EVENT, 1355 WMI_TAG_MHF_OFFLOAD_ROUTING_TABLE_ENTRY, 1356 WMI_TAG_ROAM_SCAN_CMD, 1357 WMI_TAG_REQ_STATS_EXT_CMD, 1358 WMI_TAG_STATS_EXT_EVENT, 1359 WMI_TAG_OBSS_SCAN_ENABLE_CMD, 1360 WMI_TAG_OBSS_SCAN_DISABLE_CMD, 1361 WMI_TAG_OFFLOAD_PRB_RSP_TX_STATUS_EVENT, 1362 WMI_TAG_PDEV_SET_LED_CONFIG_CMD, 1363 WMI_TAG_HOST_AUTO_SHUTDOWN_CFG_CMD, 1364 WMI_TAG_HOST_AUTO_SHUTDOWN_EVENT, 1365 WMI_TAG_UPDATE_WHAL_MIB_STATS_EVENT, 1366 WMI_TAG_CHAN_AVOID_UPDATE_CMD_PARAM, 1367 WMI_TAG_WOW_IOAC_PKT_PATTERN_T, 1368 WMI_TAG_WOW_IOAC_TMR_PATTERN_T, 1369 WMI_TAG_WOW_IOAC_ADD_KEEPALIVE_CMD, 1370 WMI_TAG_WOW_IOAC_DEL_KEEPALIVE_CMD, 1371 WMI_TAG_WOW_IOAC_KEEPALIVE_T, 1372 WMI_TAG_WOW_IOAC_ADD_PATTERN_CMD, 1373 WMI_TAG_WOW_IOAC_DEL_PATTERN_CMD, 1374 WMI_TAG_START_LINK_STATS_CMD, 1375 WMI_TAG_CLEAR_LINK_STATS_CMD, 1376 WMI_TAG_REQUEST_LINK_STATS_CMD, 1377 WMI_TAG_IFACE_LINK_STATS_EVENT, 1378 WMI_TAG_RADIO_LINK_STATS_EVENT, 1379 WMI_TAG_PEER_STATS_EVENT, 1380 WMI_TAG_CHANNEL_STATS, 1381 WMI_TAG_RADIO_LINK_STATS, 1382 WMI_TAG_RATE_STATS, 1383 WMI_TAG_PEER_LINK_STATS, 1384 WMI_TAG_WMM_AC_STATS, 1385 WMI_TAG_IFACE_LINK_STATS, 1386 WMI_TAG_LPI_MGMT_SNOOPING_CONFIG_CMD, 1387 WMI_TAG_LPI_START_SCAN_CMD, 1388 WMI_TAG_LPI_STOP_SCAN_CMD, 1389 WMI_TAG_LPI_RESULT_EVENT, 1390 WMI_TAG_PEER_STATE_EVENT, 1391 WMI_TAG_EXTSCAN_BUCKET_CMD, 1392 WMI_TAG_EXTSCAN_BUCKET_CHANNEL_EVENT, 1393 WMI_TAG_EXTSCAN_START_CMD, 1394 WMI_TAG_EXTSCAN_STOP_CMD, 1395 WMI_TAG_EXTSCAN_CONFIGURE_WLAN_CHANGE_MONITOR_CMD, 1396 WMI_TAG_EXTSCAN_WLAN_CHANGE_BSSID_PARAM_CMD, 1397 WMI_TAG_EXTSCAN_CONFIGURE_HOTLIST_MONITOR_CMD, 1398 WMI_TAG_EXTSCAN_GET_CACHED_RESULTS_CMD, 1399 WMI_TAG_EXTSCAN_GET_WLAN_CHANGE_RESULTS_CMD, 1400 WMI_TAG_EXTSCAN_SET_CAPABILITIES_CMD, 1401 WMI_TAG_EXTSCAN_GET_CAPABILITIES_CMD, 1402 WMI_TAG_EXTSCAN_OPERATION_EVENT, 1403 WMI_TAG_EXTSCAN_START_STOP_EVENT, 1404 WMI_TAG_EXTSCAN_TABLE_USAGE_EVENT, 1405 WMI_TAG_EXTSCAN_WLAN_DESCRIPTOR_EVENT, 1406 WMI_TAG_EXTSCAN_RSSI_INFO_EVENT, 1407 WMI_TAG_EXTSCAN_CACHED_RESULTS_EVENT, 1408 WMI_TAG_EXTSCAN_WLAN_CHANGE_RESULTS_EVENT, 1409 WMI_TAG_EXTSCAN_WLAN_CHANGE_RESULT_BSSID_EVENT, 1410 WMI_TAG_EXTSCAN_HOTLIST_MATCH_EVENT, 1411 WMI_TAG_EXTSCAN_CAPABILITIES_EVENT, 1412 WMI_TAG_EXTSCAN_CACHE_CAPABILITIES_EVENT, 1413 WMI_TAG_EXTSCAN_WLAN_CHANGE_MONITOR_CAPABILITIES_EVENT, 1414 WMI_TAG_EXTSCAN_HOTLIST_MONITOR_CAPABILITIES_EVENT, 1415 WMI_TAG_D0_WOW_ENABLE_DISABLE_CMD, 1416 WMI_TAG_D0_WOW_DISABLE_ACK_EVENT, 1417 WMI_TAG_UNIT_TEST_CMD, 1418 WMI_TAG_ROAM_OFFLOAD_TLV_PARAM, 1419 WMI_TAG_ROAM_11I_OFFLOAD_TLV_PARAM, 1420 WMI_TAG_ROAM_11R_OFFLOAD_TLV_PARAM, 1421 WMI_TAG_ROAM_ESE_OFFLOAD_TLV_PARAM, 1422 WMI_TAG_ROAM_SYNCH_EVENT, 1423 WMI_TAG_ROAM_SYNCH_COMPLETE, 1424 WMI_TAG_EXTWOW_ENABLE_CMD, 1425 WMI_TAG_EXTWOW_SET_APP_TYPE1_PARAMS_CMD, 1426 WMI_TAG_EXTWOW_SET_APP_TYPE2_PARAMS_CMD, 1427 WMI_TAG_LPI_STATUS_EVENT, 1428 WMI_TAG_LPI_HANDOFF_EVENT, 1429 WMI_TAG_VDEV_RATE_STATS_EVENT, 1430 WMI_TAG_VDEV_RATE_HT_INFO, 1431 WMI_TAG_RIC_REQUEST, 1432 WMI_TAG_PDEV_GET_TEMPERATURE_CMD, 1433 WMI_TAG_PDEV_TEMPERATURE_EVENT, 1434 WMI_TAG_SET_DHCP_SERVER_OFFLOAD_CMD, 1435 WMI_TAG_TPC_CHAINMASK_CONFIG_CMD, 1436 WMI_TAG_RIC_TSPEC, 1437 WMI_TAG_TPC_CHAINMASK_CONFIG, 1438 WMI_TAG_IPA_OFFLOAD_ENABLE_DISABLE_CMD, 1439 WMI_TAG_SCAN_PROB_REQ_OUI_CMD, 1440 WMI_TAG_KEY_MATERIAL, 1441 WMI_TAG_TDLS_SET_OFFCHAN_MODE_CMD, 1442 WMI_TAG_SET_LED_FLASHING_CMD, 1443 WMI_TAG_MDNS_OFFLOAD_CMD, 1444 WMI_TAG_MDNS_SET_FQDN_CMD, 1445 WMI_TAG_MDNS_SET_RESP_CMD, 1446 WMI_TAG_MDNS_GET_STATS_CMD, 1447 WMI_TAG_MDNS_STATS_EVENT, 1448 WMI_TAG_ROAM_INVOKE_CMD, 1449 WMI_TAG_PDEV_RESUME_EVENT, 1450 WMI_TAG_PDEV_SET_ANTENNA_DIVERSITY_CMD, 1451 WMI_TAG_SAP_OFL_ENABLE_CMD, 1452 WMI_TAG_SAP_OFL_ADD_STA_EVENT, 1453 WMI_TAG_SAP_OFL_DEL_STA_EVENT, 1454 WMI_TAG_APFIND_CMD_PARAM, 1455 WMI_TAG_APFIND_EVENT_HDR, 1456 WMI_TAG_OCB_SET_SCHED_CMD, 1457 WMI_TAG_OCB_SET_SCHED_EVENT, 1458 WMI_TAG_OCB_SET_CONFIG_CMD, 1459 WMI_TAG_OCB_SET_CONFIG_RESP_EVENT, 1460 WMI_TAG_OCB_SET_UTC_TIME_CMD, 1461 WMI_TAG_OCB_START_TIMING_ADVERT_CMD, 1462 WMI_TAG_OCB_STOP_TIMING_ADVERT_CMD, 1463 WMI_TAG_OCB_GET_TSF_TIMER_CMD, 1464 WMI_TAG_OCB_GET_TSF_TIMER_RESP_EVENT, 1465 WMI_TAG_DCC_GET_STATS_CMD, 1466 WMI_TAG_DCC_CHANNEL_STATS_REQUEST, 1467 WMI_TAG_DCC_GET_STATS_RESP_EVENT, 1468 WMI_TAG_DCC_CLEAR_STATS_CMD, 1469 WMI_TAG_DCC_UPDATE_NDL_CMD, 1470 WMI_TAG_DCC_UPDATE_NDL_RESP_EVENT, 1471 WMI_TAG_DCC_STATS_EVENT, 1472 WMI_TAG_OCB_CHANNEL, 1473 WMI_TAG_OCB_SCHEDULE_ELEMENT, 1474 WMI_TAG_DCC_NDL_STATS_PER_CHANNEL, 1475 WMI_TAG_DCC_NDL_CHAN, 1476 WMI_TAG_QOS_PARAMETER, 1477 WMI_TAG_DCC_NDL_ACTIVE_STATE_CONFIG, 1478 WMI_TAG_ROAM_SCAN_EXTENDED_THRESHOLD_PARAM, 1479 WMI_TAG_ROAM_FILTER, 1480 WMI_TAG_PASSPOINT_CONFIG_CMD, 1481 WMI_TAG_PASSPOINT_EVENT_HDR, 1482 WMI_TAG_EXTSCAN_CONFIGURE_HOTLIST_SSID_MONITOR_CMD, 1483 WMI_TAG_EXTSCAN_HOTLIST_SSID_MATCH_EVENT, 1484 WMI_TAG_VDEV_TSF_TSTAMP_ACTION_CMD, 1485 WMI_TAG_VDEV_TSF_REPORT_EVENT, 1486 WMI_TAG_GET_FW_MEM_DUMP, 1487 WMI_TAG_UPDATE_FW_MEM_DUMP, 1488 WMI_TAG_FW_MEM_DUMP_PARAMS, 1489 WMI_TAG_DEBUG_MESG_FLUSH, 1490 WMI_TAG_DEBUG_MESG_FLUSH_COMPLETE, 1491 WMI_TAG_PEER_SET_RATE_REPORT_CONDITION, 1492 WMI_TAG_ROAM_SUBNET_CHANGE_CONFIG, 1493 WMI_TAG_VDEV_SET_IE_CMD, 1494 WMI_TAG_RSSI_BREACH_MONITOR_CONFIG, 1495 WMI_TAG_RSSI_BREACH_EVENT, 1496 WMI_TAG_WOW_EVENT_INITIAL_WAKEUP, 1497 WMI_TAG_SOC_SET_PCL_CMD, 1498 WMI_TAG_SOC_SET_HW_MODE_CMD, 1499 WMI_TAG_SOC_SET_HW_MODE_RESPONSE_EVENT, 1500 WMI_TAG_SOC_HW_MODE_TRANSITION_EVENT, 1501 WMI_TAG_VDEV_TXRX_STREAMS, 1502 WMI_TAG_SOC_SET_HW_MODE_RESPONSE_VDEV_MAC_ENTRY, 1503 WMI_TAG_SOC_SET_DUAL_MAC_CONFIG_CMD, 1504 WMI_TAG_SOC_SET_DUAL_MAC_CONFIG_RESPONSE_EVENT, 1505 WMI_TAG_WOW_IOAC_SOCK_PATTERN_T, 1506 WMI_TAG_WOW_ENABLE_ICMPV6_NA_FLT_CMD, 1507 WMI_TAG_DIAG_EVENT_LOG_CONFIG, 1508 WMI_TAG_DIAG_EVENT_LOG_SUPPORTED_EVENT_FIXED_PARAMS, 1509 WMI_TAG_PACKET_FILTER_CONFIG, 1510 WMI_TAG_PACKET_FILTER_ENABLE, 1511 WMI_TAG_SAP_SET_BLACKLIST_PARAM_CMD, 1512 WMI_TAG_MGMT_TX_SEND_CMD, 1513 WMI_TAG_MGMT_TX_COMPL_EVENT, 1514 WMI_TAG_SOC_SET_ANTENNA_MODE_CMD, 1515 WMI_TAG_WOW_UDP_SVC_OFLD_CMD, 1516 WMI_TAG_LRO_INFO_CMD, 1517 WMI_TAG_ROAM_EARLYSTOP_RSSI_THRES_PARAM, 1518 WMI_TAG_SERVICE_READY_EXT_EVENT, 1519 WMI_TAG_MAWC_SENSOR_REPORT_IND_CMD, 1520 WMI_TAG_MAWC_ENABLE_SENSOR_EVENT, 1521 WMI_TAG_ROAM_CONFIGURE_MAWC_CMD, 1522 WMI_TAG_NLO_CONFIGURE_MAWC_CMD, 1523 WMI_TAG_EXTSCAN_CONFIGURE_MAWC_CMD, 1524 WMI_TAG_PEER_ASSOC_CONF_EVENT, 1525 WMI_TAG_WOW_HOSTWAKEUP_GPIO_PIN_PATTERN_CONFIG_CMD, 1526 WMI_TAG_AP_PS_EGAP_PARAM_CMD, 1527 WMI_TAG_AP_PS_EGAP_INFO_EVENT, 1528 WMI_TAG_PMF_OFFLOAD_SET_SA_QUERY_CMD, 1529 WMI_TAG_TRANSFER_DATA_TO_FLASH_CMD, 1530 WMI_TAG_TRANSFER_DATA_TO_FLASH_COMPLETE_EVENT, 1531 WMI_TAG_SCPC_EVENT, 1532 WMI_TAG_AP_PS_EGAP_INFO_CHAINMASK_LIST, 1533 WMI_TAG_STA_SMPS_FORCE_MODE_COMPLETE_EVENT, 1534 WMI_TAG_BPF_GET_CAPABILITY_CMD, 1535 WMI_TAG_BPF_CAPABILITY_INFO_EVT, 1536 WMI_TAG_BPF_GET_VDEV_STATS_CMD, 1537 WMI_TAG_BPF_VDEV_STATS_INFO_EVT, 1538 WMI_TAG_BPF_SET_VDEV_INSTRUCTIONS_CMD, 1539 WMI_TAG_BPF_DEL_VDEV_INSTRUCTIONS_CMD, 1540 WMI_TAG_VDEV_DELETE_RESP_EVENT, 1541 WMI_TAG_PEER_DELETE_RESP_EVENT, 1542 WMI_TAG_ROAM_DENSE_THRES_PARAM, 1543 WMI_TAG_ENLO_CANDIDATE_SCORE_PARAM, 1544 WMI_TAG_PEER_UPDATE_WDS_ENTRY_CMD, 1545 WMI_TAG_VDEV_CONFIG_RATEMASK, 1546 WMI_TAG_PDEV_FIPS_CMD, 1547 WMI_TAG_PDEV_SMART_ANT_ENABLE_CMD, 1548 WMI_TAG_PDEV_SMART_ANT_SET_RX_ANTENNA_CMD, 1549 WMI_TAG_PEER_SMART_ANT_SET_TX_ANTENNA_CMD, 1550 WMI_TAG_PEER_SMART_ANT_SET_TRAIN_ANTENNA_CMD, 1551 WMI_TAG_PEER_SMART_ANT_SET_NODE_CONFIG_OPS_CMD, 1552 WMI_TAG_PDEV_SET_ANT_SWITCH_TBL_CMD, 1553 WMI_TAG_PDEV_SET_CTL_TABLE_CMD, 1554 WMI_TAG_PDEV_SET_MIMOGAIN_TABLE_CMD, 1555 WMI_TAG_FWTEST_SET_PARAM_CMD, 1556 WMI_TAG_PEER_ATF_REQUEST, 1557 WMI_TAG_VDEV_ATF_REQUEST, 1558 WMI_TAG_PDEV_GET_ANI_CCK_CONFIG_CMD, 1559 WMI_TAG_PDEV_GET_ANI_OFDM_CONFIG_CMD, 1560 WMI_TAG_INST_RSSI_STATS_RESP, 1561 WMI_TAG_MED_UTIL_REPORT_EVENT, 1562 WMI_TAG_PEER_STA_PS_STATECHANGE_EVENT, 1563 WMI_TAG_WDS_ADDR_EVENT, 1564 WMI_TAG_PEER_RATECODE_LIST_EVENT, 1565 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_EVENT, 1566 WMI_TAG_PDEV_TPC_EVENT, 1567 WMI_TAG_ANI_OFDM_EVENT, 1568 WMI_TAG_ANI_CCK_EVENT, 1569 WMI_TAG_PDEV_CHANNEL_HOPPING_EVENT, 1570 WMI_TAG_PDEV_FIPS_EVENT, 1571 WMI_TAG_ATF_PEER_INFO, 1572 WMI_TAG_PDEV_GET_TPC_CMD, 1573 WMI_TAG_VDEV_FILTER_NRP_CONFIG_CMD, 1574 WMI_TAG_QBOOST_CFG_CMD, 1575 WMI_TAG_PDEV_SMART_ANT_GPIO_HANDLE, 1576 WMI_TAG_PEER_SMART_ANT_SET_TX_ANTENNA_SERIES, 1577 WMI_TAG_PEER_SMART_ANT_SET_TRAIN_ANTENNA_PARAM, 1578 WMI_TAG_PDEV_SET_ANT_CTRL_CHAIN, 1579 WMI_TAG_PEER_CCK_OFDM_RATE_INFO, 1580 WMI_TAG_PEER_MCS_RATE_INFO, 1581 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_NFDBR, 1582 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_NFDBM, 1583 WMI_TAG_PDEV_NFCAL_POWER_ALL_CHANNELS_FREQNUM, 1584 WMI_TAG_MU_REPORT_TOTAL_MU, 1585 WMI_TAG_VDEV_SET_DSCP_TID_MAP_CMD, 1586 WMI_TAG_ROAM_SET_MBO, 1587 WMI_TAG_MIB_STATS_ENABLE_CMD, 1588 WMI_TAG_NAN_DISC_IFACE_CREATED_EVENT, 1589 WMI_TAG_NAN_DISC_IFACE_DELETED_EVENT, 1590 WMI_TAG_NAN_STARTED_CLUSTER_EVENT, 1591 WMI_TAG_NAN_JOINED_CLUSTER_EVENT, 1592 WMI_TAG_NDI_GET_CAP_REQ, 1593 WMI_TAG_NDP_INITIATOR_REQ, 1594 WMI_TAG_NDP_RESPONDER_REQ, 1595 WMI_TAG_NDP_END_REQ, 1596 WMI_TAG_NDI_CAP_RSP_EVENT, 1597 WMI_TAG_NDP_INITIATOR_RSP_EVENT, 1598 WMI_TAG_NDP_RESPONDER_RSP_EVENT, 1599 WMI_TAG_NDP_END_RSP_EVENT, 1600 WMI_TAG_NDP_INDICATION_EVENT, 1601 WMI_TAG_NDP_CONFIRM_EVENT, 1602 WMI_TAG_NDP_END_INDICATION_EVENT, 1603 WMI_TAG_VDEV_SET_QUIET_CMD, 1604 WMI_TAG_PDEV_SET_PCL_CMD, 1605 WMI_TAG_PDEV_SET_HW_MODE_CMD, 1606 WMI_TAG_PDEV_SET_MAC_CONFIG_CMD, 1607 WMI_TAG_PDEV_SET_ANTENNA_MODE_CMD, 1608 WMI_TAG_PDEV_SET_HW_MODE_RESPONSE_EVENT, 1609 WMI_TAG_PDEV_HW_MODE_TRANSITION_EVENT, 1610 WMI_TAG_PDEV_SET_HW_MODE_RESPONSE_VDEV_MAC_ENTRY, 1611 WMI_TAG_PDEV_SET_MAC_CONFIG_RESPONSE_EVENT, 1612 WMI_TAG_COEX_CONFIG_CMD, 1613 WMI_TAG_CONFIG_ENHANCED_MCAST_FILTER, 1614 WMI_TAG_CHAN_AVOID_RPT_ALLOW_CMD, 1615 WMI_TAG_SET_PERIODIC_CHANNEL_STATS_CONFIG, 1616 WMI_TAG_VDEV_SET_CUSTOM_AGGR_SIZE_CMD, 1617 WMI_TAG_PDEV_WAL_POWER_DEBUG_CMD, 1618 WMI_TAG_MAC_PHY_CAPABILITIES, 1619 WMI_TAG_HW_MODE_CAPABILITIES, 1620 WMI_TAG_SOC_MAC_PHY_HW_MODE_CAPS, 1621 WMI_TAG_HAL_REG_CAPABILITIES_EXT, 1622 WMI_TAG_SOC_HAL_REG_CAPABILITIES, 1623 WMI_TAG_VDEV_WISA_CMD, 1624 WMI_TAG_TX_POWER_LEVEL_STATS_EVT, 1625 WMI_TAG_SCAN_ADAPTIVE_DWELL_PARAMETERS_TLV, 1626 WMI_TAG_SCAN_ADAPTIVE_DWELL_CONFIG, 1627 WMI_TAG_WOW_SET_ACTION_WAKE_UP_CMD, 1628 WMI_TAG_NDP_END_RSP_PER_NDI, 1629 WMI_TAG_PEER_BWF_REQUEST, 1630 WMI_TAG_BWF_PEER_INFO, 1631 WMI_TAG_DBGLOG_TIME_STAMP_SYNC_CMD, 1632 WMI_TAG_RMC_SET_LEADER_CMD, 1633 WMI_TAG_RMC_MANUAL_LEADER_EVENT, 1634 WMI_TAG_PER_CHAIN_RSSI_STATS, 1635 WMI_TAG_RSSI_STATS, 1636 WMI_TAG_P2P_LO_START_CMD, 1637 WMI_TAG_P2P_LO_STOP_CMD, 1638 WMI_TAG_P2P_LO_STOPPED_EVENT, 1639 WMI_TAG_REORDER_QUEUE_SETUP_CMD, 1640 WMI_TAG_REORDER_QUEUE_REMOVE_CMD, 1641 WMI_TAG_SET_MULTIPLE_MCAST_FILTER_CMD, 1642 WMI_TAG_MGMT_TX_COMPL_BUNDLE_EVENT, 1643 WMI_TAG_READ_DATA_FROM_FLASH_CMD, 1644 WMI_TAG_READ_DATA_FROM_FLASH_EVENT, 1645 WMI_TAG_PDEV_SET_REORDER_TIMEOUT_VAL_CMD, 1646 WMI_TAG_PEER_SET_RX_BLOCKSIZE_CMD, 1647 WMI_TAG_PDEV_SET_WAKEUP_CONFIG_CMDID, 1648 WMI_TAG_TLV_BUF_LEN_PARAM, 1649 WMI_TAG_SERVICE_AVAILABLE_EVENT, 1650 WMI_TAG_PEER_ANTDIV_INFO_REQ_CMD, 1651 WMI_TAG_PEER_ANTDIV_INFO_EVENT, 1652 WMI_TAG_PEER_ANTDIV_INFO, 1653 WMI_TAG_PDEV_GET_ANTDIV_STATUS_CMD, 1654 WMI_TAG_PDEV_ANTDIV_STATUS_EVENT, 1655 WMI_TAG_MNT_FILTER_CMD, 1656 WMI_TAG_GET_CHIP_POWER_STATS_CMD, 1657 WMI_TAG_PDEV_CHIP_POWER_STATS_EVENT, 1658 WMI_TAG_COEX_GET_ANTENNA_ISOLATION_CMD, 1659 WMI_TAG_COEX_REPORT_ISOLATION_EVENT, 1660 WMI_TAG_CHAN_CCA_STATS, 1661 WMI_TAG_PEER_SIGNAL_STATS, 1662 WMI_TAG_TX_STATS, 1663 WMI_TAG_PEER_AC_TX_STATS, 1664 WMI_TAG_RX_STATS, 1665 WMI_TAG_PEER_AC_RX_STATS, 1666 WMI_TAG_REPORT_STATS_EVENT, 1667 WMI_TAG_CHAN_CCA_STATS_THRESH, 1668 WMI_TAG_PEER_SIGNAL_STATS_THRESH, 1669 WMI_TAG_TX_STATS_THRESH, 1670 WMI_TAG_RX_STATS_THRESH, 1671 WMI_TAG_PDEV_SET_STATS_THRESHOLD_CMD, 1672 WMI_TAG_REQUEST_WLAN_STATS_CMD, 1673 WMI_TAG_RX_AGGR_FAILURE_EVENT, 1674 WMI_TAG_RX_AGGR_FAILURE_INFO, 1675 WMI_TAG_VDEV_ENCRYPT_DECRYPT_DATA_REQ_CMD, 1676 WMI_TAG_VDEV_ENCRYPT_DECRYPT_DATA_RESP_EVENT, 1677 WMI_TAG_PDEV_BAND_TO_MAC, 1678 WMI_TAG_TBTT_OFFSET_INFO, 1679 WMI_TAG_TBTT_OFFSET_EXT_EVENT, 1680 WMI_TAG_SAR_LIMITS_CMD, 1681 WMI_TAG_SAR_LIMIT_CMD_ROW, 1682 WMI_TAG_PDEV_DFS_PHYERR_OFFLOAD_ENABLE_CMD, 1683 WMI_TAG_PDEV_DFS_PHYERR_OFFLOAD_DISABLE_CMD, 1684 WMI_TAG_VDEV_ADFS_CH_CFG_CMD, 1685 WMI_TAG_VDEV_ADFS_OCAC_ABORT_CMD, 1686 WMI_TAG_PDEV_DFS_RADAR_DETECTION_EVENT, 1687 WMI_TAG_VDEV_ADFS_OCAC_COMPLETE_EVENT, 1688 WMI_TAG_VDEV_DFS_CAC_COMPLETE_EVENT, 1689 WMI_TAG_VENDOR_OUI, 1690 WMI_TAG_REQUEST_RCPI_CMD, 1691 WMI_TAG_UPDATE_RCPI_EVENT, 1692 WMI_TAG_REQUEST_PEER_STATS_INFO_CMD, 1693 WMI_TAG_PEER_STATS_INFO, 1694 WMI_TAG_PEER_STATS_INFO_EVENT, 1695 WMI_TAG_PKGID_EVENT, 1696 WMI_TAG_CONNECTED_NLO_RSSI_PARAMS, 1697 WMI_TAG_SET_CURRENT_COUNTRY_CMD, 1698 WMI_TAG_REGULATORY_RULE_STRUCT, 1699 WMI_TAG_REG_CHAN_LIST_CC_EVENT, 1700 WMI_TAG_11D_SCAN_START_CMD, 1701 WMI_TAG_11D_SCAN_STOP_CMD, 1702 WMI_TAG_11D_NEW_COUNTRY_EVENT, 1703 WMI_TAG_REQUEST_RADIO_CHAN_STATS_CMD, 1704 WMI_TAG_RADIO_CHAN_STATS, 1705 WMI_TAG_RADIO_CHAN_STATS_EVENT, 1706 WMI_TAG_ROAM_PER_CONFIG, 1707 WMI_TAG_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_CMD, 1708 WMI_TAG_VDEV_ADD_MAC_ADDR_TO_RX_FILTER_STATUS_EVENT, 1709 WMI_TAG_BPF_SET_VDEV_ACTIVE_MODE_CMD, 1710 WMI_TAG_HW_DATA_FILTER_CMD, 1711 WMI_TAG_CONNECTED_NLO_BSS_BAND_RSSI_PREF, 1712 WMI_TAG_PEER_OPER_MODE_CHANGE_EVENT, 1713 WMI_TAG_CHIP_POWER_SAVE_FAILURE_DETECTED, 1714 WMI_TAG_PDEV_MULTIPLE_VDEV_RESTART_REQUEST_CMD, 1715 WMI_TAG_PDEV_CSA_SWITCH_COUNT_STATUS_EVENT, 1716 WMI_TAG_PDEV_UPDATE_PKT_ROUTING_CMD, 1717 WMI_TAG_PDEV_CHECK_CAL_VERSION_CMD, 1718 WMI_TAG_PDEV_CHECK_CAL_VERSION_EVENT, 1719 WMI_TAG_PDEV_SET_DIVERSITY_GAIN_CMD, 1720 WMI_TAG_MAC_PHY_CHAINMASK_COMBO, 1721 WMI_TAG_MAC_PHY_CHAINMASK_CAPABILITY, 1722 WMI_TAG_VDEV_SET_ARP_STATS_CMD, 1723 WMI_TAG_VDEV_GET_ARP_STATS_CMD, 1724 WMI_TAG_VDEV_GET_ARP_STATS_EVENT, 1725 WMI_TAG_IFACE_OFFLOAD_STATS, 1726 WMI_TAG_REQUEST_STATS_CMD_SUB_STRUCT_PARAM, 1727 WMI_TAG_RSSI_CTL_EXT, 1728 WMI_TAG_SINGLE_PHYERR_EXT_RX_HDR, 1729 WMI_TAG_COEX_BT_ACTIVITY_EVENT, 1730 WMI_TAG_VDEV_GET_TX_POWER_CMD, 1731 WMI_TAG_VDEV_TX_POWER_EVENT, 1732 WMI_TAG_OFFCHAN_DATA_TX_COMPL_EVENT, 1733 WMI_TAG_OFFCHAN_DATA_TX_SEND_CMD, 1734 WMI_TAG_TX_SEND_PARAMS, 1735 WMI_TAG_HE_RATE_SET, 1736 WMI_TAG_CONGESTION_STATS, 1737 WMI_TAG_SET_INIT_COUNTRY_CMD, 1738 WMI_TAG_SCAN_DBS_DUTY_CYCLE, 1739 WMI_TAG_SCAN_DBS_DUTY_CYCLE_PARAM_TLV, 1740 WMI_TAG_PDEV_DIV_GET_RSSI_ANTID, 1741 WMI_TAG_THERM_THROT_CONFIG_REQUEST, 1742 WMI_TAG_THERM_THROT_LEVEL_CONFIG_INFO, 1743 WMI_TAG_THERM_THROT_STATS_EVENT, 1744 WMI_TAG_THERM_THROT_LEVEL_STATS_INFO, 1745 WMI_TAG_PDEV_DIV_RSSI_ANTID_EVENT, 1746 WMI_TAG_OEM_DMA_RING_CAPABILITIES, 1747 WMI_TAG_OEM_DMA_RING_CFG_REQ, 1748 WMI_TAG_OEM_DMA_RING_CFG_RSP, 1749 WMI_TAG_OEM_INDIRECT_DATA, 1750 WMI_TAG_OEM_DMA_BUF_RELEASE, 1751 WMI_TAG_OEM_DMA_BUF_RELEASE_ENTRY, 1752 WMI_TAG_PDEV_BSS_CHAN_INFO_REQUEST, 1753 WMI_TAG_PDEV_BSS_CHAN_INFO_EVENT, 1754 WMI_TAG_ROAM_LCA_DISALLOW_CONFIG, 1755 WMI_TAG_VDEV_LIMIT_OFFCHAN_CMD, 1756 WMI_TAG_ROAM_RSSI_REJECTION_OCE_CONFIG, 1757 WMI_TAG_UNIT_TEST_EVENT, 1758 WMI_TAG_ROAM_FILS_OFFLOAD, 1759 WMI_TAG_PDEV_UPDATE_PMK_CACHE_CMD, 1760 WMI_TAG_PMK_CACHE, 1761 WMI_TAG_PDEV_UPDATE_FILS_HLP_PKT_CMD, 1762 WMI_TAG_ROAM_FILS_SYNCH, 1763 WMI_TAG_GTK_OFFLOAD_EXTENDED, 1764 WMI_TAG_ROAM_BG_SCAN_ROAMING, 1765 WMI_TAG_OIC_PING_OFFLOAD_PARAMS_CMD, 1766 WMI_TAG_OIC_PING_OFFLOAD_SET_ENABLE_CMD, 1767 WMI_TAG_OIC_PING_HANDOFF_EVENT, 1768 WMI_TAG_DHCP_LEASE_RENEW_OFFLOAD_CMD, 1769 WMI_TAG_DHCP_LEASE_RENEW_EVENT, 1770 WMI_TAG_BTM_CONFIG, 1771 WMI_TAG_DEBUG_MESG_FW_DATA_STALL, 1772 WMI_TAG_WLM_CONFIG_CMD, 1773 WMI_TAG_PDEV_UPDATE_CTLTABLE_REQUEST, 1774 WMI_TAG_PDEV_UPDATE_CTLTABLE_EVENT, 1775 WMI_TAG_ROAM_CND_SCORING_PARAM, 1776 WMI_TAG_PDEV_CONFIG_VENDOR_OUI_ACTION, 1777 WMI_TAG_VENDOR_OUI_EXT, 1778 WMI_TAG_ROAM_SYNCH_FRAME_EVENT, 1779 WMI_TAG_FD_SEND_FROM_HOST_CMD, 1780 WMI_TAG_ENABLE_FILS_CMD, 1781 WMI_TAG_HOST_SWFDA_EVENT, 1782 WMI_TAG_BCN_OFFLOAD_CTRL_CMD, 1783 WMI_TAG_PDEV_SET_AC_TX_QUEUE_OPTIMIZED_CMD, 1784 WMI_TAG_STATS_PERIOD, 1785 WMI_TAG_NDL_SCHEDULE_UPDATE, 1786 WMI_TAG_PEER_TID_MSDUQ_QDEPTH_THRESH_UPDATE_CMD, 1787 WMI_TAG_MSDUQ_QDEPTH_THRESH_UPDATE, 1788 WMI_TAG_PDEV_SET_RX_FILTER_PROMISCUOUS_CMD, 1789 WMI_TAG_SAR2_RESULT_EVENT, 1790 WMI_TAG_SAR_CAPABILITIES, 1791 WMI_TAG_SAP_OBSS_DETECTION_CFG_CMD, 1792 WMI_TAG_SAP_OBSS_DETECTION_INFO_EVT, 1793 WMI_TAG_DMA_RING_CAPABILITIES, 1794 WMI_TAG_DMA_RING_CFG_REQ, 1795 WMI_TAG_DMA_RING_CFG_RSP, 1796 WMI_TAG_DMA_BUF_RELEASE, 1797 WMI_TAG_DMA_BUF_RELEASE_ENTRY, 1798 WMI_TAG_SAR_GET_LIMITS_CMD, 1799 WMI_TAG_SAR_GET_LIMITS_EVENT, 1800 WMI_TAG_SAR_GET_LIMITS_EVENT_ROW, 1801 WMI_TAG_OFFLOAD_11K_REPORT, 1802 WMI_TAG_INVOKE_NEIGHBOR_REPORT, 1803 WMI_TAG_NEIGHBOR_REPORT_OFFLOAD, 1804 WMI_TAG_VDEV_SET_CONNECTIVITY_CHECK_STATS, 1805 WMI_TAG_VDEV_GET_CONNECTIVITY_CHECK_STATS, 1806 WMI_TAG_BPF_SET_VDEV_ENABLE_CMD, 1807 WMI_TAG_BPF_SET_VDEV_WORK_MEMORY_CMD, 1808 WMI_TAG_BPF_GET_VDEV_WORK_MEMORY_CMD, 1809 WMI_TAG_BPF_GET_VDEV_WORK_MEMORY_RESP_EVT, 1810 WMI_TAG_PDEV_GET_NFCAL_POWER, 1811 WMI_TAG_BSS_COLOR_CHANGE_ENABLE, 1812 WMI_TAG_OBSS_COLOR_COLLISION_DET_CONFIG, 1813 WMI_TAG_OBSS_COLOR_COLLISION_EVT, 1814 WMI_TAG_RUNTIME_DPD_RECAL_CMD, 1815 WMI_TAG_TWT_ENABLE_CMD, 1816 WMI_TAG_TWT_DISABLE_CMD, 1817 WMI_TAG_TWT_ADD_DIALOG_CMD, 1818 WMI_TAG_TWT_DEL_DIALOG_CMD, 1819 WMI_TAG_TWT_PAUSE_DIALOG_CMD, 1820 WMI_TAG_TWT_RESUME_DIALOG_CMD, 1821 WMI_TAG_TWT_ENABLE_COMPLETE_EVENT, 1822 WMI_TAG_TWT_DISABLE_COMPLETE_EVENT, 1823 WMI_TAG_TWT_ADD_DIALOG_COMPLETE_EVENT, 1824 WMI_TAG_TWT_DEL_DIALOG_COMPLETE_EVENT, 1825 WMI_TAG_TWT_PAUSE_DIALOG_COMPLETE_EVENT, 1826 WMI_TAG_TWT_RESUME_DIALOG_COMPLETE_EVENT, 1827 WMI_TAG_REQUEST_ROAM_SCAN_STATS_CMD, 1828 WMI_TAG_ROAM_SCAN_STATS_EVENT, 1829 WMI_TAG_PEER_TID_CONFIGURATIONS_CMD, 1830 WMI_TAG_VDEV_SET_CUSTOM_SW_RETRY_TH_CMD, 1831 WMI_TAG_GET_TPC_POWER_CMD, 1832 WMI_TAG_GET_TPC_POWER_EVENT, 1833 WMI_TAG_DMA_BUF_RELEASE_SPECTRAL_META_DATA, 1834 WMI_TAG_MOTION_DET_CONFIG_PARAMS_CMD, 1835 WMI_TAG_MOTION_DET_BASE_LINE_CONFIG_PARAMS_CMD, 1836 WMI_TAG_MOTION_DET_START_STOP_CMD, 1837 WMI_TAG_MOTION_DET_BASE_LINE_START_STOP_CMD, 1838 WMI_TAG_MOTION_DET_EVENT, 1839 WMI_TAG_MOTION_DET_BASE_LINE_EVENT, 1840 WMI_TAG_NDP_TRANSPORT_IP, 1841 WMI_TAG_OBSS_SPATIAL_REUSE_SET_CMD, 1842 WMI_TAG_ESP_ESTIMATE_EVENT, 1843 WMI_TAG_NAN_HOST_CONFIG, 1844 WMI_TAG_SPECTRAL_BIN_SCALING_PARAMS, 1845 WMI_TAG_PEER_CFR_CAPTURE_CMD, 1846 WMI_TAG_PEER_CHAN_WIDTH_SWITCH_CMD, 1847 WMI_TAG_CHAN_WIDTH_PEER_LIST, 1848 WMI_TAG_OBSS_SPATIAL_REUSE_SET_DEF_OBSS_THRESH_CMD, 1849 WMI_TAG_PDEV_HE_TB_ACTION_FRM_CMD, 1850 WMI_TAG_PEER_EXTD2_STATS, 1851 WMI_TAG_HPCS_PULSE_START_CMD, 1852 WMI_TAG_PDEV_CTL_FAILSAFE_CHECK_EVENT, 1853 WMI_TAG_VDEV_CHAINMASK_CONFIG_CMD, 1854 WMI_TAG_VDEV_BCN_OFFLOAD_QUIET_CONFIG_CMD, 1855 WMI_TAG_NAN_EVENT_INFO, 1856 WMI_TAG_NDP_CHANNEL_INFO, 1857 WMI_TAG_NDP_CMD, 1858 WMI_TAG_NDP_EVENT, 1859 WMI_TAG_PDEV_PEER_PKTLOG_FILTER_CMD = 0x301, 1860 WMI_TAG_PDEV_PEER_PKTLOG_FILTER_INFO, 1861 WMI_TAG_FILS_DISCOVERY_TMPL_CMD = 0x344, 1862 WMI_TAG_PDEV_SRG_BSS_COLOR_BITMAP_CMD = 0x37b, 1863 WMI_TAG_PDEV_SRG_PARTIAL_BSSID_BITMAP_CMD, 1864 WMI_TAG_PDEV_SRG_OBSS_COLOR_ENABLE_BITMAP_CMD = 0x381, 1865 WMI_TAG_PDEV_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD, 1866 WMI_TAG_PDEV_NON_SRG_OBSS_COLOR_ENABLE_BITMAP_CMD, 1867 WMI_TAG_PDEV_NON_SRG_OBSS_BSSID_ENABLE_BITMAP_CMD, 1868 WMI_TAG_PDEV_SET_BIOS_SAR_TABLE_CMD = 0x3D8, 1869 WMI_TAG_PDEV_SET_BIOS_GEO_TABLE_CMD, 1870 WMI_TAG_MAX 1871 }; 1872 1873 enum wmi_tlv_service { 1874 WMI_TLV_SERVICE_BEACON_OFFLOAD = 0, 1875 WMI_TLV_SERVICE_SCAN_OFFLOAD = 1, 1876 WMI_TLV_SERVICE_ROAM_SCAN_OFFLOAD = 2, 1877 WMI_TLV_SERVICE_BCN_MISS_OFFLOAD = 3, 1878 WMI_TLV_SERVICE_STA_PWRSAVE = 4, 1879 WMI_TLV_SERVICE_STA_ADVANCED_PWRSAVE = 5, 1880 WMI_TLV_SERVICE_AP_UAPSD = 6, 1881 WMI_TLV_SERVICE_AP_DFS = 7, 1882 WMI_TLV_SERVICE_11AC = 8, 1883 WMI_TLV_SERVICE_BLOCKACK = 9, 1884 WMI_TLV_SERVICE_PHYERR = 10, 1885 WMI_TLV_SERVICE_BCN_FILTER = 11, 1886 WMI_TLV_SERVICE_RTT = 12, 1887 WMI_TLV_SERVICE_WOW = 13, 1888 WMI_TLV_SERVICE_RATECTRL_CACHE = 14, 1889 WMI_TLV_SERVICE_IRAM_TIDS = 15, 1890 WMI_TLV_SERVICE_ARPNS_OFFLOAD = 16, 1891 WMI_TLV_SERVICE_NLO = 17, 1892 WMI_TLV_SERVICE_GTK_OFFLOAD = 18, 1893 WMI_TLV_SERVICE_SCAN_SCH = 19, 1894 WMI_TLV_SERVICE_CSA_OFFLOAD = 20, 1895 WMI_TLV_SERVICE_CHATTER = 21, 1896 WMI_TLV_SERVICE_COEX_FREQAVOID = 22, 1897 WMI_TLV_SERVICE_PACKET_POWER_SAVE = 23, 1898 WMI_TLV_SERVICE_FORCE_FW_HANG = 24, 1899 WMI_TLV_SERVICE_GPIO = 25, 1900 WMI_TLV_SERVICE_STA_DTIM_PS_MODULATED_DTIM = 26, 1901 WMI_STA_UAPSD_BASIC_AUTO_TRIG = 27, 1902 WMI_STA_UAPSD_VAR_AUTO_TRIG = 28, 1903 WMI_TLV_SERVICE_STA_KEEP_ALIVE = 29, 1904 WMI_TLV_SERVICE_TX_ENCAP = 30, 1905 WMI_TLV_SERVICE_AP_PS_DETECT_OUT_OF_SYNC = 31, 1906 WMI_TLV_SERVICE_EARLY_RX = 32, 1907 WMI_TLV_SERVICE_STA_SMPS = 33, 1908 WMI_TLV_SERVICE_FWTEST = 34, 1909 WMI_TLV_SERVICE_STA_WMMAC = 35, 1910 WMI_TLV_SERVICE_TDLS = 36, 1911 WMI_TLV_SERVICE_BURST = 37, 1912 WMI_TLV_SERVICE_MCC_BCN_INTERVAL_CHANGE = 38, 1913 WMI_TLV_SERVICE_ADAPTIVE_OCS = 39, 1914 WMI_TLV_SERVICE_BA_SSN_SUPPORT = 40, 1915 WMI_TLV_SERVICE_FILTER_IPSEC_NATKEEPALIVE = 41, 1916 WMI_TLV_SERVICE_WLAN_HB = 42, 1917 WMI_TLV_SERVICE_LTE_ANT_SHARE_SUPPORT = 43, 1918 WMI_TLV_SERVICE_BATCH_SCAN = 44, 1919 WMI_TLV_SERVICE_QPOWER = 45, 1920 WMI_TLV_SERVICE_PLMREQ = 46, 1921 WMI_TLV_SERVICE_THERMAL_MGMT = 47, 1922 WMI_TLV_SERVICE_RMC = 48, 1923 WMI_TLV_SERVICE_MHF_OFFLOAD = 49, 1924 WMI_TLV_SERVICE_COEX_SAR = 50, 1925 WMI_TLV_SERVICE_BCN_TXRATE_OVERRIDE = 51, 1926 WMI_TLV_SERVICE_NAN = 52, 1927 WMI_TLV_SERVICE_L1SS_STAT = 53, 1928 WMI_TLV_SERVICE_ESTIMATE_LINKSPEED = 54, 1929 WMI_TLV_SERVICE_OBSS_SCAN = 55, 1930 WMI_TLV_SERVICE_TDLS_OFFCHAN = 56, 1931 WMI_TLV_SERVICE_TDLS_UAPSD_BUFFER_STA = 57, 1932 WMI_TLV_SERVICE_TDLS_UAPSD_SLEEP_STA = 58, 1933 WMI_TLV_SERVICE_IBSS_PWRSAVE = 59, 1934 WMI_TLV_SERVICE_LPASS = 60, 1935 WMI_TLV_SERVICE_EXTSCAN = 61, 1936 WMI_TLV_SERVICE_D0WOW = 62, 1937 WMI_TLV_SERVICE_HSOFFLOAD = 63, 1938 WMI_TLV_SERVICE_ROAM_HO_OFFLOAD = 64, 1939 WMI_TLV_SERVICE_RX_FULL_REORDER = 65, 1940 WMI_TLV_SERVICE_DHCP_OFFLOAD = 66, 1941 WMI_TLV_SERVICE_STA_RX_IPA_OFFLOAD_SUPPORT = 67, 1942 WMI_TLV_SERVICE_MDNS_OFFLOAD = 68, 1943 WMI_TLV_SERVICE_SAP_AUTH_OFFLOAD = 69, 1944 WMI_TLV_SERVICE_DUAL_BAND_SIMULTANEOUS_SUPPORT = 70, 1945 WMI_TLV_SERVICE_OCB = 71, 1946 WMI_TLV_SERVICE_AP_ARPNS_OFFLOAD = 72, 1947 WMI_TLV_SERVICE_PER_BAND_CHAINMASK_SUPPORT = 73, 1948 WMI_TLV_SERVICE_PACKET_FILTER_OFFLOAD = 74, 1949 WMI_TLV_SERVICE_MGMT_TX_HTT = 75, 1950 WMI_TLV_SERVICE_MGMT_TX_WMI = 76, 1951 WMI_TLV_SERVICE_EXT_MSG = 77, 1952 WMI_TLV_SERVICE_MAWC = 78, 1953 WMI_TLV_SERVICE_PEER_ASSOC_CONF = 79, 1954 WMI_TLV_SERVICE_EGAP = 80, 1955 WMI_TLV_SERVICE_STA_PMF_OFFLOAD = 81, 1956 WMI_TLV_SERVICE_UNIFIED_WOW_CAPABILITY = 82, 1957 WMI_TLV_SERVICE_ENHANCED_PROXY_STA = 83, 1958 WMI_TLV_SERVICE_ATF = 84, 1959 WMI_TLV_SERVICE_COEX_GPIO = 85, 1960 WMI_TLV_SERVICE_AUX_SPECTRAL_INTF = 86, 1961 WMI_TLV_SERVICE_AUX_CHAN_LOAD_INTF = 87, 1962 WMI_TLV_SERVICE_BSS_CHANNEL_INFO_64 = 88, 1963 WMI_TLV_SERVICE_ENTERPRISE_MESH = 89, 1964 WMI_TLV_SERVICE_RESTRT_CHNL_SUPPORT = 90, 1965 WMI_TLV_SERVICE_BPF_OFFLOAD = 91, 1966 WMI_TLV_SERVICE_SYNC_DELETE_CMDS = 92, 1967 WMI_TLV_SERVICE_SMART_ANTENNA_SW_SUPPORT = 93, 1968 WMI_TLV_SERVICE_SMART_ANTENNA_HW_SUPPORT = 94, 1969 WMI_TLV_SERVICE_RATECTRL_LIMIT_MAX_MIN_RATES = 95, 1970 WMI_TLV_SERVICE_NAN_DATA = 96, 1971 WMI_TLV_SERVICE_NAN_RTT = 97, 1972 WMI_TLV_SERVICE_11AX = 98, 1973 WMI_TLV_SERVICE_DEPRECATED_REPLACE = 99, 1974 WMI_TLV_SERVICE_TDLS_CONN_TRACKER_IN_HOST_MODE = 100, 1975 WMI_TLV_SERVICE_ENHANCED_MCAST_FILTER = 101, 1976 WMI_TLV_SERVICE_PERIODIC_CHAN_STAT_SUPPORT = 102, 1977 WMI_TLV_SERVICE_MESH_11S = 103, 1978 WMI_TLV_SERVICE_HALF_RATE_QUARTER_RATE_SUPPORT = 104, 1979 WMI_TLV_SERVICE_VDEV_RX_FILTER = 105, 1980 WMI_TLV_SERVICE_P2P_LISTEN_OFFLOAD_SUPPORT = 106, 1981 WMI_TLV_SERVICE_MARK_FIRST_WAKEUP_PACKET = 107, 1982 WMI_TLV_SERVICE_MULTIPLE_MCAST_FILTER_SET = 108, 1983 WMI_TLV_SERVICE_HOST_MANAGED_RX_REORDER = 109, 1984 WMI_TLV_SERVICE_FLASH_RDWR_SUPPORT = 110, 1985 WMI_TLV_SERVICE_WLAN_STATS_REPORT = 111, 1986 WMI_TLV_SERVICE_TX_MSDU_ID_NEW_PARTITION_SUPPORT = 112, 1987 WMI_TLV_SERVICE_DFS_PHYERR_OFFLOAD = 113, 1988 WMI_TLV_SERVICE_RCPI_SUPPORT = 114, 1989 WMI_TLV_SERVICE_FW_MEM_DUMP_SUPPORT = 115, 1990 WMI_TLV_SERVICE_PEER_STATS_INFO = 116, 1991 WMI_TLV_SERVICE_REGULATORY_DB = 117, 1992 WMI_TLV_SERVICE_11D_OFFLOAD = 118, 1993 WMI_TLV_SERVICE_HW_DATA_FILTERING = 119, 1994 WMI_TLV_SERVICE_MULTIPLE_VDEV_RESTART = 120, 1995 WMI_TLV_SERVICE_PKT_ROUTING = 121, 1996 WMI_TLV_SERVICE_CHECK_CAL_VERSION = 122, 1997 WMI_TLV_SERVICE_OFFCHAN_TX_WMI = 123, 1998 WMI_TLV_SERVICE_8SS_TX_BFEE = 124, 1999 WMI_TLV_SERVICE_EXTENDED_NSS_SUPPORT = 125, 2000 WMI_TLV_SERVICE_ACK_TIMEOUT = 126, 2001 WMI_TLV_SERVICE_PDEV_BSS_CHANNEL_INFO_64 = 127, 2002 2003 /* The first 128 bits */ 2004 WMI_MAX_SERVICE = 128, 2005 2006 WMI_TLV_SERVICE_CHAN_LOAD_INFO = 128, 2007 WMI_TLV_SERVICE_TX_PPDU_INFO_STATS_SUPPORT = 129, 2008 WMI_TLV_SERVICE_VDEV_LIMIT_OFFCHAN_SUPPORT = 130, 2009 WMI_TLV_SERVICE_FILS_SUPPORT = 131, 2010 WMI_TLV_SERVICE_WLAN_OIC_PING_OFFLOAD = 132, 2011 WMI_TLV_SERVICE_WLAN_DHCP_RENEW = 133, 2012 WMI_TLV_SERVICE_MAWC_SUPPORT = 134, 2013 WMI_TLV_SERVICE_VDEV_LATENCY_CONFIG = 135, 2014 WMI_TLV_SERVICE_PDEV_UPDATE_CTLTABLE_SUPPORT = 136, 2015 WMI_TLV_SERVICE_PKTLOG_SUPPORT_OVER_HTT = 137, 2016 WMI_TLV_SERVICE_VDEV_MULTI_GROUP_KEY_SUPPORT = 138, 2017 WMI_TLV_SERVICE_SCAN_PHYMODE_SUPPORT = 139, 2018 WMI_TLV_SERVICE_THERM_THROT = 140, 2019 WMI_TLV_SERVICE_BCN_OFFLOAD_START_STOP_SUPPORT = 141, 2020 WMI_TLV_SERVICE_WOW_WAKEUP_BY_TIMER_PATTERN = 142, 2021 WMI_TLV_SERVICE_PEER_MAP_UNMAP_V2_SUPPORT = 143, 2022 WMI_TLV_SERVICE_OFFCHAN_DATA_TID_SUPPORT = 144, 2023 WMI_TLV_SERVICE_RX_PROMISC_ENABLE_SUPPORT = 145, 2024 WMI_TLV_SERVICE_SUPPORT_DIRECT_DMA = 146, 2025 WMI_TLV_SERVICE_AP_OBSS_DETECTION_OFFLOAD = 147, 2026 WMI_TLV_SERVICE_11K_NEIGHBOUR_REPORT_SUPPORT = 148, 2027 WMI_TLV_SERVICE_LISTEN_INTERVAL_OFFLOAD_SUPPORT = 149, 2028 WMI_TLV_SERVICE_BSS_COLOR_OFFLOAD = 150, 2029 WMI_TLV_SERVICE_RUNTIME_DPD_RECAL = 151, 2030 WMI_TLV_SERVICE_STA_TWT = 152, 2031 WMI_TLV_SERVICE_AP_TWT = 153, 2032 WMI_TLV_SERVICE_GMAC_OFFLOAD_SUPPORT = 154, 2033 WMI_TLV_SERVICE_SPOOF_MAC_SUPPORT = 155, 2034 WMI_TLV_SERVICE_PEER_TID_CONFIGS_SUPPORT = 156, 2035 WMI_TLV_SERVICE_VDEV_SWRETRY_PER_AC_CONFIG_SUPPORT = 157, 2036 WMI_TLV_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_SCC_SUPPORT = 158, 2037 WMI_TLV_SERVICE_DUAL_BEACON_ON_SINGLE_MAC_MCC_SUPPORT = 159, 2038 WMI_TLV_SERVICE_MOTION_DET = 160, 2039 WMI_TLV_SERVICE_INFRA_MBSSID = 161, 2040 WMI_TLV_SERVICE_OBSS_SPATIAL_REUSE = 162, 2041 WMI_TLV_SERVICE_VDEV_DIFFERENT_BEACON_INTERVAL_SUPPORT = 163, 2042 WMI_TLV_SERVICE_NAN_DBS_SUPPORT = 164, 2043 WMI_TLV_SERVICE_NDI_DBS_SUPPORT = 165, 2044 WMI_TLV_SERVICE_NAN_SAP_SUPPORT = 166, 2045 WMI_TLV_SERVICE_NDI_SAP_SUPPORT = 167, 2046 WMI_TLV_SERVICE_CFR_CAPTURE_SUPPORT = 168, 2047 WMI_TLV_SERVICE_CFR_CAPTURE_IND_MSG_TYPE_1 = 169, 2048 WMI_TLV_SERVICE_ESP_SUPPORT = 170, 2049 WMI_TLV_SERVICE_PEER_CHWIDTH_CHANGE = 171, 2050 WMI_TLV_SERVICE_WLAN_HPCS_PULSE = 172, 2051 WMI_TLV_SERVICE_PER_VDEV_CHAINMASK_CONFIG_SUPPORT = 173, 2052 WMI_TLV_SERVICE_TX_DATA_MGMT_ACK_RSSI = 174, 2053 WMI_TLV_SERVICE_NAN_DISABLE_SUPPORT = 175, 2054 WMI_TLV_SERVICE_HTT_H2T_NO_HTC_HDR_LEN_IN_MSG_LEN = 176, 2055 WMI_TLV_SERVICE_COEX_SUPPORT_UNEQUAL_ISOLATION = 177, 2056 WMI_TLV_SERVICE_HW_DB2DBM_CONVERSION_SUPPORT = 178, 2057 WMI_TLV_SERVICE_SUPPORT_EXTEND_ADDRESS = 179, 2058 WMI_TLV_SERVICE_BEACON_RECEPTION_STATS = 180, 2059 WMI_TLV_SERVICE_FETCH_TX_PN = 181, 2060 WMI_TLV_SERVICE_PEER_UNMAP_RESPONSE_SUPPORT = 182, 2061 WMI_TLV_SERVICE_TX_PER_PEER_AMPDU_SIZE = 183, 2062 WMI_TLV_SERVICE_BSS_COLOR_SWITCH_COUNT = 184, 2063 WMI_TLV_SERVICE_HTT_PEER_STATS_SUPPORT = 185, 2064 WMI_TLV_SERVICE_UL_RU26_ALLOWED = 186, 2065 WMI_TLV_SERVICE_GET_MWS_COEX_STATE = 187, 2066 WMI_TLV_SERVICE_GET_MWS_DPWB_STATE = 188, 2067 WMI_TLV_SERVICE_GET_MWS_TDM_STATE = 189, 2068 WMI_TLV_SERVICE_GET_MWS_IDRX_STATE = 190, 2069 WMI_TLV_SERVICE_GET_MWS_ANTENNA_SHARING_STATE = 191, 2070 WMI_TLV_SERVICE_ENHANCED_TPC_CONFIG_EVENT = 192, 2071 WMI_TLV_SERVICE_WLM_STATS_REQUEST = 193, 2072 WMI_TLV_SERVICE_EXT_PEER_TID_CONFIGS_SUPPORT = 194, 2073 WMI_TLV_SERVICE_WPA3_FT_SAE_SUPPORT = 195, 2074 WMI_TLV_SERVICE_WPA3_FT_SUITE_B_SUPPORT = 196, 2075 WMI_TLV_SERVICE_VOW_ENABLE = 197, 2076 WMI_TLV_SERVICE_CFR_CAPTURE_IND_EVT_TYPE_1 = 198, 2077 WMI_TLV_SERVICE_BROADCAST_TWT = 199, 2078 WMI_TLV_SERVICE_RAP_DETECTION_SUPPORT = 200, 2079 WMI_TLV_SERVICE_PS_TDCC = 201, 2080 WMI_TLV_SERVICE_THREE_WAY_COEX_CONFIG_LEGACY = 202, 2081 WMI_TLV_SERVICE_THREE_WAY_COEX_CONFIG_OVERRIDE = 203, 2082 WMI_TLV_SERVICE_TX_PWR_PER_PEER = 204, 2083 WMI_TLV_SERVICE_STA_PLUS_STA_SUPPORT = 205, 2084 WMI_TLV_SERVICE_WPA3_FT_FILS = 206, 2085 WMI_TLV_SERVICE_ADAPTIVE_11R_ROAM = 207, 2086 WMI_TLV_SERVICE_CHAN_RF_CHARACTERIZATION_INFO = 208, 2087 WMI_TLV_SERVICE_FW_IFACE_COMBINATION_SUPPORT = 209, 2088 WMI_TLV_SERVICE_TX_COMPL_TSF64 = 210, 2089 WMI_TLV_SERVICE_DSM_ROAM_FILTER = 211, 2090 WMI_TLV_SERVICE_PACKET_CAPTURE_SUPPORT = 212, 2091 WMI_TLV_SERVICE_PER_PEER_HTT_STATS_RESET = 213, 2092 WMI_TLV_SERVICE_FREQINFO_IN_METADATA = 219, 2093 WMI_TLV_SERVICE_EXT2_MSG = 220, 2094 WMI_TLV_SERVICE_PEER_POWER_SAVE_DURATION_SUPPORT = 246, 2095 WMI_TLV_SERVICE_SRG_SRP_SPATIAL_REUSE_SUPPORT = 249, 2096 2097 /* The second 128 bits */ 2098 WMI_MAX_EXT_SERVICE = 256, 2099 WMI_TLV_SERVICE_BIOS_SAR_SUPPORT = 326, 2100 2101 /* The third 128 bits */ 2102 WMI_MAX_EXT2_SERVICE = 384 2103 }; 2104 2105 enum { 2106 WMI_SMPS_FORCED_MODE_NONE = 0, 2107 WMI_SMPS_FORCED_MODE_DISABLED, 2108 WMI_SMPS_FORCED_MODE_STATIC, 2109 WMI_SMPS_FORCED_MODE_DYNAMIC 2110 }; 2111 2112 #define WMI_TPC_CHAINMASK_CONFIG_BAND_2G 0 2113 #define WMI_TPC_CHAINMASK_CONFIG_BAND_5G 1 2114 #define WMI_NUM_SUPPORTED_BAND_MAX 2 2115 2116 #define WMI_PEER_MIMO_PS_STATE 0x1 2117 #define WMI_PEER_AMPDU 0x2 2118 #define WMI_PEER_AUTHORIZE 0x3 2119 #define WMI_PEER_CHWIDTH 0x4 2120 #define WMI_PEER_NSS 0x5 2121 #define WMI_PEER_USE_4ADDR 0x6 2122 #define WMI_PEER_MEMBERSHIP 0x7 2123 #define WMI_PEER_USERPOS 0x8 2124 #define WMI_PEER_CRIT_PROTO_HINT_ENABLED 0x9 2125 #define WMI_PEER_TX_FAIL_CNT_THR 0xA 2126 #define WMI_PEER_SET_HW_RETRY_CTS2S 0xB 2127 #define WMI_PEER_IBSS_ATIM_WINDOW_LENGTH 0xC 2128 #define WMI_PEER_PHYMODE 0xD 2129 #define WMI_PEER_USE_FIXED_PWR 0xE 2130 #define WMI_PEER_PARAM_FIXED_RATE 0xF 2131 #define WMI_PEER_SET_MU_WHITELIST 0x10 2132 #define WMI_PEER_SET_MAX_TX_RATE 0x11 2133 #define WMI_PEER_SET_MIN_TX_RATE 0x12 2134 #define WMI_PEER_SET_DEFAULT_ROUTING 0x13 2135 2136 /* slot time long */ 2137 #define WMI_VDEV_SLOT_TIME_LONG 0x1 2138 /* slot time short */ 2139 #define WMI_VDEV_SLOT_TIME_SHORT 0x2 2140 /* preablbe long */ 2141 #define WMI_VDEV_PREAMBLE_LONG 0x1 2142 /* preablbe short */ 2143 #define WMI_VDEV_PREAMBLE_SHORT 0x2 2144 2145 enum wmi_peer_smps_state { 2146 WMI_PEER_SMPS_PS_NONE = 0x0, 2147 WMI_PEER_SMPS_STATIC = 0x1, 2148 WMI_PEER_SMPS_DYNAMIC = 0x2 2149 }; 2150 2151 enum wmi_peer_chwidth { 2152 WMI_PEER_CHWIDTH_20MHZ = 0, 2153 WMI_PEER_CHWIDTH_40MHZ = 1, 2154 WMI_PEER_CHWIDTH_80MHZ = 2, 2155 WMI_PEER_CHWIDTH_160MHZ = 3, 2156 }; 2157 2158 enum wmi_beacon_gen_mode { 2159 WMI_BEACON_STAGGERED_MODE = 0, 2160 WMI_BEACON_BURST_MODE = 1 2161 }; 2162 2163 enum wmi_direct_buffer_module { 2164 WMI_DIRECT_BUF_SPECTRAL = 0, 2165 WMI_DIRECT_BUF_CFR = 1, 2166 2167 /* keep it last */ 2168 WMI_DIRECT_BUF_MAX 2169 }; 2170 2171 /* enum wmi_nss_ratio - NSS ratio received from FW during service ready ext 2172 * event 2173 * WMI_NSS_RATIO_1BY2_NSS -Max nss of 160MHz is equals to half of the max nss 2174 * of 80MHz 2175 * WMI_NSS_RATIO_3BY4_NSS - Max nss of 160MHz is equals to 3/4 of the max nss 2176 * of 80MHz 2177 * WMI_NSS_RATIO_1_NSS - Max nss of 160MHz is equals to the max nss of 80MHz 2178 * WMI_NSS_RATIO_2_NSS - Max nss of 160MHz is equals to two times the max 2179 * nss of 80MHz 2180 */ 2181 2182 enum wmi_nss_ratio { 2183 WMI_NSS_RATIO_1BY2_NSS = 0x0, 2184 WMI_NSS_RATIO_3BY4_NSS = 0x1, 2185 WMI_NSS_RATIO_1_NSS = 0x2, 2186 WMI_NSS_RATIO_2_NSS = 0x3, 2187 }; 2188 2189 enum wmi_dtim_policy { 2190 WMI_DTIM_POLICY_IGNORE = 1, 2191 WMI_DTIM_POLICY_NORMAL = 2, 2192 WMI_DTIM_POLICY_STICK = 3, 2193 WMI_DTIM_POLICY_AUTO = 4, 2194 }; 2195 2196 struct wmi_host_pdev_band_to_mac { 2197 u32 pdev_id; 2198 u32 start_freq; 2199 u32 end_freq; 2200 }; 2201 2202 struct ath11k_ppe_threshold { 2203 u32 numss_m1; 2204 u32 ru_bit_mask; 2205 u32 ppet16_ppet8_ru3_ru0[PSOC_HOST_MAX_NUM_SS]; 2206 }; 2207 2208 struct ath11k_service_ext_param { 2209 u32 default_conc_scan_config_bits; 2210 u32 default_fw_config_bits; 2211 struct ath11k_ppe_threshold ppet; 2212 u32 he_cap_info; 2213 u32 mpdu_density; 2214 u32 max_bssid_rx_filters; 2215 u32 num_hw_modes; 2216 u32 num_phy; 2217 }; 2218 2219 struct ath11k_hw_mode_caps { 2220 u32 hw_mode_id; 2221 u32 phy_id_map; 2222 u32 hw_mode_config_type; 2223 }; 2224 2225 #define PSOC_HOST_MAX_PHY_SIZE (3) 2226 #define ATH11K_11B_SUPPORT BIT(0) 2227 #define ATH11K_11G_SUPPORT BIT(1) 2228 #define ATH11K_11A_SUPPORT BIT(2) 2229 #define ATH11K_11N_SUPPORT BIT(3) 2230 #define ATH11K_11AC_SUPPORT BIT(4) 2231 #define ATH11K_11AX_SUPPORT BIT(5) 2232 2233 struct ath11k_hal_reg_capabilities_ext { 2234 u32 phy_id; 2235 u32 eeprom_reg_domain; 2236 u32 eeprom_reg_domain_ext; 2237 u32 regcap1; 2238 u32 regcap2; 2239 u32 wireless_modes; 2240 u32 low_2ghz_chan; 2241 u32 high_2ghz_chan; 2242 u32 low_5ghz_chan; 2243 u32 high_5ghz_chan; 2244 }; 2245 2246 #define WMI_HOST_MAX_PDEV 3 2247 2248 struct wlan_host_mem_chunk { 2249 u32 tlv_header; 2250 u32 req_id; 2251 u32 ptr; 2252 u32 size; 2253 } __packed; 2254 2255 struct wmi_host_mem_chunk { 2256 void *vaddr; 2257 dma_addr_t paddr; 2258 u32 len; 2259 u32 req_id; 2260 }; 2261 2262 struct wmi_init_cmd_param { 2263 u32 tlv_header; 2264 struct target_resource_config *res_cfg; 2265 u8 num_mem_chunks; 2266 struct wmi_host_mem_chunk *mem_chunks; 2267 u32 hw_mode_id; 2268 u32 num_band_to_mac; 2269 struct wmi_host_pdev_band_to_mac band_to_mac[WMI_HOST_MAX_PDEV]; 2270 }; 2271 2272 struct wmi_pdev_band_to_mac { 2273 u32 tlv_header; 2274 u32 pdev_id; 2275 u32 start_freq; 2276 u32 end_freq; 2277 } __packed; 2278 2279 struct wmi_pdev_set_hw_mode_cmd_param { 2280 u32 tlv_header; 2281 u32 pdev_id; 2282 u32 hw_mode_index; 2283 u32 num_band_to_mac; 2284 } __packed; 2285 2286 struct wmi_ppe_threshold { 2287 u32 numss_m1; /** NSS - 1*/ 2288 union { 2289 u32 ru_count; 2290 u32 ru_mask; 2291 } __packed; 2292 u32 ppet16_ppet8_ru3_ru0[WMI_MAX_NUM_SS]; 2293 } __packed; 2294 2295 #define HW_BD_INFO_SIZE 5 2296 2297 struct wmi_abi_version { 2298 u32 abi_version_0; 2299 u32 abi_version_1; 2300 u32 abi_version_ns_0; 2301 u32 abi_version_ns_1; 2302 u32 abi_version_ns_2; 2303 u32 abi_version_ns_3; 2304 } __packed; 2305 2306 struct wmi_init_cmd { 2307 u32 tlv_header; 2308 struct wmi_abi_version host_abi_vers; 2309 u32 num_host_mem_chunks; 2310 } __packed; 2311 2312 #define WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64 BIT(5) 2313 2314 struct wmi_resource_config { 2315 u32 tlv_header; 2316 u32 num_vdevs; 2317 u32 num_peers; 2318 u32 num_offload_peers; 2319 u32 num_offload_reorder_buffs; 2320 u32 num_peer_keys; 2321 u32 num_tids; 2322 u32 ast_skid_limit; 2323 u32 tx_chain_mask; 2324 u32 rx_chain_mask; 2325 u32 rx_timeout_pri[4]; 2326 u32 rx_decap_mode; 2327 u32 scan_max_pending_req; 2328 u32 bmiss_offload_max_vdev; 2329 u32 roam_offload_max_vdev; 2330 u32 roam_offload_max_ap_profiles; 2331 u32 num_mcast_groups; 2332 u32 num_mcast_table_elems; 2333 u32 mcast2ucast_mode; 2334 u32 tx_dbg_log_size; 2335 u32 num_wds_entries; 2336 u32 dma_burst_size; 2337 u32 mac_aggr_delim; 2338 u32 rx_skip_defrag_timeout_dup_detection_check; 2339 u32 vow_config; 2340 u32 gtk_offload_max_vdev; 2341 u32 num_msdu_desc; 2342 u32 max_frag_entries; 2343 u32 num_tdls_vdevs; 2344 u32 num_tdls_conn_table_entries; 2345 u32 beacon_tx_offload_max_vdev; 2346 u32 num_multicast_filter_entries; 2347 u32 num_wow_filters; 2348 u32 num_keep_alive_pattern; 2349 u32 keep_alive_pattern_size; 2350 u32 max_tdls_concurrent_sleep_sta; 2351 u32 max_tdls_concurrent_buffer_sta; 2352 u32 wmi_send_separate; 2353 u32 num_ocb_vdevs; 2354 u32 num_ocb_channels; 2355 u32 num_ocb_schedules; 2356 u32 flag1; 2357 u32 smart_ant_cap; 2358 u32 bk_minfree; 2359 u32 be_minfree; 2360 u32 vi_minfree; 2361 u32 vo_minfree; 2362 u32 alloc_frag_desc_for_data_pkt; 2363 u32 num_ns_ext_tuples_cfg; 2364 u32 bpf_instruction_size; 2365 u32 max_bssid_rx_filters; 2366 u32 use_pdev_id; 2367 u32 max_num_dbs_scan_duty_cycle; 2368 u32 max_num_group_keys; 2369 u32 peer_map_unmap_v2_support; 2370 u32 sched_params; 2371 u32 twt_ap_pdev_count; 2372 u32 twt_ap_sta_count; 2373 } __packed; 2374 2375 struct wmi_service_ready_event { 2376 u32 fw_build_vers; 2377 struct wmi_abi_version fw_abi_vers; 2378 u32 phy_capability; 2379 u32 max_frag_entry; 2380 u32 num_rf_chains; 2381 u32 ht_cap_info; 2382 u32 vht_cap_info; 2383 u32 vht_supp_mcs; 2384 u32 hw_min_tx_power; 2385 u32 hw_max_tx_power; 2386 u32 sys_cap_info; 2387 u32 min_pkt_size_enable; 2388 u32 max_bcn_ie_size; 2389 u32 num_mem_reqs; 2390 u32 max_num_scan_channels; 2391 u32 hw_bd_id; 2392 u32 hw_bd_info[HW_BD_INFO_SIZE]; 2393 u32 max_supported_macs; 2394 u32 wmi_fw_sub_feat_caps; 2395 u32 num_dbs_hw_modes; 2396 /* txrx_chainmask 2397 * [7:0] - 2G band tx chain mask 2398 * [15:8] - 2G band rx chain mask 2399 * [23:16] - 5G band tx chain mask 2400 * [31:24] - 5G band rx chain mask 2401 */ 2402 u32 txrx_chainmask; 2403 u32 default_dbs_hw_mode_index; 2404 u32 num_msdu_desc; 2405 } __packed; 2406 2407 #define WMI_SERVICE_BM_SIZE ((WMI_MAX_SERVICE + sizeof(u32) - 1) / sizeof(u32)) 2408 2409 #define WMI_SERVICE_SEGMENT_BM_SIZE32 4 /* 4x u32 = 128 bits */ 2410 #define WMI_SERVICE_EXT_BM_SIZE (WMI_SERVICE_SEGMENT_BM_SIZE32 * sizeof(u32)) 2411 #define WMI_AVAIL_SERVICE_BITS_IN_SIZE32 32 2412 #define WMI_SERVICE_BITS_IN_SIZE32 4 2413 2414 struct wmi_service_ready_ext_event { 2415 u32 default_conc_scan_config_bits; 2416 u32 default_fw_config_bits; 2417 struct wmi_ppe_threshold ppet; 2418 u32 he_cap_info; 2419 u32 mpdu_density; 2420 u32 max_bssid_rx_filters; 2421 u32 fw_build_vers_ext; 2422 u32 max_nlo_ssids; 2423 u32 max_bssid_indicator; 2424 u32 he_cap_info_ext; 2425 } __packed; 2426 2427 struct wmi_soc_mac_phy_hw_mode_caps { 2428 u32 num_hw_modes; 2429 u32 num_chainmask_tables; 2430 } __packed; 2431 2432 struct wmi_hw_mode_capabilities { 2433 u32 tlv_header; 2434 u32 hw_mode_id; 2435 u32 phy_id_map; 2436 u32 hw_mode_config_type; 2437 } __packed; 2438 2439 #define WMI_MAX_HECAP_PHY_SIZE (3) 2440 #define WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS BIT(0) 2441 #define WMI_NSS_RATIO_ENABLE_DISABLE_GET(_val) \ 2442 FIELD_GET(WMI_NSS_RATIO_ENABLE_DISABLE_BITPOS, _val) 2443 #define WMI_NSS_RATIO_INFO_BITPOS GENMASK(4, 1) 2444 #define WMI_NSS_RATIO_INFO_GET(_val) \ 2445 FIELD_GET(WMI_NSS_RATIO_INFO_BITPOS, _val) 2446 2447 struct wmi_mac_phy_capabilities { 2448 u32 hw_mode_id; 2449 u32 pdev_id; 2450 u32 phy_id; 2451 u32 supported_flags; 2452 u32 supported_bands; 2453 u32 ampdu_density; 2454 u32 max_bw_supported_2g; 2455 u32 ht_cap_info_2g; 2456 u32 vht_cap_info_2g; 2457 u32 vht_supp_mcs_2g; 2458 u32 he_cap_info_2g; 2459 u32 he_supp_mcs_2g; 2460 u32 tx_chain_mask_2g; 2461 u32 rx_chain_mask_2g; 2462 u32 max_bw_supported_5g; 2463 u32 ht_cap_info_5g; 2464 u32 vht_cap_info_5g; 2465 u32 vht_supp_mcs_5g; 2466 u32 he_cap_info_5g; 2467 u32 he_supp_mcs_5g; 2468 u32 tx_chain_mask_5g; 2469 u32 rx_chain_mask_5g; 2470 u32 he_cap_phy_info_2g[WMI_MAX_HECAP_PHY_SIZE]; 2471 u32 he_cap_phy_info_5g[WMI_MAX_HECAP_PHY_SIZE]; 2472 struct wmi_ppe_threshold he_ppet2g; 2473 struct wmi_ppe_threshold he_ppet5g; 2474 u32 chainmask_table_id; 2475 u32 lmac_id; 2476 u32 he_cap_info_2g_ext; 2477 u32 he_cap_info_5g_ext; 2478 u32 he_cap_info_internal; 2479 u32 wireless_modes; 2480 u32 low_2ghz_chan_freq; 2481 u32 high_2ghz_chan_freq; 2482 u32 low_5ghz_chan_freq; 2483 u32 high_5ghz_chan_freq; 2484 u32 nss_ratio; 2485 } __packed; 2486 2487 struct wmi_hal_reg_capabilities_ext { 2488 u32 tlv_header; 2489 u32 phy_id; 2490 u32 eeprom_reg_domain; 2491 u32 eeprom_reg_domain_ext; 2492 u32 regcap1; 2493 u32 regcap2; 2494 u32 wireless_modes; 2495 u32 low_2ghz_chan; 2496 u32 high_2ghz_chan; 2497 u32 low_5ghz_chan; 2498 u32 high_5ghz_chan; 2499 } __packed; 2500 2501 struct wmi_soc_hal_reg_capabilities { 2502 u32 num_phy; 2503 } __packed; 2504 2505 /* 2 word representation of MAC addr */ 2506 struct wmi_mac_addr { 2507 union { 2508 u8 addr[6]; 2509 struct { 2510 u32 word0; 2511 u32 word1; 2512 } __packed; 2513 } __packed; 2514 } __packed; 2515 2516 struct wmi_dma_ring_capabilities { 2517 u32 tlv_header; 2518 u32 pdev_id; 2519 u32 module_id; 2520 u32 min_elem; 2521 u32 min_buf_sz; 2522 u32 min_buf_align; 2523 } __packed; 2524 2525 struct wmi_ready_event_min { 2526 struct wmi_abi_version fw_abi_vers; 2527 struct wmi_mac_addr mac_addr; 2528 u32 status; 2529 u32 num_dscp_table; 2530 u32 num_extra_mac_addr; 2531 u32 num_total_peers; 2532 u32 num_extra_peers; 2533 } __packed; 2534 2535 struct wmi_ready_event { 2536 struct wmi_ready_event_min ready_event_min; 2537 u32 max_ast_index; 2538 u32 pktlog_defs_checksum; 2539 } __packed; 2540 2541 struct wmi_service_available_event { 2542 u32 wmi_service_segment_offset; 2543 u32 wmi_service_segment_bitmap[WMI_SERVICE_SEGMENT_BM_SIZE32]; 2544 } __packed; 2545 2546 struct ath11k_pdev_wmi { 2547 struct ath11k_wmi_base *wmi_ab; 2548 enum ath11k_htc_ep_id eid; 2549 const struct wmi_peer_flags_map *peer_flags; 2550 u32 rx_decap_mode; 2551 wait_queue_head_t tx_ce_desc_wq; 2552 }; 2553 2554 struct vdev_create_params { 2555 u8 if_id; 2556 u32 type; 2557 u32 subtype; 2558 struct { 2559 u8 tx; 2560 u8 rx; 2561 } chains[NUM_NL80211_BANDS]; 2562 u32 pdev_id; 2563 }; 2564 2565 struct wmi_vdev_create_cmd { 2566 u32 tlv_header; 2567 u32 vdev_id; 2568 u32 vdev_type; 2569 u32 vdev_subtype; 2570 struct wmi_mac_addr vdev_macaddr; 2571 u32 num_cfg_txrx_streams; 2572 u32 pdev_id; 2573 } __packed; 2574 2575 struct wmi_vdev_txrx_streams { 2576 u32 tlv_header; 2577 u32 band; 2578 u32 supported_tx_streams; 2579 u32 supported_rx_streams; 2580 } __packed; 2581 2582 struct wmi_vdev_delete_cmd { 2583 u32 tlv_header; 2584 u32 vdev_id; 2585 } __packed; 2586 2587 struct wmi_vdev_up_cmd { 2588 u32 tlv_header; 2589 u32 vdev_id; 2590 u32 vdev_assoc_id; 2591 struct wmi_mac_addr vdev_bssid; 2592 struct wmi_mac_addr trans_bssid; 2593 u32 profile_idx; 2594 u32 profile_num; 2595 } __packed; 2596 2597 struct wmi_vdev_stop_cmd { 2598 u32 tlv_header; 2599 u32 vdev_id; 2600 } __packed; 2601 2602 struct wmi_vdev_down_cmd { 2603 u32 tlv_header; 2604 u32 vdev_id; 2605 } __packed; 2606 2607 #define WMI_VDEV_START_HIDDEN_SSID BIT(0) 2608 #define WMI_VDEV_START_PMF_ENABLED BIT(1) 2609 #define WMI_VDEV_START_LDPC_RX_ENABLED BIT(3) 2610 #define WMI_VDEV_START_HW_ENCRYPTION_DISABLED BIT(4) 2611 2612 struct wmi_ssid { 2613 u32 ssid_len; 2614 u32 ssid[8]; 2615 } __packed; 2616 2617 #define ATH11K_VDEV_SETUP_TIMEOUT_HZ (1 * HZ) 2618 2619 struct wmi_vdev_start_request_cmd { 2620 u32 tlv_header; 2621 u32 vdev_id; 2622 u32 requestor_id; 2623 u32 beacon_interval; 2624 u32 dtim_period; 2625 u32 flags; 2626 struct wmi_ssid ssid; 2627 u32 bcn_tx_rate; 2628 u32 bcn_txpower; 2629 u32 num_noa_descriptors; 2630 u32 disable_hw_ack; 2631 u32 preferred_tx_streams; 2632 u32 preferred_rx_streams; 2633 u32 he_ops; 2634 u32 cac_duration_ms; 2635 u32 regdomain; 2636 } __packed; 2637 2638 #define MGMT_TX_DL_FRM_LEN 64 2639 #define WMI_MAC_MAX_SSID_LENGTH 32 2640 struct mac_ssid { 2641 u8 length; 2642 u8 mac_ssid[WMI_MAC_MAX_SSID_LENGTH]; 2643 } __packed; 2644 2645 struct wmi_p2p_noa_descriptor { 2646 u32 type_count; 2647 u32 duration; 2648 u32 interval; 2649 u32 start_time; 2650 }; 2651 2652 struct channel_param { 2653 u8 chan_id; 2654 u8 pwr; 2655 u32 mhz; 2656 u32 half_rate:1, 2657 quarter_rate:1, 2658 dfs_set:1, 2659 dfs_set_cfreq2:1, 2660 is_chan_passive:1, 2661 allow_ht:1, 2662 allow_vht:1, 2663 allow_he:1, 2664 set_agile:1, 2665 psc_channel:1; 2666 u32 phy_mode; 2667 u32 cfreq1; 2668 u32 cfreq2; 2669 char maxpower; 2670 char minpower; 2671 char maxregpower; 2672 u8 antennamax; 2673 u8 reg_class_id; 2674 } __packed; 2675 2676 enum wmi_phy_mode { 2677 MODE_11A = 0, 2678 MODE_11G = 1, /* 11b/g Mode */ 2679 MODE_11B = 2, /* 11b Mode */ 2680 MODE_11GONLY = 3, /* 11g only Mode */ 2681 MODE_11NA_HT20 = 4, 2682 MODE_11NG_HT20 = 5, 2683 MODE_11NA_HT40 = 6, 2684 MODE_11NG_HT40 = 7, 2685 MODE_11AC_VHT20 = 8, 2686 MODE_11AC_VHT40 = 9, 2687 MODE_11AC_VHT80 = 10, 2688 MODE_11AC_VHT20_2G = 11, 2689 MODE_11AC_VHT40_2G = 12, 2690 MODE_11AC_VHT80_2G = 13, 2691 MODE_11AC_VHT80_80 = 14, 2692 MODE_11AC_VHT160 = 15, 2693 MODE_11AX_HE20 = 16, 2694 MODE_11AX_HE40 = 17, 2695 MODE_11AX_HE80 = 18, 2696 MODE_11AX_HE80_80 = 19, 2697 MODE_11AX_HE160 = 20, 2698 MODE_11AX_HE20_2G = 21, 2699 MODE_11AX_HE40_2G = 22, 2700 MODE_11AX_HE80_2G = 23, 2701 MODE_UNKNOWN = 24, 2702 MODE_MAX = 24 2703 }; 2704 2705 static inline const char *ath11k_wmi_phymode_str(enum wmi_phy_mode mode) 2706 { 2707 switch (mode) { 2708 case MODE_11A: 2709 return "11a"; 2710 case MODE_11G: 2711 return "11g"; 2712 case MODE_11B: 2713 return "11b"; 2714 case MODE_11GONLY: 2715 return "11gonly"; 2716 case MODE_11NA_HT20: 2717 return "11na-ht20"; 2718 case MODE_11NG_HT20: 2719 return "11ng-ht20"; 2720 case MODE_11NA_HT40: 2721 return "11na-ht40"; 2722 case MODE_11NG_HT40: 2723 return "11ng-ht40"; 2724 case MODE_11AC_VHT20: 2725 return "11ac-vht20"; 2726 case MODE_11AC_VHT40: 2727 return "11ac-vht40"; 2728 case MODE_11AC_VHT80: 2729 return "11ac-vht80"; 2730 case MODE_11AC_VHT160: 2731 return "11ac-vht160"; 2732 case MODE_11AC_VHT80_80: 2733 return "11ac-vht80+80"; 2734 case MODE_11AC_VHT20_2G: 2735 return "11ac-vht20-2g"; 2736 case MODE_11AC_VHT40_2G: 2737 return "11ac-vht40-2g"; 2738 case MODE_11AC_VHT80_2G: 2739 return "11ac-vht80-2g"; 2740 case MODE_11AX_HE20: 2741 return "11ax-he20"; 2742 case MODE_11AX_HE40: 2743 return "11ax-he40"; 2744 case MODE_11AX_HE80: 2745 return "11ax-he80"; 2746 case MODE_11AX_HE80_80: 2747 return "11ax-he80+80"; 2748 case MODE_11AX_HE160: 2749 return "11ax-he160"; 2750 case MODE_11AX_HE20_2G: 2751 return "11ax-he20-2g"; 2752 case MODE_11AX_HE40_2G: 2753 return "11ax-he40-2g"; 2754 case MODE_11AX_HE80_2G: 2755 return "11ax-he80-2g"; 2756 case MODE_UNKNOWN: 2757 /* skip */ 2758 break; 2759 2760 /* no default handler to allow compiler to check that the 2761 * enum is fully handled 2762 */ 2763 } 2764 2765 return "<unknown>"; 2766 } 2767 2768 struct wmi_channel_arg { 2769 u32 freq; 2770 u32 band_center_freq1; 2771 u32 band_center_freq2; 2772 bool passive; 2773 bool allow_ibss; 2774 bool allow_ht; 2775 bool allow_vht; 2776 bool ht40plus; 2777 bool chan_radar; 2778 bool freq2_radar; 2779 bool allow_he; 2780 u32 min_power; 2781 u32 max_power; 2782 u32 max_reg_power; 2783 u32 max_antenna_gain; 2784 enum wmi_phy_mode mode; 2785 }; 2786 2787 struct wmi_vdev_start_req_arg { 2788 u32 vdev_id; 2789 struct wmi_channel_arg channel; 2790 u32 bcn_intval; 2791 u32 dtim_period; 2792 u8 *ssid; 2793 u32 ssid_len; 2794 u32 bcn_tx_rate; 2795 u32 bcn_tx_power; 2796 bool disable_hw_ack; 2797 bool hidden_ssid; 2798 bool pmf_enabled; 2799 u32 he_ops; 2800 u32 cac_duration_ms; 2801 u32 regdomain; 2802 u32 pref_rx_streams; 2803 u32 pref_tx_streams; 2804 u32 num_noa_descriptors; 2805 }; 2806 2807 struct peer_create_params { 2808 const u8 *peer_addr; 2809 u32 peer_type; 2810 u32 vdev_id; 2811 }; 2812 2813 struct peer_delete_params { 2814 u8 vdev_id; 2815 }; 2816 2817 struct peer_flush_params { 2818 u32 peer_tid_bitmap; 2819 u8 vdev_id; 2820 }; 2821 2822 struct pdev_set_regdomain_params { 2823 u16 current_rd_in_use; 2824 u16 current_rd_2g; 2825 u16 current_rd_5g; 2826 u32 ctl_2g; 2827 u32 ctl_5g; 2828 u8 dfs_domain; 2829 u32 pdev_id; 2830 }; 2831 2832 struct rx_reorder_queue_remove_params { 2833 u8 *peer_macaddr; 2834 u16 vdev_id; 2835 u32 peer_tid_bitmap; 2836 }; 2837 2838 #define WMI_HOST_PDEV_ID_SOC 0xFF 2839 #define WMI_HOST_PDEV_ID_0 0 2840 #define WMI_HOST_PDEV_ID_1 1 2841 #define WMI_HOST_PDEV_ID_2 2 2842 2843 #define WMI_PDEV_ID_SOC 0 2844 #define WMI_PDEV_ID_1ST 1 2845 #define WMI_PDEV_ID_2ND 2 2846 #define WMI_PDEV_ID_3RD 3 2847 2848 /* Freq units in MHz */ 2849 #define REG_RULE_START_FREQ 0x0000ffff 2850 #define REG_RULE_END_FREQ 0xffff0000 2851 #define REG_RULE_FLAGS 0x0000ffff 2852 #define REG_RULE_MAX_BW 0x0000ffff 2853 #define REG_RULE_REG_PWR 0x00ff0000 2854 #define REG_RULE_ANT_GAIN 0xff000000 2855 2856 #define WMI_VDEV_PARAM_TXBF_SU_TX_BFEE BIT(0) 2857 #define WMI_VDEV_PARAM_TXBF_MU_TX_BFEE BIT(1) 2858 #define WMI_VDEV_PARAM_TXBF_SU_TX_BFER BIT(2) 2859 #define WMI_VDEV_PARAM_TXBF_MU_TX_BFER BIT(3) 2860 2861 #define HECAP_PHYDWORD_0 0 2862 #define HECAP_PHYDWORD_1 1 2863 #define HECAP_PHYDWORD_2 2 2864 2865 #define HECAP_PHY_SU_BFER BIT(31) 2866 #define HECAP_PHY_SU_BFEE BIT(0) 2867 #define HECAP_PHY_MU_BFER BIT(1) 2868 #define HECAP_PHY_UL_MUMIMO BIT(22) 2869 #define HECAP_PHY_UL_MUOFDMA BIT(23) 2870 2871 #define HECAP_PHY_SUBFMR_GET(hecap_phy) \ 2872 FIELD_GET(HECAP_PHY_SU_BFER, hecap_phy[HECAP_PHYDWORD_0]) 2873 2874 #define HECAP_PHY_SUBFME_GET(hecap_phy) \ 2875 FIELD_GET(HECAP_PHY_SU_BFEE, hecap_phy[HECAP_PHYDWORD_1]) 2876 2877 #define HECAP_PHY_MUBFMR_GET(hecap_phy) \ 2878 FIELD_GET(HECAP_PHY_MU_BFER, hecap_phy[HECAP_PHYDWORD_1]) 2879 2880 #define HECAP_PHY_ULMUMIMO_GET(hecap_phy) \ 2881 FIELD_GET(HECAP_PHY_UL_MUMIMO, hecap_phy[HECAP_PHYDWORD_0]) 2882 2883 #define HECAP_PHY_ULOFDMA_GET(hecap_phy) \ 2884 FIELD_GET(HECAP_PHY_UL_MUOFDMA, hecap_phy[HECAP_PHYDWORD_0]) 2885 2886 #define HE_MODE_SU_TX_BFEE BIT(0) 2887 #define HE_MODE_SU_TX_BFER BIT(1) 2888 #define HE_MODE_MU_TX_BFEE BIT(2) 2889 #define HE_MODE_MU_TX_BFER BIT(3) 2890 #define HE_MODE_DL_OFDMA BIT(4) 2891 #define HE_MODE_UL_OFDMA BIT(5) 2892 #define HE_MODE_UL_MUMIMO BIT(6) 2893 2894 #define HE_DL_MUOFDMA_ENABLE 1 2895 #define HE_UL_MUOFDMA_ENABLE 1 2896 #define HE_DL_MUMIMO_ENABLE 1 2897 #define HE_MU_BFEE_ENABLE 1 2898 #define HE_SU_BFEE_ENABLE 1 2899 2900 #define HE_VHT_SOUNDING_MODE_ENABLE 1 2901 #define HE_SU_MU_SOUNDING_MODE_ENABLE 1 2902 #define HE_TRIG_NONTRIG_SOUNDING_MODE_ENABLE 1 2903 2904 /* HE or VHT Sounding */ 2905 #define HE_VHT_SOUNDING_MODE BIT(0) 2906 /* SU or MU Sounding */ 2907 #define HE_SU_MU_SOUNDING_MODE BIT(2) 2908 /* Trig or Non-Trig Sounding */ 2909 #define HE_TRIG_NONTRIG_SOUNDING_MODE BIT(3) 2910 2911 #define WMI_TXBF_STS_CAP_OFFSET_LSB 4 2912 #define WMI_TXBF_STS_CAP_OFFSET_MASK 0x70 2913 #define WMI_BF_SOUND_DIM_OFFSET_LSB 8 2914 #define WMI_BF_SOUND_DIM_OFFSET_MASK 0x700 2915 2916 struct pdev_params { 2917 u32 param_id; 2918 u32 param_value; 2919 }; 2920 2921 enum wmi_peer_type { 2922 WMI_PEER_TYPE_DEFAULT = 0, 2923 WMI_PEER_TYPE_BSS = 1, 2924 WMI_PEER_TYPE_TDLS = 2, 2925 }; 2926 2927 struct wmi_peer_create_cmd { 2928 u32 tlv_header; 2929 u32 vdev_id; 2930 struct wmi_mac_addr peer_macaddr; 2931 u32 peer_type; 2932 } __packed; 2933 2934 struct wmi_peer_delete_cmd { 2935 u32 tlv_header; 2936 u32 vdev_id; 2937 struct wmi_mac_addr peer_macaddr; 2938 } __packed; 2939 2940 struct wmi_peer_reorder_queue_setup_cmd { 2941 u32 tlv_header; 2942 u32 vdev_id; 2943 struct wmi_mac_addr peer_macaddr; 2944 u32 tid; 2945 u32 queue_ptr_lo; 2946 u32 queue_ptr_hi; 2947 u32 queue_no; 2948 u32 ba_window_size_valid; 2949 u32 ba_window_size; 2950 } __packed; 2951 2952 struct wmi_peer_reorder_queue_remove_cmd { 2953 u32 tlv_header; 2954 u32 vdev_id; 2955 struct wmi_mac_addr peer_macaddr; 2956 u32 tid_mask; 2957 } __packed; 2958 2959 struct gpio_config_params { 2960 u32 gpio_num; 2961 u32 input; 2962 u32 pull_type; 2963 u32 intr_mode; 2964 }; 2965 2966 enum wmi_gpio_type { 2967 WMI_GPIO_PULL_NONE, 2968 WMI_GPIO_PULL_UP, 2969 WMI_GPIO_PULL_DOWN 2970 }; 2971 2972 enum wmi_gpio_intr_type { 2973 WMI_GPIO_INTTYPE_DISABLE, 2974 WMI_GPIO_INTTYPE_RISING_EDGE, 2975 WMI_GPIO_INTTYPE_FALLING_EDGE, 2976 WMI_GPIO_INTTYPE_BOTH_EDGE, 2977 WMI_GPIO_INTTYPE_LEVEL_LOW, 2978 WMI_GPIO_INTTYPE_LEVEL_HIGH 2979 }; 2980 2981 enum wmi_bss_chan_info_req_type { 2982 WMI_BSS_SURVEY_REQ_TYPE_READ = 1, 2983 WMI_BSS_SURVEY_REQ_TYPE_READ_CLEAR, 2984 }; 2985 2986 struct wmi_gpio_config_cmd_param { 2987 u32 tlv_header; 2988 u32 gpio_num; 2989 u32 input; 2990 u32 pull_type; 2991 u32 intr_mode; 2992 }; 2993 2994 struct gpio_output_params { 2995 u32 gpio_num; 2996 u32 set; 2997 }; 2998 2999 struct wmi_gpio_output_cmd_param { 3000 u32 tlv_header; 3001 u32 gpio_num; 3002 u32 set; 3003 }; 3004 3005 struct set_fwtest_params { 3006 u32 arg; 3007 u32 value; 3008 }; 3009 3010 struct wmi_fwtest_set_param_cmd_param { 3011 u32 tlv_header; 3012 u32 param_id; 3013 u32 param_value; 3014 }; 3015 3016 struct wmi_pdev_set_param_cmd { 3017 u32 tlv_header; 3018 u32 pdev_id; 3019 u32 param_id; 3020 u32 param_value; 3021 } __packed; 3022 3023 struct wmi_pdev_set_ps_mode_cmd { 3024 u32 tlv_header; 3025 u32 vdev_id; 3026 u32 sta_ps_mode; 3027 } __packed; 3028 3029 struct wmi_pdev_suspend_cmd { 3030 u32 tlv_header; 3031 u32 pdev_id; 3032 u32 suspend_opt; 3033 } __packed; 3034 3035 struct wmi_pdev_resume_cmd { 3036 u32 tlv_header; 3037 u32 pdev_id; 3038 } __packed; 3039 3040 struct wmi_pdev_bss_chan_info_req_cmd { 3041 u32 tlv_header; 3042 /* ref wmi_bss_chan_info_req_type */ 3043 u32 req_type; 3044 u32 pdev_id; 3045 } __packed; 3046 3047 struct wmi_ap_ps_peer_cmd { 3048 u32 tlv_header; 3049 u32 vdev_id; 3050 struct wmi_mac_addr peer_macaddr; 3051 u32 param; 3052 u32 value; 3053 } __packed; 3054 3055 struct wmi_sta_powersave_param_cmd { 3056 u32 tlv_header; 3057 u32 vdev_id; 3058 u32 param; 3059 u32 value; 3060 } __packed; 3061 3062 struct wmi_pdev_set_regdomain_cmd { 3063 u32 tlv_header; 3064 u32 pdev_id; 3065 u32 reg_domain; 3066 u32 reg_domain_2g; 3067 u32 reg_domain_5g; 3068 u32 conformance_test_limit_2g; 3069 u32 conformance_test_limit_5g; 3070 u32 dfs_domain; 3071 } __packed; 3072 3073 struct wmi_peer_set_param_cmd { 3074 u32 tlv_header; 3075 u32 vdev_id; 3076 struct wmi_mac_addr peer_macaddr; 3077 u32 param_id; 3078 u32 param_value; 3079 } __packed; 3080 3081 struct wmi_peer_flush_tids_cmd { 3082 u32 tlv_header; 3083 u32 vdev_id; 3084 struct wmi_mac_addr peer_macaddr; 3085 u32 peer_tid_bitmap; 3086 } __packed; 3087 3088 struct wmi_dfs_phyerr_offload_cmd { 3089 u32 tlv_header; 3090 u32 pdev_id; 3091 } __packed; 3092 3093 struct wmi_bcn_offload_ctrl_cmd { 3094 u32 tlv_header; 3095 u32 vdev_id; 3096 u32 bcn_ctrl_op; 3097 } __packed; 3098 3099 enum scan_dwelltime_adaptive_mode { 3100 SCAN_DWELL_MODE_DEFAULT = 0, 3101 SCAN_DWELL_MODE_CONSERVATIVE = 1, 3102 SCAN_DWELL_MODE_MODERATE = 2, 3103 SCAN_DWELL_MODE_AGGRESSIVE = 3, 3104 SCAN_DWELL_MODE_STATIC = 4 3105 }; 3106 3107 #define WLAN_SSID_MAX_LEN 32 3108 3109 struct element_info { 3110 u32 len; 3111 u8 *ptr; 3112 }; 3113 3114 struct wlan_ssid { 3115 u8 length; 3116 u8 ssid[WLAN_SSID_MAX_LEN]; 3117 }; 3118 3119 #define WMI_IE_BITMAP_SIZE 8 3120 3121 /* prefix used by scan requestor ids on the host */ 3122 #define WMI_HOST_SCAN_REQUESTOR_ID_PREFIX 0xA000 3123 3124 /* prefix used by scan request ids generated on the host */ 3125 /* host cycles through the lower 12 bits to generate ids */ 3126 #define WMI_HOST_SCAN_REQ_ID_PREFIX 0xA000 3127 3128 /* Values lower than this may be refused by some firmware revisions with a scan 3129 * completion with a timedout reason. 3130 */ 3131 #define WMI_SCAN_CHAN_MIN_TIME_MSEC 40 3132 3133 /* Scan priority numbers must be sequential, starting with 0 */ 3134 enum wmi_scan_priority { 3135 WMI_SCAN_PRIORITY_VERY_LOW = 0, 3136 WMI_SCAN_PRIORITY_LOW, 3137 WMI_SCAN_PRIORITY_MEDIUM, 3138 WMI_SCAN_PRIORITY_HIGH, 3139 WMI_SCAN_PRIORITY_VERY_HIGH, 3140 WMI_SCAN_PRIORITY_COUNT /* number of priorities supported */ 3141 }; 3142 3143 enum wmi_scan_event_type { 3144 WMI_SCAN_EVENT_STARTED = BIT(0), 3145 WMI_SCAN_EVENT_COMPLETED = BIT(1), 3146 WMI_SCAN_EVENT_BSS_CHANNEL = BIT(2), 3147 WMI_SCAN_EVENT_FOREIGN_CHAN = BIT(3), 3148 WMI_SCAN_EVENT_DEQUEUED = BIT(4), 3149 /* possibly by high-prio scan */ 3150 WMI_SCAN_EVENT_PREEMPTED = BIT(5), 3151 WMI_SCAN_EVENT_START_FAILED = BIT(6), 3152 WMI_SCAN_EVENT_RESTARTED = BIT(7), 3153 WMI_SCAN_EVENT_FOREIGN_CHAN_EXIT = BIT(8), 3154 WMI_SCAN_EVENT_SUSPENDED = BIT(9), 3155 WMI_SCAN_EVENT_RESUMED = BIT(10), 3156 WMI_SCAN_EVENT_MAX = BIT(15), 3157 }; 3158 3159 enum wmi_scan_completion_reason { 3160 WMI_SCAN_REASON_COMPLETED, 3161 WMI_SCAN_REASON_CANCELLED, 3162 WMI_SCAN_REASON_PREEMPTED, 3163 WMI_SCAN_REASON_TIMEDOUT, 3164 WMI_SCAN_REASON_INTERNAL_FAILURE, 3165 WMI_SCAN_REASON_MAX, 3166 }; 3167 3168 struct wmi_start_scan_cmd { 3169 u32 tlv_header; 3170 u32 scan_id; 3171 u32 scan_req_id; 3172 u32 vdev_id; 3173 u32 scan_priority; 3174 u32 notify_scan_events; 3175 u32 dwell_time_active; 3176 u32 dwell_time_passive; 3177 u32 min_rest_time; 3178 u32 max_rest_time; 3179 u32 repeat_probe_time; 3180 u32 probe_spacing_time; 3181 u32 idle_time; 3182 u32 max_scan_time; 3183 u32 probe_delay; 3184 u32 scan_ctrl_flags; 3185 u32 burst_duration; 3186 u32 num_chan; 3187 u32 num_bssid; 3188 u32 num_ssids; 3189 u32 ie_len; 3190 u32 n_probes; 3191 struct wmi_mac_addr mac_addr; 3192 struct wmi_mac_addr mac_mask; 3193 u32 ie_bitmap[WMI_IE_BITMAP_SIZE]; 3194 u32 num_vendor_oui; 3195 u32 scan_ctrl_flags_ext; 3196 u32 dwell_time_active_2g; 3197 u32 dwell_time_active_6g; 3198 u32 dwell_time_passive_6g; 3199 u32 scan_start_offset; 3200 } __packed; 3201 3202 #define WMI_SCAN_FLAG_PASSIVE 0x1 3203 #define WMI_SCAN_ADD_BCAST_PROBE_REQ 0x2 3204 #define WMI_SCAN_ADD_CCK_RATES 0x4 3205 #define WMI_SCAN_ADD_OFDM_RATES 0x8 3206 #define WMI_SCAN_CHAN_STAT_EVENT 0x10 3207 #define WMI_SCAN_FILTER_PROBE_REQ 0x20 3208 #define WMI_SCAN_BYPASS_DFS_CHN 0x40 3209 #define WMI_SCAN_CONTINUE_ON_ERROR 0x80 3210 #define WMI_SCAN_FILTER_PROMISCUOS 0x100 3211 #define WMI_SCAN_FLAG_FORCE_ACTIVE_ON_DFS 0x200 3212 #define WMI_SCAN_ADD_TPC_IE_IN_PROBE_REQ 0x400 3213 #define WMI_SCAN_ADD_DS_IE_IN_PROBE_REQ 0x800 3214 #define WMI_SCAN_ADD_SPOOF_MAC_IN_PROBE_REQ 0x1000 3215 #define WMI_SCAN_OFFCHAN_MGMT_TX 0x2000 3216 #define WMI_SCAN_OFFCHAN_DATA_TX 0x4000 3217 #define WMI_SCAN_CAPTURE_PHY_ERROR 0x8000 3218 #define WMI_SCAN_FLAG_STRICT_PASSIVE_ON_PCHN 0x10000 3219 #define WMI_SCAN_FLAG_HALF_RATE_SUPPORT 0x20000 3220 #define WMI_SCAN_FLAG_QUARTER_RATE_SUPPORT 0x40000 3221 #define WMI_SCAN_RANDOM_SEQ_NO_IN_PROBE_REQ 0x80000 3222 #define WMI_SCAN_ENABLE_IE_WHTELIST_IN_PROBE_REQ 0x100000 3223 3224 #define WMI_SCAN_DWELL_MODE_MASK 0x00E00000 3225 #define WMI_SCAN_DWELL_MODE_SHIFT 21 3226 3227 enum { 3228 WMI_SCAN_DWELL_MODE_DEFAULT = 0, 3229 WMI_SCAN_DWELL_MODE_CONSERVATIVE = 1, 3230 WMI_SCAN_DWELL_MODE_MODERATE = 2, 3231 WMI_SCAN_DWELL_MODE_AGGRESSIVE = 3, 3232 WMI_SCAN_DWELL_MODE_STATIC = 4, 3233 }; 3234 3235 #define WMI_SCAN_SET_DWELL_MODE(flag, mode) \ 3236 ((flag) |= (((mode) << WMI_SCAN_DWELL_MODE_SHIFT) & \ 3237 WMI_SCAN_DWELL_MODE_MASK)) 3238 3239 struct hint_short_ssid { 3240 u32 freq_flags; 3241 u32 short_ssid; 3242 }; 3243 3244 struct hint_bssid { 3245 u32 freq_flags; 3246 struct wmi_mac_addr bssid; 3247 }; 3248 3249 struct scan_req_params { 3250 u32 scan_id; 3251 u32 scan_req_id; 3252 u32 vdev_id; 3253 u32 pdev_id; 3254 enum wmi_scan_priority scan_priority; 3255 union { 3256 struct { 3257 u32 scan_ev_started:1, 3258 scan_ev_completed:1, 3259 scan_ev_bss_chan:1, 3260 scan_ev_foreign_chan:1, 3261 scan_ev_dequeued:1, 3262 scan_ev_preempted:1, 3263 scan_ev_start_failed:1, 3264 scan_ev_restarted:1, 3265 scan_ev_foreign_chn_exit:1, 3266 scan_ev_invalid:1, 3267 scan_ev_gpio_timeout:1, 3268 scan_ev_suspended:1, 3269 scan_ev_resumed:1; 3270 }; 3271 u32 scan_events; 3272 }; 3273 u32 dwell_time_active; 3274 u32 dwell_time_active_2g; 3275 u32 dwell_time_passive; 3276 u32 dwell_time_active_6g; 3277 u32 dwell_time_passive_6g; 3278 u32 min_rest_time; 3279 u32 max_rest_time; 3280 u32 repeat_probe_time; 3281 u32 probe_spacing_time; 3282 u32 idle_time; 3283 u32 max_scan_time; 3284 u32 probe_delay; 3285 union { 3286 struct { 3287 u32 scan_f_passive:1, 3288 scan_f_bcast_probe:1, 3289 scan_f_cck_rates:1, 3290 scan_f_ofdm_rates:1, 3291 scan_f_chan_stat_evnt:1, 3292 scan_f_filter_prb_req:1, 3293 scan_f_bypass_dfs_chn:1, 3294 scan_f_continue_on_err:1, 3295 scan_f_offchan_mgmt_tx:1, 3296 scan_f_offchan_data_tx:1, 3297 scan_f_promisc_mode:1, 3298 scan_f_capture_phy_err:1, 3299 scan_f_strict_passive_pch:1, 3300 scan_f_half_rate:1, 3301 scan_f_quarter_rate:1, 3302 scan_f_force_active_dfs_chn:1, 3303 scan_f_add_tpc_ie_in_probe:1, 3304 scan_f_add_ds_ie_in_probe:1, 3305 scan_f_add_spoofed_mac_in_probe:1, 3306 scan_f_add_rand_seq_in_probe:1, 3307 scan_f_en_ie_whitelist_in_probe:1, 3308 scan_f_forced:1, 3309 scan_f_2ghz:1, 3310 scan_f_5ghz:1, 3311 scan_f_80mhz:1; 3312 }; 3313 u32 scan_flags; 3314 }; 3315 enum scan_dwelltime_adaptive_mode adaptive_dwell_time_mode; 3316 u32 burst_duration; 3317 u32 num_chan; 3318 u32 num_bssid; 3319 u32 num_ssids; 3320 u32 n_probes; 3321 u32 *chan_list; 3322 u32 notify_scan_events; 3323 struct wlan_ssid ssid[WLAN_SCAN_PARAMS_MAX_SSID]; 3324 struct wmi_mac_addr bssid_list[WLAN_SCAN_PARAMS_MAX_BSSID]; 3325 struct element_info extraie; 3326 struct element_info htcap; 3327 struct element_info vhtcap; 3328 u32 num_hint_s_ssid; 3329 u32 num_hint_bssid; 3330 struct hint_short_ssid hint_s_ssid[WLAN_SCAN_MAX_HINT_S_SSID]; 3331 struct hint_bssid hint_bssid[WLAN_SCAN_MAX_HINT_BSSID]; 3332 struct wmi_mac_addr mac_addr; 3333 struct wmi_mac_addr mac_mask; 3334 }; 3335 3336 struct wmi_ssid_arg { 3337 int len; 3338 const u8 *ssid; 3339 }; 3340 3341 struct wmi_bssid_arg { 3342 const u8 *bssid; 3343 }; 3344 3345 struct wmi_start_scan_arg { 3346 u32 scan_id; 3347 u32 scan_req_id; 3348 u32 vdev_id; 3349 u32 scan_priority; 3350 u32 notify_scan_events; 3351 u32 dwell_time_active; 3352 u32 dwell_time_passive; 3353 u32 min_rest_time; 3354 u32 max_rest_time; 3355 u32 repeat_probe_time; 3356 u32 probe_spacing_time; 3357 u32 idle_time; 3358 u32 max_scan_time; 3359 u32 probe_delay; 3360 u32 scan_ctrl_flags; 3361 3362 u32 ie_len; 3363 u32 n_channels; 3364 u32 n_ssids; 3365 u32 n_bssids; 3366 3367 u8 ie[WLAN_SCAN_PARAMS_MAX_IE_LEN]; 3368 u32 channels[64]; 3369 struct wmi_ssid_arg ssids[WLAN_SCAN_PARAMS_MAX_SSID]; 3370 struct wmi_bssid_arg bssids[WLAN_SCAN_PARAMS_MAX_BSSID]; 3371 }; 3372 3373 #define WMI_SCAN_STOP_ONE 0x00000000 3374 #define WMI_SCN_STOP_VAP_ALL 0x01000000 3375 #define WMI_SCAN_STOP_ALL 0x04000000 3376 3377 /* Prefix 0xA000 indicates that the scan request 3378 * is trigger by HOST 3379 */ 3380 #define ATH11K_SCAN_ID 0xA000 3381 3382 enum scan_cancel_req_type { 3383 WLAN_SCAN_CANCEL_SINGLE = 1, 3384 WLAN_SCAN_CANCEL_VDEV_ALL, 3385 WLAN_SCAN_CANCEL_PDEV_ALL, 3386 }; 3387 3388 struct scan_cancel_param { 3389 u32 requester; 3390 u32 scan_id; 3391 enum scan_cancel_req_type req_type; 3392 u32 vdev_id; 3393 u32 pdev_id; 3394 }; 3395 3396 struct wmi_bcn_send_from_host_cmd { 3397 u32 tlv_header; 3398 u32 vdev_id; 3399 u32 data_len; 3400 union { 3401 u32 frag_ptr; 3402 u32 frag_ptr_lo; 3403 }; 3404 u32 frame_ctrl; 3405 u32 dtim_flag; 3406 u32 bcn_antenna; 3407 u32 frag_ptr_hi; 3408 }; 3409 3410 #define WMI_CHAN_INFO_MODE GENMASK(5, 0) 3411 #define WMI_CHAN_INFO_HT40_PLUS BIT(6) 3412 #define WMI_CHAN_INFO_PASSIVE BIT(7) 3413 #define WMI_CHAN_INFO_ADHOC_ALLOWED BIT(8) 3414 #define WMI_CHAN_INFO_AP_DISABLED BIT(9) 3415 #define WMI_CHAN_INFO_DFS BIT(10) 3416 #define WMI_CHAN_INFO_ALLOW_HT BIT(11) 3417 #define WMI_CHAN_INFO_ALLOW_VHT BIT(12) 3418 #define WMI_CHAN_INFO_CHAN_CHANGE_CAUSE_CSA BIT(13) 3419 #define WMI_CHAN_INFO_HALF_RATE BIT(14) 3420 #define WMI_CHAN_INFO_QUARTER_RATE BIT(15) 3421 #define WMI_CHAN_INFO_DFS_FREQ2 BIT(16) 3422 #define WMI_CHAN_INFO_ALLOW_HE BIT(17) 3423 #define WMI_CHAN_INFO_PSC BIT(18) 3424 3425 #define WMI_CHAN_REG_INFO1_MIN_PWR GENMASK(7, 0) 3426 #define WMI_CHAN_REG_INFO1_MAX_PWR GENMASK(15, 8) 3427 #define WMI_CHAN_REG_INFO1_MAX_REG_PWR GENMASK(23, 16) 3428 #define WMI_CHAN_REG_INFO1_REG_CLS GENMASK(31, 24) 3429 3430 #define WMI_CHAN_REG_INFO2_ANT_MAX GENMASK(7, 0) 3431 #define WMI_CHAN_REG_INFO2_MAX_TX_PWR GENMASK(15, 8) 3432 3433 struct wmi_channel { 3434 u32 tlv_header; 3435 u32 mhz; 3436 u32 band_center_freq1; 3437 u32 band_center_freq2; 3438 u32 info; 3439 u32 reg_info_1; 3440 u32 reg_info_2; 3441 } __packed; 3442 3443 struct wmi_mgmt_params { 3444 void *tx_frame; 3445 u16 frm_len; 3446 u8 vdev_id; 3447 u16 chanfreq; 3448 void *pdata; 3449 u16 desc_id; 3450 u8 *macaddr; 3451 }; 3452 3453 enum wmi_sta_ps_mode { 3454 WMI_STA_PS_MODE_DISABLED = 0, 3455 WMI_STA_PS_MODE_ENABLED = 1, 3456 }; 3457 3458 #define WMI_SMPS_MASK_LOWER_16BITS 0xFF 3459 #define WMI_SMPS_MASK_UPPER_3BITS 0x7 3460 #define WMI_SMPS_PARAM_VALUE_SHIFT 29 3461 3462 #define ATH11K_WMI_FW_HANG_ASSERT_TYPE 1 3463 #define ATH11K_WMI_FW_HANG_DELAY 0 3464 3465 /* type, 0:unused 1: ASSERT 2: not respond detect command 3466 * delay_time_ms, the simulate will delay time 3467 */ 3468 3469 struct wmi_force_fw_hang_cmd { 3470 u32 tlv_header; 3471 u32 type; 3472 u32 delay_time_ms; 3473 }; 3474 3475 struct wmi_vdev_set_param_cmd { 3476 u32 tlv_header; 3477 u32 vdev_id; 3478 u32 param_id; 3479 u32 param_value; 3480 } __packed; 3481 3482 enum wmi_stats_id { 3483 WMI_REQUEST_PEER_STAT = BIT(0), 3484 WMI_REQUEST_AP_STAT = BIT(1), 3485 WMI_REQUEST_PDEV_STAT = BIT(2), 3486 WMI_REQUEST_VDEV_STAT = BIT(3), 3487 WMI_REQUEST_BCNFLT_STAT = BIT(4), 3488 WMI_REQUEST_VDEV_RATE_STAT = BIT(5), 3489 WMI_REQUEST_INST_STAT = BIT(6), 3490 WMI_REQUEST_MIB_STAT = BIT(7), 3491 WMI_REQUEST_RSSI_PER_CHAIN_STAT = BIT(8), 3492 WMI_REQUEST_CONGESTION_STAT = BIT(9), 3493 WMI_REQUEST_PEER_EXTD_STAT = BIT(10), 3494 WMI_REQUEST_BCN_STAT = BIT(11), 3495 WMI_REQUEST_BCN_STAT_RESET = BIT(12), 3496 WMI_REQUEST_PEER_EXTD2_STAT = BIT(13), 3497 }; 3498 3499 struct wmi_request_stats_cmd { 3500 u32 tlv_header; 3501 enum wmi_stats_id stats_id; 3502 u32 vdev_id; 3503 struct wmi_mac_addr peer_macaddr; 3504 u32 pdev_id; 3505 } __packed; 3506 3507 struct wmi_get_pdev_temperature_cmd { 3508 u32 tlv_header; 3509 u32 param; 3510 u32 pdev_id; 3511 } __packed; 3512 3513 #define WMI_BEACON_TX_BUFFER_SIZE 512 3514 3515 struct wmi_bcn_tmpl_cmd { 3516 u32 tlv_header; 3517 u32 vdev_id; 3518 u32 tim_ie_offset; 3519 u32 buf_len; 3520 u32 csa_switch_count_offset; 3521 u32 ext_csa_switch_count_offset; 3522 u32 csa_event_bitmap; 3523 u32 mbssid_ie_offset; 3524 u32 esp_ie_offset; 3525 } __packed; 3526 3527 struct wmi_key_seq_counter { 3528 u32 key_seq_counter_l; 3529 u32 key_seq_counter_h; 3530 } __packed; 3531 3532 struct wmi_vdev_install_key_cmd { 3533 u32 tlv_header; 3534 u32 vdev_id; 3535 struct wmi_mac_addr peer_macaddr; 3536 u32 key_idx; 3537 u32 key_flags; 3538 u32 key_cipher; 3539 struct wmi_key_seq_counter key_rsc_counter; 3540 struct wmi_key_seq_counter key_global_rsc_counter; 3541 struct wmi_key_seq_counter key_tsc_counter; 3542 u8 wpi_key_rsc_counter[16]; 3543 u8 wpi_key_tsc_counter[16]; 3544 u32 key_len; 3545 u32 key_txmic_len; 3546 u32 key_rxmic_len; 3547 u32 is_group_key_id_valid; 3548 u32 group_key_id; 3549 3550 /* Followed by key_data containing key followed by 3551 * tx mic and then rx mic 3552 */ 3553 } __packed; 3554 3555 struct wmi_vdev_install_key_arg { 3556 u32 vdev_id; 3557 const u8 *macaddr; 3558 u32 key_idx; 3559 u32 key_flags; 3560 u32 key_cipher; 3561 u32 key_len; 3562 u32 key_txmic_len; 3563 u32 key_rxmic_len; 3564 u64 key_rsc_counter; 3565 const void *key_data; 3566 }; 3567 3568 #define WMI_MAX_SUPPORTED_RATES 128 3569 #define WMI_HOST_MAX_HECAP_PHY_SIZE 3 3570 #define WMI_HOST_MAX_HE_RATE_SET 3 3571 #define WMI_HECAP_TXRX_MCS_NSS_IDX_80 0 3572 #define WMI_HECAP_TXRX_MCS_NSS_IDX_160 1 3573 #define WMI_HECAP_TXRX_MCS_NSS_IDX_80_80 2 3574 3575 struct wmi_rate_set_arg { 3576 u32 num_rates; 3577 u8 rates[WMI_MAX_SUPPORTED_RATES]; 3578 }; 3579 3580 struct peer_assoc_params { 3581 struct wmi_mac_addr peer_macaddr; 3582 u32 vdev_id; 3583 u32 peer_new_assoc; 3584 u32 peer_associd; 3585 u32 peer_flags; 3586 u32 peer_caps; 3587 u32 peer_listen_intval; 3588 u32 peer_ht_caps; 3589 u32 peer_max_mpdu; 3590 u32 peer_mpdu_density; 3591 u32 peer_rate_caps; 3592 u32 peer_nss; 3593 u32 peer_vht_caps; 3594 u32 peer_phymode; 3595 u32 peer_ht_info[2]; 3596 struct wmi_rate_set_arg peer_legacy_rates; 3597 struct wmi_rate_set_arg peer_ht_rates; 3598 u32 rx_max_rate; 3599 u32 rx_mcs_set; 3600 u32 tx_max_rate; 3601 u32 tx_mcs_set; 3602 u8 vht_capable; 3603 u8 min_data_rate; 3604 u32 tx_max_mcs_nss; 3605 u32 peer_bw_rxnss_override; 3606 bool is_pmf_enabled; 3607 bool is_wme_set; 3608 bool qos_flag; 3609 bool apsd_flag; 3610 bool ht_flag; 3611 bool bw_40; 3612 bool bw_80; 3613 bool bw_160; 3614 bool stbc_flag; 3615 bool ldpc_flag; 3616 bool static_mimops_flag; 3617 bool dynamic_mimops_flag; 3618 bool spatial_mux_flag; 3619 bool vht_flag; 3620 bool vht_ng_flag; 3621 bool need_ptk_4_way; 3622 bool need_gtk_2_way; 3623 bool auth_flag; 3624 bool safe_mode_enabled; 3625 bool amsdu_disable; 3626 /* Use common structure */ 3627 u8 peer_mac[ETH_ALEN]; 3628 3629 bool he_flag; 3630 u32 peer_he_cap_macinfo[2]; 3631 u32 peer_he_cap_macinfo_internal; 3632 u32 peer_he_caps_6ghz; 3633 u32 peer_he_ops; 3634 u32 peer_he_cap_phyinfo[WMI_HOST_MAX_HECAP_PHY_SIZE]; 3635 u32 peer_he_mcs_count; 3636 u32 peer_he_rx_mcs_set[WMI_HOST_MAX_HE_RATE_SET]; 3637 u32 peer_he_tx_mcs_set[WMI_HOST_MAX_HE_RATE_SET]; 3638 bool twt_responder; 3639 bool twt_requester; 3640 bool is_assoc; 3641 struct ath11k_ppe_threshold peer_ppet; 3642 }; 3643 3644 struct wmi_peer_assoc_complete_cmd { 3645 u32 tlv_header; 3646 struct wmi_mac_addr peer_macaddr; 3647 u32 vdev_id; 3648 u32 peer_new_assoc; 3649 u32 peer_associd; 3650 u32 peer_flags; 3651 u32 peer_caps; 3652 u32 peer_listen_intval; 3653 u32 peer_ht_caps; 3654 u32 peer_max_mpdu; 3655 u32 peer_mpdu_density; 3656 u32 peer_rate_caps; 3657 u32 peer_nss; 3658 u32 peer_vht_caps; 3659 u32 peer_phymode; 3660 u32 peer_ht_info[2]; 3661 u32 num_peer_legacy_rates; 3662 u32 num_peer_ht_rates; 3663 u32 peer_bw_rxnss_override; 3664 struct wmi_ppe_threshold peer_ppet; 3665 u32 peer_he_cap_info; 3666 u32 peer_he_ops; 3667 u32 peer_he_cap_phy[WMI_MAX_HECAP_PHY_SIZE]; 3668 u32 peer_he_mcs; 3669 u32 peer_he_cap_info_ext; 3670 u32 peer_he_cap_info_internal; 3671 u32 min_data_rate; 3672 u32 peer_he_caps_6ghz; 3673 } __packed; 3674 3675 struct wmi_stop_scan_cmd { 3676 u32 tlv_header; 3677 u32 requestor; 3678 u32 scan_id; 3679 u32 req_type; 3680 u32 vdev_id; 3681 u32 pdev_id; 3682 }; 3683 3684 struct scan_chan_list_params { 3685 u32 pdev_id; 3686 u16 nallchans; 3687 struct channel_param ch_param[]; 3688 }; 3689 3690 struct wmi_scan_chan_list_cmd { 3691 u32 tlv_header; 3692 u32 num_scan_chans; 3693 u32 flags; 3694 u32 pdev_id; 3695 } __packed; 3696 3697 struct wmi_scan_prob_req_oui_cmd { 3698 u32 tlv_header; 3699 u32 prob_req_oui; 3700 } __packed; 3701 3702 #define WMI_MGMT_SEND_DOWNLD_LEN 64 3703 3704 #define WMI_TX_PARAMS_DWORD0_POWER GENMASK(7, 0) 3705 #define WMI_TX_PARAMS_DWORD0_MCS_MASK GENMASK(19, 8) 3706 #define WMI_TX_PARAMS_DWORD0_NSS_MASK GENMASK(27, 20) 3707 #define WMI_TX_PARAMS_DWORD0_RETRY_LIMIT GENMASK(31, 28) 3708 3709 #define WMI_TX_PARAMS_DWORD1_CHAIN_MASK GENMASK(7, 0) 3710 #define WMI_TX_PARAMS_DWORD1_BW_MASK GENMASK(14, 8) 3711 #define WMI_TX_PARAMS_DWORD1_PREAMBLE_TYPE GENMASK(19, 15) 3712 #define WMI_TX_PARAMS_DWORD1_FRAME_TYPE BIT(20) 3713 #define WMI_TX_PARAMS_DWORD1_RSVD GENMASK(31, 21) 3714 3715 struct wmi_mgmt_send_params { 3716 u32 tlv_header; 3717 u32 tx_params_dword0; 3718 u32 tx_params_dword1; 3719 }; 3720 3721 struct wmi_mgmt_send_cmd { 3722 u32 tlv_header; 3723 u32 vdev_id; 3724 u32 desc_id; 3725 u32 chanfreq; 3726 u32 paddr_lo; 3727 u32 paddr_hi; 3728 u32 frame_len; 3729 u32 buf_len; 3730 u32 tx_params_valid; 3731 3732 /* This TLV is followed by struct wmi_mgmt_frame */ 3733 3734 /* Followed by struct wmi_mgmt_send_params */ 3735 } __packed; 3736 3737 struct wmi_sta_powersave_mode_cmd { 3738 u32 tlv_header; 3739 u32 vdev_id; 3740 u32 sta_ps_mode; 3741 }; 3742 3743 struct wmi_sta_smps_force_mode_cmd { 3744 u32 tlv_header; 3745 u32 vdev_id; 3746 u32 forced_mode; 3747 }; 3748 3749 struct wmi_sta_smps_param_cmd { 3750 u32 tlv_header; 3751 u32 vdev_id; 3752 u32 param; 3753 u32 value; 3754 }; 3755 3756 struct wmi_bcn_prb_info { 3757 u32 tlv_header; 3758 u32 caps; 3759 u32 erp; 3760 } __packed; 3761 3762 enum { 3763 WMI_PDEV_SUSPEND, 3764 WMI_PDEV_SUSPEND_AND_DISABLE_INTR, 3765 }; 3766 3767 struct green_ap_ps_params { 3768 u32 value; 3769 }; 3770 3771 struct wmi_pdev_green_ap_ps_enable_cmd_param { 3772 u32 tlv_header; 3773 u32 pdev_id; 3774 u32 enable; 3775 }; 3776 3777 struct ap_ps_params { 3778 u32 vdev_id; 3779 u32 param; 3780 u32 value; 3781 }; 3782 3783 struct vdev_set_params { 3784 u32 if_id; 3785 u32 param_id; 3786 u32 param_value; 3787 }; 3788 3789 struct stats_request_params { 3790 u32 stats_id; 3791 u32 vdev_id; 3792 u32 pdev_id; 3793 }; 3794 3795 struct wmi_set_current_country_params { 3796 u8 alpha2[3]; 3797 }; 3798 3799 struct wmi_set_current_country_cmd { 3800 u32 tlv_header; 3801 u32 pdev_id; 3802 u32 new_alpha2; 3803 } __packed; 3804 3805 enum set_init_cc_type { 3806 WMI_COUNTRY_INFO_TYPE_ALPHA, 3807 WMI_COUNTRY_INFO_TYPE_COUNTRY_CODE, 3808 WMI_COUNTRY_INFO_TYPE_REGDOMAIN, 3809 }; 3810 3811 enum set_init_cc_flags { 3812 INVALID_CC, 3813 CC_IS_SET, 3814 REGDMN_IS_SET, 3815 ALPHA_IS_SET, 3816 }; 3817 3818 struct wmi_init_country_params { 3819 union { 3820 u16 country_code; 3821 u16 regdom_id; 3822 u8 alpha2[3]; 3823 } cc_info; 3824 enum set_init_cc_flags flags; 3825 }; 3826 3827 struct wmi_init_country_cmd { 3828 u32 tlv_header; 3829 u32 pdev_id; 3830 u32 init_cc_type; 3831 union { 3832 u32 country_code; 3833 u32 regdom_id; 3834 u32 alpha2; 3835 } cc_info; 3836 } __packed; 3837 3838 struct wmi_11d_scan_start_params { 3839 u32 vdev_id; 3840 u32 scan_period_msec; 3841 u32 start_interval_msec; 3842 }; 3843 3844 struct wmi_11d_scan_start_cmd { 3845 u32 tlv_header; 3846 u32 vdev_id; 3847 u32 scan_period_msec; 3848 u32 start_interval_msec; 3849 } __packed; 3850 3851 struct wmi_11d_scan_stop_cmd { 3852 u32 tlv_header; 3853 u32 vdev_id; 3854 } __packed; 3855 3856 struct wmi_11d_new_cc_ev { 3857 u32 new_alpha2; 3858 } __packed; 3859 3860 #define THERMAL_LEVELS 1 3861 struct tt_level_config { 3862 u32 tmplwm; 3863 u32 tmphwm; 3864 u32 dcoffpercent; 3865 u32 priority; 3866 }; 3867 3868 struct thermal_mitigation_params { 3869 u32 pdev_id; 3870 u32 enable; 3871 u32 dc; 3872 u32 dc_per_event; 3873 struct tt_level_config levelconf[THERMAL_LEVELS]; 3874 }; 3875 3876 struct wmi_therm_throt_config_request_cmd { 3877 u32 tlv_header; 3878 u32 pdev_id; 3879 u32 enable; 3880 u32 dc; 3881 u32 dc_per_event; 3882 u32 therm_throt_levels; 3883 } __packed; 3884 3885 struct wmi_therm_throt_level_config_info { 3886 u32 tlv_header; 3887 u32 temp_lwm; 3888 u32 temp_hwm; 3889 u32 dc_off_percent; 3890 u32 prio; 3891 } __packed; 3892 3893 struct wmi_delba_send_cmd { 3894 u32 tlv_header; 3895 u32 vdev_id; 3896 struct wmi_mac_addr peer_macaddr; 3897 u32 tid; 3898 u32 initiator; 3899 u32 reasoncode; 3900 } __packed; 3901 3902 struct wmi_addba_setresponse_cmd { 3903 u32 tlv_header; 3904 u32 vdev_id; 3905 struct wmi_mac_addr peer_macaddr; 3906 u32 tid; 3907 u32 statuscode; 3908 } __packed; 3909 3910 struct wmi_addba_send_cmd { 3911 u32 tlv_header; 3912 u32 vdev_id; 3913 struct wmi_mac_addr peer_macaddr; 3914 u32 tid; 3915 u32 buffersize; 3916 } __packed; 3917 3918 struct wmi_addba_clear_resp_cmd { 3919 u32 tlv_header; 3920 u32 vdev_id; 3921 struct wmi_mac_addr peer_macaddr; 3922 } __packed; 3923 3924 struct wmi_pdev_pktlog_filter_info { 3925 u32 tlv_header; 3926 struct wmi_mac_addr peer_macaddr; 3927 } __packed; 3928 3929 struct wmi_pdev_pktlog_filter_cmd { 3930 u32 tlv_header; 3931 u32 pdev_id; 3932 u32 enable; 3933 u32 filter_type; 3934 u32 num_mac; 3935 } __packed; 3936 3937 enum ath11k_wmi_pktlog_enable { 3938 ATH11K_WMI_PKTLOG_ENABLE_AUTO = 0, 3939 ATH11K_WMI_PKTLOG_ENABLE_FORCE = 1, 3940 }; 3941 3942 struct wmi_pktlog_enable_cmd { 3943 u32 tlv_header; 3944 u32 pdev_id; 3945 u32 evlist; /* WMI_PKTLOG_EVENT */ 3946 u32 enable; 3947 } __packed; 3948 3949 struct wmi_pktlog_disable_cmd { 3950 u32 tlv_header; 3951 u32 pdev_id; 3952 } __packed; 3953 3954 #define DFS_PHYERR_UNIT_TEST_CMD 0 3955 #define DFS_UNIT_TEST_MODULE 0x2b 3956 #define DFS_UNIT_TEST_TOKEN 0xAA 3957 3958 enum dfs_test_args_idx { 3959 DFS_TEST_CMDID = 0, 3960 DFS_TEST_PDEV_ID, 3961 DFS_TEST_RADAR_PARAM, 3962 DFS_MAX_TEST_ARGS, 3963 }; 3964 3965 struct wmi_dfs_unit_test_arg { 3966 u32 cmd_id; 3967 u32 pdev_id; 3968 u32 radar_param; 3969 }; 3970 3971 struct wmi_unit_test_cmd { 3972 u32 tlv_header; 3973 u32 vdev_id; 3974 u32 module_id; 3975 u32 num_args; 3976 u32 diag_token; 3977 /* Followed by test args*/ 3978 } __packed; 3979 3980 #define MAX_SUPPORTED_RATES 128 3981 3982 #define WMI_PEER_AUTH 0x00000001 3983 #define WMI_PEER_QOS 0x00000002 3984 #define WMI_PEER_NEED_PTK_4_WAY 0x00000004 3985 #define WMI_PEER_NEED_GTK_2_WAY 0x00000010 3986 #define WMI_PEER_HE 0x00000400 3987 #define WMI_PEER_APSD 0x00000800 3988 #define WMI_PEER_HT 0x00001000 3989 #define WMI_PEER_40MHZ 0x00002000 3990 #define WMI_PEER_STBC 0x00008000 3991 #define WMI_PEER_LDPC 0x00010000 3992 #define WMI_PEER_DYN_MIMOPS 0x00020000 3993 #define WMI_PEER_STATIC_MIMOPS 0x00040000 3994 #define WMI_PEER_SPATIAL_MUX 0x00200000 3995 #define WMI_PEER_TWT_REQ 0x00400000 3996 #define WMI_PEER_TWT_RESP 0x00800000 3997 #define WMI_PEER_VHT 0x02000000 3998 #define WMI_PEER_80MHZ 0x04000000 3999 #define WMI_PEER_PMF 0x08000000 4000 /* TODO: Place holder for WLAN_PEER_F_PS_PRESEND_REQUIRED = 0x10000000. 4001 * Need to be cleaned up 4002 */ 4003 #define WMI_PEER_IS_P2P_CAPABLE 0x20000000 4004 #define WMI_PEER_160MHZ 0x40000000 4005 #define WMI_PEER_SAFEMODE_EN 0x80000000 4006 4007 struct beacon_tmpl_params { 4008 u8 vdev_id; 4009 u32 tim_ie_offset; 4010 u32 tmpl_len; 4011 u32 tmpl_len_aligned; 4012 u32 csa_switch_count_offset; 4013 u32 ext_csa_switch_count_offset; 4014 u8 *frm; 4015 }; 4016 4017 struct wmi_rate_set { 4018 u32 num_rates; 4019 u32 rates[(MAX_SUPPORTED_RATES / 4) + 1]; 4020 }; 4021 4022 struct wmi_vht_rate_set { 4023 u32 tlv_header; 4024 u32 rx_max_rate; 4025 u32 rx_mcs_set; 4026 u32 tx_max_rate; 4027 u32 tx_mcs_set; 4028 u32 tx_max_mcs_nss; 4029 } __packed; 4030 4031 struct wmi_he_rate_set { 4032 u32 tlv_header; 4033 4034 /* MCS at which the peer can receive */ 4035 u32 rx_mcs_set; 4036 4037 /* MCS at which the peer can transmit */ 4038 u32 tx_mcs_set; 4039 } __packed; 4040 4041 #define MAX_REG_RULES 10 4042 #define REG_ALPHA2_LEN 2 4043 4044 enum wmi_start_event_param { 4045 WMI_VDEV_START_RESP_EVENT = 0, 4046 WMI_VDEV_RESTART_RESP_EVENT, 4047 }; 4048 4049 struct wmi_vdev_start_resp_event { 4050 u32 vdev_id; 4051 u32 requestor_id; 4052 enum wmi_start_event_param resp_type; 4053 u32 status; 4054 u32 chain_mask; 4055 u32 smps_mode; 4056 union { 4057 u32 mac_id; 4058 u32 pdev_id; 4059 }; 4060 u32 cfgd_tx_streams; 4061 u32 cfgd_rx_streams; 4062 } __packed; 4063 4064 /* VDEV start response status codes */ 4065 enum wmi_vdev_start_resp_status_code { 4066 WMI_VDEV_START_RESPONSE_STATUS_SUCCESS = 0, 4067 WMI_VDEV_START_RESPONSE_INVALID_VDEVID = 1, 4068 WMI_VDEV_START_RESPONSE_NOT_SUPPORTED = 2, 4069 WMI_VDEV_START_RESPONSE_DFS_VIOLATION = 3, 4070 WMI_VDEV_START_RESPONSE_INVALID_REGDOMAIN = 4, 4071 }; 4072 4073 ; 4074 enum cc_setting_code { 4075 REG_SET_CC_STATUS_PASS = 0, 4076 REG_CURRENT_ALPHA2_NOT_FOUND = 1, 4077 REG_INIT_ALPHA2_NOT_FOUND = 2, 4078 REG_SET_CC_CHANGE_NOT_ALLOWED = 3, 4079 REG_SET_CC_STATUS_NO_MEMORY = 4, 4080 REG_SET_CC_STATUS_FAIL = 5, 4081 }; 4082 4083 /* Regaulatory Rule Flags Passed by FW */ 4084 #define REGULATORY_CHAN_DISABLED BIT(0) 4085 #define REGULATORY_CHAN_NO_IR BIT(1) 4086 #define REGULATORY_CHAN_RADAR BIT(3) 4087 #define REGULATORY_CHAN_NO_OFDM BIT(6) 4088 #define REGULATORY_CHAN_INDOOR_ONLY BIT(9) 4089 4090 #define REGULATORY_CHAN_NO_HT40 BIT(4) 4091 #define REGULATORY_CHAN_NO_80MHZ BIT(7) 4092 #define REGULATORY_CHAN_NO_160MHZ BIT(8) 4093 #define REGULATORY_CHAN_NO_20MHZ BIT(11) 4094 #define REGULATORY_CHAN_NO_10MHZ BIT(12) 4095 4096 enum { 4097 WMI_REG_SET_CC_STATUS_PASS = 0, 4098 WMI_REG_CURRENT_ALPHA2_NOT_FOUND = 1, 4099 WMI_REG_INIT_ALPHA2_NOT_FOUND = 2, 4100 WMI_REG_SET_CC_CHANGE_NOT_ALLOWED = 3, 4101 WMI_REG_SET_CC_STATUS_NO_MEMORY = 4, 4102 WMI_REG_SET_CC_STATUS_FAIL = 5, 4103 }; 4104 4105 struct cur_reg_rule { 4106 u16 start_freq; 4107 u16 end_freq; 4108 u16 max_bw; 4109 u8 reg_power; 4110 u8 ant_gain; 4111 u16 flags; 4112 }; 4113 4114 struct cur_regulatory_info { 4115 enum cc_setting_code status_code; 4116 u8 num_phy; 4117 u8 phy_id; 4118 u16 reg_dmn_pair; 4119 u16 ctry_code; 4120 u8 alpha2[REG_ALPHA2_LEN + 1]; 4121 u32 dfs_region; 4122 u32 phybitmap; 4123 u32 min_bw_2g; 4124 u32 max_bw_2g; 4125 u32 min_bw_5g; 4126 u32 max_bw_5g; 4127 u32 num_2g_reg_rules; 4128 u32 num_5g_reg_rules; 4129 struct cur_reg_rule *reg_rules_2g_ptr; 4130 struct cur_reg_rule *reg_rules_5g_ptr; 4131 }; 4132 4133 struct wmi_reg_chan_list_cc_event { 4134 u32 status_code; 4135 u32 phy_id; 4136 u32 alpha2; 4137 u32 num_phy; 4138 u32 country_id; 4139 u32 domain_code; 4140 u32 dfs_region; 4141 u32 phybitmap; 4142 u32 min_bw_2g; 4143 u32 max_bw_2g; 4144 u32 min_bw_5g; 4145 u32 max_bw_5g; 4146 u32 num_2g_reg_rules; 4147 u32 num_5g_reg_rules; 4148 } __packed; 4149 4150 struct wmi_regulatory_rule_struct { 4151 u32 tlv_header; 4152 u32 freq_info; 4153 u32 bw_pwr_info; 4154 u32 flag_info; 4155 }; 4156 4157 struct wmi_vdev_delete_resp_event { 4158 u32 vdev_id; 4159 } __packed; 4160 4161 struct wmi_peer_delete_resp_event { 4162 u32 vdev_id; 4163 struct wmi_mac_addr peer_macaddr; 4164 } __packed; 4165 4166 struct wmi_bcn_tx_status_event { 4167 u32 vdev_id; 4168 u32 tx_status; 4169 } __packed; 4170 4171 struct wmi_vdev_stopped_event { 4172 u32 vdev_id; 4173 } __packed; 4174 4175 struct wmi_pdev_bss_chan_info_event { 4176 u32 freq; /* Units in MHz */ 4177 u32 noise_floor; /* units are dBm */ 4178 /* rx clear - how often the channel was unused */ 4179 u32 rx_clear_count_low; 4180 u32 rx_clear_count_high; 4181 /* cycle count - elapsed time during measured period, in clock ticks */ 4182 u32 cycle_count_low; 4183 u32 cycle_count_high; 4184 /* tx cycle count - elapsed time spent in tx, in clock ticks */ 4185 u32 tx_cycle_count_low; 4186 u32 tx_cycle_count_high; 4187 /* rx cycle count - elapsed time spent in rx, in clock ticks */ 4188 u32 rx_cycle_count_low; 4189 u32 rx_cycle_count_high; 4190 /*rx_cycle cnt for my bss in 64bits format */ 4191 u32 rx_bss_cycle_count_low; 4192 u32 rx_bss_cycle_count_high; 4193 u32 pdev_id; 4194 } __packed; 4195 4196 #define WMI_VDEV_INSTALL_KEY_COMPL_STATUS_SUCCESS 0 4197 4198 struct wmi_vdev_install_key_compl_event { 4199 u32 vdev_id; 4200 struct wmi_mac_addr peer_macaddr; 4201 u32 key_idx; 4202 u32 key_flags; 4203 u32 status; 4204 } __packed; 4205 4206 struct wmi_vdev_install_key_complete_arg { 4207 u32 vdev_id; 4208 const u8 *macaddr; 4209 u32 key_idx; 4210 u32 key_flags; 4211 u32 status; 4212 }; 4213 4214 struct wmi_peer_assoc_conf_event { 4215 u32 vdev_id; 4216 struct wmi_mac_addr peer_macaddr; 4217 } __packed; 4218 4219 struct wmi_peer_assoc_conf_arg { 4220 u32 vdev_id; 4221 const u8 *macaddr; 4222 }; 4223 4224 struct wmi_fils_discovery_event { 4225 u32 vdev_id; 4226 u32 fils_tt; 4227 u32 tbtt; 4228 } __packed; 4229 4230 struct wmi_probe_resp_tx_status_event { 4231 u32 vdev_id; 4232 u32 tx_status; 4233 } __packed; 4234 4235 /* 4236 * PDEV statistics 4237 */ 4238 struct wmi_pdev_stats_base { 4239 s32 chan_nf; 4240 u32 tx_frame_count; /* Cycles spent transmitting frames */ 4241 u32 rx_frame_count; /* Cycles spent receiving frames */ 4242 u32 rx_clear_count; /* Total channel busy time, evidently */ 4243 u32 cycle_count; /* Total on-channel time */ 4244 u32 phy_err_count; 4245 u32 chan_tx_pwr; 4246 } __packed; 4247 4248 struct wmi_pdev_stats_extra { 4249 u32 ack_rx_bad; 4250 u32 rts_bad; 4251 u32 rts_good; 4252 u32 fcs_bad; 4253 u32 no_beacons; 4254 u32 mib_int_count; 4255 } __packed; 4256 4257 struct wmi_pdev_stats_tx { 4258 /* Num HTT cookies queued to dispatch list */ 4259 s32 comp_queued; 4260 4261 /* Num HTT cookies dispatched */ 4262 s32 comp_delivered; 4263 4264 /* Num MSDU queued to WAL */ 4265 s32 msdu_enqued; 4266 4267 /* Num MPDU queue to WAL */ 4268 s32 mpdu_enqued; 4269 4270 /* Num MSDUs dropped by WMM limit */ 4271 s32 wmm_drop; 4272 4273 /* Num Local frames queued */ 4274 s32 local_enqued; 4275 4276 /* Num Local frames done */ 4277 s32 local_freed; 4278 4279 /* Num queued to HW */ 4280 s32 hw_queued; 4281 4282 /* Num PPDU reaped from HW */ 4283 s32 hw_reaped; 4284 4285 /* Num underruns */ 4286 s32 underrun; 4287 4288 /* Num hw paused */ 4289 u32 hw_paused; 4290 4291 /* Num PPDUs cleaned up in TX abort */ 4292 s32 tx_abort; 4293 4294 /* Num MPDUs requeued by SW */ 4295 s32 mpdus_requeued; 4296 4297 /* excessive retries */ 4298 u32 tx_ko; 4299 4300 u32 tx_xretry; 4301 4302 /* data hw rate code */ 4303 u32 data_rc; 4304 4305 /* Scheduler self triggers */ 4306 u32 self_triggers; 4307 4308 /* frames dropped due to excessive sw retries */ 4309 u32 sw_retry_failure; 4310 4311 /* illegal rate phy errors */ 4312 u32 illgl_rate_phy_err; 4313 4314 /* wal pdev continuous xretry */ 4315 u32 pdev_cont_xretry; 4316 4317 /* wal pdev tx timeouts */ 4318 u32 pdev_tx_timeout; 4319 4320 /* wal pdev resets */ 4321 u32 pdev_resets; 4322 4323 /* frames dropped due to non-availability of stateless TIDs */ 4324 u32 stateless_tid_alloc_failure; 4325 4326 /* PhY/BB underrun */ 4327 u32 phy_underrun; 4328 4329 /* MPDU is more than txop limit */ 4330 u32 txop_ovf; 4331 4332 /* Num sequences posted */ 4333 u32 seq_posted; 4334 4335 /* Num sequences failed in queueing */ 4336 u32 seq_failed_queueing; 4337 4338 /* Num sequences completed */ 4339 u32 seq_completed; 4340 4341 /* Num sequences restarted */ 4342 u32 seq_restarted; 4343 4344 /* Num of MU sequences posted */ 4345 u32 mu_seq_posted; 4346 4347 /* Num MPDUs flushed by SW, HWPAUSED, SW TXABORT 4348 * (Reset,channel change) 4349 */ 4350 s32 mpdus_sw_flush; 4351 4352 /* Num MPDUs filtered by HW, all filter condition (TTL expired) */ 4353 s32 mpdus_hw_filter; 4354 4355 /* Num MPDUs truncated by PDG (TXOP, TBTT, 4356 * PPDU_duration based on rate, dyn_bw) 4357 */ 4358 s32 mpdus_truncated; 4359 4360 /* Num MPDUs that was tried but didn't receive ACK or BA */ 4361 s32 mpdus_ack_failed; 4362 4363 /* Num MPDUs that was dropped du to expiry. */ 4364 s32 mpdus_expired; 4365 } __packed; 4366 4367 struct wmi_pdev_stats_rx { 4368 /* Cnts any change in ring routing mid-ppdu */ 4369 s32 mid_ppdu_route_change; 4370 4371 /* Total number of statuses processed */ 4372 s32 status_rcvd; 4373 4374 /* Extra frags on rings 0-3 */ 4375 s32 r0_frags; 4376 s32 r1_frags; 4377 s32 r2_frags; 4378 s32 r3_frags; 4379 4380 /* MSDUs / MPDUs delivered to HTT */ 4381 s32 htt_msdus; 4382 s32 htt_mpdus; 4383 4384 /* MSDUs / MPDUs delivered to local stack */ 4385 s32 loc_msdus; 4386 s32 loc_mpdus; 4387 4388 /* AMSDUs that have more MSDUs than the status ring size */ 4389 s32 oversize_amsdu; 4390 4391 /* Number of PHY errors */ 4392 s32 phy_errs; 4393 4394 /* Number of PHY errors drops */ 4395 s32 phy_err_drop; 4396 4397 /* Number of mpdu errors - FCS, MIC, ENC etc. */ 4398 s32 mpdu_errs; 4399 4400 /* Num overflow errors */ 4401 s32 rx_ovfl_errs; 4402 } __packed; 4403 4404 struct wmi_pdev_stats { 4405 struct wmi_pdev_stats_base base; 4406 struct wmi_pdev_stats_tx tx; 4407 struct wmi_pdev_stats_rx rx; 4408 } __packed; 4409 4410 #define WLAN_MAX_AC 4 4411 #define MAX_TX_RATE_VALUES 10 4412 #define MAX_TX_RATE_VALUES 10 4413 4414 struct wmi_vdev_stats { 4415 u32 vdev_id; 4416 u32 beacon_snr; 4417 u32 data_snr; 4418 u32 num_tx_frames[WLAN_MAX_AC]; 4419 u32 num_rx_frames; 4420 u32 num_tx_frames_retries[WLAN_MAX_AC]; 4421 u32 num_tx_frames_failures[WLAN_MAX_AC]; 4422 u32 num_rts_fail; 4423 u32 num_rts_success; 4424 u32 num_rx_err; 4425 u32 num_rx_discard; 4426 u32 num_tx_not_acked; 4427 u32 tx_rate_history[MAX_TX_RATE_VALUES]; 4428 u32 beacon_rssi_history[MAX_TX_RATE_VALUES]; 4429 } __packed; 4430 4431 struct wmi_bcn_stats { 4432 u32 vdev_id; 4433 u32 tx_bcn_succ_cnt; 4434 u32 tx_bcn_outage_cnt; 4435 } __packed; 4436 4437 struct wmi_stats_event { 4438 u32 stats_id; 4439 u32 num_pdev_stats; 4440 u32 num_vdev_stats; 4441 u32 num_peer_stats; 4442 u32 num_bcnflt_stats; 4443 u32 num_chan_stats; 4444 u32 num_mib_stats; 4445 u32 pdev_id; 4446 u32 num_bcn_stats; 4447 u32 num_peer_extd_stats; 4448 u32 num_peer_extd2_stats; 4449 } __packed; 4450 4451 struct wmi_rssi_stats { 4452 u32 vdev_id; 4453 u32 rssi_avg_beacon[WMI_MAX_CHAINS]; 4454 u32 rssi_avg_data[WMI_MAX_CHAINS]; 4455 struct wmi_mac_addr peer_macaddr; 4456 } __packed; 4457 4458 struct wmi_per_chain_rssi_stats { 4459 u32 num_per_chain_rssi_stats; 4460 } __packed; 4461 4462 struct wmi_pdev_ctl_failsafe_chk_event { 4463 u32 pdev_id; 4464 u32 ctl_failsafe_status; 4465 } __packed; 4466 4467 struct wmi_pdev_csa_switch_ev { 4468 u32 pdev_id; 4469 u32 current_switch_count; 4470 u32 num_vdevs; 4471 } __packed; 4472 4473 struct wmi_pdev_radar_ev { 4474 u32 pdev_id; 4475 u32 detection_mode; 4476 u32 chan_freq; 4477 u32 chan_width; 4478 u32 detector_id; 4479 u32 segment_id; 4480 u32 timestamp; 4481 u32 is_chirp; 4482 s32 freq_offset; 4483 s32 sidx; 4484 } __packed; 4485 4486 struct wmi_pdev_temperature_event { 4487 /* temperature value in Celsius degree */ 4488 s32 temp; 4489 u32 pdev_id; 4490 } __packed; 4491 4492 #define WMI_RX_STATUS_OK 0x00 4493 #define WMI_RX_STATUS_ERR_CRC 0x01 4494 #define WMI_RX_STATUS_ERR_DECRYPT 0x08 4495 #define WMI_RX_STATUS_ERR_MIC 0x10 4496 #define WMI_RX_STATUS_ERR_KEY_CACHE_MISS 0x20 4497 4498 #define WLAN_MGMT_TXRX_HOST_MAX_ANTENNA 4 4499 4500 struct mgmt_rx_event_params { 4501 u32 chan_freq; 4502 u32 channel; 4503 u32 snr; 4504 u8 rssi_ctl[WLAN_MGMT_TXRX_HOST_MAX_ANTENNA]; 4505 u32 rate; 4506 enum wmi_phy_mode phy_mode; 4507 u32 buf_len; 4508 int status; 4509 u32 flags; 4510 int rssi; 4511 u32 tsf_delta; 4512 u8 pdev_id; 4513 }; 4514 4515 #define ATH_MAX_ANTENNA 4 4516 4517 struct wmi_mgmt_rx_hdr { 4518 u32 channel; 4519 u32 snr; 4520 u32 rate; 4521 u32 phy_mode; 4522 u32 buf_len; 4523 u32 status; 4524 u32 rssi_ctl[ATH_MAX_ANTENNA]; 4525 u32 flags; 4526 int rssi; 4527 u32 tsf_delta; 4528 u32 rx_tsf_l32; 4529 u32 rx_tsf_u32; 4530 u32 pdev_id; 4531 u32 chan_freq; 4532 } __packed; 4533 4534 #define MAX_ANTENNA_EIGHT 8 4535 4536 struct wmi_rssi_ctl_ext { 4537 u32 tlv_header; 4538 u32 rssi_ctl_ext[MAX_ANTENNA_EIGHT - ATH_MAX_ANTENNA]; 4539 }; 4540 4541 struct wmi_mgmt_tx_compl_event { 4542 u32 desc_id; 4543 u32 status; 4544 u32 pdev_id; 4545 } __packed; 4546 4547 struct wmi_scan_event { 4548 u32 event_type; /* %WMI_SCAN_EVENT_ */ 4549 u32 reason; /* %WMI_SCAN_REASON_ */ 4550 u32 channel_freq; /* only valid for WMI_SCAN_EVENT_FOREIGN_CHANNEL */ 4551 u32 scan_req_id; 4552 u32 scan_id; 4553 u32 vdev_id; 4554 /* TSF Timestamp when the scan event (%WMI_SCAN_EVENT_) is completed 4555 * In case of AP it is TSF of the AP vdev 4556 * In case of STA connected state, this is the TSF of the AP 4557 * In case of STA not connected, it will be the free running HW timer 4558 */ 4559 u32 tsf_timestamp; 4560 } __packed; 4561 4562 struct wmi_peer_sta_kickout_arg { 4563 const u8 *mac_addr; 4564 }; 4565 4566 struct wmi_peer_sta_kickout_event { 4567 struct wmi_mac_addr peer_macaddr; 4568 } __packed; 4569 4570 enum wmi_roam_reason { 4571 WMI_ROAM_REASON_BETTER_AP = 1, 4572 WMI_ROAM_REASON_BEACON_MISS = 2, 4573 WMI_ROAM_REASON_LOW_RSSI = 3, 4574 WMI_ROAM_REASON_SUITABLE_AP_FOUND = 4, 4575 WMI_ROAM_REASON_HO_FAILED = 5, 4576 4577 /* keep last */ 4578 WMI_ROAM_REASON_MAX, 4579 }; 4580 4581 struct wmi_roam_event { 4582 u32 vdev_id; 4583 u32 reason; 4584 u32 rssi; 4585 } __packed; 4586 4587 #define WMI_CHAN_INFO_START_RESP 0 4588 #define WMI_CHAN_INFO_END_RESP 1 4589 4590 struct wmi_chan_info_event { 4591 u32 err_code; 4592 u32 freq; 4593 u32 cmd_flags; 4594 u32 noise_floor; 4595 u32 rx_clear_count; 4596 u32 cycle_count; 4597 u32 chan_tx_pwr_range; 4598 u32 chan_tx_pwr_tp; 4599 u32 rx_frame_count; 4600 u32 my_bss_rx_cycle_count; 4601 u32 rx_11b_mode_data_duration; 4602 u32 tx_frame_cnt; 4603 u32 mac_clk_mhz; 4604 u32 vdev_id; 4605 } __packed; 4606 4607 struct ath11k_targ_cap { 4608 u32 phy_capability; 4609 u32 max_frag_entry; 4610 u32 num_rf_chains; 4611 u32 ht_cap_info; 4612 u32 vht_cap_info; 4613 u32 vht_supp_mcs; 4614 u32 hw_min_tx_power; 4615 u32 hw_max_tx_power; 4616 u32 sys_cap_info; 4617 u32 min_pkt_size_enable; 4618 u32 max_bcn_ie_size; 4619 u32 max_num_scan_channels; 4620 u32 max_supported_macs; 4621 u32 wmi_fw_sub_feat_caps; 4622 u32 txrx_chainmask; 4623 u32 default_dbs_hw_mode_index; 4624 u32 num_msdu_desc; 4625 }; 4626 4627 enum wmi_vdev_type { 4628 WMI_VDEV_TYPE_AP = 1, 4629 WMI_VDEV_TYPE_STA = 2, 4630 WMI_VDEV_TYPE_IBSS = 3, 4631 WMI_VDEV_TYPE_MONITOR = 4, 4632 }; 4633 4634 enum wmi_vdev_subtype { 4635 WMI_VDEV_SUBTYPE_NONE, 4636 WMI_VDEV_SUBTYPE_P2P_DEVICE, 4637 WMI_VDEV_SUBTYPE_P2P_CLIENT, 4638 WMI_VDEV_SUBTYPE_P2P_GO, 4639 WMI_VDEV_SUBTYPE_PROXY_STA, 4640 WMI_VDEV_SUBTYPE_MESH_NON_11S, 4641 WMI_VDEV_SUBTYPE_MESH_11S, 4642 }; 4643 4644 enum wmi_sta_powersave_param { 4645 WMI_STA_PS_PARAM_RX_WAKE_POLICY = 0, 4646 WMI_STA_PS_PARAM_TX_WAKE_THRESHOLD = 1, 4647 WMI_STA_PS_PARAM_PSPOLL_COUNT = 2, 4648 WMI_STA_PS_PARAM_INACTIVITY_TIME = 3, 4649 WMI_STA_PS_PARAM_UAPSD = 4, 4650 }; 4651 4652 #define WMI_UAPSD_AC_TYPE_DELI 0 4653 #define WMI_UAPSD_AC_TYPE_TRIG 1 4654 4655 #define WMI_UAPSD_AC_BIT_MASK(ac, type) \ 4656 ((type == WMI_UAPSD_AC_TYPE_DELI) ? \ 4657 (1 << (ac << 1)) : (1 << ((ac << 1) + 1))) 4658 4659 enum wmi_sta_ps_param_uapsd { 4660 WMI_STA_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0), 4661 WMI_STA_PS_UAPSD_AC0_TRIGGER_EN = (1 << 1), 4662 WMI_STA_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2), 4663 WMI_STA_PS_UAPSD_AC1_TRIGGER_EN = (1 << 3), 4664 WMI_STA_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4), 4665 WMI_STA_PS_UAPSD_AC2_TRIGGER_EN = (1 << 5), 4666 WMI_STA_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6), 4667 WMI_STA_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7), 4668 }; 4669 4670 #define WMI_STA_UAPSD_MAX_INTERVAL_MSEC UINT_MAX 4671 4672 struct wmi_sta_uapsd_auto_trig_param { 4673 u32 wmm_ac; 4674 u32 user_priority; 4675 u32 service_interval; 4676 u32 suspend_interval; 4677 u32 delay_interval; 4678 }; 4679 4680 struct wmi_sta_uapsd_auto_trig_cmd_fixed_param { 4681 u32 vdev_id; 4682 struct wmi_mac_addr peer_macaddr; 4683 u32 num_ac; 4684 }; 4685 4686 struct wmi_sta_uapsd_auto_trig_arg { 4687 u32 wmm_ac; 4688 u32 user_priority; 4689 u32 service_interval; 4690 u32 suspend_interval; 4691 u32 delay_interval; 4692 }; 4693 4694 enum wmi_sta_ps_param_tx_wake_threshold { 4695 WMI_STA_PS_TX_WAKE_THRESHOLD_NEVER = 0, 4696 WMI_STA_PS_TX_WAKE_THRESHOLD_ALWAYS = 1, 4697 4698 /* Values greater than one indicate that many TX attempts per beacon 4699 * interval before the STA will wake up 4700 */ 4701 }; 4702 4703 /* The maximum number of PS-Poll frames the FW will send in response to 4704 * traffic advertised in TIM before waking up (by sending a null frame with PS 4705 * = 0). Value 0 has a special meaning: there is no maximum count and the FW 4706 * will send as many PS-Poll as are necessary to retrieve buffered BU. This 4707 * parameter is used when the RX wake policy is 4708 * WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD and ignored when the RX wake 4709 * policy is WMI_STA_PS_RX_WAKE_POLICY_WAKE. 4710 */ 4711 enum wmi_sta_ps_param_pspoll_count { 4712 WMI_STA_PS_PSPOLL_COUNT_NO_MAX = 0, 4713 /* Values greater than 0 indicate the maximum number of PS-Poll frames 4714 * FW will send before waking up. 4715 */ 4716 }; 4717 4718 /* U-APSD configuration of peer station from (re)assoc request and TSPECs */ 4719 enum wmi_ap_ps_param_uapsd { 4720 WMI_AP_PS_UAPSD_AC0_DELIVERY_EN = (1 << 0), 4721 WMI_AP_PS_UAPSD_AC0_TRIGGER_EN = (1 << 1), 4722 WMI_AP_PS_UAPSD_AC1_DELIVERY_EN = (1 << 2), 4723 WMI_AP_PS_UAPSD_AC1_TRIGGER_EN = (1 << 3), 4724 WMI_AP_PS_UAPSD_AC2_DELIVERY_EN = (1 << 4), 4725 WMI_AP_PS_UAPSD_AC2_TRIGGER_EN = (1 << 5), 4726 WMI_AP_PS_UAPSD_AC3_DELIVERY_EN = (1 << 6), 4727 WMI_AP_PS_UAPSD_AC3_TRIGGER_EN = (1 << 7), 4728 }; 4729 4730 /* U-APSD maximum service period of peer station */ 4731 enum wmi_ap_ps_peer_param_max_sp { 4732 WMI_AP_PS_PEER_PARAM_MAX_SP_UNLIMITED = 0, 4733 WMI_AP_PS_PEER_PARAM_MAX_SP_2 = 1, 4734 WMI_AP_PS_PEER_PARAM_MAX_SP_4 = 2, 4735 WMI_AP_PS_PEER_PARAM_MAX_SP_6 = 3, 4736 MAX_WMI_AP_PS_PEER_PARAM_MAX_SP, 4737 }; 4738 4739 enum wmi_ap_ps_peer_param { 4740 /** Set uapsd configuration for a given peer. 4741 * 4742 * This include the delivery and trigger enabled state for each AC. 4743 * The host MLME needs to set this based on AP capability and stations 4744 * request Set in the association request received from the station. 4745 * 4746 * Lower 8 bits of the value specify the UAPSD configuration. 4747 * 4748 * (see enum wmi_ap_ps_param_uapsd) 4749 * The default value is 0. 4750 */ 4751 WMI_AP_PS_PEER_PARAM_UAPSD = 0, 4752 4753 /** 4754 * Set the service period for a UAPSD capable station 4755 * 4756 * The service period from wme ie in the (re)assoc request frame. 4757 * 4758 * (see enum wmi_ap_ps_peer_param_max_sp) 4759 */ 4760 WMI_AP_PS_PEER_PARAM_MAX_SP = 1, 4761 4762 /** Time in seconds for aging out buffered frames 4763 * for STA in power save 4764 */ 4765 WMI_AP_PS_PEER_PARAM_AGEOUT_TIME = 2, 4766 4767 /** Specify frame types that are considered SIFS 4768 * RESP trigger frame 4769 */ 4770 WMI_AP_PS_PEER_PARAM_SIFS_RESP_FRMTYPE = 3, 4771 4772 /** Specifies the trigger state of TID. 4773 * Valid only for UAPSD frame type 4774 */ 4775 WMI_AP_PS_PEER_PARAM_SIFS_RESP_UAPSD = 4, 4776 4777 /* Specifies the WNM sleep state of a STA */ 4778 WMI_AP_PS_PEER_PARAM_WNM_SLEEP = 5, 4779 }; 4780 4781 #define DISABLE_SIFS_RESPONSE_TRIGGER 0 4782 4783 #define WMI_MAX_KEY_INDEX 3 4784 #define WMI_MAX_KEY_LEN 32 4785 4786 #define WMI_KEY_PAIRWISE 0x00 4787 #define WMI_KEY_GROUP 0x01 4788 4789 #define WMI_CIPHER_NONE 0x0 /* clear key */ 4790 #define WMI_CIPHER_WEP 0x1 4791 #define WMI_CIPHER_TKIP 0x2 4792 #define WMI_CIPHER_AES_OCB 0x3 4793 #define WMI_CIPHER_AES_CCM 0x4 4794 #define WMI_CIPHER_WAPI 0x5 4795 #define WMI_CIPHER_CKIP 0x6 4796 #define WMI_CIPHER_AES_CMAC 0x7 4797 #define WMI_CIPHER_ANY 0x8 4798 #define WMI_CIPHER_AES_GCM 0x9 4799 #define WMI_CIPHER_AES_GMAC 0xa 4800 4801 /* Value to disable fixed rate setting */ 4802 #define WMI_FIXED_RATE_NONE (0xffff) 4803 4804 #define ATH11K_RC_VERSION_OFFSET 28 4805 #define ATH11K_RC_PREAMBLE_OFFSET 8 4806 #define ATH11K_RC_NSS_OFFSET 5 4807 4808 #define ATH11K_HW_RATE_CODE(rate, nss, preamble) \ 4809 ((1 << ATH11K_RC_VERSION_OFFSET) | \ 4810 ((nss) << ATH11K_RC_NSS_OFFSET) | \ 4811 ((preamble) << ATH11K_RC_PREAMBLE_OFFSET) | \ 4812 (rate)) 4813 4814 /* Preamble types to be used with VDEV fixed rate configuration */ 4815 enum wmi_rate_preamble { 4816 WMI_RATE_PREAMBLE_OFDM, 4817 WMI_RATE_PREAMBLE_CCK, 4818 WMI_RATE_PREAMBLE_HT, 4819 WMI_RATE_PREAMBLE_VHT, 4820 WMI_RATE_PREAMBLE_HE, 4821 }; 4822 4823 /** 4824 * enum wmi_rtscts_prot_mode - Enable/Disable RTS/CTS and CTS2Self Protection. 4825 * @WMI_RTS_CTS_DISABLED: RTS/CTS protection is disabled. 4826 * @WMI_USE_RTS_CTS: RTS/CTS Enabled. 4827 * @WMI_USE_CTS2SELF: CTS to self protection Enabled. 4828 */ 4829 enum wmi_rtscts_prot_mode { 4830 WMI_RTS_CTS_DISABLED = 0, 4831 WMI_USE_RTS_CTS = 1, 4832 WMI_USE_CTS2SELF = 2, 4833 }; 4834 4835 /** 4836 * enum wmi_rtscts_profile - Selection of RTS CTS profile along with enabling 4837 * protection mode. 4838 * @WMI_RTSCTS_FOR_NO_RATESERIES: Neither of rate-series should use RTS-CTS 4839 * @WMI_RTSCTS_FOR_SECOND_RATESERIES: Only second rate-series will use RTS-CTS 4840 * @WMI_RTSCTS_ACROSS_SW_RETRIES: Only the second rate-series will use RTS-CTS, 4841 * but if there's a sw retry, both the rate 4842 * series will use RTS-CTS. 4843 * @WMI_RTSCTS_ERP: RTS/CTS used for ERP protection for every PPDU. 4844 * @WMI_RTSCTS_FOR_ALL_RATESERIES: Enable RTS-CTS for all rate series. 4845 */ 4846 enum wmi_rtscts_profile { 4847 WMI_RTSCTS_FOR_NO_RATESERIES = 0, 4848 WMI_RTSCTS_FOR_SECOND_RATESERIES = 1, 4849 WMI_RTSCTS_ACROSS_SW_RETRIES = 2, 4850 WMI_RTSCTS_ERP = 3, 4851 WMI_RTSCTS_FOR_ALL_RATESERIES = 4, 4852 }; 4853 4854 struct ath11k_hal_reg_cap { 4855 u32 eeprom_rd; 4856 u32 eeprom_rd_ext; 4857 u32 regcap1; 4858 u32 regcap2; 4859 u32 wireless_modes; 4860 u32 low_2ghz_chan; 4861 u32 high_2ghz_chan; 4862 u32 low_5ghz_chan; 4863 u32 high_5ghz_chan; 4864 }; 4865 4866 struct ath11k_mem_chunk { 4867 void *vaddr; 4868 dma_addr_t paddr; 4869 u32 len; 4870 u32 req_id; 4871 }; 4872 4873 #define WMI_SKB_HEADROOM sizeof(struct wmi_cmd_hdr) 4874 4875 enum wmi_sta_ps_param_rx_wake_policy { 4876 WMI_STA_PS_RX_WAKE_POLICY_WAKE = 0, 4877 WMI_STA_PS_RX_WAKE_POLICY_POLL_UAPSD = 1, 4878 }; 4879 4880 /* Do not change existing values! Used by ath11k_frame_mode parameter 4881 * module parameter. 4882 */ 4883 enum ath11k_hw_txrx_mode { 4884 ATH11K_HW_TXRX_RAW = 0, 4885 ATH11K_HW_TXRX_NATIVE_WIFI = 1, 4886 ATH11K_HW_TXRX_ETHERNET = 2, 4887 }; 4888 4889 struct wmi_wmm_params { 4890 u32 tlv_header; 4891 u32 cwmin; 4892 u32 cwmax; 4893 u32 aifs; 4894 u32 txoplimit; 4895 u32 acm; 4896 u32 no_ack; 4897 } __packed; 4898 4899 struct wmi_wmm_params_arg { 4900 u8 acm; 4901 u8 aifs; 4902 u16 cwmin; 4903 u16 cwmax; 4904 u16 txop; 4905 u8 no_ack; 4906 }; 4907 4908 struct wmi_vdev_set_wmm_params_cmd { 4909 u32 tlv_header; 4910 u32 vdev_id; 4911 struct wmi_wmm_params wmm_params[4]; 4912 u32 wmm_param_type; 4913 } __packed; 4914 4915 struct wmi_wmm_params_all_arg { 4916 struct wmi_wmm_params_arg ac_be; 4917 struct wmi_wmm_params_arg ac_bk; 4918 struct wmi_wmm_params_arg ac_vi; 4919 struct wmi_wmm_params_arg ac_vo; 4920 }; 4921 4922 #define ATH11K_TWT_DEF_STA_CONG_TIMER_MS 5000 4923 #define ATH11K_TWT_DEF_DEFAULT_SLOT_SIZE 10 4924 #define ATH11K_TWT_DEF_CONGESTION_THRESH_SETUP 50 4925 #define ATH11K_TWT_DEF_CONGESTION_THRESH_TEARDOWN 20 4926 #define ATH11K_TWT_DEF_CONGESTION_THRESH_CRITICAL 100 4927 #define ATH11K_TWT_DEF_INTERFERENCE_THRESH_TEARDOWN 80 4928 #define ATH11K_TWT_DEF_INTERFERENCE_THRESH_SETUP 50 4929 #define ATH11K_TWT_DEF_MIN_NO_STA_SETUP 10 4930 #define ATH11K_TWT_DEF_MIN_NO_STA_TEARDOWN 2 4931 #define ATH11K_TWT_DEF_NO_OF_BCAST_MCAST_SLOTS 2 4932 #define ATH11K_TWT_DEF_MIN_NO_TWT_SLOTS 2 4933 #define ATH11K_TWT_DEF_MAX_NO_STA_TWT 500 4934 #define ATH11K_TWT_DEF_MODE_CHECK_INTERVAL 10000 4935 #define ATH11K_TWT_DEF_ADD_STA_SLOT_INTERVAL 1000 4936 #define ATH11K_TWT_DEF_REMOVE_STA_SLOT_INTERVAL 5000 4937 4938 struct wmi_twt_enable_params { 4939 u32 sta_cong_timer_ms; 4940 u32 mbss_support; 4941 u32 default_slot_size; 4942 u32 congestion_thresh_setup; 4943 u32 congestion_thresh_teardown; 4944 u32 congestion_thresh_critical; 4945 u32 interference_thresh_teardown; 4946 u32 interference_thresh_setup; 4947 u32 min_no_sta_setup; 4948 u32 min_no_sta_teardown; 4949 u32 no_of_bcast_mcast_slots; 4950 u32 min_no_twt_slots; 4951 u32 max_no_sta_twt; 4952 u32 mode_check_interval; 4953 u32 add_sta_slot_interval; 4954 u32 remove_sta_slot_interval; 4955 }; 4956 4957 struct wmi_twt_enable_params_cmd { 4958 u32 tlv_header; 4959 u32 pdev_id; 4960 u32 sta_cong_timer_ms; 4961 u32 mbss_support; 4962 u32 default_slot_size; 4963 u32 congestion_thresh_setup; 4964 u32 congestion_thresh_teardown; 4965 u32 congestion_thresh_critical; 4966 u32 interference_thresh_teardown; 4967 u32 interference_thresh_setup; 4968 u32 min_no_sta_setup; 4969 u32 min_no_sta_teardown; 4970 u32 no_of_bcast_mcast_slots; 4971 u32 min_no_twt_slots; 4972 u32 max_no_sta_twt; 4973 u32 mode_check_interval; 4974 u32 add_sta_slot_interval; 4975 u32 remove_sta_slot_interval; 4976 } __packed; 4977 4978 struct wmi_twt_disable_params_cmd { 4979 u32 tlv_header; 4980 u32 pdev_id; 4981 } __packed; 4982 4983 enum WMI_HOST_TWT_COMMAND { 4984 WMI_HOST_TWT_COMMAND_REQUEST_TWT = 0, 4985 WMI_HOST_TWT_COMMAND_SUGGEST_TWT, 4986 WMI_HOST_TWT_COMMAND_DEMAND_TWT, 4987 WMI_HOST_TWT_COMMAND_TWT_GROUPING, 4988 WMI_HOST_TWT_COMMAND_ACCEPT_TWT, 4989 WMI_HOST_TWT_COMMAND_ALTERNATE_TWT, 4990 WMI_HOST_TWT_COMMAND_DICTATE_TWT, 4991 WMI_HOST_TWT_COMMAND_REJECT_TWT, 4992 }; 4993 4994 #define WMI_TWT_ADD_DIALOG_FLAG_BCAST BIT(8) 4995 #define WMI_TWT_ADD_DIALOG_FLAG_TRIGGER BIT(9) 4996 #define WMI_TWT_ADD_DIALOG_FLAG_FLOW_TYPE BIT(10) 4997 #define WMI_TWT_ADD_DIALOG_FLAG_PROTECTION BIT(11) 4998 4999 struct wmi_twt_add_dialog_params_cmd { 5000 u32 tlv_header; 5001 u32 vdev_id; 5002 struct wmi_mac_addr peer_macaddr; 5003 u32 dialog_id; 5004 u32 wake_intvl_us; 5005 u32 wake_intvl_mantis; 5006 u32 wake_dura_us; 5007 u32 sp_offset_us; 5008 u32 flags; 5009 } __packed; 5010 5011 struct wmi_twt_add_dialog_params { 5012 u32 vdev_id; 5013 u8 peer_macaddr[ETH_ALEN]; 5014 u32 dialog_id; 5015 u32 wake_intvl_us; 5016 u32 wake_intvl_mantis; 5017 u32 wake_dura_us; 5018 u32 sp_offset_us; 5019 u8 twt_cmd; 5020 u8 flag_bcast; 5021 u8 flag_trigger; 5022 u8 flag_flow_type; 5023 u8 flag_protection; 5024 } __packed; 5025 5026 enum wmi_twt_add_dialog_status { 5027 WMI_ADD_TWT_STATUS_OK, 5028 WMI_ADD_TWT_STATUS_TWT_NOT_ENABLED, 5029 WMI_ADD_TWT_STATUS_USED_DIALOG_ID, 5030 WMI_ADD_TWT_STATUS_INVALID_PARAM, 5031 WMI_ADD_TWT_STATUS_NOT_READY, 5032 WMI_ADD_TWT_STATUS_NO_RESOURCE, 5033 WMI_ADD_TWT_STATUS_NO_ACK, 5034 WMI_ADD_TWT_STATUS_NO_RESPONSE, 5035 WMI_ADD_TWT_STATUS_DENIED, 5036 WMI_ADD_TWT_STATUS_UNKNOWN_ERROR, 5037 }; 5038 5039 struct wmi_twt_add_dialog_event { 5040 u32 vdev_id; 5041 struct wmi_mac_addr peer_macaddr; 5042 u32 dialog_id; 5043 u32 status; 5044 } __packed; 5045 5046 struct wmi_twt_del_dialog_params { 5047 u32 vdev_id; 5048 u8 peer_macaddr[ETH_ALEN]; 5049 u32 dialog_id; 5050 } __packed; 5051 5052 struct wmi_twt_del_dialog_params_cmd { 5053 u32 tlv_header; 5054 u32 vdev_id; 5055 struct wmi_mac_addr peer_macaddr; 5056 u32 dialog_id; 5057 } __packed; 5058 5059 struct wmi_twt_pause_dialog_params { 5060 u32 vdev_id; 5061 u8 peer_macaddr[ETH_ALEN]; 5062 u32 dialog_id; 5063 } __packed; 5064 5065 struct wmi_twt_pause_dialog_params_cmd { 5066 u32 tlv_header; 5067 u32 vdev_id; 5068 struct wmi_mac_addr peer_macaddr; 5069 u32 dialog_id; 5070 } __packed; 5071 5072 struct wmi_twt_resume_dialog_params { 5073 u32 vdev_id; 5074 u8 peer_macaddr[ETH_ALEN]; 5075 u32 dialog_id; 5076 u32 sp_offset_us; 5077 u32 next_twt_size; 5078 } __packed; 5079 5080 struct wmi_twt_resume_dialog_params_cmd { 5081 u32 tlv_header; 5082 u32 vdev_id; 5083 struct wmi_mac_addr peer_macaddr; 5084 u32 dialog_id; 5085 u32 sp_offset_us; 5086 u32 next_twt_size; 5087 } __packed; 5088 5089 struct wmi_obss_spatial_reuse_params_cmd { 5090 u32 tlv_header; 5091 u32 pdev_id; 5092 u32 enable; 5093 s32 obss_min; 5094 s32 obss_max; 5095 u32 vdev_id; 5096 } __packed; 5097 5098 struct wmi_pdev_obss_pd_bitmap_cmd { 5099 u32 tlv_header; 5100 u32 pdev_id; 5101 u32 bitmap[2]; 5102 } __packed; 5103 5104 #define ATH11K_BSS_COLOR_COLLISION_SCAN_PERIOD_MS 200 5105 #define ATH11K_OBSS_COLOR_COLLISION_DETECTION_DISABLE 0 5106 #define ATH11K_OBSS_COLOR_COLLISION_DETECTION 1 5107 5108 #define ATH11K_BSS_COLOR_COLLISION_DETECTION_STA_PERIOD_MS 10000 5109 #define ATH11K_BSS_COLOR_COLLISION_DETECTION_AP_PERIOD_MS 5000 5110 5111 enum wmi_bss_color_collision { 5112 WMI_BSS_COLOR_COLLISION_DISABLE = 0, 5113 WMI_BSS_COLOR_COLLISION_DETECTION, 5114 WMI_BSS_COLOR_FREE_SLOT_TIMER_EXPIRY, 5115 WMI_BSS_COLOR_FREE_SLOT_AVAILABLE, 5116 }; 5117 5118 struct wmi_obss_color_collision_cfg_params_cmd { 5119 u32 tlv_header; 5120 u32 vdev_id; 5121 u32 flags; 5122 u32 evt_type; 5123 u32 current_bss_color; 5124 u32 detection_period_ms; 5125 u32 scan_period_ms; 5126 u32 free_slot_expiry_time_ms; 5127 } __packed; 5128 5129 struct wmi_bss_color_change_enable_params_cmd { 5130 u32 tlv_header; 5131 u32 vdev_id; 5132 u32 enable; 5133 } __packed; 5134 5135 struct wmi_obss_color_collision_event { 5136 u32 vdev_id; 5137 u32 evt_type; 5138 u64 obss_color_bitmap; 5139 } __packed; 5140 5141 #define ATH11K_IPV4_TH_SEED_SIZE 5 5142 #define ATH11K_IPV6_TH_SEED_SIZE 11 5143 5144 struct ath11k_wmi_pdev_lro_config_cmd { 5145 u32 tlv_header; 5146 u32 lro_enable; 5147 u32 res; 5148 u32 th_4[ATH11K_IPV4_TH_SEED_SIZE]; 5149 u32 th_6[ATH11K_IPV6_TH_SEED_SIZE]; 5150 u32 pdev_id; 5151 } __packed; 5152 5153 #define ATH11K_WMI_SPECTRAL_COUNT_DEFAULT 0 5154 #define ATH11K_WMI_SPECTRAL_PERIOD_DEFAULT 224 5155 #define ATH11K_WMI_SPECTRAL_PRIORITY_DEFAULT 1 5156 #define ATH11K_WMI_SPECTRAL_FFT_SIZE_DEFAULT 7 5157 #define ATH11K_WMI_SPECTRAL_GC_ENA_DEFAULT 1 5158 #define ATH11K_WMI_SPECTRAL_RESTART_ENA_DEFAULT 0 5159 #define ATH11K_WMI_SPECTRAL_NOISE_FLOOR_REF_DEFAULT -96 5160 #define ATH11K_WMI_SPECTRAL_INIT_DELAY_DEFAULT 80 5161 #define ATH11K_WMI_SPECTRAL_NB_TONE_THR_DEFAULT 12 5162 #define ATH11K_WMI_SPECTRAL_STR_BIN_THR_DEFAULT 8 5163 #define ATH11K_WMI_SPECTRAL_WB_RPT_MODE_DEFAULT 0 5164 #define ATH11K_WMI_SPECTRAL_RSSI_RPT_MODE_DEFAULT 0 5165 #define ATH11K_WMI_SPECTRAL_RSSI_THR_DEFAULT 0xf0 5166 #define ATH11K_WMI_SPECTRAL_PWR_FORMAT_DEFAULT 0 5167 #define ATH11K_WMI_SPECTRAL_RPT_MODE_DEFAULT 2 5168 #define ATH11K_WMI_SPECTRAL_BIN_SCALE_DEFAULT 1 5169 #define ATH11K_WMI_SPECTRAL_DBM_ADJ_DEFAULT 1 5170 #define ATH11K_WMI_SPECTRAL_CHN_MASK_DEFAULT 1 5171 5172 struct ath11k_wmi_vdev_spectral_conf_param { 5173 u32 vdev_id; 5174 u32 scan_count; 5175 u32 scan_period; 5176 u32 scan_priority; 5177 u32 scan_fft_size; 5178 u32 scan_gc_ena; 5179 u32 scan_restart_ena; 5180 u32 scan_noise_floor_ref; 5181 u32 scan_init_delay; 5182 u32 scan_nb_tone_thr; 5183 u32 scan_str_bin_thr; 5184 u32 scan_wb_rpt_mode; 5185 u32 scan_rssi_rpt_mode; 5186 u32 scan_rssi_thr; 5187 u32 scan_pwr_format; 5188 u32 scan_rpt_mode; 5189 u32 scan_bin_scale; 5190 u32 scan_dbm_adj; 5191 u32 scan_chn_mask; 5192 } __packed; 5193 5194 struct ath11k_wmi_vdev_spectral_conf_cmd { 5195 u32 tlv_header; 5196 struct ath11k_wmi_vdev_spectral_conf_param param; 5197 } __packed; 5198 5199 #define ATH11K_WMI_SPECTRAL_TRIGGER_CMD_TRIGGER 1 5200 #define ATH11K_WMI_SPECTRAL_TRIGGER_CMD_CLEAR 2 5201 #define ATH11K_WMI_SPECTRAL_ENABLE_CMD_ENABLE 1 5202 #define ATH11K_WMI_SPECTRAL_ENABLE_CMD_DISABLE 2 5203 5204 struct ath11k_wmi_vdev_spectral_enable_cmd { 5205 u32 tlv_header; 5206 u32 vdev_id; 5207 u32 trigger_cmd; 5208 u32 enable_cmd; 5209 } __packed; 5210 5211 struct ath11k_wmi_pdev_dma_ring_cfg_req_cmd { 5212 u32 tlv_header; 5213 u32 pdev_id; 5214 u32 module_id; /* see enum wmi_direct_buffer_module */ 5215 u32 base_paddr_lo; 5216 u32 base_paddr_hi; 5217 u32 head_idx_paddr_lo; 5218 u32 head_idx_paddr_hi; 5219 u32 tail_idx_paddr_lo; 5220 u32 tail_idx_paddr_hi; 5221 u32 num_elems; /* Number of elems in the ring */ 5222 u32 buf_size; /* size of allocated buffer in bytes */ 5223 5224 /* Number of wmi_dma_buf_release_entry packed together */ 5225 u32 num_resp_per_event; 5226 5227 /* Target should timeout and send whatever resp 5228 * it has if this time expires, units in milliseconds 5229 */ 5230 u32 event_timeout_ms; 5231 } __packed; 5232 5233 struct ath11k_wmi_dma_buf_release_fixed_param { 5234 u32 pdev_id; 5235 u32 module_id; 5236 u32 num_buf_release_entry; 5237 u32 num_meta_data_entry; 5238 } __packed; 5239 5240 struct wmi_dma_buf_release_entry { 5241 u32 tlv_header; 5242 u32 paddr_lo; 5243 5244 /* Bits 11:0: address of data 5245 * Bits 31:12: host context data 5246 */ 5247 u32 paddr_hi; 5248 } __packed; 5249 5250 #define WMI_SPECTRAL_META_INFO1_FREQ1 GENMASK(15, 0) 5251 #define WMI_SPECTRAL_META_INFO1_FREQ2 GENMASK(31, 16) 5252 5253 #define WMI_SPECTRAL_META_INFO2_CHN_WIDTH GENMASK(7, 0) 5254 5255 struct wmi_dma_buf_release_meta_data { 5256 u32 tlv_header; 5257 s32 noise_floor[WMI_MAX_CHAINS]; 5258 u32 reset_delay; 5259 u32 freq1; 5260 u32 freq2; 5261 u32 ch_width; 5262 } __packed; 5263 5264 enum wmi_fils_discovery_cmd_type { 5265 WMI_FILS_DISCOVERY_CMD, 5266 WMI_UNSOL_BCAST_PROBE_RESP, 5267 }; 5268 5269 struct wmi_fils_discovery_cmd { 5270 u32 tlv_header; 5271 u32 vdev_id; 5272 u32 interval; 5273 u32 config; /* enum wmi_fils_discovery_cmd_type */ 5274 } __packed; 5275 5276 struct wmi_fils_discovery_tmpl_cmd { 5277 u32 tlv_header; 5278 u32 vdev_id; 5279 u32 buf_len; 5280 } __packed; 5281 5282 struct wmi_probe_tmpl_cmd { 5283 u32 tlv_header; 5284 u32 vdev_id; 5285 u32 buf_len; 5286 } __packed; 5287 5288 struct target_resource_config { 5289 u32 num_vdevs; 5290 u32 num_peers; 5291 u32 num_active_peers; 5292 u32 num_offload_peers; 5293 u32 num_offload_reorder_buffs; 5294 u32 num_peer_keys; 5295 u32 num_tids; 5296 u32 ast_skid_limit; 5297 u32 tx_chain_mask; 5298 u32 rx_chain_mask; 5299 u32 rx_timeout_pri[4]; 5300 u32 rx_decap_mode; 5301 u32 scan_max_pending_req; 5302 u32 bmiss_offload_max_vdev; 5303 u32 roam_offload_max_vdev; 5304 u32 roam_offload_max_ap_profiles; 5305 u32 num_mcast_groups; 5306 u32 num_mcast_table_elems; 5307 u32 mcast2ucast_mode; 5308 u32 tx_dbg_log_size; 5309 u32 num_wds_entries; 5310 u32 dma_burst_size; 5311 u32 mac_aggr_delim; 5312 u32 rx_skip_defrag_timeout_dup_detection_check; 5313 u32 vow_config; 5314 u32 gtk_offload_max_vdev; 5315 u32 num_msdu_desc; 5316 u32 max_frag_entries; 5317 u32 max_peer_ext_stats; 5318 u32 smart_ant_cap; 5319 u32 bk_minfree; 5320 u32 be_minfree; 5321 u32 vi_minfree; 5322 u32 vo_minfree; 5323 u32 rx_batchmode; 5324 u32 tt_support; 5325 u32 flag1; 5326 u32 iphdr_pad_config; 5327 u32 qwrap_config:16, 5328 alloc_frag_desc_for_data_pkt:16; 5329 u32 num_tdls_vdevs; 5330 u32 num_tdls_conn_table_entries; 5331 u32 beacon_tx_offload_max_vdev; 5332 u32 num_multicast_filter_entries; 5333 u32 num_wow_filters; 5334 u32 num_keep_alive_pattern; 5335 u32 keep_alive_pattern_size; 5336 u32 max_tdls_concurrent_sleep_sta; 5337 u32 max_tdls_concurrent_buffer_sta; 5338 u32 wmi_send_separate; 5339 u32 num_ocb_vdevs; 5340 u32 num_ocb_channels; 5341 u32 num_ocb_schedules; 5342 u32 num_ns_ext_tuples_cfg; 5343 u32 bpf_instruction_size; 5344 u32 max_bssid_rx_filters; 5345 u32 use_pdev_id; 5346 u32 peer_map_unmap_v2_support; 5347 u32 sched_params; 5348 u32 twt_ap_pdev_count; 5349 u32 twt_ap_sta_count; 5350 }; 5351 5352 enum wmi_debug_log_param { 5353 WMI_DEBUG_LOG_PARAM_LOG_LEVEL = 0x1, 5354 WMI_DEBUG_LOG_PARAM_VDEV_ENABLE, 5355 WMI_DEBUG_LOG_PARAM_VDEV_DISABLE, 5356 WMI_DEBUG_LOG_PARAM_VDEV_ENABLE_BITMAP, 5357 WMI_DEBUG_LOG_PARAM_MOD_ENABLE_BITMAP, 5358 WMI_DEBUG_LOG_PARAM_WOW_MOD_ENABLE_BITMAP, 5359 }; 5360 5361 struct wmi_debug_log_config_cmd_fixed_param { 5362 u32 tlv_header; 5363 u32 dbg_log_param; 5364 u32 value; 5365 } __packed; 5366 5367 #define WMI_MAX_MEM_REQS 32 5368 5369 #define MAX_RADIOS 3 5370 5371 #define WMI_SERVICE_READY_TIMEOUT_HZ (5 * HZ) 5372 #define WMI_SEND_TIMEOUT_HZ (3 * HZ) 5373 5374 enum ath11k_wmi_peer_ps_state { 5375 WMI_PEER_PS_STATE_OFF, 5376 WMI_PEER_PS_STATE_ON, 5377 WMI_PEER_PS_STATE_DISABLED, 5378 }; 5379 5380 enum wmi_peer_ps_supported_bitmap { 5381 /* Used to indicate that power save state change is valid */ 5382 WMI_PEER_PS_VALID = 0x1, 5383 WMI_PEER_PS_STATE_TIMESTAMP = 0x2, 5384 }; 5385 5386 struct wmi_peer_sta_ps_state_chg_event { 5387 struct wmi_mac_addr peer_macaddr; 5388 u32 peer_ps_state; 5389 u32 ps_supported_bitmap; 5390 u32 peer_ps_valid; 5391 u32 peer_ps_timestamp; 5392 } __packed; 5393 5394 struct ath11k_wmi_base { 5395 struct ath11k_base *ab; 5396 struct ath11k_pdev_wmi wmi[MAX_RADIOS]; 5397 enum ath11k_htc_ep_id wmi_endpoint_id[MAX_RADIOS]; 5398 u32 max_msg_len[MAX_RADIOS]; 5399 5400 struct completion service_ready; 5401 struct completion unified_ready; 5402 DECLARE_BITMAP(svc_map, WMI_MAX_EXT2_SERVICE); 5403 wait_queue_head_t tx_credits_wq; 5404 const struct wmi_peer_flags_map *peer_flags; 5405 u32 num_mem_chunks; 5406 u32 rx_decap_mode; 5407 struct wmi_host_mem_chunk mem_chunks[WMI_MAX_MEM_REQS]; 5408 5409 enum wmi_host_hw_mode_config_type preferred_hw_mode; 5410 struct target_resource_config wlan_resource_config; 5411 5412 struct ath11k_targ_cap *targ_cap; 5413 }; 5414 5415 /* Definition of HW data filtering */ 5416 enum hw_data_filter_type { 5417 WMI_HW_DATA_FILTER_DROP_NON_ARP_BC = BIT(0), 5418 WMI_HW_DATA_FILTER_DROP_NON_ICMPV6_MC = BIT(1), 5419 }; 5420 5421 struct wmi_hw_data_filter_cmd { 5422 u32 tlv_header; 5423 u32 vdev_id; 5424 u32 enable; 5425 u32 hw_filter_bitmap; 5426 } __packed; 5427 5428 /* WOW structures */ 5429 enum wmi_wow_wakeup_event { 5430 WOW_BMISS_EVENT = 0, 5431 WOW_BETTER_AP_EVENT, 5432 WOW_DEAUTH_RECVD_EVENT, 5433 WOW_MAGIC_PKT_RECVD_EVENT, 5434 WOW_GTK_ERR_EVENT, 5435 WOW_FOURWAY_HSHAKE_EVENT, 5436 WOW_EAPOL_RECVD_EVENT, 5437 WOW_NLO_DETECTED_EVENT, 5438 WOW_DISASSOC_RECVD_EVENT, 5439 WOW_PATTERN_MATCH_EVENT, 5440 WOW_CSA_IE_EVENT, 5441 WOW_PROBE_REQ_WPS_IE_EVENT, 5442 WOW_AUTH_REQ_EVENT, 5443 WOW_ASSOC_REQ_EVENT, 5444 WOW_HTT_EVENT, 5445 WOW_RA_MATCH_EVENT, 5446 WOW_HOST_AUTO_SHUTDOWN_EVENT, 5447 WOW_IOAC_MAGIC_EVENT, 5448 WOW_IOAC_SHORT_EVENT, 5449 WOW_IOAC_EXTEND_EVENT, 5450 WOW_IOAC_TIMER_EVENT, 5451 WOW_DFS_PHYERR_RADAR_EVENT, 5452 WOW_BEACON_EVENT, 5453 WOW_CLIENT_KICKOUT_EVENT, 5454 WOW_EVENT_MAX, 5455 }; 5456 5457 enum wmi_wow_interface_cfg { 5458 WOW_IFACE_PAUSE_ENABLED, 5459 WOW_IFACE_PAUSE_DISABLED 5460 }; 5461 5462 #define C2S(x) case x: return #x 5463 5464 static inline const char *wow_wakeup_event(enum wmi_wow_wakeup_event ev) 5465 { 5466 switch (ev) { 5467 C2S(WOW_BMISS_EVENT); 5468 C2S(WOW_BETTER_AP_EVENT); 5469 C2S(WOW_DEAUTH_RECVD_EVENT); 5470 C2S(WOW_MAGIC_PKT_RECVD_EVENT); 5471 C2S(WOW_GTK_ERR_EVENT); 5472 C2S(WOW_FOURWAY_HSHAKE_EVENT); 5473 C2S(WOW_EAPOL_RECVD_EVENT); 5474 C2S(WOW_NLO_DETECTED_EVENT); 5475 C2S(WOW_DISASSOC_RECVD_EVENT); 5476 C2S(WOW_PATTERN_MATCH_EVENT); 5477 C2S(WOW_CSA_IE_EVENT); 5478 C2S(WOW_PROBE_REQ_WPS_IE_EVENT); 5479 C2S(WOW_AUTH_REQ_EVENT); 5480 C2S(WOW_ASSOC_REQ_EVENT); 5481 C2S(WOW_HTT_EVENT); 5482 C2S(WOW_RA_MATCH_EVENT); 5483 C2S(WOW_HOST_AUTO_SHUTDOWN_EVENT); 5484 C2S(WOW_IOAC_MAGIC_EVENT); 5485 C2S(WOW_IOAC_SHORT_EVENT); 5486 C2S(WOW_IOAC_EXTEND_EVENT); 5487 C2S(WOW_IOAC_TIMER_EVENT); 5488 C2S(WOW_DFS_PHYERR_RADAR_EVENT); 5489 C2S(WOW_BEACON_EVENT); 5490 C2S(WOW_CLIENT_KICKOUT_EVENT); 5491 C2S(WOW_EVENT_MAX); 5492 default: 5493 return NULL; 5494 } 5495 } 5496 5497 enum wmi_wow_wake_reason { 5498 WOW_REASON_UNSPECIFIED = -1, 5499 WOW_REASON_NLOD = 0, 5500 WOW_REASON_AP_ASSOC_LOST, 5501 WOW_REASON_LOW_RSSI, 5502 WOW_REASON_DEAUTH_RECVD, 5503 WOW_REASON_DISASSOC_RECVD, 5504 WOW_REASON_GTK_HS_ERR, 5505 WOW_REASON_EAP_REQ, 5506 WOW_REASON_FOURWAY_HS_RECV, 5507 WOW_REASON_TIMER_INTR_RECV, 5508 WOW_REASON_PATTERN_MATCH_FOUND, 5509 WOW_REASON_RECV_MAGIC_PATTERN, 5510 WOW_REASON_P2P_DISC, 5511 WOW_REASON_WLAN_HB, 5512 WOW_REASON_CSA_EVENT, 5513 WOW_REASON_PROBE_REQ_WPS_IE_RECV, 5514 WOW_REASON_AUTH_REQ_RECV, 5515 WOW_REASON_ASSOC_REQ_RECV, 5516 WOW_REASON_HTT_EVENT, 5517 WOW_REASON_RA_MATCH, 5518 WOW_REASON_HOST_AUTO_SHUTDOWN, 5519 WOW_REASON_IOAC_MAGIC_EVENT, 5520 WOW_REASON_IOAC_SHORT_EVENT, 5521 WOW_REASON_IOAC_EXTEND_EVENT, 5522 WOW_REASON_IOAC_TIMER_EVENT, 5523 WOW_REASON_ROAM_HO, 5524 WOW_REASON_DFS_PHYERR_RADADR_EVENT, 5525 WOW_REASON_BEACON_RECV, 5526 WOW_REASON_CLIENT_KICKOUT_EVENT, 5527 WOW_REASON_PAGE_FAULT = 0x3a, 5528 WOW_REASON_DEBUG_TEST = 0xFF, 5529 }; 5530 5531 static inline const char *wow_reason(enum wmi_wow_wake_reason reason) 5532 { 5533 switch (reason) { 5534 C2S(WOW_REASON_UNSPECIFIED); 5535 C2S(WOW_REASON_NLOD); 5536 C2S(WOW_REASON_AP_ASSOC_LOST); 5537 C2S(WOW_REASON_LOW_RSSI); 5538 C2S(WOW_REASON_DEAUTH_RECVD); 5539 C2S(WOW_REASON_DISASSOC_RECVD); 5540 C2S(WOW_REASON_GTK_HS_ERR); 5541 C2S(WOW_REASON_EAP_REQ); 5542 C2S(WOW_REASON_FOURWAY_HS_RECV); 5543 C2S(WOW_REASON_TIMER_INTR_RECV); 5544 C2S(WOW_REASON_PATTERN_MATCH_FOUND); 5545 C2S(WOW_REASON_RECV_MAGIC_PATTERN); 5546 C2S(WOW_REASON_P2P_DISC); 5547 C2S(WOW_REASON_WLAN_HB); 5548 C2S(WOW_REASON_CSA_EVENT); 5549 C2S(WOW_REASON_PROBE_REQ_WPS_IE_RECV); 5550 C2S(WOW_REASON_AUTH_REQ_RECV); 5551 C2S(WOW_REASON_ASSOC_REQ_RECV); 5552 C2S(WOW_REASON_HTT_EVENT); 5553 C2S(WOW_REASON_RA_MATCH); 5554 C2S(WOW_REASON_HOST_AUTO_SHUTDOWN); 5555 C2S(WOW_REASON_IOAC_MAGIC_EVENT); 5556 C2S(WOW_REASON_IOAC_SHORT_EVENT); 5557 C2S(WOW_REASON_IOAC_EXTEND_EVENT); 5558 C2S(WOW_REASON_IOAC_TIMER_EVENT); 5559 C2S(WOW_REASON_ROAM_HO); 5560 C2S(WOW_REASON_DFS_PHYERR_RADADR_EVENT); 5561 C2S(WOW_REASON_BEACON_RECV); 5562 C2S(WOW_REASON_CLIENT_KICKOUT_EVENT); 5563 C2S(WOW_REASON_PAGE_FAULT); 5564 C2S(WOW_REASON_DEBUG_TEST); 5565 default: 5566 return NULL; 5567 } 5568 } 5569 5570 #undef C2S 5571 5572 struct wmi_wow_ev_arg { 5573 u32 vdev_id; 5574 u32 flag; 5575 enum wmi_wow_wake_reason wake_reason; 5576 u32 data_len; 5577 }; 5578 5579 enum wmi_tlv_pattern_type { 5580 WOW_PATTERN_MIN = 0, 5581 WOW_BITMAP_PATTERN = WOW_PATTERN_MIN, 5582 WOW_IPV4_SYNC_PATTERN, 5583 WOW_IPV6_SYNC_PATTERN, 5584 WOW_WILD_CARD_PATTERN, 5585 WOW_TIMER_PATTERN, 5586 WOW_MAGIC_PATTERN, 5587 WOW_IPV6_RA_PATTERN, 5588 WOW_IOAC_PKT_PATTERN, 5589 WOW_IOAC_TMR_PATTERN, 5590 WOW_PATTERN_MAX 5591 }; 5592 5593 #define WOW_DEFAULT_BITMAP_PATTERN_SIZE 148 5594 #define WOW_DEFAULT_BITMASK_SIZE 148 5595 5596 #define WOW_MIN_PATTERN_SIZE 1 5597 #define WOW_MAX_PATTERN_SIZE 148 5598 #define WOW_MAX_PKT_OFFSET 128 5599 #define WOW_HDR_LEN (sizeof(struct ieee80211_hdr_3addr) + \ 5600 sizeof(struct rfc1042_hdr)) 5601 #define WOW_MAX_REDUCE (WOW_HDR_LEN - sizeof(struct ethhdr) - \ 5602 offsetof(struct ieee80211_hdr_3addr, addr1)) 5603 5604 struct wmi_wow_add_del_event_cmd { 5605 u32 tlv_header; 5606 u32 vdev_id; 5607 u32 is_add; 5608 u32 event_bitmap; 5609 } __packed; 5610 5611 struct wmi_wow_enable_cmd { 5612 u32 tlv_header; 5613 u32 enable; 5614 u32 pause_iface_config; 5615 u32 flags; 5616 } __packed; 5617 5618 struct wmi_wow_host_wakeup_ind { 5619 u32 tlv_header; 5620 u32 reserved; 5621 } __packed; 5622 5623 struct wmi_tlv_wow_event_info { 5624 u32 vdev_id; 5625 u32 flag; 5626 u32 wake_reason; 5627 u32 data_len; 5628 } __packed; 5629 5630 struct wmi_wow_bitmap_pattern { 5631 u32 tlv_header; 5632 u8 patternbuf[WOW_DEFAULT_BITMAP_PATTERN_SIZE]; 5633 u8 bitmaskbuf[WOW_DEFAULT_BITMASK_SIZE]; 5634 u32 pattern_offset; 5635 u32 pattern_len; 5636 u32 bitmask_len; 5637 u32 pattern_id; 5638 } __packed; 5639 5640 struct wmi_wow_add_pattern_cmd { 5641 u32 tlv_header; 5642 u32 vdev_id; 5643 u32 pattern_id; 5644 u32 pattern_type; 5645 } __packed; 5646 5647 struct wmi_wow_del_pattern_cmd { 5648 u32 tlv_header; 5649 u32 vdev_id; 5650 u32 pattern_id; 5651 u32 pattern_type; 5652 } __packed; 5653 5654 #define WMI_PNO_MAX_SCHED_SCAN_PLANS 2 5655 #define WMI_PNO_MAX_SCHED_SCAN_PLAN_INT 7200 5656 #define WMI_PNO_MAX_SCHED_SCAN_PLAN_ITRNS 100 5657 #define WMI_PNO_MAX_NETW_CHANNELS 26 5658 #define WMI_PNO_MAX_NETW_CHANNELS_EX 60 5659 #define WMI_PNO_MAX_SUPP_NETWORKS WLAN_SCAN_PARAMS_MAX_SSID 5660 #define WMI_PNO_MAX_IE_LENGTH WLAN_SCAN_PARAMS_MAX_IE_LEN 5661 5662 /* size based of dot11 declaration without extra IEs as we will not carry those for PNO */ 5663 #define WMI_PNO_MAX_PB_REQ_SIZE 450 5664 5665 #define WMI_PNO_24G_DEFAULT_CH 1 5666 #define WMI_PNO_5G_DEFAULT_CH 36 5667 5668 #define WMI_ACTIVE_MAX_CHANNEL_TIME 40 5669 #define WMI_PASSIVE_MAX_CHANNEL_TIME 110 5670 5671 /* SSID broadcast type */ 5672 enum wmi_ssid_bcast_type { 5673 BCAST_UNKNOWN = 0, 5674 BCAST_NORMAL = 1, 5675 BCAST_HIDDEN = 2, 5676 }; 5677 5678 #define WMI_NLO_MAX_SSIDS 16 5679 #define WMI_NLO_MAX_CHAN 48 5680 5681 #define WMI_NLO_CONFIG_STOP BIT(0) 5682 #define WMI_NLO_CONFIG_START BIT(1) 5683 #define WMI_NLO_CONFIG_RESET BIT(2) 5684 #define WMI_NLO_CONFIG_SLOW_SCAN BIT(4) 5685 #define WMI_NLO_CONFIG_FAST_SCAN BIT(5) 5686 #define WMI_NLO_CONFIG_SSID_HIDE_EN BIT(6) 5687 5688 /* This bit is used to indicate if EPNO or supplicant PNO is enabled. 5689 * Only one of them can be enabled at a given time 5690 */ 5691 #define WMI_NLO_CONFIG_ENLO BIT(7) 5692 #define WMI_NLO_CONFIG_SCAN_PASSIVE BIT(8) 5693 #define WMI_NLO_CONFIG_ENLO_RESET BIT(9) 5694 #define WMI_NLO_CONFIG_SPOOFED_MAC_IN_PROBE_REQ BIT(10) 5695 #define WMI_NLO_CONFIG_RANDOM_SEQ_NO_IN_PROBE_REQ BIT(11) 5696 #define WMI_NLO_CONFIG_ENABLE_IE_WHITELIST_IN_PROBE_REQ BIT(12) 5697 #define WMI_NLO_CONFIG_ENABLE_CNLO_RSSI_CONFIG BIT(13) 5698 5699 struct wmi_nlo_ssid_param { 5700 u32 valid; 5701 struct wmi_ssid ssid; 5702 } __packed; 5703 5704 struct wmi_nlo_enc_param { 5705 u32 valid; 5706 u32 enc_type; 5707 } __packed; 5708 5709 struct wmi_nlo_auth_param { 5710 u32 valid; 5711 u32 auth_type; 5712 } __packed; 5713 5714 struct wmi_nlo_bcast_nw_param { 5715 u32 valid; 5716 u32 bcast_nw_type; 5717 } __packed; 5718 5719 struct wmi_nlo_rssi_param { 5720 u32 valid; 5721 s32 rssi; 5722 } __packed; 5723 5724 struct nlo_configured_parameters { 5725 /* TLV tag and len;*/ 5726 u32 tlv_header; 5727 struct wmi_nlo_ssid_param ssid; 5728 struct wmi_nlo_enc_param enc_type; 5729 struct wmi_nlo_auth_param auth_type; 5730 struct wmi_nlo_rssi_param rssi_cond; 5731 5732 /* indicates if the SSID is hidden or not */ 5733 struct wmi_nlo_bcast_nw_param bcast_nw_type; 5734 } __packed; 5735 5736 struct wmi_network_type { 5737 struct wmi_ssid ssid; 5738 u32 authentication; 5739 u32 encryption; 5740 u32 bcast_nw_type; 5741 u8 channel_count; 5742 u16 channels[WMI_PNO_MAX_NETW_CHANNELS_EX]; 5743 s32 rssi_threshold; 5744 }; 5745 5746 struct wmi_pno_scan_req { 5747 u8 enable; 5748 u8 vdev_id; 5749 u8 uc_networks_count; 5750 struct wmi_network_type a_networks[WMI_PNO_MAX_SUPP_NETWORKS]; 5751 u32 fast_scan_period; 5752 u32 slow_scan_period; 5753 u8 fast_scan_max_cycles; 5754 5755 bool do_passive_scan; 5756 5757 u32 delay_start_time; 5758 u32 active_min_time; 5759 u32 active_max_time; 5760 u32 passive_min_time; 5761 u32 passive_max_time; 5762 5763 /* mac address randomization attributes */ 5764 u32 enable_pno_scan_randomization; 5765 u8 mac_addr[ETH_ALEN]; 5766 u8 mac_addr_mask[ETH_ALEN]; 5767 }; 5768 5769 struct wmi_wow_nlo_config_cmd { 5770 u32 tlv_header; 5771 u32 flags; 5772 u32 vdev_id; 5773 u32 fast_scan_max_cycles; 5774 u32 active_dwell_time; 5775 u32 passive_dwell_time; 5776 u32 probe_bundle_size; 5777 5778 /* ART = IRT */ 5779 u32 rest_time; 5780 5781 /* Max value that can be reached after SBM */ 5782 u32 max_rest_time; 5783 5784 /* SBM */ 5785 u32 scan_backoff_multiplier; 5786 5787 /* SCBM */ 5788 u32 fast_scan_period; 5789 5790 /* specific to windows */ 5791 u32 slow_scan_period; 5792 5793 u32 no_of_ssids; 5794 5795 u32 num_of_channels; 5796 5797 /* NLO scan start delay time in milliseconds */ 5798 u32 delay_start_time; 5799 5800 /* MAC Address to use in Probe Req as SA */ 5801 struct wmi_mac_addr mac_addr; 5802 5803 /* Mask on which MAC has to be randomized */ 5804 struct wmi_mac_addr mac_mask; 5805 5806 /* IE bitmap to use in Probe Req */ 5807 u32 ie_bitmap[8]; 5808 5809 /* Number of vendor OUIs. In the TLV vendor_oui[] */ 5810 u32 num_vendor_oui; 5811 5812 /* Number of connected NLO band preferences */ 5813 u32 num_cnlo_band_pref; 5814 5815 /* The TLVs will follow. 5816 * nlo_configured_parameters nlo_list[]; 5817 * u32 channel_list[num_of_channels]; 5818 */ 5819 } __packed; 5820 5821 #define WMI_MAX_NS_OFFLOADS 2 5822 #define WMI_MAX_ARP_OFFLOADS 2 5823 5824 #define WMI_ARPOL_FLAGS_VALID BIT(0) 5825 #define WMI_ARPOL_FLAGS_MAC_VALID BIT(1) 5826 #define WMI_ARPOL_FLAGS_REMOTE_IP_VALID BIT(2) 5827 5828 struct wmi_arp_offload_tuple { 5829 u32 tlv_header; 5830 u32 flags; 5831 u8 target_ipaddr[4]; 5832 u8 remote_ipaddr[4]; 5833 struct wmi_mac_addr target_mac; 5834 } __packed; 5835 5836 #define WMI_NSOL_FLAGS_VALID BIT(0) 5837 #define WMI_NSOL_FLAGS_MAC_VALID BIT(1) 5838 #define WMI_NSOL_FLAGS_REMOTE_IP_VALID BIT(2) 5839 #define WMI_NSOL_FLAGS_IS_IPV6_ANYCAST BIT(3) 5840 5841 #define WMI_NSOL_MAX_TARGET_IPS 2 5842 5843 struct wmi_ns_offload_tuple { 5844 u32 tlv_header; 5845 u32 flags; 5846 u8 target_ipaddr[WMI_NSOL_MAX_TARGET_IPS][16]; 5847 u8 solicitation_ipaddr[16]; 5848 u8 remote_ipaddr[16]; 5849 struct wmi_mac_addr target_mac; 5850 } __packed; 5851 5852 struct wmi_set_arp_ns_offload_cmd { 5853 u32 tlv_header; 5854 u32 flags; 5855 u32 vdev_id; 5856 u32 num_ns_ext_tuples; 5857 /* The TLVs follow: 5858 * wmi_ns_offload_tuple ns_tuples[WMI_MAX_NS_OFFLOADS]; 5859 * wmi_arp_offload_tuple arp_tuples[WMI_MAX_ARP_OFFLOADS]; 5860 * wmi_ns_offload_tuple ns_ext_tuples[num_ns_ext_tuples]; 5861 */ 5862 } __packed; 5863 5864 #define GTK_OFFLOAD_OPCODE_MASK 0xFF000000 5865 #define GTK_OFFLOAD_ENABLE_OPCODE 0x01000000 5866 #define GTK_OFFLOAD_DISABLE_OPCODE 0x02000000 5867 #define GTK_OFFLOAD_REQUEST_STATUS_OPCODE 0x04000000 5868 5869 #define GTK_OFFLOAD_KEK_BYTES 16 5870 #define GTK_OFFLOAD_KCK_BYTES 16 5871 #define GTK_REPLAY_COUNTER_BYTES 8 5872 #define WMI_MAX_KEY_LEN 32 5873 #define IGTK_PN_SIZE 6 5874 5875 struct wmi_replayc_cnt { 5876 union { 5877 u8 counter[GTK_REPLAY_COUNTER_BYTES]; 5878 struct { 5879 u32 word0; 5880 u32 word1; 5881 } __packed; 5882 } __packed; 5883 } __packed; 5884 5885 struct wmi_gtk_offload_status_event { 5886 u32 vdev_id; 5887 u32 flags; 5888 u32 refresh_cnt; 5889 struct wmi_replayc_cnt replay_ctr; 5890 u8 igtk_key_index; 5891 u8 igtk_key_length; 5892 u8 igtk_key_rsc[IGTK_PN_SIZE]; 5893 u8 igtk_key[WMI_MAX_KEY_LEN]; 5894 u8 gtk_key_index; 5895 u8 gtk_key_length; 5896 u8 gtk_key_rsc[GTK_REPLAY_COUNTER_BYTES]; 5897 u8 gtk_key[WMI_MAX_KEY_LEN]; 5898 } __packed; 5899 5900 struct wmi_gtk_rekey_offload_cmd { 5901 u32 tlv_header; 5902 u32 vdev_id; 5903 u32 flags; 5904 u8 kek[GTK_OFFLOAD_KEK_BYTES]; 5905 u8 kck[GTK_OFFLOAD_KCK_BYTES]; 5906 u8 replay_ctr[GTK_REPLAY_COUNTER_BYTES]; 5907 } __packed; 5908 5909 #define BIOS_SAR_TABLE_LEN (22) 5910 #define BIOS_SAR_RSVD1_LEN (6) 5911 #define BIOS_SAR_RSVD2_LEN (18) 5912 5913 struct wmi_pdev_set_sar_table_cmd { 5914 u32 tlv_header; 5915 u32 pdev_id; 5916 u32 sar_len; 5917 u32 rsvd_len; 5918 } __packed; 5919 5920 struct wmi_pdev_set_geo_table_cmd { 5921 u32 tlv_header; 5922 u32 pdev_id; 5923 u32 rsvd_len; 5924 } __packed; 5925 5926 struct wmi_sta_keepalive_cmd { 5927 u32 tlv_header; 5928 u32 vdev_id; 5929 u32 enabled; 5930 5931 /* WMI_STA_KEEPALIVE_METHOD_ */ 5932 u32 method; 5933 5934 /* in seconds */ 5935 u32 interval; 5936 5937 /* following this structure is the TLV for struct 5938 * wmi_sta_keepalive_arp_resp 5939 */ 5940 } __packed; 5941 5942 struct wmi_sta_keepalive_arp_resp { 5943 u32 tlv_header; 5944 u32 src_ip4_addr; 5945 u32 dest_ip4_addr; 5946 struct wmi_mac_addr dest_mac_addr; 5947 } __packed; 5948 5949 struct wmi_sta_keepalive_arg { 5950 u32 vdev_id; 5951 u32 enabled; 5952 u32 method; 5953 u32 interval; 5954 u32 src_ip4_addr; 5955 u32 dest_ip4_addr; 5956 const u8 dest_mac_addr[ETH_ALEN]; 5957 }; 5958 5959 enum wmi_sta_keepalive_method { 5960 WMI_STA_KEEPALIVE_METHOD_NULL_FRAME = 1, 5961 WMI_STA_KEEPALIVE_METHOD_UNSOLICITED_ARP_RESPONSE = 2, 5962 WMI_STA_KEEPALIVE_METHOD_ETHERNET_LOOPBACK = 3, 5963 WMI_STA_KEEPALIVE_METHOD_GRATUITOUS_ARP_REQUEST = 4, 5964 WMI_STA_KEEPALIVE_METHOD_MGMT_VENDOR_ACTION = 5, 5965 }; 5966 5967 #define WMI_STA_KEEPALIVE_INTERVAL_DEFAULT 30 5968 #define WMI_STA_KEEPALIVE_INTERVAL_DISABLE 0 5969 5970 int ath11k_wmi_cmd_send(struct ath11k_pdev_wmi *wmi, struct sk_buff *skb, 5971 u32 cmd_id); 5972 struct sk_buff *ath11k_wmi_alloc_skb(struct ath11k_wmi_base *wmi_sc, u32 len); 5973 int ath11k_wmi_mgmt_send(struct ath11k *ar, u32 vdev_id, u32 buf_id, 5974 struct sk_buff *frame); 5975 int ath11k_wmi_bcn_tmpl(struct ath11k *ar, u32 vdev_id, 5976 struct ieee80211_mutable_offsets *offs, 5977 struct sk_buff *bcn); 5978 int ath11k_wmi_vdev_down(struct ath11k *ar, u8 vdev_id); 5979 int ath11k_wmi_vdev_up(struct ath11k *ar, u32 vdev_id, u32 aid, 5980 const u8 *bssid); 5981 int ath11k_wmi_vdev_stop(struct ath11k *ar, u8 vdev_id); 5982 int ath11k_wmi_vdev_start(struct ath11k *ar, struct wmi_vdev_start_req_arg *arg, 5983 bool restart); 5984 int ath11k_wmi_set_peer_param(struct ath11k *ar, const u8 *peer_addr, 5985 u32 vdev_id, u32 param_id, u32 param_val); 5986 int ath11k_wmi_pdev_set_param(struct ath11k *ar, u32 param_id, 5987 u32 param_value, u8 pdev_id); 5988 int ath11k_wmi_pdev_set_ps_mode(struct ath11k *ar, int vdev_id, 5989 enum wmi_sta_ps_mode psmode); 5990 int ath11k_wmi_wait_for_unified_ready(struct ath11k_base *ab); 5991 int ath11k_wmi_cmd_init(struct ath11k_base *ab); 5992 int ath11k_wmi_wait_for_service_ready(struct ath11k_base *ab); 5993 int ath11k_wmi_connect(struct ath11k_base *ab); 5994 int ath11k_wmi_pdev_attach(struct ath11k_base *ab, 5995 u8 pdev_id); 5996 int ath11k_wmi_attach(struct ath11k_base *ab); 5997 void ath11k_wmi_detach(struct ath11k_base *ab); 5998 int ath11k_wmi_vdev_create(struct ath11k *ar, u8 *macaddr, 5999 struct vdev_create_params *param); 6000 int ath11k_wmi_peer_rx_reorder_queue_setup(struct ath11k *ar, int vdev_id, 6001 const u8 *addr, dma_addr_t paddr, 6002 u8 tid, u8 ba_window_size_valid, 6003 u32 ba_window_size); 6004 int ath11k_wmi_send_peer_create_cmd(struct ath11k *ar, 6005 struct peer_create_params *param); 6006 int ath11k_wmi_vdev_set_param_cmd(struct ath11k *ar, u32 vdev_id, 6007 u32 param_id, u32 param_value); 6008 6009 int ath11k_wmi_set_sta_ps_param(struct ath11k *ar, u32 vdev_id, 6010 u32 param, u32 param_value); 6011 int ath11k_wmi_force_fw_hang_cmd(struct ath11k *ar, u32 type, u32 delay_time_ms); 6012 int ath11k_wmi_send_peer_delete_cmd(struct ath11k *ar, 6013 const u8 *peer_addr, u8 vdev_id); 6014 int ath11k_wmi_vdev_delete(struct ath11k *ar, u8 vdev_id); 6015 void ath11k_wmi_start_scan_init(struct ath11k *ar, struct scan_req_params *arg); 6016 int ath11k_wmi_send_scan_start_cmd(struct ath11k *ar, 6017 struct scan_req_params *params); 6018 int ath11k_wmi_send_scan_stop_cmd(struct ath11k *ar, 6019 struct scan_cancel_param *param); 6020 int ath11k_wmi_send_wmm_update_cmd_tlv(struct ath11k *ar, u32 vdev_id, 6021 struct wmi_wmm_params_all_arg *param); 6022 int ath11k_wmi_pdev_suspend(struct ath11k *ar, u32 suspend_opt, 6023 u32 pdev_id); 6024 int ath11k_wmi_pdev_resume(struct ath11k *ar, u32 pdev_id); 6025 6026 int ath11k_wmi_send_peer_assoc_cmd(struct ath11k *ar, 6027 struct peer_assoc_params *param); 6028 int ath11k_wmi_vdev_install_key(struct ath11k *ar, 6029 struct wmi_vdev_install_key_arg *arg); 6030 int ath11k_wmi_pdev_bss_chan_info_request(struct ath11k *ar, 6031 enum wmi_bss_chan_info_req_type type); 6032 int ath11k_wmi_send_stats_request_cmd(struct ath11k *ar, 6033 struct stats_request_params *param); 6034 int ath11k_wmi_send_pdev_temperature_cmd(struct ath11k *ar); 6035 int ath11k_wmi_send_peer_flush_tids_cmd(struct ath11k *ar, 6036 u8 peer_addr[ETH_ALEN], 6037 struct peer_flush_params *param); 6038 int ath11k_wmi_send_set_ap_ps_param_cmd(struct ath11k *ar, u8 *peer_addr, 6039 struct ap_ps_params *param); 6040 int ath11k_wmi_send_scan_chan_list_cmd(struct ath11k *ar, 6041 struct scan_chan_list_params *chan_list); 6042 int ath11k_wmi_send_dfs_phyerr_offload_enable_cmd(struct ath11k *ar, 6043 u32 pdev_id); 6044 int ath11k_wmi_addba_clear_resp(struct ath11k *ar, u32 vdev_id, const u8 *mac); 6045 int ath11k_wmi_addba_send(struct ath11k *ar, u32 vdev_id, const u8 *mac, 6046 u32 tid, u32 buf_size); 6047 int ath11k_wmi_addba_set_resp(struct ath11k *ar, u32 vdev_id, const u8 *mac, 6048 u32 tid, u32 status); 6049 int ath11k_wmi_delba_send(struct ath11k *ar, u32 vdev_id, const u8 *mac, 6050 u32 tid, u32 initiator, u32 reason); 6051 int ath11k_wmi_send_bcn_offload_control_cmd(struct ath11k *ar, 6052 u32 vdev_id, u32 bcn_ctrl_op); 6053 int ath11k_wmi_send_set_current_country_cmd(struct ath11k *ar, 6054 struct wmi_set_current_country_params *param); 6055 int 6056 ath11k_wmi_send_init_country_cmd(struct ath11k *ar, 6057 struct wmi_init_country_params init_cc_param); 6058 6059 int ath11k_wmi_send_11d_scan_start_cmd(struct ath11k *ar, 6060 struct wmi_11d_scan_start_params *param); 6061 int ath11k_wmi_send_11d_scan_stop_cmd(struct ath11k *ar, u32 vdev_id); 6062 6063 int 6064 ath11k_wmi_send_thermal_mitigation_param_cmd(struct ath11k *ar, 6065 struct thermal_mitigation_params *param); 6066 int ath11k_wmi_pdev_pktlog_enable(struct ath11k *ar, u32 pktlog_filter); 6067 int ath11k_wmi_pdev_pktlog_disable(struct ath11k *ar); 6068 int ath11k_wmi_pdev_peer_pktlog_filter(struct ath11k *ar, u8 *addr, u8 enable); 6069 int 6070 ath11k_wmi_rx_reord_queue_remove(struct ath11k *ar, 6071 struct rx_reorder_queue_remove_params *param); 6072 int ath11k_wmi_send_pdev_set_regdomain(struct ath11k *ar, 6073 struct pdev_set_regdomain_params *param); 6074 int ath11k_wmi_pull_fw_stats(struct ath11k_base *ab, struct sk_buff *skb, 6075 struct ath11k_fw_stats *stats); 6076 size_t ath11k_wmi_fw_stats_num_peers(struct list_head *head); 6077 size_t ath11k_wmi_fw_stats_num_peers_extd(struct list_head *head); 6078 size_t ath11k_wmi_fw_stats_num_vdevs(struct list_head *head); 6079 void ath11k_wmi_fw_stats_fill(struct ath11k *ar, 6080 struct ath11k_fw_stats *fw_stats, u32 stats_id, 6081 char *buf); 6082 int ath11k_wmi_simulate_radar(struct ath11k *ar); 6083 void ath11k_wmi_fill_default_twt_params(struct wmi_twt_enable_params *twt_params); 6084 int ath11k_wmi_send_twt_enable_cmd(struct ath11k *ar, u32 pdev_id, 6085 struct wmi_twt_enable_params *params); 6086 int ath11k_wmi_send_twt_disable_cmd(struct ath11k *ar, u32 pdev_id); 6087 int ath11k_wmi_send_twt_add_dialog_cmd(struct ath11k *ar, 6088 struct wmi_twt_add_dialog_params *params); 6089 int ath11k_wmi_send_twt_del_dialog_cmd(struct ath11k *ar, 6090 struct wmi_twt_del_dialog_params *params); 6091 int ath11k_wmi_send_twt_pause_dialog_cmd(struct ath11k *ar, 6092 struct wmi_twt_pause_dialog_params *params); 6093 int ath11k_wmi_send_twt_resume_dialog_cmd(struct ath11k *ar, 6094 struct wmi_twt_resume_dialog_params *params); 6095 int ath11k_wmi_send_obss_spr_cmd(struct ath11k *ar, u32 vdev_id, 6096 struct ieee80211_he_obss_pd *he_obss_pd); 6097 int ath11k_wmi_pdev_set_srg_bss_color_bitmap(struct ath11k *ar, u32 *bitmap); 6098 int ath11k_wmi_pdev_set_srg_patial_bssid_bitmap(struct ath11k *ar, u32 *bitmap); 6099 int ath11k_wmi_pdev_srg_obss_color_enable_bitmap(struct ath11k *ar, 6100 u32 *bitmap); 6101 int ath11k_wmi_pdev_srg_obss_bssid_enable_bitmap(struct ath11k *ar, 6102 u32 *bitmap); 6103 int ath11k_wmi_pdev_non_srg_obss_color_enable_bitmap(struct ath11k *ar, 6104 u32 *bitmap); 6105 int ath11k_wmi_pdev_non_srg_obss_bssid_enable_bitmap(struct ath11k *ar, 6106 u32 *bitmap); 6107 int ath11k_wmi_send_obss_color_collision_cfg_cmd(struct ath11k *ar, u32 vdev_id, 6108 u8 bss_color, u32 period, 6109 bool enable); 6110 int ath11k_wmi_send_bss_color_change_enable_cmd(struct ath11k *ar, u32 vdev_id, 6111 bool enable); 6112 int ath11k_wmi_pdev_lro_cfg(struct ath11k *ar, int pdev_id); 6113 int ath11k_wmi_pdev_dma_ring_cfg(struct ath11k *ar, 6114 struct ath11k_wmi_pdev_dma_ring_cfg_req_cmd *param); 6115 int ath11k_wmi_vdev_spectral_enable(struct ath11k *ar, u32 vdev_id, 6116 u32 trigger, u32 enable); 6117 int ath11k_wmi_vdev_spectral_conf(struct ath11k *ar, 6118 struct ath11k_wmi_vdev_spectral_conf_param *param); 6119 int ath11k_wmi_fils_discovery_tmpl(struct ath11k *ar, u32 vdev_id, 6120 struct sk_buff *tmpl); 6121 int ath11k_wmi_fils_discovery(struct ath11k *ar, u32 vdev_id, u32 interval, 6122 bool unsol_bcast_probe_resp_enabled); 6123 int ath11k_wmi_probe_resp_tmpl(struct ath11k *ar, u32 vdev_id, 6124 struct sk_buff *tmpl); 6125 int ath11k_wmi_set_hw_mode(struct ath11k_base *ab, 6126 enum wmi_host_hw_mode_config_type mode); 6127 int ath11k_wmi_wow_host_wakeup_ind(struct ath11k *ar); 6128 int ath11k_wmi_wow_enable(struct ath11k *ar); 6129 int ath11k_wmi_scan_prob_req_oui(struct ath11k *ar, 6130 const u8 mac_addr[ETH_ALEN]); 6131 int ath11k_wmi_fw_dbglog_cfg(struct ath11k *ar, u32 *module_id_bitmap, 6132 struct ath11k_fw_dbglog *dbglog); 6133 int ath11k_wmi_wow_config_pno(struct ath11k *ar, u32 vdev_id, 6134 struct wmi_pno_scan_req *pno_scan); 6135 int ath11k_wmi_wow_del_pattern(struct ath11k *ar, u32 vdev_id, u32 pattern_id); 6136 int ath11k_wmi_wow_add_pattern(struct ath11k *ar, u32 vdev_id, u32 pattern_id, 6137 const u8 *pattern, const u8 *mask, 6138 int pattern_len, int pattern_offset); 6139 int ath11k_wmi_wow_add_wakeup_event(struct ath11k *ar, u32 vdev_id, 6140 enum wmi_wow_wakeup_event event, 6141 u32 enable); 6142 int ath11k_wmi_hw_data_filter_cmd(struct ath11k *ar, u32 vdev_id, 6143 u32 filter_bitmap, bool enable); 6144 int ath11k_wmi_arp_ns_offload(struct ath11k *ar, 6145 struct ath11k_vif *arvif, bool enable); 6146 int ath11k_wmi_gtk_rekey_offload(struct ath11k *ar, 6147 struct ath11k_vif *arvif, bool enable); 6148 int ath11k_wmi_gtk_rekey_getinfo(struct ath11k *ar, 6149 struct ath11k_vif *arvif); 6150 int ath11k_wmi_pdev_set_bios_sar_table_param(struct ath11k *ar, const u8 *sar_val); 6151 int ath11k_wmi_pdev_set_bios_geo_table_param(struct ath11k *ar); 6152 int ath11k_wmi_sta_keepalive(struct ath11k *ar, 6153 const struct wmi_sta_keepalive_arg *arg); 6154 6155 #endif 6156