1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4  */
5 #ifndef ATH11K_RX_DESC_H
6 #define ATH11K_RX_DESC_H
7 
8 enum rx_desc_rxpcu_filter {
9 	RX_DESC_RXPCU_FILTER_PASS,
10 	RX_DESC_RXPCU_FILTER_MONITOR_CLIENT,
11 	RX_DESC_RXPCU_FILTER_MONITOR_OTHER,
12 };
13 
14 /* rxpcu_filter_pass
15  *		This MPDU passed the normal frame filter programming of rxpcu.
16  *
17  * rxpcu_filter_monitor_client
18  *		 This MPDU did not pass the regular frame filter and would
19  *		 have been dropped, were it not for the frame fitting into the
20  *		 'monitor_client' category.
21  *
22  * rxpcu_filter_monitor_other
23  *		This MPDU did not pass the regular frame filter and also did
24  *		not pass the rxpcu_monitor_client filter. It would have been
25  *		dropped accept that it did pass the 'monitor_other' category.
26  */
27 
28 #define RX_DESC_INFO0_RXPCU_MPDU_FITLER	GENMASK(1, 0)
29 #define RX_DESC_INFO0_SW_FRAME_GRP_ID	GENMASK(8, 2)
30 
31 enum rx_desc_sw_frame_grp_id {
32 	RX_DESC_SW_FRAME_GRP_ID_NDP_FRAME,
33 	RX_DESC_SW_FRAME_GRP_ID_MCAST_DATA,
34 	RX_DESC_SW_FRAME_GRP_ID_UCAST_DATA,
35 	RX_DESC_SW_FRAME_GRP_ID_NULL_DATA,
36 	RX_DESC_SW_FRAME_GRP_ID_MGMT_0000,
37 	RX_DESC_SW_FRAME_GRP_ID_MGMT_0001,
38 	RX_DESC_SW_FRAME_GRP_ID_MGMT_0010,
39 	RX_DESC_SW_FRAME_GRP_ID_MGMT_0011,
40 	RX_DESC_SW_FRAME_GRP_ID_MGMT_0100,
41 	RX_DESC_SW_FRAME_GRP_ID_MGMT_0101,
42 	RX_DESC_SW_FRAME_GRP_ID_MGMT_0110,
43 	RX_DESC_SW_FRAME_GRP_ID_MGMT_0111,
44 	RX_DESC_SW_FRAME_GRP_ID_MGMT_1000,
45 	RX_DESC_SW_FRAME_GRP_ID_MGMT_1001,
46 	RX_DESC_SW_FRAME_GRP_ID_MGMT_1010,
47 	RX_DESC_SW_FRAME_GRP_ID_MGMT_1011,
48 	RX_DESC_SW_FRAME_GRP_ID_MGMT_1100,
49 	RX_DESC_SW_FRAME_GRP_ID_MGMT_1101,
50 	RX_DESC_SW_FRAME_GRP_ID_MGMT_1110,
51 	RX_DESC_SW_FRAME_GRP_ID_MGMT_1111,
52 	RX_DESC_SW_FRAME_GRP_ID_CTRL_0000,
53 	RX_DESC_SW_FRAME_GRP_ID_CTRL_0001,
54 	RX_DESC_SW_FRAME_GRP_ID_CTRL_0010,
55 	RX_DESC_SW_FRAME_GRP_ID_CTRL_0011,
56 	RX_DESC_SW_FRAME_GRP_ID_CTRL_0100,
57 	RX_DESC_SW_FRAME_GRP_ID_CTRL_0101,
58 	RX_DESC_SW_FRAME_GRP_ID_CTRL_0110,
59 	RX_DESC_SW_FRAME_GRP_ID_CTRL_0111,
60 	RX_DESC_SW_FRAME_GRP_ID_CTRL_1000,
61 	RX_DESC_SW_FRAME_GRP_ID_CTRL_1001,
62 	RX_DESC_SW_FRAME_GRP_ID_CTRL_1010,
63 	RX_DESC_SW_FRAME_GRP_ID_CTRL_1011,
64 	RX_DESC_SW_FRAME_GRP_ID_CTRL_1100,
65 	RX_DESC_SW_FRAME_GRP_ID_CTRL_1101,
66 	RX_DESC_SW_FRAME_GRP_ID_CTRL_1110,
67 	RX_DESC_SW_FRAME_GRP_ID_CTRL_1111,
68 	RX_DESC_SW_FRAME_GRP_ID_UNSUPPORTED,
69 	RX_DESC_SW_FRAME_GRP_ID_PHY_ERR,
70 };
71 
72 enum rx_desc_decap_type {
73 	RX_DESC_DECAP_TYPE_RAW,
74 	RX_DESC_DECAP_TYPE_NATIVE_WIFI,
75 	RX_DESC_DECAP_TYPE_ETHERNET2_DIX,
76 	RX_DESC_DECAP_TYPE_8023,
77 };
78 
79 enum rx_desc_decrypt_status_code {
80 	RX_DESC_DECRYPT_STATUS_CODE_OK,
81 	RX_DESC_DECRYPT_STATUS_CODE_UNPROTECTED_FRAME,
82 	RX_DESC_DECRYPT_STATUS_CODE_DATA_ERR,
83 	RX_DESC_DECRYPT_STATUS_CODE_KEY_INVALID,
84 	RX_DESC_DECRYPT_STATUS_CODE_PEER_ENTRY_INVALID,
85 	RX_DESC_DECRYPT_STATUS_CODE_OTHER,
86 };
87 
88 #define RX_ATTENTION_INFO1_FIRST_MPDU		BIT(0)
89 #define RX_ATTENTION_INFO1_RSVD_1A		BIT(1)
90 #define RX_ATTENTION_INFO1_MCAST_BCAST		BIT(2)
91 #define RX_ATTENTION_INFO1_AST_IDX_NOT_FOUND	BIT(3)
92 #define RX_ATTENTION_INFO1_AST_IDX_TIMEDOUT	BIT(4)
93 #define RX_ATTENTION_INFO1_POWER_MGMT		BIT(5)
94 #define RX_ATTENTION_INFO1_NON_QOS		BIT(6)
95 #define RX_ATTENTION_INFO1_NULL_DATA		BIT(7)
96 #define RX_ATTENTION_INFO1_MGMT_TYPE		BIT(8)
97 #define RX_ATTENTION_INFO1_CTRL_TYPE		BIT(9)
98 #define RX_ATTENTION_INFO1_MORE_DATA		BIT(10)
99 #define RX_ATTENTION_INFO1_EOSP			BIT(11)
100 #define RX_ATTENTION_INFO1_A_MSDU_ERROR		BIT(12)
101 #define RX_ATTENTION_INFO1_FRAGMENT		BIT(13)
102 #define RX_ATTENTION_INFO1_ORDER		BIT(14)
103 #define RX_ATTENTION_INFO1_CCE_MATCH		BIT(15)
104 #define RX_ATTENTION_INFO1_OVERFLOW_ERR		BIT(16)
105 #define RX_ATTENTION_INFO1_MSDU_LEN_ERR		BIT(17)
106 #define RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL	BIT(18)
107 #define RX_ATTENTION_INFO1_IP_CKSUM_FAIL	BIT(19)
108 #define RX_ATTENTION_INFO1_SA_IDX_INVALID	BIT(20)
109 #define RX_ATTENTION_INFO1_DA_IDX_INVALID	BIT(21)
110 #define RX_ATTENTION_INFO1_RSVD_1B		BIT(22)
111 #define RX_ATTENTION_INFO1_RX_IN_TX_DECRYPT_BYP	BIT(23)
112 #define RX_ATTENTION_INFO1_ENCRYPT_REQUIRED	BIT(24)
113 #define RX_ATTENTION_INFO1_DIRECTED		BIT(25)
114 #define RX_ATTENTION_INFO1_BUFFER_FRAGMENT	BIT(26)
115 #define RX_ATTENTION_INFO1_MPDU_LEN_ERR		BIT(27)
116 #define RX_ATTENTION_INFO1_TKIP_MIC_ERR		BIT(28)
117 #define RX_ATTENTION_INFO1_DECRYPT_ERR		BIT(29)
118 #define RX_ATTENTION_INFO1_UNDECRYPT_FRAME_ERR	BIT(30)
119 #define RX_ATTENTION_INFO1_FCS_ERR		BIT(31)
120 
121 #define RX_ATTENTION_INFO2_FLOW_IDX_TIMEOUT	BIT(0)
122 #define RX_ATTENTION_INFO2_FLOW_IDX_INVALID	BIT(1)
123 #define RX_ATTENTION_INFO2_WIFI_PARSER_ERR	BIT(2)
124 #define RX_ATTENTION_INFO2_AMSDU_PARSER_ERR	BIT(3)
125 #define RX_ATTENTION_INFO2_SA_IDX_TIMEOUT	BIT(4)
126 #define RX_ATTENTION_INFO2_DA_IDX_TIMEOUT	BIT(5)
127 #define RX_ATTENTION_INFO2_MSDU_LIMIT_ERR	BIT(6)
128 #define RX_ATTENTION_INFO2_DA_IS_VALID		BIT(7)
129 #define RX_ATTENTION_INFO2_DA_IS_MCBC		BIT(8)
130 #define RX_ATTENTION_INFO2_SA_IS_VALID		BIT(9)
131 #define RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE	GENMASK(12, 10)
132 #define RX_ATTENTION_INFO2_RX_BITMAP_NOT_UPDED	BIT(13)
133 #define RX_ATTENTION_INFO2_MSDU_DONE		BIT(31)
134 
135 struct rx_attention {
136 	__le16 info0;
137 	__le16 phy_ppdu_id;
138 	__le32 info1;
139 	__le32 info2;
140 } __packed;
141 
142 /* rx_attention
143  *
144  * rxpcu_mpdu_filter_in_category
145  *		Field indicates what the reason was that this mpdu frame
146  *		was allowed to come into the receive path by rxpcu. Values
147  *		are defined in enum %RX_DESC_RXPCU_FILTER_*.
148  *
149  * sw_frame_group_id
150  *		SW processes frames based on certain classifications. Values
151  *		are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*.
152  *
153  * phy_ppdu_id
154  *		A ppdu counter value that PHY increments for every PPDU
155  *		received. The counter value wraps around.
156  *
157  * first_mpdu
158  *		Indicates the first MSDU of the PPDU.  If both first_mpdu
159  *		and last_mpdu are set in the MSDU then this is a not an
160  *		A-MPDU frame but a stand alone MPDU.  Interior MPDU in an
161  *		A-MPDU shall have both first_mpdu and last_mpdu bits set to
162  *		0.  The PPDU start status will only be valid when this bit
163  *		is set.
164  *
165  * mcast_bcast
166  *		Multicast / broadcast indicator.  Only set when the MAC
167  *		address 1 bit 0 is set indicating mcast/bcast and the BSSID
168  *		matches one of the 4 BSSID registers. Only set when
169  *		first_msdu is set.
170  *
171  * ast_index_not_found
172  *		Only valid when first_msdu is set. Indicates no AST matching
173  *		entries within the max search count.
174  *
175  * ast_index_timeout
176  *		Only valid when first_msdu is set. Indicates an unsuccessful
177  *		search in the address search table due to timeout.
178  *
179  * power_mgmt
180  *		Power management bit set in the 802.11 header.  Only set
181  *		when first_msdu is set.
182  *
183  * non_qos
184  *		Set if packet is not a non-QoS data frame.  Only set when
185  *		first_msdu is set.
186  *
187  * null_data
188  *		Set if frame type indicates either null data or QoS null
189  *		data format.  Only set when first_msdu is set.
190  *
191  * mgmt_type
192  *		Set if packet is a management packet.  Only set when
193  *		first_msdu is set.
194  *
195  * ctrl_type
196  *		Set if packet is a control packet.  Only set when first_msdu
197  *		is set.
198  *
199  * more_data
200  *		Set if more bit in frame control is set.  Only set when
201  *		first_msdu is set.
202  *
203  * eosp
204  *		Set if the EOSP (end of service period) bit in the QoS
205  *		control field is set.  Only set when first_msdu is set.
206  *
207  * a_msdu_error
208  *		Set if number of MSDUs in A-MSDU is above a threshold or if the
209  *		size of the MSDU is invalid. This receive buffer will contain
210  *		all of the remainder of MSDUs in this MPDU w/o decapsulation.
211  *
212  * fragment
213  *		Indicates that this is an 802.11 fragment frame.  This is
214  *		set when either the more_frag bit is set in the frame
215  *		control or the fragment number is not zero.  Only set when
216  *		first_msdu is set.
217  *
218  * order
219  *		Set if the order bit in the frame control is set.  Only set
220  *		when first_msdu is set.
221  *
222  * cce_match
223  *		Indicates that this status has a corresponding MSDU that
224  *		requires FW processing. The OLE will have classification
225  *		ring mask registers which will indicate the ring(s) for
226  *		packets and descriptors which need FW attention.
227  *
228  * overflow_err
229  *		PCU Receive FIFO does not have enough space to store the
230  *		full receive packet.  Enough space is reserved in the
231  *		receive FIFO for the status is written.  This MPDU remaining
232  *		packets in the PPDU will be filtered and no Ack response
233  *		will be transmitted.
234  *
235  * msdu_length_err
236  *		Indicates that the MSDU length from the 802.3 encapsulated
237  *		length field extends beyond the MPDU boundary.
238  *
239  * tcp_udp_chksum_fail
240  *		Indicates that the computed checksum (tcp_udp_chksum) did
241  *		not match the checksum in the TCP/UDP header.
242  *
243  * ip_chksum_fail
244  *		Indicates that the computed checksum did not match the
245  *		checksum in the IP header.
246  *
247  * sa_idx_invalid
248  *		Indicates no matching entry was found in the address search
249  *		table for the source MAC address.
250  *
251  * da_idx_invalid
252  *		Indicates no matching entry was found in the address search
253  *		table for the destination MAC address.
254  *
255  * rx_in_tx_decrypt_byp
256  *		Indicates that RX packet is not decrypted as Crypto is busy
257  *		with TX packet processing.
258  *
259  * encrypt_required
260  *		Indicates that this data type frame is not encrypted even if
261  *		the policy for this MPDU requires encryption as indicated in
262  *		the peer table key type.
263  *
264  * directed
265  *		MPDU is a directed packet which means that the RA matched
266  *		our STA addresses.  In proxySTA it means that the TA matched
267  *		an entry in our address search table with the corresponding
268  *		'no_ack' bit is the address search entry cleared.
269  *
270  * buffer_fragment
271  *		Indicates that at least one of the rx buffers has been
272  *		fragmented.  If set the FW should look at the rx_frag_info
273  *		descriptor described below.
274  *
275  * mpdu_length_err
276  *		Indicates that the MPDU was pre-maturely terminated
277  *		resulting in a truncated MPDU.  Don't trust the MPDU length
278  *		field.
279  *
280  * tkip_mic_err
281  *		Indicates that the MPDU Michael integrity check failed
282  *
283  * decrypt_err
284  *		Indicates that the MPDU decrypt integrity check failed
285  *
286  * fcs_err
287  *		Indicates that the MPDU FCS check failed
288  *
289  * flow_idx_timeout
290  *		Indicates an unsuccessful flow search due to the expiring of
291  *		the search timer.
292  *
293  * flow_idx_invalid
294  *		flow id is not valid.
295  *
296  * amsdu_parser_error
297  *		A-MSDU could not be properly de-agregated.
298  *
299  * sa_idx_timeout
300  *		Indicates an unsuccessful search for the source MAC address
301  *		due to the expiring of the search timer.
302  *
303  * da_idx_timeout
304  *		Indicates an unsuccessful search for the destination MAC
305  *		address due to the expiring of the search timer.
306  *
307  * msdu_limit_error
308  *		Indicates that the MSDU threshold was exceeded and thus
309  *		all the rest of the MSDUs will not be scattered and will not
310  *		be decasulated but will be DMA'ed in RAW format as a single
311  *		MSDU buffer.
312  *
313  * da_is_valid
314  *		Indicates that OLE found a valid DA entry.
315  *
316  * da_is_mcbc
317  *		Field Only valid if da_is_valid is set. Indicates the DA address
318  *		was a Multicast or Broadcast address.
319  *
320  * sa_is_valid
321  *		Indicates that OLE found a valid SA entry.
322  *
323  * decrypt_status_code
324  *		Field provides insight into the decryption performed. Values are
325  *		defined in enum %RX_DESC_DECRYPT_STATUS_CODE*.
326  *
327  * rx_bitmap_not_updated
328  *		Frame is received, but RXPCU could not update the receive bitmap
329  *		due to (temporary) fifo constraints.
330  *
331  * msdu_done
332  *		If set indicates that the RX packet data, RX header data, RX
333  *		PPDU start descriptor, RX MPDU start/end descriptor, RX MSDU
334  *		start/end descriptors and RX Attention descriptor are all
335  *		valid.  This bit must be in the last octet of the
336  *		descriptor.
337  */
338 
339 #define RX_MPDU_START_INFO0_NDP_FRAME		BIT(9)
340 #define RX_MPDU_START_INFO0_PHY_ERR		BIT(10)
341 #define RX_MPDU_START_INFO0_PHY_ERR_MPDU_HDR	BIT(11)
342 #define RX_MPDU_START_INFO0_PROTO_VER_ERR	BIT(12)
343 #define RX_MPDU_START_INFO0_AST_LOOKUP_VALID	BIT(13)
344 
345 #define RX_MPDU_START_INFO1_MPDU_FCTRL_VALID	BIT(0)
346 #define RX_MPDU_START_INFO1_MPDU_DUR_VALID	BIT(1)
347 #define RX_MPDU_START_INFO1_MAC_ADDR1_VALID	BIT(2)
348 #define RX_MPDU_START_INFO1_MAC_ADDR2_VALID	BIT(3)
349 #define RX_MPDU_START_INFO1_MAC_ADDR3_VALID	BIT(4)
350 #define RX_MPDU_START_INFO1_MAC_ADDR4_VALID	BIT(5)
351 #define RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID	BIT(6)
352 #define RX_MPDU_START_INFO1_MPDU_QOS_CTRL_VALID	BIT(7)
353 #define RX_MPDU_START_INFO1_MPDU_HT_CTRL_VALID	BIT(8)
354 #define RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID	BIT(9)
355 #define RX_MPDU_START_INFO1_MPDU_FRAG_NUMBER	GENMASK(13, 10)
356 #define RX_MPDU_START_INFO1_MORE_FRAG_FLAG	BIT(14)
357 #define RX_MPDU_START_INFO1_FROM_DS		BIT(16)
358 #define RX_MPDU_START_INFO1_TO_DS		BIT(17)
359 #define RX_MPDU_START_INFO1_ENCRYPTED		BIT(18)
360 #define RX_MPDU_START_INFO1_MPDU_RETRY		BIT(19)
361 #define RX_MPDU_START_INFO1_MPDU_SEQ_NUM	GENMASK(31, 20)
362 
363 #define RX_MPDU_START_INFO2_EPD_EN		BIT(0)
364 #define RX_MPDU_START_INFO2_ALL_FRAME_ENCPD	BIT(1)
365 #define RX_MPDU_START_INFO2_ENC_TYPE		GENMASK(5, 2)
366 #define RX_MPDU_START_INFO2_VAR_WEP_KEY_WIDTH	GENMASK(7, 6)
367 #define RX_MPDU_START_INFO2_MESH_STA		BIT(8)
368 #define RX_MPDU_START_INFO2_BSSID_HIT		BIT(9)
369 #define RX_MPDU_START_INFO2_BSSID_NUM		GENMASK(13, 10)
370 #define RX_MPDU_START_INFO2_TID			GENMASK(17, 14)
371 #define RX_MPDU_START_INFO2_TID_WCN6855		GENMASK(18, 15)
372 
373 #define RX_MPDU_START_INFO3_REO_DEST_IND		GENMASK(4, 0)
374 #define RX_MPDU_START_INFO3_FLOW_ID_TOEPLITZ		BIT(7)
375 #define RX_MPDU_START_INFO3_PKT_SEL_FP_UCAST_DATA	BIT(8)
376 #define RX_MPDU_START_INFO3_PKT_SEL_FP_MCAST_DATA	BIT(9)
377 #define RX_MPDU_START_INFO3_PKT_SEL_FP_CTRL_BAR		BIT(10)
378 #define RX_MPDU_START_INFO3_RXDMA0_SRC_RING_SEL		GENMASK(12, 11)
379 #define RX_MPDU_START_INFO3_RXDMA0_DST_RING_SEL		GENMASK(14, 13)
380 
381 #define RX_MPDU_START_INFO4_REO_QUEUE_DESC_HI	GENMASK(7, 0)
382 #define RX_MPDU_START_INFO4_RECV_QUEUE_NUM	GENMASK(23, 8)
383 #define RX_MPDU_START_INFO4_PRE_DELIM_ERR_WARN	BIT(24)
384 #define RX_MPDU_START_INFO4_FIRST_DELIM_ERR	BIT(25)
385 
386 #define RX_MPDU_START_INFO5_KEY_ID		GENMASK(7, 0)
387 #define RX_MPDU_START_INFO5_NEW_PEER_ENTRY	BIT(8)
388 #define RX_MPDU_START_INFO5_DECRYPT_NEEDED	BIT(9)
389 #define RX_MPDU_START_INFO5_DECAP_TYPE		GENMASK(11, 10)
390 #define RX_MPDU_START_INFO5_VLAN_TAG_C_PADDING	BIT(12)
391 #define RX_MPDU_START_INFO5_VLAN_TAG_S_PADDING	BIT(13)
392 #define RX_MPDU_START_INFO5_STRIP_VLAN_TAG_C	BIT(14)
393 #define RX_MPDU_START_INFO5_STRIP_VLAN_TAG_S	BIT(15)
394 #define RX_MPDU_START_INFO5_PRE_DELIM_COUNT	GENMASK(27, 16)
395 #define RX_MPDU_START_INFO5_AMPDU_FLAG		BIT(28)
396 #define RX_MPDU_START_INFO5_BAR_FRAME		BIT(29)
397 
398 #define RX_MPDU_START_INFO6_MPDU_LEN		GENMASK(13, 0)
399 #define RX_MPDU_START_INFO6_FIRST_MPDU		BIT(14)
400 #define RX_MPDU_START_INFO6_MCAST_BCAST		BIT(15)
401 #define RX_MPDU_START_INFO6_AST_IDX_NOT_FOUND	BIT(16)
402 #define RX_MPDU_START_INFO6_AST_IDX_TIMEOUT	BIT(17)
403 #define RX_MPDU_START_INFO6_POWER_MGMT		BIT(18)
404 #define RX_MPDU_START_INFO6_NON_QOS		BIT(19)
405 #define RX_MPDU_START_INFO6_NULL_DATA		BIT(20)
406 #define RX_MPDU_START_INFO6_MGMT_TYPE		BIT(21)
407 #define RX_MPDU_START_INFO6_CTRL_TYPE		BIT(22)
408 #define RX_MPDU_START_INFO6_MORE_DATA		BIT(23)
409 #define RX_MPDU_START_INFO6_EOSP		BIT(24)
410 #define RX_MPDU_START_INFO6_FRAGMENT		BIT(25)
411 #define RX_MPDU_START_INFO6_ORDER		BIT(26)
412 #define RX_MPDU_START_INFO6_UAPSD_TRIGGER	BIT(27)
413 #define RX_MPDU_START_INFO6_ENCRYPT_REQUIRED	BIT(28)
414 #define RX_MPDU_START_INFO6_DIRECTED		BIT(29)
415 
416 #define RX_MPDU_START_RAW_MPDU			BIT(0)
417 
418 struct rx_mpdu_start_ipq8074 {
419 	__le16 info0;
420 	__le16 phy_ppdu_id;
421 	__le16 ast_index;
422 	__le16 sw_peer_id;
423 	__le32 info1;
424 	__le32 info2;
425 	__le32 pn[4];
426 	__le32 peer_meta_data;
427 	__le32 info3;
428 	__le32 reo_queue_desc_lo;
429 	__le32 info4;
430 	__le32 info5;
431 	__le32 info6;
432 	__le16 frame_ctrl;
433 	__le16 duration;
434 	u8 addr1[ETH_ALEN];
435 	u8 addr2[ETH_ALEN];
436 	u8 addr3[ETH_ALEN];
437 	__le16 seq_ctrl;
438 	u8 addr4[ETH_ALEN];
439 	__le16 qos_ctrl;
440 	__le32 ht_ctrl;
441 	__le32 raw;
442 } __packed;
443 
444 #define RX_MPDU_START_INFO7_REO_DEST_IND		GENMASK(4, 0)
445 #define RX_MPDU_START_INFO7_LMAC_PEER_ID_MSB		GENMASK(6, 5)
446 #define RX_MPDU_START_INFO7_FLOW_ID_TOEPLITZ		BIT(7)
447 #define RX_MPDU_START_INFO7_PKT_SEL_FP_UCAST_DATA	BIT(8)
448 #define RX_MPDU_START_INFO7_PKT_SEL_FP_MCAST_DATA	BIT(9)
449 #define RX_MPDU_START_INFO7_PKT_SEL_FP_CTRL_BAR		BIT(10)
450 #define RX_MPDU_START_INFO7_RXDMA0_SRC_RING_SEL		GENMASK(12, 11)
451 #define RX_MPDU_START_INFO7_RXDMA0_DST_RING_SEL		GENMASK(14, 13)
452 
453 #define RX_MPDU_START_INFO8_REO_QUEUE_DESC_HI		GENMASK(7, 0)
454 #define RX_MPDU_START_INFO8_RECV_QUEUE_NUM		GENMASK(23, 8)
455 #define RX_MPDU_START_INFO8_PRE_DELIM_ERR_WARN		BIT(24)
456 #define RX_MPDU_START_INFO8_FIRST_DELIM_ERR		BIT(25)
457 
458 #define RX_MPDU_START_INFO9_EPD_EN			BIT(0)
459 #define RX_MPDU_START_INFO9_ALL_FRAME_ENCPD		BIT(1)
460 #define RX_MPDU_START_INFO9_ENC_TYPE			GENMASK(5, 2)
461 #define RX_MPDU_START_INFO9_VAR_WEP_KEY_WIDTH		GENMASK(7, 6)
462 #define RX_MPDU_START_INFO9_MESH_STA			GENMASK(9, 8)
463 #define RX_MPDU_START_INFO9_BSSID_HIT			BIT(10)
464 #define RX_MPDU_START_INFO9_BSSID_NUM			GENMASK(14, 11)
465 #define RX_MPDU_START_INFO9_TID				GENMASK(18, 15)
466 
467 #define RX_MPDU_START_INFO10_RXPCU_MPDU_FLTR		GENMASK(1, 0)
468 #define RX_MPDU_START_INFO10_SW_FRAME_GRP_ID		GENMASK(8, 2)
469 #define RX_MPDU_START_INFO10_NDP_FRAME			BIT(9)
470 #define RX_MPDU_START_INFO10_PHY_ERR			BIT(10)
471 #define RX_MPDU_START_INFO10_PHY_ERR_MPDU_HDR		BIT(11)
472 #define RX_MPDU_START_INFO10_PROTO_VER_ERR		BIT(12)
473 #define RX_MPDU_START_INFO10_AST_LOOKUP_VALID		BIT(13)
474 
475 #define RX_MPDU_START_INFO11_MPDU_FCTRL_VALID		BIT(0)
476 #define RX_MPDU_START_INFO11_MPDU_DUR_VALID		BIT(1)
477 #define RX_MPDU_START_INFO11_MAC_ADDR1_VALID		BIT(2)
478 #define RX_MPDU_START_INFO11_MAC_ADDR2_VALID		BIT(3)
479 #define RX_MPDU_START_INFO11_MAC_ADDR3_VALID		BIT(4)
480 #define RX_MPDU_START_INFO11_MAC_ADDR4_VALID		BIT(5)
481 #define RX_MPDU_START_INFO11_MPDU_SEQ_CTRL_VALID	BIT(6)
482 #define RX_MPDU_START_INFO11_MPDU_QOS_CTRL_VALID	BIT(7)
483 #define RX_MPDU_START_INFO11_MPDU_HT_CTRL_VALID		BIT(8)
484 #define RX_MPDU_START_INFO11_ENCRYPT_INFO_VALID		BIT(9)
485 #define RX_MPDU_START_INFO11_MPDU_FRAG_NUMBER		GENMASK(13, 10)
486 #define RX_MPDU_START_INFO11_MORE_FRAG_FLAG		BIT(14)
487 #define RX_MPDU_START_INFO11_FROM_DS			BIT(16)
488 #define RX_MPDU_START_INFO11_TO_DS			BIT(17)
489 #define RX_MPDU_START_INFO11_ENCRYPTED			BIT(18)
490 #define RX_MPDU_START_INFO11_MPDU_RETRY			BIT(19)
491 #define RX_MPDU_START_INFO11_MPDU_SEQ_NUM		GENMASK(31, 20)
492 
493 #define RX_MPDU_START_INFO12_KEY_ID			GENMASK(7, 0)
494 #define RX_MPDU_START_INFO12_NEW_PEER_ENTRY		BIT(8)
495 #define RX_MPDU_START_INFO12_DECRYPT_NEEDED		BIT(9)
496 #define RX_MPDU_START_INFO12_DECAP_TYPE			GENMASK(11, 10)
497 #define RX_MPDU_START_INFO12_VLAN_TAG_C_PADDING		BIT(12)
498 #define RX_MPDU_START_INFO12_VLAN_TAG_S_PADDING		BIT(13)
499 #define RX_MPDU_START_INFO12_STRIP_VLAN_TAG_C		BIT(14)
500 #define RX_MPDU_START_INFO12_STRIP_VLAN_TAG_S		BIT(15)
501 #define RX_MPDU_START_INFO12_PRE_DELIM_COUNT		GENMASK(27, 16)
502 #define RX_MPDU_START_INFO12_AMPDU_FLAG			BIT(28)
503 #define RX_MPDU_START_INFO12_BAR_FRAME			BIT(29)
504 #define RX_MPDU_START_INFO12_RAW_MPDU			BIT(30)
505 
506 #define RX_MPDU_START_INFO13_MPDU_LEN			GENMASK(13, 0)
507 #define RX_MPDU_START_INFO13_FIRST_MPDU			BIT(14)
508 #define RX_MPDU_START_INFO13_MCAST_BCAST		BIT(15)
509 #define RX_MPDU_START_INFO13_AST_IDX_NOT_FOUND		BIT(16)
510 #define RX_MPDU_START_INFO13_AST_IDX_TIMEOUT		BIT(17)
511 #define RX_MPDU_START_INFO13_POWER_MGMT			BIT(18)
512 #define RX_MPDU_START_INFO13_NON_QOS			BIT(19)
513 #define RX_MPDU_START_INFO13_NULL_DATA			BIT(20)
514 #define RX_MPDU_START_INFO13_MGMT_TYPE			BIT(21)
515 #define RX_MPDU_START_INFO13_CTRL_TYPE			BIT(22)
516 #define RX_MPDU_START_INFO13_MORE_DATA			BIT(23)
517 #define RX_MPDU_START_INFO13_EOSP			BIT(24)
518 #define RX_MPDU_START_INFO13_FRAGMENT			BIT(25)
519 #define RX_MPDU_START_INFO13_ORDER			BIT(26)
520 #define RX_MPDU_START_INFO13_UAPSD_TRIGGER		BIT(27)
521 #define RX_MPDU_START_INFO13_ENCRYPT_REQUIRED		BIT(28)
522 #define RX_MPDU_START_INFO13_DIRECTED			BIT(29)
523 #define RX_MPDU_START_INFO13_AMSDU_PRESENT		BIT(30)
524 
525 struct rx_mpdu_start_qcn9074 {
526 	__le32 info7;
527 	__le32 reo_queue_desc_lo;
528 	__le32 info8;
529 	__le32 pn[4];
530 	__le32 info9;
531 	__le32 peer_meta_data;
532 	__le16 info10;
533 	__le16 phy_ppdu_id;
534 	__le16 ast_index;
535 	__le16 sw_peer_id;
536 	__le32 info11;
537 	__le32 info12;
538 	__le32 info13;
539 	__le16 frame_ctrl;
540 	__le16 duration;
541 	u8 addr1[ETH_ALEN];
542 	u8 addr2[ETH_ALEN];
543 	u8 addr3[ETH_ALEN];
544 	__le16 seq_ctrl;
545 	u8 addr4[ETH_ALEN];
546 	__le16 qos_ctrl;
547 	__le32 ht_ctrl;
548 } __packed;
549 
550 struct rx_mpdu_start_wcn6855 {
551 	__le32 info3;
552 	__le32 reo_queue_desc_lo;
553 	__le32 info4;
554 	__le32 pn[4];
555 	__le32 info2;
556 	__le32 peer_meta_data;
557 	__le16 info0;
558 	__le16 phy_ppdu_id;
559 	__le16 ast_index;
560 	__le16 sw_peer_id;
561 	__le32 info1;
562 	__le32 info5;
563 	__le32 info6;
564 	__le16 frame_ctrl;
565 	__le16 duration;
566 	u8 addr1[ETH_ALEN];
567 	u8 addr2[ETH_ALEN];
568 	u8 addr3[ETH_ALEN];
569 	__le16 seq_ctrl;
570 	u8 addr4[ETH_ALEN];
571 	__le16 qos_ctrl;
572 	__le32 ht_ctrl;
573 } __packed;
574 
575 /* rx_mpdu_start
576  *
577  * rxpcu_mpdu_filter_in_category
578  *		Field indicates what the reason was that this mpdu frame
579  *		was allowed to come into the receive path by rxpcu. Values
580  *		are defined in enum %RX_DESC_RXPCU_FILTER_*.
581  *		Note: for ndp frame, if it was expected because the preceding
582  *		NDPA was filter_pass, the setting rxpcu_filter_pass will be
583  *		used. This setting will also be used for every ndp frame in
584  *		case Promiscuous mode is enabled.
585  *
586  * sw_frame_group_id
587  *		SW processes frames based on certain classifications. Values
588  *		are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*.
589  *
590  * ndp_frame
591  *		Indicates that the received frame was an NDP frame.
592  *
593  * phy_err
594  *		Indicates that PHY error was received before MAC received data.
595  *
596  * phy_err_during_mpdu_header
597  *		PHY error was received before MAC received the complete MPDU
598  *		header which was needed for proper decoding.
599  *
600  * protocol_version_err
601  *		RXPCU detected a version error in the frame control field.
602  *
603  * ast_based_lookup_valid
604  *		AST based lookup for this frame has found a valid result.
605  *
606  * phy_ppdu_id
607  *		A ppdu counter value that PHY increments for every PPDU
608  *		received. The counter value wraps around.
609  *
610  * ast_index
611  *		This field indicates the index of the AST entry corresponding
612  *		to this MPDU. It is provided by the GSE module instantiated in
613  *		RXPCU. A value of 0xFFFF indicates an invalid AST index.
614  *
615  * sw_peer_id
616  *		This field indicates a unique peer identifier. It is set equal
617  *		to field 'sw_peer_id' from the AST entry.
618  *
619  * mpdu_frame_control_valid, mpdu_duration_valid, mpdu_qos_control_valid,
620  * mpdu_ht_control_valid, frame_encryption_info_valid
621  *		Indicates that each fields have valid entries.
622  *
623  * mac_addr_adx_valid
624  *		Corresponding mac_addr_adx_{lo/hi} has valid entries.
625  *
626  * from_ds, to_ds
627  *		Valid only when mpdu_frame_control_valid is set. Indicates that
628  *		frame is received from DS and sent to DS.
629  *
630  * encrypted
631  *		Protected bit from the frame control.
632  *
633  * mpdu_retry
634  *		Retry bit from frame control. Only valid when first_msdu is set.
635  *
636  * mpdu_sequence_number
637  *		The sequence number from the 802.11 header.
638  *
639  * epd_en
640  *		If set, use EPD instead of LPD.
641  *
642  * all_frames_shall_be_encrypted
643  *		If set, all frames (data only?) shall be encrypted. If not,
644  *		RX CRYPTO shall set an error flag.
645  *
646  * encrypt_type
647  *		Values are defined in enum %HAL_ENCRYPT_TYPE_.
648  *
649  * mesh_sta
650  *		Indicates a Mesh (11s) STA.
651  *
652  * bssid_hit
653  *		 BSSID of the incoming frame matched one of the 8 BSSID
654  *		 register values.
655  *
656  * bssid_number
657  *		This number indicates which one out of the 8 BSSID register
658  *		values matched the incoming frame.
659  *
660  * tid
661  *		TID field in the QoS control field
662  *
663  * pn
664  *		The PN number.
665  *
666  * peer_meta_data
667  *		Meta data that SW has programmed in the Peer table entry
668  *		of the transmitting STA.
669  *
670  * rx_reo_queue_desc_addr_lo
671  *		Address (lower 32 bits) of the REO queue descriptor.
672  *
673  * rx_reo_queue_desc_addr_hi
674  *		Address (upper 8 bits) of the REO queue descriptor.
675  *
676  * receive_queue_number
677  *		Indicates the MPDU queue ID to which this MPDU link
678  *		descriptor belongs.
679  *
680  * pre_delim_err_warning
681  *		Indicates that a delimiter FCS error was found in between the
682  *		previous MPDU and this MPDU. Note that this is just a warning,
683  *		and does not mean that this MPDU is corrupted in any way. If
684  *		it is, there will be other errors indicated such as FCS or
685  *		decrypt errors.
686  *
687  * first_delim_err
688  *		Indicates that the first delimiter had a FCS failure.
689  *
690  * key_id
691  *		The key ID octet from the IV.
692  *
693  * new_peer_entry
694  *		Set if new RX_PEER_ENTRY TLV follows. If clear, RX_PEER_ENTRY
695  *		doesn't follow so RX DECRYPTION module either uses old peer
696  *		entry or not decrypt.
697  *
698  * decrypt_needed
699  *		When RXPCU sets bit 'ast_index_not_found or ast_index_timeout',
700  *		RXPCU will also ensure that this bit is NOT set. CRYPTO for that
701  *		reason only needs to evaluate this bit and non of the other ones
702  *
703  * decap_type
704  *		Used by the OLE during decapsulation. Values are defined in
705  *		enum %MPDU_START_DECAP_TYPE_*.
706  *
707  * rx_insert_vlan_c_tag_padding
708  * rx_insert_vlan_s_tag_padding
709  *		Insert 4 byte of all zeros as VLAN tag or double VLAN tag if
710  *		the rx payload does not have VLAN.
711  *
712  * strip_vlan_c_tag_decap
713  * strip_vlan_s_tag_decap
714  *		Strip VLAN or double VLAN during decapsulation.
715  *
716  * pre_delim_count
717  *		The number of delimiters before this MPDU. Note that this
718  *		number is cleared at PPDU start. If this MPDU is the first
719  *		received MPDU in the PPDU and this MPDU gets filtered-in,
720  *		this field will indicate the number of delimiters located
721  *		after the last MPDU in the previous PPDU.
722  *
723  *		If this MPDU is located after the first received MPDU in
724  *		an PPDU, this field will indicate the number of delimiters
725  *		located between the previous MPDU and this MPDU.
726  *
727  * ampdu_flag
728  *		Received frame was part of an A-MPDU.
729  *
730  * bar_frame
731  *		Received frame is a BAR frame
732  *
733  * mpdu_length
734  *		MPDU length before decapsulation.
735  *
736  * first_mpdu..directed
737  *		See definition in RX attention descriptor
738  *
739  */
740 
741 enum rx_msdu_start_pkt_type {
742 	RX_MSDU_START_PKT_TYPE_11A,
743 	RX_MSDU_START_PKT_TYPE_11B,
744 	RX_MSDU_START_PKT_TYPE_11N,
745 	RX_MSDU_START_PKT_TYPE_11AC,
746 	RX_MSDU_START_PKT_TYPE_11AX,
747 };
748 
749 enum rx_msdu_start_sgi {
750 	RX_MSDU_START_SGI_0_8_US,
751 	RX_MSDU_START_SGI_0_4_US,
752 	RX_MSDU_START_SGI_1_6_US,
753 	RX_MSDU_START_SGI_3_2_US,
754 };
755 
756 enum rx_msdu_start_recv_bw {
757 	RX_MSDU_START_RECV_BW_20MHZ,
758 	RX_MSDU_START_RECV_BW_40MHZ,
759 	RX_MSDU_START_RECV_BW_80MHZ,
760 	RX_MSDU_START_RECV_BW_160MHZ,
761 };
762 
763 enum rx_msdu_start_reception_type {
764 	RX_MSDU_START_RECEPTION_TYPE_SU,
765 	RX_MSDU_START_RECEPTION_TYPE_DL_MU_MIMO,
766 	RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA,
767 	RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA_MIMO,
768 	RX_MSDU_START_RECEPTION_TYPE_UL_MU_MIMO,
769 	RX_MSDU_START_RECEPTION_TYPE_UL_MU_OFDMA,
770 	RX_MSDU_START_RECEPTION_TYPE_UL_MU_OFDMA_MIMO,
771 };
772 
773 #define RX_MSDU_START_INFO1_MSDU_LENGTH		GENMASK(13, 0)
774 #define RX_MSDU_START_INFO1_RSVD_1A		BIT(14)
775 #define RX_MSDU_START_INFO1_IPSEC_ESP		BIT(15)
776 #define RX_MSDU_START_INFO1_L3_OFFSET		GENMASK(22, 16)
777 #define RX_MSDU_START_INFO1_IPSEC_AH		BIT(23)
778 #define RX_MSDU_START_INFO1_L4_OFFSET		GENMASK(31, 24)
779 
780 #define RX_MSDU_START_INFO2_MSDU_NUMBER		GENMASK(7, 0)
781 #define RX_MSDU_START_INFO2_DECAP_TYPE		GENMASK(9, 8)
782 #define RX_MSDU_START_INFO2_IPV4		BIT(10)
783 #define RX_MSDU_START_INFO2_IPV6		BIT(11)
784 #define RX_MSDU_START_INFO2_TCP			BIT(12)
785 #define RX_MSDU_START_INFO2_UDP			BIT(13)
786 #define RX_MSDU_START_INFO2_IP_FRAG		BIT(14)
787 #define RX_MSDU_START_INFO2_TCP_ONLY_ACK	BIT(15)
788 #define RX_MSDU_START_INFO2_DA_IS_BCAST_MCAST	BIT(16)
789 #define RX_MSDU_START_INFO2_SELECTED_TOEPLITZ_HASH	GENMASK(18, 17)
790 #define RX_MSDU_START_INFO2_IP_FIXED_HDR_VALID		BIT(19)
791 #define RX_MSDU_START_INFO2_IP_EXTN_HDR_VALID		BIT(20)
792 #define RX_MSDU_START_INFO2_IP_TCP_UDP_HDR_VALID	BIT(21)
793 #define RX_MSDU_START_INFO2_MESH_CTRL_PRESENT		BIT(22)
794 #define RX_MSDU_START_INFO2_LDPC			BIT(23)
795 #define RX_MSDU_START_INFO2_IP4_IP6_NXT_HDR		GENMASK(31, 24)
796 #define RX_MSDU_START_INFO2_DECAP_FORMAT		GENMASK(9, 8)
797 
798 #define RX_MSDU_START_INFO3_USER_RSSI		GENMASK(7, 0)
799 #define RX_MSDU_START_INFO3_PKT_TYPE		GENMASK(11, 8)
800 #define RX_MSDU_START_INFO3_STBC		BIT(12)
801 #define RX_MSDU_START_INFO3_SGI			GENMASK(14, 13)
802 #define RX_MSDU_START_INFO3_RATE_MCS		GENMASK(18, 15)
803 #define RX_MSDU_START_INFO3_RECV_BW		GENMASK(20, 19)
804 #define RX_MSDU_START_INFO3_RECEPTION_TYPE	GENMASK(23, 21)
805 #define RX_MSDU_START_INFO3_MIMO_SS_BITMAP	GENMASK(31, 24)
806 
807 struct rx_msdu_start_ipq8074 {
808 	__le16 info0;
809 	__le16 phy_ppdu_id;
810 	__le32 info1;
811 	__le32 info2;
812 	__le32 toeplitz_hash;
813 	__le32 flow_id_toeplitz;
814 	__le32 info3;
815 	__le32 ppdu_start_timestamp;
816 	__le32 phy_meta_data;
817 } __packed;
818 
819 struct rx_msdu_start_qcn9074 {
820 	__le16 info0;
821 	__le16 phy_ppdu_id;
822 	__le32 info1;
823 	__le32 info2;
824 	__le32 toeplitz_hash;
825 	__le32 flow_id_toeplitz;
826 	__le32 info3;
827 	__le32 ppdu_start_timestamp;
828 	__le32 phy_meta_data;
829 	__le16 vlan_ctag_c1;
830 	__le16 vlan_stag_c1;
831 } __packed;
832 
833 struct rx_msdu_start_wcn6855 {
834 	__le16 info0;
835 	__le16 phy_ppdu_id;
836 	__le32 info1;
837 	__le32 info2;
838 	__le32 toeplitz_hash;
839 	__le32 flow_id_toeplitz;
840 	__le32 info3;
841 	__le32 ppdu_start_timestamp;
842 	__le32 phy_meta_data;
843 	__le16 vlan_ctag_ci;
844 	__le16 vlan_stag_ci;
845 } __packed;
846 
847 /* rx_msdu_start
848  *
849  * rxpcu_mpdu_filter_in_category
850  *		Field indicates what the reason was that this mpdu frame
851  *		was allowed to come into the receive path by rxpcu. Values
852  *		are defined in enum %RX_DESC_RXPCU_FILTER_*.
853  *
854  * sw_frame_group_id
855  *		SW processes frames based on certain classifications. Values
856  *		are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*.
857  *
858  * phy_ppdu_id
859  *		A ppdu counter value that PHY increments for every PPDU
860  *		received. The counter value wraps around.
861  *
862  * msdu_length
863  *		MSDU length in bytes after decapsulation.
864  *
865  * ipsec_esp
866  *		Set if IPv4/v6 packet is using IPsec ESP.
867  *
868  * l3_offset
869  *		Depending upon mode bit, this field either indicates the
870  *		L3 offset in bytes from the start of the RX_HEADER or the IP
871  *		offset in bytes from the start of the packet after
872  *		decapsulation. The latter is only valid if ipv4_proto or
873  *		ipv6_proto is set.
874  *
875  * ipsec_ah
876  *		Set if IPv4/v6 packet is using IPsec AH
877  *
878  * l4_offset
879  *		Depending upon mode bit, this field either indicates the
880  *		L4 offset nin bytes from the start of RX_HEADER (only valid
881  *		if either ipv4_proto or ipv6_proto is set to 1) or indicates
882  *		the offset in bytes to the start of TCP or UDP header from
883  *		the start of the IP header after decapsulation (Only valid if
884  *		tcp_proto or udp_proto is set). The value 0 indicates that
885  *		the offset is longer than 127 bytes.
886  *
887  * msdu_number
888  *		Indicates the MSDU number within a MPDU.  This value is
889  *		reset to zero at the start of each MPDU.  If the number of
890  *		MSDU exceeds 255 this number will wrap using modulo 256.
891  *
892  * decap_type
893  *		Indicates the format after decapsulation. Values are defined in
894  *		enum %MPDU_START_DECAP_TYPE_*.
895  *
896  * ipv4_proto
897  *		Set if L2 layer indicates IPv4 protocol.
898  *
899  * ipv6_proto
900  *		Set if L2 layer indicates IPv6 protocol.
901  *
902  * tcp_proto
903  *		Set if the ipv4_proto or ipv6_proto are set and the IP protocol
904  *		indicates TCP.
905  *
906  * udp_proto
907  *		Set if the ipv4_proto or ipv6_proto are set and the IP protocol
908  *		indicates UDP.
909  *
910  * ip_frag
911  *		Indicates that either the IP More frag bit is set or IP frag
912  *		number is non-zero.  If set indicates that this is a fragmented
913  *		IP packet.
914  *
915  * tcp_only_ack
916  *		Set if only the TCP Ack bit is set in the TCP flags and if
917  *		the TCP payload is 0.
918  *
919  * da_is_bcast_mcast
920  *		The destination address is broadcast or multicast.
921  *
922  * toeplitz_hash
923  *		Actual chosen Hash.
924  *		0 - Toeplitz hash of 2-tuple (IP source address, IP
925  *		    destination address)
926  *		1 - Toeplitz hash of 4-tuple (IP source	address,
927  *		    IP destination address, L4 (TCP/UDP) source port,
928  *		    L4 (TCP/UDP) destination port)
929  *		2 - Toeplitz of flow_id
930  *		3 - Zero is used
931  *
932  * ip_fixed_header_valid
933  *		Fixed 20-byte IPv4 header or 40-byte IPv6 header parsed
934  *		fully within first 256 bytes of the packet
935  *
936  * ip_extn_header_valid
937  *		IPv6/IPv6 header, including IPv4 options and
938  *		recognizable extension headers parsed fully within first 256
939  *		bytes of the packet
940  *
941  * tcp_udp_header_valid
942  *		Fixed 20-byte TCP (excluding TCP options) or 8-byte UDP
943  *		header parsed fully within first 256 bytes of the packet
944  *
945  * mesh_control_present
946  *		When set, this MSDU includes the 'Mesh Control' field
947  *
948  * ldpc
949  *
950  * ip4_protocol_ip6_next_header
951  *		For IPv4, this is the 8 bit protocol field set). For IPv6 this
952  *		is the 8 bit next_header field.
953  *
954  * toeplitz_hash_2_or_4
955  *		Controlled by RxOLE register - If register bit set to 0,
956  *		Toeplitz hash is computed over 2-tuple IPv4 or IPv6 src/dest
957  *		addresses; otherwise, toeplitz hash is computed over 4-tuple
958  *		IPv4 or IPv6 src/dest addresses and src/dest ports.
959  *
960  * flow_id_toeplitz
961  *		Toeplitz hash of 5-tuple
962  *		{IP source address, IP destination address, IP source port, IP
963  *		destination port, L4 protocol}  in case of non-IPSec.
964  *
965  *		In case of IPSec - Toeplitz hash of 4-tuple
966  *		{IP source address, IP destination address, SPI, L4 protocol}
967  *
968  *		The relevant Toeplitz key registers are provided in RxOLE's
969  *		instance of common parser module. These registers are separate
970  *		from the Toeplitz keys used by ASE/FSE modules inside RxOLE.
971  *		The actual value will be passed on from common parser module
972  *		to RxOLE in one of the WHO_* TLVs.
973  *
974  * user_rssi
975  *		RSSI for this user
976  *
977  * pkt_type
978  *		Values are defined in enum %RX_MSDU_START_PKT_TYPE_*.
979  *
980  * stbc
981  *		When set, use STBC transmission rates.
982  *
983  * sgi
984  *		Field only valid when pkt type is HT, VHT or HE. Values are
985  *		defined in enum %RX_MSDU_START_SGI_*.
986  *
987  * rate_mcs
988  *		MCS Rate used.
989  *
990  * receive_bandwidth
991  *		Full receive Bandwidth. Values are defined in enum
992  *		%RX_MSDU_START_RECV_*.
993  *
994  * reception_type
995  *		Indicates what type of reception this is and defined in enum
996  *		%RX_MSDU_START_RECEPTION_TYPE_*.
997  *
998  * mimo_ss_bitmap
999  *		Field only valid when
1000  *		Reception_type is RX_MSDU_START_RECEPTION_TYPE_DL_MU_MIMO or
1001  *		RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA_MIMO.
1002  *
1003  *		Bitmap, with each bit indicating if the related spatial
1004  *		stream is used for this STA
1005  *
1006  *		LSB related to SS 0
1007  *
1008  *		0 - spatial stream not used for this reception
1009  *		1 - spatial stream used for this reception
1010  *
1011  * ppdu_start_timestamp
1012  *		Timestamp that indicates when the PPDU that contained this MPDU
1013  *		started on the medium.
1014  *
1015  * phy_meta_data
1016  *		SW programmed Meta data provided by the PHY. Can be used for SW
1017  *		to indicate the channel the device is on.
1018  */
1019 
1020 #define RX_MSDU_END_INFO0_RXPCU_MPDU_FITLER	GENMASK(1, 0)
1021 #define RX_MSDU_END_INFO0_SW_FRAME_GRP_ID	GENMASK(8, 2)
1022 
1023 #define RX_MSDU_END_INFO1_KEY_ID		GENMASK(7, 0)
1024 #define RX_MSDU_END_INFO1_CCE_SUPER_RULE	GENMASK(13, 8)
1025 #define RX_MSDU_END_INFO1_CCND_TRUNCATE		BIT(14)
1026 #define RX_MSDU_END_INFO1_CCND_CCE_DIS		BIT(15)
1027 #define RX_MSDU_END_INFO1_EXT_WAPI_PN		GENMASK(31, 16)
1028 
1029 #define RX_MSDU_END_INFO2_REPORTED_MPDU_LEN	GENMASK(13, 0)
1030 #define RX_MSDU_END_INFO2_FIRST_MSDU		BIT(14)
1031 #define RX_MSDU_END_INFO2_FIRST_MSDU_WCN6855	BIT(28)
1032 #define RX_MSDU_END_INFO2_LAST_MSDU		BIT(15)
1033 #define RX_MSDU_END_INFO2_LAST_MSDU_WCN6855	BIT(29)
1034 #define RX_MSDU_END_INFO2_SA_IDX_TIMEOUT	BIT(16)
1035 #define RX_MSDU_END_INFO2_DA_IDX_TIMEOUT	BIT(17)
1036 #define RX_MSDU_END_INFO2_MSDU_LIMIT_ERR	BIT(18)
1037 #define RX_MSDU_END_INFO2_FLOW_IDX_TIMEOUT	BIT(19)
1038 #define RX_MSDU_END_INFO2_FLOW_IDX_INVALID	BIT(20)
1039 #define RX_MSDU_END_INFO2_WIFI_PARSER_ERR	BIT(21)
1040 #define RX_MSDU_END_INFO2_AMSDU_PARSET_ERR	BIT(22)
1041 #define RX_MSDU_END_INFO2_SA_IS_VALID		BIT(23)
1042 #define RX_MSDU_END_INFO2_DA_IS_VALID		BIT(24)
1043 #define RX_MSDU_END_INFO2_DA_IS_MCBC		BIT(25)
1044 #define RX_MSDU_END_INFO2_L3_HDR_PADDING	GENMASK(27, 26)
1045 
1046 #define RX_MSDU_END_INFO3_TCP_FLAG		GENMASK(8, 0)
1047 #define RX_MSDU_END_INFO3_LRO_ELIGIBLE		BIT(9)
1048 
1049 #define RX_MSDU_END_INFO4_DA_OFFSET		GENMASK(5, 0)
1050 #define RX_MSDU_END_INFO4_SA_OFFSET		GENMASK(11, 6)
1051 #define RX_MSDU_END_INFO4_DA_OFFSET_VALID	BIT(12)
1052 #define RX_MSDU_END_INFO4_SA_OFFSET_VALID	BIT(13)
1053 #define RX_MSDU_END_INFO4_L3_TYPE		GENMASK(31, 16)
1054 
1055 #define RX_MSDU_END_INFO5_MSDU_DROP		BIT(0)
1056 #define RX_MSDU_END_INFO5_REO_DEST_IND		GENMASK(5, 1)
1057 #define RX_MSDU_END_INFO5_FLOW_IDX		GENMASK(25, 6)
1058 
1059 struct rx_msdu_end_ipq8074 {
1060 	__le16 info0;
1061 	__le16 phy_ppdu_id;
1062 	__le16 ip_hdr_cksum;
1063 	__le16 tcp_udp_cksum;
1064 	__le32 info1;
1065 	__le32 ext_wapi_pn[2];
1066 	__le32 info2;
1067 	__le32 ipv6_options_crc;
1068 	__le32 tcp_seq_num;
1069 	__le32 tcp_ack_num;
1070 	__le16 info3;
1071 	__le16 window_size;
1072 	__le32 info4;
1073 	__le32 rule_indication[2];
1074 	__le16 sa_idx;
1075 	__le16 da_idx;
1076 	__le32 info5;
1077 	__le32 fse_metadata;
1078 	__le16 cce_metadata;
1079 	__le16 sa_sw_peer_id;
1080 } __packed;
1081 
1082 struct rx_msdu_end_wcn6855 {
1083 	__le16 info0;
1084 	__le16 phy_ppdu_id;
1085 	__le16 ip_hdr_cksum;
1086 	__le16 reported_mpdu_len;
1087 	__le32 info1;
1088 	__le32 ext_wapi_pn[2];
1089 	__le32 info4;
1090 	__le32 ipv6_options_crc;
1091 	__le32 tcp_seq_num;
1092 	__le32 tcp_ack_num;
1093 	__le16 info3;
1094 	__le16 window_size;
1095 	__le32 info2;
1096 	__le16 sa_idx;
1097 	__le16 da_idx;
1098 	__le32 info5;
1099 	__le32 fse_metadata;
1100 	__le16 cce_metadata;
1101 	__le16 sa_sw_peer_id;
1102 	__le32 rule_indication[2];
1103 	__le32 info6;
1104 	__le32 info7;
1105 } __packed;
1106 
1107 #define RX_MSDU_END_MPDU_LENGTH_INFO		GENMASK(13, 0)
1108 
1109 #define RX_MSDU_END_INFO2_DA_OFFSET		GENMASK(5, 0)
1110 #define RX_MSDU_END_INFO2_SA_OFFSET		GENMASK(11, 6)
1111 #define RX_MSDU_END_INFO2_DA_OFFSET_VALID	BIT(12)
1112 #define RX_MSDU_END_INFO2_SA_OFFSET_VALID	BIT(13)
1113 #define RX_MSDU_END_INFO2_L3_TYPE		GENMASK(31, 16)
1114 
1115 #define RX_MSDU_END_INFO4_SA_IDX_TIMEOUT	BIT(0)
1116 #define RX_MSDU_END_INFO4_DA_IDX_TIMEOUT	BIT(1)
1117 #define RX_MSDU_END_INFO4_MSDU_LIMIT_ERR	BIT(2)
1118 #define RX_MSDU_END_INFO4_FLOW_IDX_TIMEOUT	BIT(3)
1119 #define RX_MSDU_END_INFO4_FLOW_IDX_INVALID	BIT(4)
1120 #define RX_MSDU_END_INFO4_WIFI_PARSER_ERR	BIT(5)
1121 #define RX_MSDU_END_INFO4_AMSDU_PARSER_ERR	BIT(6)
1122 #define RX_MSDU_END_INFO4_SA_IS_VALID		BIT(7)
1123 #define RX_MSDU_END_INFO4_DA_IS_VALID		BIT(8)
1124 #define RX_MSDU_END_INFO4_DA_IS_MCBC		BIT(9)
1125 #define RX_MSDU_END_INFO4_L3_HDR_PADDING	GENMASK(11, 10)
1126 #define RX_MSDU_END_INFO4_FIRST_MSDU		BIT(12)
1127 #define RX_MSDU_END_INFO4_LAST_MSDU		BIT(13)
1128 
1129 #define RX_MSDU_END_INFO6_AGGR_COUNT		GENMASK(7, 0)
1130 #define RX_MSDU_END_INFO6_FLOW_AGGR_CONTN	BIT(8)
1131 #define RX_MSDU_END_INFO6_FISA_TIMEOUT		BIT(9)
1132 
1133 struct rx_msdu_end_qcn9074 {
1134 	__le16 info0;
1135 	__le16 phy_ppdu_id;
1136 	__le16 ip_hdr_cksum;
1137 	__le16 mpdu_length_info;
1138 	__le32 info1;
1139 	__le32 rule_indication[2];
1140 	__le32 info2;
1141 	__le32 ipv6_options_crc;
1142 	__le32 tcp_seq_num;
1143 	__le32 tcp_ack_num;
1144 	__le16 info3;
1145 	__le16 window_size;
1146 	__le16 tcp_udp_cksum;
1147 	__le16 info4;
1148 	__le16 sa_idx;
1149 	__le16 da_idx;
1150 	__le32 info5;
1151 	__le32 fse_metadata;
1152 	__le16 cce_metadata;
1153 	__le16 sa_sw_peer_id;
1154 	__le32 info6;
1155 	__le16 cum_l4_cksum;
1156 	__le16 cum_ip_length;
1157 } __packed;
1158 
1159 /* rx_msdu_end
1160  *
1161  * rxpcu_mpdu_filter_in_category
1162  *		Field indicates what the reason was that this mpdu frame
1163  *		was allowed to come into the receive path by rxpcu. Values
1164  *		are defined in enum %RX_DESC_RXPCU_FILTER_*.
1165  *
1166  * sw_frame_group_id
1167  *		SW processes frames based on certain classifications. Values
1168  *		are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*.
1169  *
1170  * phy_ppdu_id
1171  *		A ppdu counter value that PHY increments for every PPDU
1172  *		received. The counter value wraps around.
1173  *
1174  * ip_hdr_cksum
1175  *		This can include the IP header checksum or the pseudo
1176  *		header checksum used by TCP/UDP checksum.
1177  *
1178  * tcp_udp_chksum
1179  *		The value of the computed TCP/UDP checksum.  A mode bit
1180  *		selects whether this checksum is the full checksum or the
1181  *		partial checksum which does not include the pseudo header.
1182  *
1183  * key_id
1184  *		The key ID octet from the IV. Only valid when first_msdu is set.
1185  *
1186  * cce_super_rule
1187  *		Indicates the super filter rule.
1188  *
1189  * cce_classify_not_done_truncate
1190  *		Classification failed due to truncated frame.
1191  *
1192  * cce_classify_not_done_cce_dis
1193  *		Classification failed due to CCE global disable
1194  *
1195  * ext_wapi_pn*
1196  *		Extension PN (packet number) which is only used by WAPI.
1197  *
1198  * reported_mpdu_length
1199  *		MPDU length before decapsulation. Only valid when first_msdu is
1200  *		set. This field is taken directly from the length field of the
1201  *		A-MPDU delimiter or the preamble length field for non-A-MPDU
1202  *		frames.
1203  *
1204  * first_msdu
1205  *		Indicates the first MSDU of A-MSDU. If both first_msdu and
1206  *		last_msdu are set in the MSDU then this is a non-aggregated MSDU
1207  *		frame: normal MPDU. Interior MSDU in an A-MSDU shall have both
1208  *		first_mpdu and last_mpdu bits set to 0.
1209  *
1210  * last_msdu
1211  *		Indicates the last MSDU of the A-MSDU. MPDU end status is only
1212  *		valid when last_msdu is set.
1213  *
1214  * sa_idx_timeout
1215  *		Indicates an unsuccessful MAC source address search due to the
1216  *		expiring of the search timer.
1217  *
1218  * da_idx_timeout
1219  *		Indicates an unsuccessful MAC destination address search due to
1220  *		the expiring of the search timer.
1221  *
1222  * msdu_limit_error
1223  *		Indicates that the MSDU threshold was exceeded and thus all the
1224  *		rest of the MSDUs will not be scattered and will not be
1225  *		decapsulated but will be DMA'ed in RAW format as a single MSDU.
1226  *
1227  * flow_idx_timeout
1228  *		Indicates an unsuccessful flow search due to the expiring of
1229  *		the search timer.
1230  *
1231  * flow_idx_invalid
1232  *		flow id is not valid.
1233  *
1234  * amsdu_parser_error
1235  *		A-MSDU could not be properly de-agregated.
1236  *
1237  * sa_is_valid
1238  *		Indicates that OLE found a valid SA entry.
1239  *
1240  * da_is_valid
1241  *		Indicates that OLE found a valid DA entry.
1242  *
1243  * da_is_mcbc
1244  *		Field Only valid if da_is_valid is set. Indicates the DA address
1245  *		was a Multicast of Broadcast address.
1246  *
1247  * l3_header_padding
1248  *		Number of bytes padded  to make sure that the L3 header will
1249  *		always start of a Dword boundary.
1250  *
1251  * ipv6_options_crc
1252  *		32 bit CRC computed out of  IP v6 extension headers.
1253  *
1254  * tcp_seq_number
1255  *		TCP sequence number.
1256  *
1257  * tcp_ack_number
1258  *		TCP acknowledge number.
1259  *
1260  * tcp_flag
1261  *		TCP flags {NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN}.
1262  *
1263  * lro_eligible
1264  *		Computed out of TCP and IP fields to indicate that this
1265  *		MSDU is eligible for LRO.
1266  *
1267  * window_size
1268  *		TCP receive window size.
1269  *
1270  * da_offset
1271  *		Offset into MSDU buffer for DA.
1272  *
1273  * sa_offset
1274  *		Offset into MSDU buffer for SA.
1275  *
1276  * da_offset_valid
1277  *		da_offset field is valid. This will be set to 0 in case
1278  *		of a dynamic A-MSDU when DA is compressed.
1279  *
1280  * sa_offset_valid
1281  *		sa_offset field is valid. This will be set to 0 in case
1282  *		of a dynamic A-MSDU when SA is compressed.
1283  *
1284  * l3_type
1285  *		The 16-bit type value indicating the type of L3 later
1286  *		extracted from LLC/SNAP, set to zero if SNAP is not
1287  *		available.
1288  *
1289  * rule_indication
1290  *		Bitmap indicating which of rules have matched.
1291  *
1292  * sa_idx
1293  *		The offset in the address table which matches MAC source address
1294  *
1295  * da_idx
1296  *		The offset in the address table which matches MAC destination
1297  *		address.
1298  *
1299  * msdu_drop
1300  *		REO shall drop this MSDU and not forward it to any other ring.
1301  *
1302  * reo_destination_indication
1303  *		The id of the reo exit ring where the msdu frame shall push
1304  *		after (MPDU level) reordering has finished. Values are defined
1305  *		in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_.
1306  *
1307  * flow_idx
1308  *		Flow table index.
1309  *
1310  * fse_metadata
1311  *		FSE related meta data.
1312  *
1313  * cce_metadata
1314  *		CCE related meta data.
1315  *
1316  * sa_sw_peer_id
1317  *		sw_peer_id from the address search entry corresponding to the
1318  *		source address of the MSDU.
1319  */
1320 
1321 enum rx_mpdu_end_rxdma_dest_ring {
1322 	RX_MPDU_END_RXDMA_DEST_RING_RELEASE,
1323 	RX_MPDU_END_RXDMA_DEST_RING_FW,
1324 	RX_MPDU_END_RXDMA_DEST_RING_SW,
1325 	RX_MPDU_END_RXDMA_DEST_RING_REO,
1326 };
1327 
1328 #define RX_MPDU_END_INFO1_UNSUP_KTYPE_SHORT_FRAME	BIT(11)
1329 #define RX_MPDU_END_INFO1_RX_IN_TX_DECRYPT_BYT		BIT(12)
1330 #define RX_MPDU_END_INFO1_OVERFLOW_ERR			BIT(13)
1331 #define RX_MPDU_END_INFO1_MPDU_LEN_ERR			BIT(14)
1332 #define RX_MPDU_END_INFO1_TKIP_MIC_ERR			BIT(15)
1333 #define RX_MPDU_END_INFO1_DECRYPT_ERR			BIT(16)
1334 #define RX_MPDU_END_INFO1_UNENCRYPTED_FRAME_ERR		BIT(17)
1335 #define RX_MPDU_END_INFO1_PN_FIELDS_VALID		BIT(18)
1336 #define RX_MPDU_END_INFO1_FCS_ERR			BIT(19)
1337 #define RX_MPDU_END_INFO1_MSDU_LEN_ERR			BIT(20)
1338 #define RX_MPDU_END_INFO1_RXDMA0_DEST_RING		GENMASK(22, 21)
1339 #define RX_MPDU_END_INFO1_RXDMA1_DEST_RING		GENMASK(24, 23)
1340 #define RX_MPDU_END_INFO1_DECRYPT_STATUS_CODE		GENMASK(27, 25)
1341 #define RX_MPDU_END_INFO1_RX_BITMAP_NOT_UPD		BIT(28)
1342 
1343 struct rx_mpdu_end {
1344 	__le16 info0;
1345 	__le16 phy_ppdu_id;
1346 	__le32 info1;
1347 } __packed;
1348 
1349 /* rx_mpdu_end
1350  *
1351  * rxpcu_mpdu_filter_in_category
1352  *		Field indicates what the reason was that this mpdu frame
1353  *		was allowed to come into the receive path by rxpcu. Values
1354  *		are defined in enum %RX_DESC_RXPCU_FILTER_*.
1355  *
1356  * sw_frame_group_id
1357  *		SW processes frames based on certain classifications. Values
1358  *		are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*.
1359  *
1360  * phy_ppdu_id
1361  *		A ppdu counter value that PHY increments for every PPDU
1362  *		received. The counter value wraps around.
1363  *
1364  * unsup_ktype_short_frame
1365  *		This bit will be '1' when WEP or TKIP or WAPI key type is
1366  *		received for 11ah short frame. Crypto will bypass the received
1367  *		packet without decryption to RxOLE after setting this bit.
1368  *
1369  * rx_in_tx_decrypt_byp
1370  *		Indicates that RX packet is not decrypted as Crypto is
1371  *		busy with TX packet processing.
1372  *
1373  * overflow_err
1374  *		RXPCU Receive FIFO ran out of space to receive the full MPDU.
1375  *		Therefore this MPDU is terminated early and is thus corrupted.
1376  *
1377  *		This MPDU will not be ACKed.
1378  *
1379  *		RXPCU might still be able to correctly receive the following
1380  *		MPDUs in the PPDU if enough fifo space became available in time.
1381  *
1382  * mpdu_length_err
1383  *		Set by RXPCU if the expected MPDU length does not correspond
1384  *		with the actually received number of bytes in the MPDU.
1385  *
1386  * tkip_mic_err
1387  *		Set by Rx crypto when crypto detected a TKIP MIC error for
1388  *		this MPDU.
1389  *
1390  * decrypt_err
1391  *		Set by RX CRYPTO when CRYPTO detected a decrypt error for this
1392  *		MPDU or CRYPTO received an encrypted frame, but did not get a
1393  *		valid corresponding key id in the peer entry.
1394  *
1395  * unencrypted_frame_err
1396  *		Set by RX CRYPTO when CRYPTO detected an unencrypted frame while
1397  *		in the peer entry field 'All_frames_shall_be_encrypted' is set.
1398  *
1399  * pn_fields_contain_valid_info
1400  *		Set by RX CRYPTO to indicate that there is a valid PN field
1401  *		present in this MPDU.
1402  *
1403  * fcs_err
1404  *		Set by RXPCU when there is an FCS error detected for this MPDU.
1405  *
1406  * msdu_length_err
1407  *		Set by RXOLE when there is an msdu length error detected
1408  *		in at least 1 of the MSDUs embedded within the MPDU.
1409  *
1410  * rxdma0_destination_ring
1411  * rxdma1_destination_ring
1412  *		The ring to which RXDMA0/1 shall push the frame, assuming
1413  *		no MPDU level errors are detected. In case of MPDU level
1414  *		errors, RXDMA0/1 might change the RXDMA0/1 destination. Values
1415  *		are defined in %enum RX_MPDU_END_RXDMA_DEST_RING_*.
1416  *
1417  * decrypt_status_code
1418  *		Field provides insight into the decryption performed. Values
1419  *		are defined in enum %RX_DESC_DECRYPT_STATUS_CODE_*.
1420  *
1421  * rx_bitmap_not_updated
1422  *		Frame is received, but RXPCU could not update the receive bitmap
1423  *		due to (temporary) fifo constraints.
1424  */
1425 
1426 /* Padding bytes to avoid TLV's spanning across 128 byte boundary */
1427 #define HAL_RX_DESC_PADDING0_BYTES	4
1428 #define HAL_RX_DESC_PADDING1_BYTES	16
1429 
1430 #define HAL_RX_DESC_HDR_STATUS_LEN	120
1431 
1432 struct hal_rx_desc_ipq8074 {
1433 	__le32 msdu_end_tag;
1434 	struct rx_msdu_end_ipq8074 msdu_end;
1435 	__le32 rx_attn_tag;
1436 	struct rx_attention attention;
1437 	__le32 msdu_start_tag;
1438 	struct rx_msdu_start_ipq8074 msdu_start;
1439 	u8 rx_padding0[HAL_RX_DESC_PADDING0_BYTES];
1440 	__le32 mpdu_start_tag;
1441 	struct rx_mpdu_start_ipq8074 mpdu_start;
1442 	__le32 mpdu_end_tag;
1443 	struct rx_mpdu_end mpdu_end;
1444 	u8 rx_padding1[HAL_RX_DESC_PADDING1_BYTES];
1445 	__le32 hdr_status_tag;
1446 	__le32 phy_ppdu_id;
1447 	u8 hdr_status[HAL_RX_DESC_HDR_STATUS_LEN];
1448 	u8 msdu_payload[0];
1449 } __packed;
1450 
1451 struct hal_rx_desc_qcn9074 {
1452 	__le32 msdu_end_tag;
1453 	struct rx_msdu_end_qcn9074 msdu_end;
1454 	__le32 rx_attn_tag;
1455 	struct rx_attention attention;
1456 	__le32 msdu_start_tag;
1457 	struct rx_msdu_start_qcn9074 msdu_start;
1458 	u8 rx_padding0[HAL_RX_DESC_PADDING0_BYTES];
1459 	__le32 mpdu_start_tag;
1460 	struct rx_mpdu_start_qcn9074 mpdu_start;
1461 	__le32 mpdu_end_tag;
1462 	struct rx_mpdu_end mpdu_end;
1463 	u8 rx_padding1[HAL_RX_DESC_PADDING1_BYTES];
1464 	__le32 hdr_status_tag;
1465 	__le32 phy_ppdu_id;
1466 	u8 hdr_status[HAL_RX_DESC_HDR_STATUS_LEN];
1467 	u8 msdu_payload[0];
1468 } __packed;
1469 
1470 struct hal_rx_desc_wcn6855 {
1471 	__le32 msdu_end_tag;
1472 	struct rx_msdu_end_wcn6855 msdu_end;
1473 	__le32 rx_attn_tag;
1474 	struct rx_attention attention;
1475 	__le32 msdu_start_tag;
1476 	struct rx_msdu_start_wcn6855 msdu_start;
1477 	u8 rx_padding0[HAL_RX_DESC_PADDING0_BYTES];
1478 	__le32 mpdu_start_tag;
1479 	struct rx_mpdu_start_wcn6855 mpdu_start;
1480 	__le32 mpdu_end_tag;
1481 	struct rx_mpdu_end mpdu_end;
1482 	u8 rx_padding1[HAL_RX_DESC_PADDING1_BYTES];
1483 	__le32 hdr_status_tag;
1484 	__le32 phy_ppdu_id;
1485 	u8 hdr_status[HAL_RX_DESC_HDR_STATUS_LEN];
1486 	u8 msdu_payload[0];
1487 } __packed;
1488 
1489 struct hal_rx_desc {
1490 	union {
1491 		struct hal_rx_desc_ipq8074 ipq8074;
1492 		struct hal_rx_desc_qcn9074 qcn9074;
1493 		struct hal_rx_desc_wcn6855 wcn6855;
1494 	} u;
1495 } __packed;
1496 
1497 #define HAL_RX_RU_ALLOC_TYPE_MAX 6
1498 #define RU_26  1
1499 #define RU_52  2
1500 #define RU_106 4
1501 #define RU_242 9
1502 #define RU_484 18
1503 #define RU_996 37
1504 
1505 #endif /* ATH11K_RX_DESC_H */
1506