1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef ATH11K_QMI_H 7 #define ATH11K_QMI_H 8 9 #include <linux/mutex.h> 10 #include <linux/soc/qcom/qmi.h> 11 12 #define ATH11K_HOST_VERSION_STRING "WIN" 13 #define ATH11K_QMI_WLANFW_TIMEOUT_MS 5000 14 #define ATH11K_QMI_MAX_BDF_FILE_NAME_SIZE 64 15 #define ATH11K_QMI_BDF_ADDRESS 0x4B0C0000 16 #define ATH11K_QMI_BDF_MAX_SIZE (256 * 1024) 17 #define ATH11K_QMI_CALDATA_OFFSET (128 * 1024) 18 #define ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 128 19 #define ATH11K_QMI_WLFW_SERVICE_ID_V01 0x45 20 #define ATH11K_QMI_WLFW_SERVICE_VERS_V01 0x01 21 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01 0x02 22 #define ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 32 23 #define ATH11K_QMI_RESP_LEN_MAX 8192 24 #define ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01 32 25 #define ATH11K_QMI_CALDB_SIZE 0x480000 26 #define ATH11K_QMI_DEFAULT_CAL_FILE_NAME "caldata.bin" 27 28 #define QMI_WLFW_REQUEST_MEM_IND_V01 0x0035 29 #define QMI_WLFW_FW_MEM_READY_IND_V01 0x0037 30 #define QMI_WLFW_COLD_BOOT_CAL_DONE_IND_V01 0x0021 31 #define QMI_WLFW_FW_READY_IND_V01 0x0038 32 33 #define QMI_WLANFW_MAX_DATA_SIZE_V01 6144 34 #define ATH11K_FIRMWARE_MODE_OFF 4 35 #define ATH11K_QMI_TARGET_MEM_MODE_DEFAULT 0 36 37 struct ath11k_base; 38 39 enum ath11k_qmi_file_type { 40 ATH11K_QMI_FILE_TYPE_BDF_GOLDEN, 41 ATH11K_QMI_FILE_TYPE_CALDATA, 42 ATH11K_QMI_MAX_FILE_TYPE, 43 }; 44 45 enum ath11k_qmi_event_type { 46 ATH11K_QMI_EVENT_SERVER_ARRIVE, 47 ATH11K_QMI_EVENT_SERVER_EXIT, 48 ATH11K_QMI_EVENT_REQUEST_MEM, 49 ATH11K_QMI_EVENT_FW_MEM_READY, 50 ATH11K_QMI_EVENT_FW_READY, 51 ATH11K_QMI_EVENT_COLD_BOOT_CAL_START, 52 ATH11K_QMI_EVENT_COLD_BOOT_CAL_DONE, 53 ATH11K_QMI_EVENT_REGISTER_DRIVER, 54 ATH11K_QMI_EVENT_UNREGISTER_DRIVER, 55 ATH11K_QMI_EVENT_RECOVERY, 56 ATH11K_QMI_EVENT_FORCE_FW_ASSERT, 57 ATH11K_QMI_EVENT_POWER_UP, 58 ATH11K_QMI_EVENT_POWER_DOWN, 59 ATH11K_QMI_EVENT_MAX, 60 }; 61 62 struct ath11k_qmi_driver_event { 63 struct list_head list; 64 enum ath11k_qmi_event_type type; 65 void *data; 66 }; 67 68 struct ath11k_qmi_ce_cfg { 69 const struct ce_pipe_config *tgt_ce; 70 int tgt_ce_len; 71 const struct service_to_pipe *svc_to_ce_map; 72 int svc_to_ce_map_len; 73 const u8 *shadow_reg; 74 int shadow_reg_len; 75 u8 *shadow_reg_v2; 76 int shadow_reg_v2_len; 77 }; 78 79 struct ath11k_qmi_event_msg { 80 struct list_head list; 81 enum ath11k_qmi_event_type type; 82 }; 83 84 struct target_mem_chunk { 85 u32 size; 86 u32 type; 87 dma_addr_t paddr; 88 u32 vaddr; 89 }; 90 91 struct target_info { 92 u32 chip_id; 93 u32 chip_family; 94 u32 board_id; 95 u32 soc_id; 96 u32 fw_version; 97 char fw_build_timestamp[ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 98 char fw_build_id[ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 99 }; 100 101 struct ath11k_qmi { 102 struct ath11k_base *ab; 103 struct qmi_handle handle; 104 struct sockaddr_qrtr sq; 105 struct work_struct event_work; 106 struct workqueue_struct *event_wq; 107 struct list_head event_list; 108 spinlock_t event_lock; /* spinlock for qmi event list */ 109 struct ath11k_qmi_ce_cfg ce_cfg; 110 struct target_mem_chunk target_mem[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 111 u32 mem_seg_count; 112 u32 target_mem_mode; 113 u8 cal_done; 114 struct target_info target; 115 }; 116 117 #define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN 189 118 #define QMI_WLANFW_HOST_CAP_REQ_V01 0x0034 119 #define QMI_WLANFW_HOST_CAP_RESP_MSG_V01_MAX_LEN 7 120 #define QMI_WLFW_HOST_CAP_RESP_V01 0x0034 121 #define QMI_WLFW_MAX_NUM_GPIO_V01 32 122 #define QMI_IPQ8074_FW_MEM_MODE 0xFF 123 #define HOST_DDR_REGION_TYPE 0x1 124 #define BDF_MEM_REGION_TYPE 0x2 125 #define CALDB_MEM_REGION_TYPE 0x4 126 127 struct qmi_wlanfw_host_cap_req_msg_v01 { 128 u8 num_clients_valid; 129 u32 num_clients; 130 u8 wake_msi_valid; 131 u32 wake_msi; 132 u8 gpios_valid; 133 u32 gpios_len; 134 u32 gpios[QMI_WLFW_MAX_NUM_GPIO_V01]; 135 u8 nm_modem_valid; 136 u8 nm_modem; 137 u8 bdf_support_valid; 138 u8 bdf_support; 139 u8 bdf_cache_support_valid; 140 u8 bdf_cache_support; 141 u8 m3_support_valid; 142 u8 m3_support; 143 u8 m3_cache_support_valid; 144 u8 m3_cache_support; 145 u8 cal_filesys_support_valid; 146 u8 cal_filesys_support; 147 u8 cal_cache_support_valid; 148 u8 cal_cache_support; 149 u8 cal_done_valid; 150 u8 cal_done; 151 u8 mem_bucket_valid; 152 u32 mem_bucket; 153 u8 mem_cfg_mode_valid; 154 u8 mem_cfg_mode; 155 }; 156 157 struct qmi_wlanfw_host_cap_resp_msg_v01 { 158 struct qmi_response_type_v01 resp; 159 }; 160 161 #define QMI_WLANFW_IND_REGISTER_REQ_MSG_V01_MAX_LEN 54 162 #define QMI_WLANFW_IND_REGISTER_REQ_V01 0x0020 163 #define QMI_WLANFW_IND_REGISTER_RESP_MSG_V01_MAX_LEN 18 164 #define QMI_WLANFW_IND_REGISTER_RESP_V01 0x0020 165 #define QMI_WLANFW_CLIENT_ID 0x4b4e454c 166 167 struct qmi_wlanfw_ind_register_req_msg_v01 { 168 u8 fw_ready_enable_valid; 169 u8 fw_ready_enable; 170 u8 initiate_cal_download_enable_valid; 171 u8 initiate_cal_download_enable; 172 u8 initiate_cal_update_enable_valid; 173 u8 initiate_cal_update_enable; 174 u8 msa_ready_enable_valid; 175 u8 msa_ready_enable; 176 u8 pin_connect_result_enable_valid; 177 u8 pin_connect_result_enable; 178 u8 client_id_valid; 179 u32 client_id; 180 u8 request_mem_enable_valid; 181 u8 request_mem_enable; 182 u8 fw_mem_ready_enable_valid; 183 u8 fw_mem_ready_enable; 184 u8 fw_init_done_enable_valid; 185 u8 fw_init_done_enable; 186 u8 rejuvenate_enable_valid; 187 u32 rejuvenate_enable; 188 u8 xo_cal_enable_valid; 189 u8 xo_cal_enable; 190 u8 cal_done_enable_valid; 191 u8 cal_done_enable; 192 }; 193 194 struct qmi_wlanfw_ind_register_resp_msg_v01 { 195 struct qmi_response_type_v01 resp; 196 u8 fw_status_valid; 197 u64 fw_status; 198 }; 199 200 #define QMI_WLANFW_REQUEST_MEM_IND_MSG_V01_MAX_LEN 1124 201 #define QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN 548 202 #define QMI_WLANFW_RESPOND_MEM_RESP_MSG_V01_MAX_LEN 7 203 #define QMI_WLANFW_REQUEST_MEM_IND_V01 0x0035 204 #define QMI_WLANFW_RESPOND_MEM_REQ_V01 0x0036 205 #define QMI_WLANFW_RESPOND_MEM_RESP_V01 0x0036 206 #define QMI_WLANFW_MAX_NUM_MEM_CFG_V01 2 207 208 struct qmi_wlanfw_mem_cfg_s_v01 { 209 u64 offset; 210 u32 size; 211 u8 secure_flag; 212 }; 213 214 enum qmi_wlanfw_mem_type_enum_v01 { 215 WLANFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 216 QMI_WLANFW_MEM_TYPE_MSA_V01 = 0, 217 QMI_WLANFW_MEM_TYPE_DDR_V01 = 1, 218 QMI_WLANFW_MEM_BDF_V01 = 2, 219 QMI_WLANFW_MEM_M3_V01 = 3, 220 QMI_WLANFW_MEM_CAL_V01 = 4, 221 QMI_WLANFW_MEM_DPD_V01 = 5, 222 WLANFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 223 }; 224 225 struct qmi_wlanfw_mem_seg_s_v01 { 226 u32 size; 227 enum qmi_wlanfw_mem_type_enum_v01 type; 228 u32 mem_cfg_len; 229 struct qmi_wlanfw_mem_cfg_s_v01 mem_cfg[QMI_WLANFW_MAX_NUM_MEM_CFG_V01]; 230 }; 231 232 struct qmi_wlanfw_request_mem_ind_msg_v01 { 233 u32 mem_seg_len; 234 struct qmi_wlanfw_mem_seg_s_v01 mem_seg[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 235 }; 236 237 struct qmi_wlanfw_mem_seg_resp_s_v01 { 238 u64 addr; 239 u32 size; 240 enum qmi_wlanfw_mem_type_enum_v01 type; 241 u8 restore; 242 }; 243 244 struct qmi_wlanfw_respond_mem_req_msg_v01 { 245 u32 mem_seg_len; 246 struct qmi_wlanfw_mem_seg_resp_s_v01 mem_seg[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 247 }; 248 249 struct qmi_wlanfw_respond_mem_resp_msg_v01 { 250 struct qmi_response_type_v01 resp; 251 }; 252 253 struct qmi_wlanfw_fw_mem_ready_ind_msg_v01 { 254 char placeholder; 255 }; 256 257 #define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN 0 258 #define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN 207 259 #define QMI_WLANFW_CAP_REQ_V01 0x0024 260 #define QMI_WLANFW_CAP_RESP_V01 0x0024 261 262 enum qmi_wlanfw_pipedir_enum_v01 { 263 QMI_WLFW_PIPEDIR_NONE_V01 = 0, 264 QMI_WLFW_PIPEDIR_IN_V01 = 1, 265 QMI_WLFW_PIPEDIR_OUT_V01 = 2, 266 QMI_WLFW_PIPEDIR_INOUT_V01 = 3, 267 }; 268 269 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 { 270 __le32 pipe_num; 271 __le32 pipe_dir; 272 __le32 nentries; 273 __le32 nbytes_max; 274 __le32 flags; 275 }; 276 277 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 { 278 __le32 service_id; 279 __le32 pipe_dir; 280 __le32 pipe_num; 281 }; 282 283 struct qmi_wlanfw_shadow_reg_cfg_s_v01 { 284 u16 id; 285 u16 offset; 286 }; 287 288 struct qmi_wlanfw_shadow_reg_v2_cfg_s_v01 { 289 u32 addr; 290 }; 291 292 struct qmi_wlanfw_memory_region_info_s_v01 { 293 u64 region_addr; 294 u32 size; 295 u8 secure_flag; 296 }; 297 298 struct qmi_wlanfw_rf_chip_info_s_v01 { 299 u32 chip_id; 300 u32 chip_family; 301 }; 302 303 struct qmi_wlanfw_rf_board_info_s_v01 { 304 u32 board_id; 305 }; 306 307 struct qmi_wlanfw_soc_info_s_v01 { 308 u32 soc_id; 309 }; 310 311 struct qmi_wlanfw_fw_version_info_s_v01 { 312 u32 fw_version; 313 char fw_build_timestamp[ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 314 }; 315 316 enum qmi_wlanfw_cal_temp_id_enum_v01 { 317 QMI_WLANFW_CAL_TEMP_IDX_0_V01 = 0, 318 QMI_WLANFW_CAL_TEMP_IDX_1_V01 = 1, 319 QMI_WLANFW_CAL_TEMP_IDX_2_V01 = 2, 320 QMI_WLANFW_CAL_TEMP_IDX_3_V01 = 3, 321 QMI_WLANFW_CAL_TEMP_IDX_4_V01 = 4, 322 QMI_WLANFW_CAL_TEMP_ID_MAX_V01 = 0xFF, 323 }; 324 325 struct qmi_wlanfw_cap_resp_msg_v01 { 326 struct qmi_response_type_v01 resp; 327 u8 chip_info_valid; 328 struct qmi_wlanfw_rf_chip_info_s_v01 chip_info; 329 u8 board_info_valid; 330 struct qmi_wlanfw_rf_board_info_s_v01 board_info; 331 u8 soc_info_valid; 332 struct qmi_wlanfw_soc_info_s_v01 soc_info; 333 u8 fw_version_info_valid; 334 struct qmi_wlanfw_fw_version_info_s_v01 fw_version_info; 335 u8 fw_build_id_valid; 336 char fw_build_id[ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 337 u8 num_macs_valid; 338 u8 num_macs; 339 }; 340 341 struct qmi_wlanfw_cap_req_msg_v01 { 342 char placeholder; 343 }; 344 345 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN 6182 346 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_LEN 7 347 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_V01 0x0025 348 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_V01 0x0025 349 /* TODO: Need to check with MCL and FW team that data can be pointer and 350 * can be last element in structure 351 */ 352 struct qmi_wlanfw_bdf_download_req_msg_v01 { 353 u8 valid; 354 u8 file_id_valid; 355 enum qmi_wlanfw_cal_temp_id_enum_v01 file_id; 356 u8 total_size_valid; 357 u32 total_size; 358 u8 seg_id_valid; 359 u32 seg_id; 360 u8 data_valid; 361 u32 data_len; 362 u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01]; 363 u8 end_valid; 364 u8 end; 365 u8 bdf_type_valid; 366 u8 bdf_type; 367 368 }; 369 370 struct qmi_wlanfw_bdf_download_resp_msg_v01 { 371 struct qmi_response_type_v01 resp; 372 }; 373 374 #define QMI_WLANFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN 18 375 #define QMI_WLANFW_M3_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 376 #define QMI_WLANFW_M3_INFO_RESP_V01 0x003C 377 #define QMI_WLANFW_M3_INFO_REQ_V01 0x003C 378 379 struct qmi_wlanfw_m3_info_req_msg_v01 { 380 u64 addr; 381 u32 size; 382 }; 383 384 struct qmi_wlanfw_m3_info_resp_msg_v01 { 385 struct qmi_response_type_v01 resp; 386 }; 387 388 #define QMI_WLANFW_WLAN_MODE_REQ_MSG_V01_MAX_LEN 11 389 #define QMI_WLANFW_WLAN_MODE_RESP_MSG_V01_MAX_LEN 7 390 #define QMI_WLANFW_WLAN_CFG_REQ_MSG_V01_MAX_LEN 803 391 #define QMI_WLANFW_WLAN_CFG_RESP_MSG_V01_MAX_LEN 7 392 #define QMI_WLANFW_WLAN_MODE_REQ_V01 0x0022 393 #define QMI_WLANFW_WLAN_MODE_RESP_V01 0x0022 394 #define QMI_WLANFW_WLAN_CFG_REQ_V01 0x0023 395 #define QMI_WLANFW_WLAN_CFG_RESP_V01 0x0023 396 #define QMI_WLANFW_MAX_STR_LEN_V01 16 397 #define QMI_WLANFW_MAX_NUM_CE_V01 12 398 #define QMI_WLANFW_MAX_NUM_SVC_V01 24 399 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V01 24 400 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V2_V01 36 401 402 struct qmi_wlanfw_wlan_mode_req_msg_v01 { 403 u32 mode; 404 u8 hw_debug_valid; 405 u8 hw_debug; 406 }; 407 408 struct qmi_wlanfw_wlan_mode_resp_msg_v01 { 409 struct qmi_response_type_v01 resp; 410 }; 411 412 struct qmi_wlanfw_wlan_cfg_req_msg_v01 { 413 u8 host_version_valid; 414 char host_version[QMI_WLANFW_MAX_STR_LEN_V01 + 1]; 415 u8 tgt_cfg_valid; 416 u32 tgt_cfg_len; 417 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 418 tgt_cfg[QMI_WLANFW_MAX_NUM_CE_V01]; 419 u8 svc_cfg_valid; 420 u32 svc_cfg_len; 421 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 422 svc_cfg[QMI_WLANFW_MAX_NUM_SVC_V01]; 423 u8 shadow_reg_valid; 424 u32 shadow_reg_len; 425 struct qmi_wlanfw_shadow_reg_cfg_s_v01 426 shadow_reg[QMI_WLANFW_MAX_NUM_SHADOW_REG_V01]; 427 u8 shadow_reg_v2_valid; 428 u32 shadow_reg_v2_len; 429 struct qmi_wlanfw_shadow_reg_v2_cfg_s_v01 430 shadow_reg_v2[QMI_WLANFW_MAX_NUM_SHADOW_REG_V2_V01]; 431 }; 432 433 struct qmi_wlanfw_wlan_cfg_resp_msg_v01 { 434 struct qmi_response_type_v01 resp; 435 }; 436 437 int ath11k_qmi_firmware_start(struct ath11k_base *ab, 438 u32 mode); 439 void ath11k_qmi_firmware_stop(struct ath11k_base *ab); 440 void ath11k_qmi_event_work(struct work_struct *work); 441 void ath11k_qmi_msg_recv_work(struct work_struct *work); 442 void ath11k_qmi_deinit_service(struct ath11k_base *ab); 443 int ath11k_qmi_init_service(struct ath11k_base *ab); 444 445 #endif 446