1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef ATH11K_QMI_H 7 #define ATH11K_QMI_H 8 9 #include <linux/mutex.h> 10 #include <linux/soc/qcom/qmi.h> 11 12 #define ATH11K_HOST_VERSION_STRING "WIN" 13 #define ATH11K_QMI_WLANFW_TIMEOUT_MS 10000 14 #define ATH11K_QMI_MAX_BDF_FILE_NAME_SIZE 64 15 #define ATH11K_QMI_CALDB_ADDRESS 0x4BA00000 16 #define ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 128 17 #define ATH11K_QMI_WLFW_SERVICE_ID_V01 0x45 18 #define ATH11K_QMI_WLFW_SERVICE_VERS_V01 0x01 19 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01 0x02 20 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390 0x01 21 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ8074 0x02 22 #define ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9074 0x07 23 #define ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 32 24 #define ATH11K_QMI_RESP_LEN_MAX 8192 25 #define ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01 52 26 #define ATH11K_QMI_CALDB_SIZE 0x480000 27 #define ATH11K_QMI_BDF_EXT_STR_LENGTH 0x20 28 #define ATH11K_QMI_FW_MEM_REQ_SEGMENT_CNT 3 29 30 #define QMI_WLFW_REQUEST_MEM_IND_V01 0x0035 31 #define QMI_WLFW_FW_MEM_READY_IND_V01 0x0037 32 #define QMI_WLFW_COLD_BOOT_CAL_DONE_IND_V01 0x0021 33 #define QMI_WLFW_FW_READY_IND_V01 0x0038 34 35 #define QMI_WLANFW_MAX_DATA_SIZE_V01 6144 36 #define ATH11K_FIRMWARE_MODE_OFF 4 37 #define ATH11K_QMI_TARGET_MEM_MODE_DEFAULT 0 38 #define ATH11K_COLD_BOOT_FW_RESET_DELAY (40 * HZ) 39 40 struct ath11k_base; 41 42 enum ath11k_qmi_file_type { 43 ATH11K_QMI_FILE_TYPE_BDF_GOLDEN, 44 ATH11K_QMI_FILE_TYPE_CALDATA, 45 ATH11K_QMI_FILE_TYPE_EEPROM, 46 ATH11K_QMI_MAX_FILE_TYPE, 47 }; 48 49 enum ath11k_qmi_bdf_type { 50 ATH11K_QMI_BDF_TYPE_BIN = 0, 51 ATH11K_QMI_BDF_TYPE_ELF = 1, 52 }; 53 54 enum ath11k_qmi_event_type { 55 ATH11K_QMI_EVENT_SERVER_ARRIVE, 56 ATH11K_QMI_EVENT_SERVER_EXIT, 57 ATH11K_QMI_EVENT_REQUEST_MEM, 58 ATH11K_QMI_EVENT_FW_MEM_READY, 59 ATH11K_QMI_EVENT_FW_READY, 60 ATH11K_QMI_EVENT_COLD_BOOT_CAL_START, 61 ATH11K_QMI_EVENT_COLD_BOOT_CAL_DONE, 62 ATH11K_QMI_EVENT_REGISTER_DRIVER, 63 ATH11K_QMI_EVENT_UNREGISTER_DRIVER, 64 ATH11K_QMI_EVENT_RECOVERY, 65 ATH11K_QMI_EVENT_FORCE_FW_ASSERT, 66 ATH11K_QMI_EVENT_POWER_UP, 67 ATH11K_QMI_EVENT_POWER_DOWN, 68 ATH11K_QMI_EVENT_MAX, 69 }; 70 71 struct ath11k_qmi_driver_event { 72 struct list_head list; 73 enum ath11k_qmi_event_type type; 74 void *data; 75 }; 76 77 struct ath11k_qmi_ce_cfg { 78 const struct ce_pipe_config *tgt_ce; 79 int tgt_ce_len; 80 const struct service_to_pipe *svc_to_ce_map; 81 int svc_to_ce_map_len; 82 const u8 *shadow_reg; 83 int shadow_reg_len; 84 u32 *shadow_reg_v2; 85 int shadow_reg_v2_len; 86 }; 87 88 struct ath11k_qmi_event_msg { 89 struct list_head list; 90 enum ath11k_qmi_event_type type; 91 }; 92 93 struct target_mem_chunk { 94 u32 size; 95 u32 type; 96 dma_addr_t paddr; 97 u32 *vaddr; 98 }; 99 100 struct target_info { 101 u32 chip_id; 102 u32 chip_family; 103 u32 board_id; 104 u32 soc_id; 105 u32 fw_version; 106 u32 eeprom_caldata; 107 char fw_build_timestamp[ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 108 char fw_build_id[ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 109 char bdf_ext[ATH11K_QMI_BDF_EXT_STR_LENGTH]; 110 }; 111 112 struct m3_mem_region { 113 u32 size; 114 dma_addr_t paddr; 115 void *vaddr; 116 }; 117 118 struct ath11k_qmi { 119 struct ath11k_base *ab; 120 struct qmi_handle handle; 121 struct sockaddr_qrtr sq; 122 struct work_struct event_work; 123 struct workqueue_struct *event_wq; 124 struct list_head event_list; 125 spinlock_t event_lock; /* spinlock for qmi event list */ 126 struct ath11k_qmi_ce_cfg ce_cfg; 127 struct target_mem_chunk target_mem[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 128 u32 mem_seg_count; 129 u32 target_mem_mode; 130 bool target_mem_delayed; 131 u8 cal_done; 132 struct target_info target; 133 struct m3_mem_region m3_mem; 134 unsigned int service_ins_id; 135 wait_queue_head_t cold_boot_waitq; 136 }; 137 138 #define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN 261 139 #define QMI_WLANFW_HOST_CAP_REQ_V01 0x0034 140 #define QMI_WLANFW_HOST_CAP_RESP_MSG_V01_MAX_LEN 7 141 #define QMI_WLFW_HOST_CAP_RESP_V01 0x0034 142 #define QMI_WLFW_MAX_NUM_GPIO_V01 32 143 #define QMI_IPQ8074_FW_MEM_MODE 0xFF 144 #define HOST_DDR_REGION_TYPE 0x1 145 #define BDF_MEM_REGION_TYPE 0x2 146 #define M3_DUMP_REGION_TYPE 0x3 147 #define CALDB_MEM_REGION_TYPE 0x4 148 149 struct qmi_wlanfw_host_cap_req_msg_v01 { 150 u8 num_clients_valid; 151 u32 num_clients; 152 u8 wake_msi_valid; 153 u32 wake_msi; 154 u8 gpios_valid; 155 u32 gpios_len; 156 u32 gpios[QMI_WLFW_MAX_NUM_GPIO_V01]; 157 u8 nm_modem_valid; 158 u8 nm_modem; 159 u8 bdf_support_valid; 160 u8 bdf_support; 161 u8 bdf_cache_support_valid; 162 u8 bdf_cache_support; 163 u8 m3_support_valid; 164 u8 m3_support; 165 u8 m3_cache_support_valid; 166 u8 m3_cache_support; 167 u8 cal_filesys_support_valid; 168 u8 cal_filesys_support; 169 u8 cal_cache_support_valid; 170 u8 cal_cache_support; 171 u8 cal_done_valid; 172 u8 cal_done; 173 u8 mem_bucket_valid; 174 u32 mem_bucket; 175 u8 mem_cfg_mode_valid; 176 u8 mem_cfg_mode; 177 }; 178 179 struct qmi_wlanfw_host_cap_resp_msg_v01 { 180 struct qmi_response_type_v01 resp; 181 }; 182 183 #define QMI_WLANFW_IND_REGISTER_REQ_MSG_V01_MAX_LEN 54 184 #define QMI_WLANFW_IND_REGISTER_REQ_V01 0x0020 185 #define QMI_WLANFW_IND_REGISTER_RESP_MSG_V01_MAX_LEN 18 186 #define QMI_WLANFW_IND_REGISTER_RESP_V01 0x0020 187 #define QMI_WLANFW_CLIENT_ID 0x4b4e454c 188 189 struct qmi_wlanfw_ind_register_req_msg_v01 { 190 u8 fw_ready_enable_valid; 191 u8 fw_ready_enable; 192 u8 initiate_cal_download_enable_valid; 193 u8 initiate_cal_download_enable; 194 u8 initiate_cal_update_enable_valid; 195 u8 initiate_cal_update_enable; 196 u8 msa_ready_enable_valid; 197 u8 msa_ready_enable; 198 u8 pin_connect_result_enable_valid; 199 u8 pin_connect_result_enable; 200 u8 client_id_valid; 201 u32 client_id; 202 u8 request_mem_enable_valid; 203 u8 request_mem_enable; 204 u8 fw_mem_ready_enable_valid; 205 u8 fw_mem_ready_enable; 206 u8 fw_init_done_enable_valid; 207 u8 fw_init_done_enable; 208 u8 rejuvenate_enable_valid; 209 u32 rejuvenate_enable; 210 u8 xo_cal_enable_valid; 211 u8 xo_cal_enable; 212 u8 cal_done_enable_valid; 213 u8 cal_done_enable; 214 }; 215 216 struct qmi_wlanfw_ind_register_resp_msg_v01 { 217 struct qmi_response_type_v01 resp; 218 u8 fw_status_valid; 219 u64 fw_status; 220 }; 221 222 #define QMI_WLANFW_REQUEST_MEM_IND_MSG_V01_MAX_LEN 1824 223 #define QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN 888 224 #define QMI_WLANFW_RESPOND_MEM_RESP_MSG_V01_MAX_LEN 7 225 #define QMI_WLANFW_REQUEST_MEM_IND_V01 0x0035 226 #define QMI_WLANFW_RESPOND_MEM_REQ_V01 0x0036 227 #define QMI_WLANFW_RESPOND_MEM_RESP_V01 0x0036 228 #define QMI_WLANFW_MAX_NUM_MEM_CFG_V01 2 229 230 struct qmi_wlanfw_mem_cfg_s_v01 { 231 u64 offset; 232 u32 size; 233 u8 secure_flag; 234 }; 235 236 enum qmi_wlanfw_mem_type_enum_v01 { 237 WLANFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN, 238 QMI_WLANFW_MEM_TYPE_MSA_V01 = 0, 239 QMI_WLANFW_MEM_TYPE_DDR_V01 = 1, 240 QMI_WLANFW_MEM_BDF_V01 = 2, 241 QMI_WLANFW_MEM_M3_V01 = 3, 242 QMI_WLANFW_MEM_CAL_V01 = 4, 243 QMI_WLANFW_MEM_DPD_V01 = 5, 244 WLANFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX, 245 }; 246 247 struct qmi_wlanfw_mem_seg_s_v01 { 248 u32 size; 249 enum qmi_wlanfw_mem_type_enum_v01 type; 250 u32 mem_cfg_len; 251 struct qmi_wlanfw_mem_cfg_s_v01 mem_cfg[QMI_WLANFW_MAX_NUM_MEM_CFG_V01]; 252 }; 253 254 struct qmi_wlanfw_request_mem_ind_msg_v01 { 255 u32 mem_seg_len; 256 struct qmi_wlanfw_mem_seg_s_v01 mem_seg[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 257 }; 258 259 struct qmi_wlanfw_mem_seg_resp_s_v01 { 260 u64 addr; 261 u32 size; 262 enum qmi_wlanfw_mem_type_enum_v01 type; 263 u8 restore; 264 }; 265 266 struct qmi_wlanfw_respond_mem_req_msg_v01 { 267 u32 mem_seg_len; 268 struct qmi_wlanfw_mem_seg_resp_s_v01 mem_seg[ATH11K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01]; 269 }; 270 271 struct qmi_wlanfw_respond_mem_resp_msg_v01 { 272 struct qmi_response_type_v01 resp; 273 }; 274 275 struct qmi_wlanfw_fw_mem_ready_ind_msg_v01 { 276 char placeholder; 277 }; 278 279 struct qmi_wlanfw_fw_ready_ind_msg_v01 { 280 char placeholder; 281 }; 282 283 struct qmi_wlanfw_fw_cold_cal_done_ind_msg_v01 { 284 char placeholder; 285 }; 286 287 #define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN 0 288 #define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN 235 289 #define QMI_WLANFW_CAP_REQ_V01 0x0024 290 #define QMI_WLANFW_CAP_RESP_V01 0x0024 291 292 enum qmi_wlanfw_pipedir_enum_v01 { 293 QMI_WLFW_PIPEDIR_NONE_V01 = 0, 294 QMI_WLFW_PIPEDIR_IN_V01 = 1, 295 QMI_WLFW_PIPEDIR_OUT_V01 = 2, 296 QMI_WLFW_PIPEDIR_INOUT_V01 = 3, 297 }; 298 299 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 { 300 __le32 pipe_num; 301 __le32 pipe_dir; 302 __le32 nentries; 303 __le32 nbytes_max; 304 __le32 flags; 305 }; 306 307 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 { 308 __le32 service_id; 309 __le32 pipe_dir; 310 __le32 pipe_num; 311 }; 312 313 struct qmi_wlanfw_shadow_reg_cfg_s_v01 { 314 u16 id; 315 u16 offset; 316 }; 317 318 struct qmi_wlanfw_shadow_reg_v2_cfg_s_v01 { 319 u32 addr; 320 }; 321 322 struct qmi_wlanfw_memory_region_info_s_v01 { 323 u64 region_addr; 324 u32 size; 325 u8 secure_flag; 326 }; 327 328 struct qmi_wlanfw_rf_chip_info_s_v01 { 329 u32 chip_id; 330 u32 chip_family; 331 }; 332 333 struct qmi_wlanfw_rf_board_info_s_v01 { 334 u32 board_id; 335 }; 336 337 struct qmi_wlanfw_soc_info_s_v01 { 338 u32 soc_id; 339 }; 340 341 struct qmi_wlanfw_fw_version_info_s_v01 { 342 u32 fw_version; 343 char fw_build_timestamp[ATH11K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1]; 344 }; 345 346 enum qmi_wlanfw_cal_temp_id_enum_v01 { 347 QMI_WLANFW_CAL_TEMP_IDX_0_V01 = 0, 348 QMI_WLANFW_CAL_TEMP_IDX_1_V01 = 1, 349 QMI_WLANFW_CAL_TEMP_IDX_2_V01 = 2, 350 QMI_WLANFW_CAL_TEMP_IDX_3_V01 = 3, 351 QMI_WLANFW_CAL_TEMP_IDX_4_V01 = 4, 352 QMI_WLANFW_CAL_TEMP_ID_MAX_V01 = 0xFF, 353 }; 354 355 struct qmi_wlanfw_cap_resp_msg_v01 { 356 struct qmi_response_type_v01 resp; 357 u8 chip_info_valid; 358 struct qmi_wlanfw_rf_chip_info_s_v01 chip_info; 359 u8 board_info_valid; 360 struct qmi_wlanfw_rf_board_info_s_v01 board_info; 361 u8 soc_info_valid; 362 struct qmi_wlanfw_soc_info_s_v01 soc_info; 363 u8 fw_version_info_valid; 364 struct qmi_wlanfw_fw_version_info_s_v01 fw_version_info; 365 u8 fw_build_id_valid; 366 char fw_build_id[ATH11K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1]; 367 u8 num_macs_valid; 368 u8 num_macs; 369 u8 voltage_mv_valid; 370 u32 voltage_mv; 371 u8 time_freq_hz_valid; 372 u32 time_freq_hz; 373 u8 otp_version_valid; 374 u32 otp_version; 375 u8 eeprom_read_timeout_valid; 376 u32 eeprom_read_timeout; 377 }; 378 379 struct qmi_wlanfw_cap_req_msg_v01 { 380 char placeholder; 381 }; 382 383 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN 6182 384 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_LEN 7 385 #define QMI_WLANFW_BDF_DOWNLOAD_RESP_V01 0x0025 386 #define QMI_WLANFW_BDF_DOWNLOAD_REQ_V01 0x0025 387 /* TODO: Need to check with MCL and FW team that data can be pointer and 388 * can be last element in structure 389 */ 390 struct qmi_wlanfw_bdf_download_req_msg_v01 { 391 u8 valid; 392 u8 file_id_valid; 393 enum qmi_wlanfw_cal_temp_id_enum_v01 file_id; 394 u8 total_size_valid; 395 u32 total_size; 396 u8 seg_id_valid; 397 u32 seg_id; 398 u8 data_valid; 399 u32 data_len; 400 u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01]; 401 u8 end_valid; 402 u8 end; 403 u8 bdf_type_valid; 404 u8 bdf_type; 405 406 }; 407 408 struct qmi_wlanfw_bdf_download_resp_msg_v01 { 409 struct qmi_response_type_v01 resp; 410 }; 411 412 #define QMI_WLANFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN 18 413 #define QMI_WLANFW_M3_INFO_RESP_MSG_V01_MAX_MSG_LEN 7 414 #define QMI_WLANFW_M3_INFO_RESP_V01 0x003C 415 #define QMI_WLANFW_M3_INFO_REQ_V01 0x003C 416 417 struct qmi_wlanfw_m3_info_req_msg_v01 { 418 u64 addr; 419 u32 size; 420 }; 421 422 struct qmi_wlanfw_m3_info_resp_msg_v01 { 423 struct qmi_response_type_v01 resp; 424 }; 425 426 #define QMI_WLANFW_WLAN_MODE_REQ_MSG_V01_MAX_LEN 11 427 #define QMI_WLANFW_WLAN_MODE_RESP_MSG_V01_MAX_LEN 7 428 #define QMI_WLANFW_WLAN_CFG_REQ_MSG_V01_MAX_LEN 803 429 #define QMI_WLANFW_WLAN_CFG_RESP_MSG_V01_MAX_LEN 7 430 #define QMI_WLANFW_WLAN_MODE_REQ_V01 0x0022 431 #define QMI_WLANFW_WLAN_MODE_RESP_V01 0x0022 432 #define QMI_WLANFW_WLAN_CFG_REQ_V01 0x0023 433 #define QMI_WLANFW_WLAN_CFG_RESP_V01 0x0023 434 #define QMI_WLANFW_MAX_STR_LEN_V01 16 435 #define QMI_WLANFW_MAX_NUM_CE_V01 12 436 #define QMI_WLANFW_MAX_NUM_SVC_V01 24 437 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V01 24 438 #define QMI_WLANFW_MAX_NUM_SHADOW_REG_V2_V01 36 439 440 struct qmi_wlanfw_wlan_mode_req_msg_v01 { 441 u32 mode; 442 u8 hw_debug_valid; 443 u8 hw_debug; 444 }; 445 446 struct qmi_wlanfw_wlan_mode_resp_msg_v01 { 447 struct qmi_response_type_v01 resp; 448 }; 449 450 struct qmi_wlanfw_wlan_cfg_req_msg_v01 { 451 u8 host_version_valid; 452 char host_version[QMI_WLANFW_MAX_STR_LEN_V01 + 1]; 453 u8 tgt_cfg_valid; 454 u32 tgt_cfg_len; 455 struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 456 tgt_cfg[QMI_WLANFW_MAX_NUM_CE_V01]; 457 u8 svc_cfg_valid; 458 u32 svc_cfg_len; 459 struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 460 svc_cfg[QMI_WLANFW_MAX_NUM_SVC_V01]; 461 u8 shadow_reg_valid; 462 u32 shadow_reg_len; 463 struct qmi_wlanfw_shadow_reg_cfg_s_v01 464 shadow_reg[QMI_WLANFW_MAX_NUM_SHADOW_REG_V01]; 465 u8 shadow_reg_v2_valid; 466 u32 shadow_reg_v2_len; 467 struct qmi_wlanfw_shadow_reg_v2_cfg_s_v01 468 shadow_reg_v2[QMI_WLANFW_MAX_NUM_SHADOW_REG_V2_V01]; 469 }; 470 471 struct qmi_wlanfw_wlan_cfg_resp_msg_v01 { 472 struct qmi_response_type_v01 resp; 473 }; 474 475 int ath11k_qmi_firmware_start(struct ath11k_base *ab, 476 u32 mode); 477 void ath11k_qmi_firmware_stop(struct ath11k_base *ab); 478 void ath11k_qmi_event_work(struct work_struct *work); 479 void ath11k_qmi_msg_recv_work(struct work_struct *work); 480 void ath11k_qmi_deinit_service(struct ath11k_base *ab); 481 int ath11k_qmi_init_service(struct ath11k_base *ab); 482 483 #endif 484