1*bbfdc5a7SManikanta Pubbisetty /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2*bbfdc5a7SManikanta Pubbisetty /* 3*bbfdc5a7SManikanta Pubbisetty * Copyright (c) 2019-2021 The Linux Foundation. All rights reserved. 4*bbfdc5a7SManikanta Pubbisetty * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. 5*bbfdc5a7SManikanta Pubbisetty */ 6*bbfdc5a7SManikanta Pubbisetty 7*bbfdc5a7SManikanta Pubbisetty #ifndef _ATH11K_PCI_CMN_H 8*bbfdc5a7SManikanta Pubbisetty #define _ATH11K_PCI_CMN_H 9*bbfdc5a7SManikanta Pubbisetty 10*bbfdc5a7SManikanta Pubbisetty #include "core.h" 11*bbfdc5a7SManikanta Pubbisetty #include "pci.h" 12*bbfdc5a7SManikanta Pubbisetty 13*bbfdc5a7SManikanta Pubbisetty #define ATH11K_PCI_IRQ_CE0_OFFSET 3 14*bbfdc5a7SManikanta Pubbisetty #define ATH11K_PCI_IRQ_DP_OFFSET 14 15*bbfdc5a7SManikanta Pubbisetty 16*bbfdc5a7SManikanta Pubbisetty #define ATH11K_PCI_WINDOW_ENABLE_BIT 0x40000000 17*bbfdc5a7SManikanta Pubbisetty #define ATH11K_PCI_WINDOW_REG_ADDRESS 0x310c 18*bbfdc5a7SManikanta Pubbisetty #define ATH11K_PCI_WINDOW_VALUE_MASK GENMASK(24, 19) 19*bbfdc5a7SManikanta Pubbisetty #define ATH11K_PCI_WINDOW_START 0x80000 20*bbfdc5a7SManikanta Pubbisetty #define ATH11K_PCI_WINDOW_RANGE_MASK GENMASK(18, 0) 21*bbfdc5a7SManikanta Pubbisetty 22*bbfdc5a7SManikanta Pubbisetty /* BAR0 + 4k is always accessible, and no 23*bbfdc5a7SManikanta Pubbisetty * need to force wakeup. 24*bbfdc5a7SManikanta Pubbisetty * 4K - 32 = 0xFE0 25*bbfdc5a7SManikanta Pubbisetty */ 26*bbfdc5a7SManikanta Pubbisetty #define ATH11K_PCI_ACCESS_ALWAYS_OFF 0xFE0 27*bbfdc5a7SManikanta Pubbisetty 28*bbfdc5a7SManikanta Pubbisetty int ath11k_pcic_get_user_msi_assignment(struct ath11k_pci *ar_pci, char *user_name, 29*bbfdc5a7SManikanta Pubbisetty int *num_vectors, u32 *user_base_data, 30*bbfdc5a7SManikanta Pubbisetty u32 *base_vector); 31*bbfdc5a7SManikanta Pubbisetty int ath11k_pcic_get_msi_irq(struct device *dev, unsigned int vector); 32*bbfdc5a7SManikanta Pubbisetty void ath11k_pcic_write32(struct ath11k_base *ab, u32 offset, u32 value); 33*bbfdc5a7SManikanta Pubbisetty u32 ath11k_pcic_read32(struct ath11k_base *ab, u32 offset); 34*bbfdc5a7SManikanta Pubbisetty void ath11k_pcic_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo, 35*bbfdc5a7SManikanta Pubbisetty u32 *msi_addr_hi); 36*bbfdc5a7SManikanta Pubbisetty void ath11k_pcic_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id, u32 *msi_idx); 37*bbfdc5a7SManikanta Pubbisetty void ath11k_pcic_free_irq(struct ath11k_base *ab); 38*bbfdc5a7SManikanta Pubbisetty int ath11k_pcic_config_irq(struct ath11k_base *ab); 39*bbfdc5a7SManikanta Pubbisetty void ath11k_pcic_ext_irq_enable(struct ath11k_base *ab); 40*bbfdc5a7SManikanta Pubbisetty void ath11k_pcic_ext_irq_disable(struct ath11k_base *ab); 41*bbfdc5a7SManikanta Pubbisetty void ath11k_pcic_stop(struct ath11k_base *ab); 42*bbfdc5a7SManikanta Pubbisetty int ath11k_pcic_start(struct ath11k_base *ab); 43*bbfdc5a7SManikanta Pubbisetty int ath11k_pcic_map_service_to_pipe(struct ath11k_base *ab, u16 service_id, 44*bbfdc5a7SManikanta Pubbisetty u8 *ul_pipe, u8 *dl_pipe); 45*bbfdc5a7SManikanta Pubbisetty void ath11k_pcic_ce_irqs_enable(struct ath11k_base *ab); 46*bbfdc5a7SManikanta Pubbisetty void ath11k_pcic_ce_irq_disable_sync(struct ath11k_base *ab); 47*bbfdc5a7SManikanta Pubbisetty int ath11k_get_user_msi_assignment(struct ath11k_base *ab, char *user_name, 48*bbfdc5a7SManikanta Pubbisetty int *num_vectors, u32 *user_base_data, 49*bbfdc5a7SManikanta Pubbisetty u32 *base_vector); 50*bbfdc5a7SManikanta Pubbisetty void ath11k_pcic_aspm_restore(struct ath11k_pci *ab_pci); 51*bbfdc5a7SManikanta Pubbisetty int ath11k_pcic_set_irq_affinity_hint(struct ath11k_pci *ab_pci, 52*bbfdc5a7SManikanta Pubbisetty const struct cpumask *m); 53*bbfdc5a7SManikanta Pubbisetty #endif 54