1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved. 4 */ 5 #ifndef _ATH11K_PCI_H 6 #define _ATH11K_PCI_H 7 8 #include <linux/mhi.h> 9 10 #include "core.h" 11 12 #define PCIE_SOC_GLOBAL_RESET 0x3008 13 #define PCIE_SOC_GLOBAL_RESET_V 1 14 15 #define WLAON_WARM_SW_ENTRY 0x1f80504 16 #define WLAON_SOC_RESET_CAUSE_REG 0x01f8060c 17 18 #define PCIE_Q6_COOKIE_ADDR 0x01f80500 19 #define PCIE_Q6_COOKIE_DATA 0xc0000000 20 21 /* register to wake the UMAC from power collapse */ 22 #define PCIE_SCRATCH_0_SOC_PCIE_REG 0x4040 23 24 /* register used for handshake mechanism to validate UMAC is awake */ 25 #define PCIE_SOC_WAKE_PCIE_LOCAL_REG 0x3004 26 27 #define PCIE_PCIE_PARF_LTSSM 0x1e081b0 28 #define PARM_LTSSM_VALUE 0x111 29 30 #define GCC_GCC_PCIE_HOT_RST 0x1e402bc 31 #define GCC_GCC_PCIE_HOT_RST_VAL 0x10 32 33 #define PCIE_PCIE_INT_ALL_CLEAR 0x1e08228 34 #define PCIE_SMLH_REQ_RST_LINK_DOWN 0x2 35 #define PCIE_INT_CLEAR_ALL 0xffffffff 36 37 #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG 0x01e0c0ac 38 #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL 0x10 39 #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK 0xffffffff 40 #define PCIE_USB3_PCS_MISC_OSC_DTCT_CONFIG1_REG 0x01e0c628 41 #define PCIE_USB3_PCS_MISC_OSC_DTCT_CONFIG1_VAL 0x02 42 #define PCIE_USB3_PCS_MISC_OSC_DTCT_CONFIG2_REG 0x01e0c62c 43 #define PCIE_USB3_PCS_MISC_OSC_DTCT_CONFIG2_VAL 0x52 44 #define PCIE_USB3_PCS_MISC_OSC_DTCT_CONFIG4_REG 0x01e0c634 45 #define PCIE_USB3_PCS_MISC_OSC_DTCT_CONFIG4_VAL 0xff 46 #define PCIE_USB3_PCS_MISC_OSC_DTCT_CONFIG_MSK 0x000000ff 47 48 #define WLAON_QFPROM_PWR_CTRL_REG 0x01f8031c 49 #define QFPROM_PWR_CTRL_VDD4BLOW_MASK 0x4 50 51 struct ath11k_msi_user { 52 char *name; 53 int num_vectors; 54 u32 base_vector; 55 }; 56 57 struct ath11k_msi_config { 58 int total_vectors; 59 int total_users; 60 struct ath11k_msi_user *users; 61 }; 62 63 enum ath11k_pci_flags { 64 ATH11K_PCI_FLAG_INIT_DONE, 65 ATH11K_PCI_FLAG_IS_MSI_64, 66 ATH11K_PCI_ASPM_RESTORE, 67 }; 68 69 struct ath11k_pci { 70 struct pci_dev *pdev; 71 struct ath11k_base *ab; 72 u16 dev_id; 73 char amss_path[100]; 74 u32 msi_ep_base_data; 75 struct mhi_controller *mhi_ctrl; 76 unsigned long mhi_state; 77 u32 register_window; 78 79 /* protects register_window above */ 80 spinlock_t window_lock; 81 82 /* enum ath11k_pci_flags */ 83 unsigned long flags; 84 u16 link_ctl; 85 }; 86 87 static inline struct ath11k_pci *ath11k_pci_priv(struct ath11k_base *ab) 88 { 89 return (struct ath11k_pci *)ab->drv_priv; 90 } 91 92 int ath11k_pci_get_user_msi_assignment(struct ath11k_pci *ar_pci, char *user_name, 93 int *num_vectors, u32 *user_base_data, 94 u32 *base_vector); 95 int ath11k_pci_get_msi_irq(struct device *dev, unsigned int vector); 96 void ath11k_pci_write32(struct ath11k_base *ab, u32 offset, u32 value); 97 u32 ath11k_pci_read32(struct ath11k_base *ab, u32 offset); 98 99 #endif 100