1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved. 4 */ 5 #ifndef _ATH11K_PCI_H 6 #define _ATH11K_PCI_H 7 8 #include <linux/mhi.h> 9 10 #include "core.h" 11 12 #define PCIE_SOC_GLOBAL_RESET 0x3008 13 #define PCIE_SOC_GLOBAL_RESET_V 1 14 15 #define WLAON_WARM_SW_ENTRY 0x1f80504 16 #define WLAON_SOC_RESET_CAUSE_REG 0x01f8060c 17 18 #define PCIE_Q6_COOKIE_ADDR 0x01f80500 19 #define PCIE_Q6_COOKIE_DATA 0xc0000000 20 21 /* register to wake the UMAC from power collapse */ 22 #define PCIE_SCRATCH_0_SOC_PCIE_REG 0x4040 23 24 /* register used for handshake mechanism to validate UMAC is awake */ 25 #define PCIE_SOC_WAKE_PCIE_LOCAL_REG 0x3004 26 27 #define PCIE_PCIE_PARF_LTSSM 0x1e081b0 28 #define PARM_LTSSM_VALUE 0x111 29 30 #define GCC_GCC_PCIE_HOT_RST 0x1e402bc 31 #define GCC_GCC_PCIE_HOT_RST_VAL 0x10 32 33 #define PCIE_PCIE_INT_ALL_CLEAR 0x1e08228 34 #define PCIE_SMLH_REQ_RST_LINK_DOWN 0x2 35 #define PCIE_INT_CLEAR_ALL 0xffffffff 36 37 #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(x) \ 38 (ab->hw_params.regs->pcie_qserdes_sysclk_en_sel) 39 #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL 0x10 40 #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK 0xffffffff 41 #define PCIE_PCS_OSC_DTCT_CONFIG1_REG(x) \ 42 (ab->hw_params.regs->pcie_pcs_osc_dtct_config_base) 43 #define PCIE_PCS_OSC_DTCT_CONFIG1_VAL 0x02 44 #define PCIE_PCS_OSC_DTCT_CONFIG2_REG(x) \ 45 (ab->hw_params.regs->pcie_pcs_osc_dtct_config_base + 0x4) 46 #define PCIE_PCS_OSC_DTCT_CONFIG2_VAL 0x52 47 #define PCIE_PCS_OSC_DTCT_CONFIG4_REG(x) \ 48 (ab->hw_params.regs->pcie_pcs_osc_dtct_config_base + 0xc) 49 #define PCIE_PCS_OSC_DTCT_CONFIG4_VAL 0xff 50 #define PCIE_PCS_OSC_DTCT_CONFIG_MSK 0x000000ff 51 52 #define WLAON_QFPROM_PWR_CTRL_REG 0x01f8031c 53 #define QFPROM_PWR_CTRL_VDD4BLOW_MASK 0x4 54 55 struct ath11k_msi_user { 56 char *name; 57 int num_vectors; 58 u32 base_vector; 59 }; 60 61 struct ath11k_msi_config { 62 int total_vectors; 63 int total_users; 64 struct ath11k_msi_user *users; 65 }; 66 67 enum ath11k_pci_flags { 68 ATH11K_PCI_FLAG_INIT_DONE, 69 ATH11K_PCI_FLAG_IS_MSI_64, 70 ATH11K_PCI_ASPM_RESTORE, 71 ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, 72 }; 73 74 struct ath11k_pci { 75 struct pci_dev *pdev; 76 struct ath11k_base *ab; 77 u16 dev_id; 78 char amss_path[100]; 79 u32 msi_ep_base_data; 80 struct mhi_controller *mhi_ctrl; 81 const struct ath11k_msi_config *msi_config; 82 unsigned long mhi_state; 83 u32 register_window; 84 85 /* protects register_window above */ 86 spinlock_t window_lock; 87 88 /* enum ath11k_pci_flags */ 89 unsigned long flags; 90 u16 link_ctl; 91 92 unsigned long irq_flags; 93 }; 94 95 static inline struct ath11k_pci *ath11k_pci_priv(struct ath11k_base *ab) 96 { 97 return (struct ath11k_pci *)ab->drv_priv; 98 } 99 100 int ath11k_pci_get_user_msi_assignment(struct ath11k_pci *ar_pci, char *user_name, 101 int *num_vectors, u32 *user_base_data, 102 u32 *base_vector); 103 int ath11k_pci_get_msi_irq(struct device *dev, unsigned int vector); 104 void ath11k_pci_write32(struct ath11k_base *ab, u32 offset, u32 value); 105 u32 ath11k_pci_read32(struct ath11k_base *ab, u32 offset); 106 107 #endif 108