15762613eSGovind Singh /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 25762613eSGovind Singh /* 35762613eSGovind Singh * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved. 45762613eSGovind Singh */ 51399fb87SGovind Singh #ifndef _ATH11K_PCI_H 61399fb87SGovind Singh #define _ATH11K_PCI_H 71399fb87SGovind Singh 81399fb87SGovind Singh #include <linux/mhi.h> 95762613eSGovind Singh 105762613eSGovind Singh #include "core.h" 115762613eSGovind Singh 12f3c603d4SCarl Huang #define PCIE_SOC_GLOBAL_RESET 0x3008 13f3c603d4SCarl Huang #define PCIE_SOC_GLOBAL_RESET_V 1 14f3c603d4SCarl Huang 15f3c603d4SCarl Huang #define WLAON_WARM_SW_ENTRY 0x1f80504 16f3c603d4SCarl Huang #define WLAON_SOC_RESET_CAUSE_REG 0x01f8060c 17f3c603d4SCarl Huang 18f3c603d4SCarl Huang #define PCIE_Q6_COOKIE_ADDR 0x01f80500 19f3c603d4SCarl Huang #define PCIE_Q6_COOKIE_DATA 0xc0000000 20f3c603d4SCarl Huang 21f3c603d4SCarl Huang /* register to wake the UMAC from power collapse */ 22f3c603d4SCarl Huang #define PCIE_SCRATCH_0_SOC_PCIE_REG 0x4040 23f3c603d4SCarl Huang 24f3c603d4SCarl Huang /* register used for handshake mechanism to validate UMAC is awake */ 25f3c603d4SCarl Huang #define PCIE_SOC_WAKE_PCIE_LOCAL_REG 0x3004 26f3c603d4SCarl Huang 27babb0cedSCarl Huang #define PCIE_PCIE_PARF_LTSSM 0x1e081b0 28babb0cedSCarl Huang #define PARM_LTSSM_VALUE 0x111 29babb0cedSCarl Huang 30babb0cedSCarl Huang #define GCC_GCC_PCIE_HOT_RST 0x1e402bc 31babb0cedSCarl Huang #define GCC_GCC_PCIE_HOT_RST_VAL 0x10 32babb0cedSCarl Huang 33babb0cedSCarl Huang #define PCIE_PCIE_INT_ALL_CLEAR 0x1e08228 34babb0cedSCarl Huang #define PCIE_SMLH_REQ_RST_LINK_DOWN 0x2 35babb0cedSCarl Huang #define PCIE_INT_CLEAR_ALL 0xffffffff 36babb0cedSCarl Huang 37*6fe6f68fSKarthikeyan Periyasamy #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(x) \ 38*6fe6f68fSKarthikeyan Periyasamy (ab->hw_params.regs->pcie_qserdes_sysclk_en_sel) 3906999407SCarl Huang #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL 0x10 4006999407SCarl Huang #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK 0xffffffff 41*6fe6f68fSKarthikeyan Periyasamy #define PCIE_PCS_OSC_DTCT_CONFIG1_REG(x) \ 42*6fe6f68fSKarthikeyan Periyasamy (ab->hw_params.regs->pcie_pcs_osc_dtct_config_base) 43*6fe6f68fSKarthikeyan Periyasamy #define PCIE_PCS_OSC_DTCT_CONFIG1_VAL 0x02 44*6fe6f68fSKarthikeyan Periyasamy #define PCIE_PCS_OSC_DTCT_CONFIG2_REG(x) \ 45*6fe6f68fSKarthikeyan Periyasamy (ab->hw_params.regs->pcie_pcs_osc_dtct_config_base + 0x4) 46*6fe6f68fSKarthikeyan Periyasamy #define PCIE_PCS_OSC_DTCT_CONFIG2_VAL 0x52 47*6fe6f68fSKarthikeyan Periyasamy #define PCIE_PCS_OSC_DTCT_CONFIG4_REG(x) \ 48*6fe6f68fSKarthikeyan Periyasamy (ab->hw_params.regs->pcie_pcs_osc_dtct_config_base + 0xc) 49*6fe6f68fSKarthikeyan Periyasamy #define PCIE_PCS_OSC_DTCT_CONFIG4_VAL 0xff 50*6fe6f68fSKarthikeyan Periyasamy #define PCIE_PCS_OSC_DTCT_CONFIG_MSK 0x000000ff 5106999407SCarl Huang 520ccdf439SCarl Huang #define WLAON_QFPROM_PWR_CTRL_REG 0x01f8031c 530ccdf439SCarl Huang #define QFPROM_PWR_CTRL_VDD4BLOW_MASK 0x4 540ccdf439SCarl Huang 555697a564SGovind Singh struct ath11k_msi_user { 565697a564SGovind Singh char *name; 575697a564SGovind Singh int num_vectors; 585697a564SGovind Singh u32 base_vector; 595697a564SGovind Singh }; 605697a564SGovind Singh 615697a564SGovind Singh struct ath11k_msi_config { 625697a564SGovind Singh int total_vectors; 635697a564SGovind Singh int total_users; 645697a564SGovind Singh struct ath11k_msi_user *users; 655697a564SGovind Singh }; 665697a564SGovind Singh 67a05bd851SCarl Huang enum ath11k_pci_flags { 68a05bd851SCarl Huang ATH11K_PCI_FLAG_INIT_DONE, 69e8e55d89SAnilkumar Kolli ATH11K_PCI_FLAG_IS_MSI_64, 70e9603f4bSCarl Huang ATH11K_PCI_ASPM_RESTORE, 71a05bd851SCarl Huang }; 72a05bd851SCarl Huang 735762613eSGovind Singh struct ath11k_pci { 745762613eSGovind Singh struct pci_dev *pdev; 755762613eSGovind Singh struct ath11k_base *ab; 765762613eSGovind Singh u16 dev_id; 771399fb87SGovind Singh char amss_path[100]; 785697a564SGovind Singh u32 msi_ep_base_data; 791399fb87SGovind Singh struct mhi_controller *mhi_ctrl; 807a3aed0cSAnilkumar Kolli const struct ath11k_msi_config *msi_config; 811399fb87SGovind Singh unsigned long mhi_state; 82654e959aSGovind Singh u32 register_window; 83654e959aSGovind Singh 84654e959aSGovind Singh /* protects register_window above */ 85654e959aSGovind Singh spinlock_t window_lock; 86a05bd851SCarl Huang 87a05bd851SCarl Huang /* enum ath11k_pci_flags */ 88a05bd851SCarl Huang unsigned long flags; 89e9603f4bSCarl Huang u16 link_ctl; 905762613eSGovind Singh }; 915762613eSGovind Singh 925762613eSGovind Singh static inline struct ath11k_pci *ath11k_pci_priv(struct ath11k_base *ab) 935762613eSGovind Singh { 945762613eSGovind Singh return (struct ath11k_pci *)ab->drv_priv; 955762613eSGovind Singh } 961399fb87SGovind Singh 971399fb87SGovind Singh int ath11k_pci_get_user_msi_assignment(struct ath11k_pci *ar_pci, char *user_name, 981399fb87SGovind Singh int *num_vectors, u32 *user_base_data, 991399fb87SGovind Singh u32 *base_vector); 1001399fb87SGovind Singh int ath11k_pci_get_msi_irq(struct device *dev, unsigned int vector); 101f3c603d4SCarl Huang void ath11k_pci_write32(struct ath11k_base *ab, u32 offset, u32 value); 102f3c603d4SCarl Huang u32 ath11k_pci_read32(struct ath11k_base *ab, u32 offset); 1031399fb87SGovind Singh 1041399fb87SGovind Singh #endif 105