15762613eSGovind Singh /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 25762613eSGovind Singh /* 35762613eSGovind Singh * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved. 4948171b5SManikanta Pubbisetty * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. 55762613eSGovind Singh */ 61399fb87SGovind Singh #ifndef _ATH11K_PCI_H 71399fb87SGovind Singh #define _ATH11K_PCI_H 81399fb87SGovind Singh 91399fb87SGovind Singh #include <linux/mhi.h> 105762613eSGovind Singh 115762613eSGovind Singh #include "core.h" 125762613eSGovind Singh 13f3c603d4SCarl Huang #define PCIE_SOC_GLOBAL_RESET 0x3008 14f3c603d4SCarl Huang #define PCIE_SOC_GLOBAL_RESET_V 1 15f3c603d4SCarl Huang 16f3c603d4SCarl Huang #define WLAON_WARM_SW_ENTRY 0x1f80504 17f3c603d4SCarl Huang #define WLAON_SOC_RESET_CAUSE_REG 0x01f8060c 18f3c603d4SCarl Huang 19f3c603d4SCarl Huang #define PCIE_Q6_COOKIE_ADDR 0x01f80500 20f3c603d4SCarl Huang #define PCIE_Q6_COOKIE_DATA 0xc0000000 21f3c603d4SCarl Huang 22f3c603d4SCarl Huang /* register to wake the UMAC from power collapse */ 23f3c603d4SCarl Huang #define PCIE_SCRATCH_0_SOC_PCIE_REG 0x4040 24f3c603d4SCarl Huang 25f3c603d4SCarl Huang /* register used for handshake mechanism to validate UMAC is awake */ 26f3c603d4SCarl Huang #define PCIE_SOC_WAKE_PCIE_LOCAL_REG 0x3004 27f3c603d4SCarl Huang 28babb0cedSCarl Huang #define PCIE_PCIE_PARF_LTSSM 0x1e081b0 29babb0cedSCarl Huang #define PARM_LTSSM_VALUE 0x111 30babb0cedSCarl Huang 31babb0cedSCarl Huang #define GCC_GCC_PCIE_HOT_RST 0x1e402bc 32babb0cedSCarl Huang #define GCC_GCC_PCIE_HOT_RST_VAL 0x10 33babb0cedSCarl Huang 34babb0cedSCarl Huang #define PCIE_PCIE_INT_ALL_CLEAR 0x1e08228 35babb0cedSCarl Huang #define PCIE_SMLH_REQ_RST_LINK_DOWN 0x2 36babb0cedSCarl Huang #define PCIE_INT_CLEAR_ALL 0xffffffff 37babb0cedSCarl Huang 386fe6f68fSKarthikeyan Periyasamy #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(x) \ 396fe6f68fSKarthikeyan Periyasamy (ab->hw_params.regs->pcie_qserdes_sysclk_en_sel) 4006999407SCarl Huang #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL 0x10 4106999407SCarl Huang #define PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK 0xffffffff 426fe6f68fSKarthikeyan Periyasamy #define PCIE_PCS_OSC_DTCT_CONFIG1_REG(x) \ 436fe6f68fSKarthikeyan Periyasamy (ab->hw_params.regs->pcie_pcs_osc_dtct_config_base) 446fe6f68fSKarthikeyan Periyasamy #define PCIE_PCS_OSC_DTCT_CONFIG1_VAL 0x02 456fe6f68fSKarthikeyan Periyasamy #define PCIE_PCS_OSC_DTCT_CONFIG2_REG(x) \ 466fe6f68fSKarthikeyan Periyasamy (ab->hw_params.regs->pcie_pcs_osc_dtct_config_base + 0x4) 476fe6f68fSKarthikeyan Periyasamy #define PCIE_PCS_OSC_DTCT_CONFIG2_VAL 0x52 486fe6f68fSKarthikeyan Periyasamy #define PCIE_PCS_OSC_DTCT_CONFIG4_REG(x) \ 496fe6f68fSKarthikeyan Periyasamy (ab->hw_params.regs->pcie_pcs_osc_dtct_config_base + 0xc) 506fe6f68fSKarthikeyan Periyasamy #define PCIE_PCS_OSC_DTCT_CONFIG4_VAL 0xff 516fe6f68fSKarthikeyan Periyasamy #define PCIE_PCS_OSC_DTCT_CONFIG_MSK 0x000000ff 5206999407SCarl Huang 530ccdf439SCarl Huang #define WLAON_QFPROM_PWR_CTRL_REG 0x01f8031c 540ccdf439SCarl Huang #define QFPROM_PWR_CTRL_VDD4BLOW_MASK 0x4 550ccdf439SCarl Huang 56a05bd851SCarl Huang enum ath11k_pci_flags { 57e9603f4bSCarl Huang ATH11K_PCI_ASPM_RESTORE, 58a05bd851SCarl Huang }; 59a05bd851SCarl Huang 605762613eSGovind Singh struct ath11k_pci { 615762613eSGovind Singh struct pci_dev *pdev; 625762613eSGovind Singh struct ath11k_base *ab; 635762613eSGovind Singh u16 dev_id; 641399fb87SGovind Singh char amss_path[100]; 651399fb87SGovind Singh struct mhi_controller *mhi_ctrl; 66*121210ecSKalle Valo const struct ath11k_msi_config *msi_config; 67654e959aSGovind Singh u32 register_window; 68654e959aSGovind Singh 69654e959aSGovind Singh /* protects register_window above */ 70654e959aSGovind Singh spinlock_t window_lock; 71a05bd851SCarl Huang 72a05bd851SCarl Huang /* enum ath11k_pci_flags */ 73a05bd851SCarl Huang unsigned long flags; 74e9603f4bSCarl Huang u16 link_ctl; 755762613eSGovind Singh }; 765762613eSGovind Singh ath11k_pci_priv(struct ath11k_base * ab)775762613eSGovind Singhstatic inline struct ath11k_pci *ath11k_pci_priv(struct ath11k_base *ab) 785762613eSGovind Singh { 795762613eSGovind Singh return (struct ath11k_pci *)ab->drv_priv; 805762613eSGovind Singh } 811399fb87SGovind Singh 825b32b6ddSManikanta Pubbisetty int ath11k_pci_get_msi_irq(struct ath11k_base *ab, unsigned int vector); 831399fb87SGovind Singh #endif 84