1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/module.h> 8 #include <linux/msi.h> 9 #include <linux/pci.h> 10 #include <linux/of.h> 11 12 #include "pci.h" 13 #include "core.h" 14 #include "hif.h" 15 #include "mhi.h" 16 #include "debug.h" 17 #include "pcic.h" 18 #include "qmi.h" 19 20 #define ATH11K_PCI_BAR_NUM 0 21 #define ATH11K_PCI_DMA_MASK 32 22 23 #define TCSR_SOC_HW_VERSION 0x0224 24 #define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8) 25 #define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 0) 26 27 #define QCA6390_DEVICE_ID 0x1101 28 #define QCN9074_DEVICE_ID 0x1104 29 #define WCN6855_DEVICE_ID 0x1103 30 31 static const struct pci_device_id ath11k_pci_id_table[] = { 32 { PCI_VDEVICE(QCOM, QCA6390_DEVICE_ID) }, 33 { PCI_VDEVICE(QCOM, WCN6855_DEVICE_ID) }, 34 { PCI_VDEVICE(QCOM, QCN9074_DEVICE_ID) }, 35 {0} 36 }; 37 38 MODULE_DEVICE_TABLE(pci, ath11k_pci_id_table); 39 40 static int ath11k_pci_bus_wake_up(struct ath11k_base *ab) 41 { 42 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 43 44 return mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev); 45 } 46 47 static void ath11k_pci_bus_release(struct ath11k_base *ab) 48 { 49 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 50 51 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev); 52 } 53 54 static u32 ath11k_pci_get_window_start(struct ath11k_base *ab, u32 offset) 55 { 56 if (!ab->hw_params.static_window_map) 57 return ATH11K_PCI_WINDOW_START; 58 59 if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH11K_PCI_WINDOW_RANGE_MASK) 60 /* if offset lies within DP register range, use 3rd window */ 61 return 3 * ATH11K_PCI_WINDOW_START; 62 else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab)) < 63 ATH11K_PCI_WINDOW_RANGE_MASK) 64 /* if offset lies within CE register range, use 2nd window */ 65 return 2 * ATH11K_PCI_WINDOW_START; 66 else 67 return ATH11K_PCI_WINDOW_START; 68 } 69 70 static inline void ath11k_pci_select_window(struct ath11k_pci *ab_pci, u32 offset) 71 { 72 struct ath11k_base *ab = ab_pci->ab; 73 74 u32 window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, offset); 75 76 lockdep_assert_held(&ab_pci->window_lock); 77 78 if (window != ab_pci->register_window) { 79 iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window, 80 ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS); 81 ioread32(ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS); 82 ab_pci->register_window = window; 83 } 84 } 85 86 static void 87 ath11k_pci_window_write32(struct ath11k_base *ab, u32 offset, u32 value) 88 { 89 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 90 u32 window_start; 91 92 window_start = ath11k_pci_get_window_start(ab, offset); 93 94 if (window_start == ATH11K_PCI_WINDOW_START) { 95 spin_lock_bh(&ab_pci->window_lock); 96 ath11k_pci_select_window(ab_pci, offset); 97 iowrite32(value, ab->mem + window_start + 98 (offset & ATH11K_PCI_WINDOW_RANGE_MASK)); 99 spin_unlock_bh(&ab_pci->window_lock); 100 } else { 101 iowrite32(value, ab->mem + window_start + 102 (offset & ATH11K_PCI_WINDOW_RANGE_MASK)); 103 } 104 } 105 106 static u32 ath11k_pci_window_read32(struct ath11k_base *ab, u32 offset) 107 { 108 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 109 u32 window_start, val; 110 111 window_start = ath11k_pci_get_window_start(ab, offset); 112 113 if (window_start == ATH11K_PCI_WINDOW_START) { 114 spin_lock_bh(&ab_pci->window_lock); 115 ath11k_pci_select_window(ab_pci, offset); 116 val = ioread32(ab->mem + window_start + 117 (offset & ATH11K_PCI_WINDOW_RANGE_MASK)); 118 spin_unlock_bh(&ab_pci->window_lock); 119 } else { 120 val = ioread32(ab->mem + window_start + 121 (offset & ATH11K_PCI_WINDOW_RANGE_MASK)); 122 } 123 124 return val; 125 } 126 127 int ath11k_pci_get_msi_irq(struct ath11k_base *ab, unsigned int vector) 128 { 129 struct pci_dev *pci_dev = to_pci_dev(ab->dev); 130 131 return pci_irq_vector(pci_dev, vector); 132 } 133 134 static const struct ath11k_pci_ops ath11k_pci_ops_qca6390 = { 135 .wakeup = ath11k_pci_bus_wake_up, 136 .release = ath11k_pci_bus_release, 137 .get_msi_irq = ath11k_pci_get_msi_irq, 138 .window_write32 = ath11k_pci_window_write32, 139 .window_read32 = ath11k_pci_window_read32, 140 }; 141 142 static const struct ath11k_pci_ops ath11k_pci_ops_qcn9074 = { 143 .wakeup = NULL, 144 .release = NULL, 145 .get_msi_irq = ath11k_pci_get_msi_irq, 146 .window_write32 = ath11k_pci_window_write32, 147 .window_read32 = ath11k_pci_window_read32, 148 }; 149 150 static const struct ath11k_msi_config msi_config_one_msi = { 151 .total_vectors = 1, 152 .total_users = 4, 153 .users = (struct ath11k_msi_user[]) { 154 { .name = "MHI", .num_vectors = 3, .base_vector = 0 }, 155 { .name = "CE", .num_vectors = 1, .base_vector = 0 }, 156 { .name = "WAKE", .num_vectors = 1, .base_vector = 0 }, 157 { .name = "DP", .num_vectors = 1, .base_vector = 0 }, 158 }, 159 }; 160 161 static inline void ath11k_pci_select_static_window(struct ath11k_pci *ab_pci) 162 { 163 u32 umac_window; 164 u32 ce_window; 165 u32 window; 166 167 umac_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_SEQ_WCSS_UMAC_OFFSET); 168 ce_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_CE_WFSS_CE_REG_BASE); 169 window = (umac_window << 12) | (ce_window << 6); 170 171 iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window, 172 ab_pci->ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS); 173 } 174 175 static void ath11k_pci_soc_global_reset(struct ath11k_base *ab) 176 { 177 u32 val, delay; 178 179 val = ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET); 180 181 val |= PCIE_SOC_GLOBAL_RESET_V; 182 183 ath11k_pcic_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 184 185 /* TODO: exact time to sleep is uncertain */ 186 delay = 10; 187 mdelay(delay); 188 189 /* Need to toggle V bit back otherwise stuck in reset status */ 190 val &= ~PCIE_SOC_GLOBAL_RESET_V; 191 192 ath11k_pcic_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 193 194 mdelay(delay); 195 196 val = ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET); 197 if (val == 0xffffffff) 198 ath11k_warn(ab, "link down error during global reset\n"); 199 } 200 201 static void ath11k_pci_clear_dbg_registers(struct ath11k_base *ab) 202 { 203 u32 val; 204 205 /* read cookie */ 206 val = ath11k_pcic_read32(ab, PCIE_Q6_COOKIE_ADDR); 207 ath11k_dbg(ab, ATH11K_DBG_PCI, "pcie_q6_cookie_addr 0x%x\n", val); 208 209 val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY); 210 ath11k_dbg(ab, ATH11K_DBG_PCI, "wlaon_warm_sw_entry 0x%x\n", val); 211 212 /* TODO: exact time to sleep is uncertain */ 213 mdelay(10); 214 215 /* write 0 to WLAON_WARM_SW_ENTRY to prevent Q6 from 216 * continuing warm path and entering dead loop. 217 */ 218 ath11k_pcic_write32(ab, WLAON_WARM_SW_ENTRY, 0); 219 mdelay(10); 220 221 val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY); 222 ath11k_dbg(ab, ATH11K_DBG_PCI, "wlaon_warm_sw_entry 0x%x\n", val); 223 224 /* A read clear register. clear the register to prevent 225 * Q6 from entering wrong code path. 226 */ 227 val = ath11k_pcic_read32(ab, WLAON_SOC_RESET_CAUSE_REG); 228 ath11k_dbg(ab, ATH11K_DBG_PCI, "soc reset cause %d\n", val); 229 } 230 231 static int ath11k_pci_set_link_reg(struct ath11k_base *ab, 232 u32 offset, u32 value, u32 mask) 233 { 234 u32 v; 235 int i; 236 237 v = ath11k_pcic_read32(ab, offset); 238 if ((v & mask) == value) 239 return 0; 240 241 for (i = 0; i < 10; i++) { 242 ath11k_pcic_write32(ab, offset, (v & ~mask) | value); 243 244 v = ath11k_pcic_read32(ab, offset); 245 if ((v & mask) == value) 246 return 0; 247 248 mdelay(2); 249 } 250 251 ath11k_warn(ab, "failed to set pcie link register 0x%08x: 0x%08x != 0x%08x\n", 252 offset, v & mask, value); 253 254 return -ETIMEDOUT; 255 } 256 257 static int ath11k_pci_fix_l1ss(struct ath11k_base *ab) 258 { 259 int ret; 260 261 ret = ath11k_pci_set_link_reg(ab, 262 PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(ab), 263 PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL, 264 PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK); 265 if (ret) { 266 ath11k_warn(ab, "failed to set sysclk: %d\n", ret); 267 return ret; 268 } 269 270 ret = ath11k_pci_set_link_reg(ab, 271 PCIE_PCS_OSC_DTCT_CONFIG1_REG(ab), 272 PCIE_PCS_OSC_DTCT_CONFIG1_VAL, 273 PCIE_PCS_OSC_DTCT_CONFIG_MSK); 274 if (ret) { 275 ath11k_warn(ab, "failed to set dtct config1 error: %d\n", ret); 276 return ret; 277 } 278 279 ret = ath11k_pci_set_link_reg(ab, 280 PCIE_PCS_OSC_DTCT_CONFIG2_REG(ab), 281 PCIE_PCS_OSC_DTCT_CONFIG2_VAL, 282 PCIE_PCS_OSC_DTCT_CONFIG_MSK); 283 if (ret) { 284 ath11k_warn(ab, "failed to set dtct config2: %d\n", ret); 285 return ret; 286 } 287 288 ret = ath11k_pci_set_link_reg(ab, 289 PCIE_PCS_OSC_DTCT_CONFIG4_REG(ab), 290 PCIE_PCS_OSC_DTCT_CONFIG4_VAL, 291 PCIE_PCS_OSC_DTCT_CONFIG_MSK); 292 if (ret) { 293 ath11k_warn(ab, "failed to set dtct config4: %d\n", ret); 294 return ret; 295 } 296 297 return 0; 298 } 299 300 static void ath11k_pci_enable_ltssm(struct ath11k_base *ab) 301 { 302 u32 val; 303 int i; 304 305 val = ath11k_pcic_read32(ab, PCIE_PCIE_PARF_LTSSM); 306 307 /* PCIE link seems very unstable after the Hot Reset*/ 308 for (i = 0; val != PARM_LTSSM_VALUE && i < 5; i++) { 309 if (val == 0xffffffff) 310 mdelay(5); 311 312 ath11k_pcic_write32(ab, PCIE_PCIE_PARF_LTSSM, PARM_LTSSM_VALUE); 313 val = ath11k_pcic_read32(ab, PCIE_PCIE_PARF_LTSSM); 314 } 315 316 ath11k_dbg(ab, ATH11K_DBG_PCI, "ltssm 0x%x\n", val); 317 318 val = ath11k_pcic_read32(ab, GCC_GCC_PCIE_HOT_RST); 319 val |= GCC_GCC_PCIE_HOT_RST_VAL; 320 ath11k_pcic_write32(ab, GCC_GCC_PCIE_HOT_RST, val); 321 val = ath11k_pcic_read32(ab, GCC_GCC_PCIE_HOT_RST); 322 323 ath11k_dbg(ab, ATH11K_DBG_PCI, "pcie_hot_rst 0x%x\n", val); 324 325 mdelay(5); 326 } 327 328 static void ath11k_pci_clear_all_intrs(struct ath11k_base *ab) 329 { 330 /* This is a WAR for PCIE Hotreset. 331 * When target receive Hotreset, but will set the interrupt. 332 * So when download SBL again, SBL will open Interrupt and 333 * receive it, and crash immediately. 334 */ 335 ath11k_pcic_write32(ab, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL); 336 } 337 338 static void ath11k_pci_set_wlaon_pwr_ctrl(struct ath11k_base *ab) 339 { 340 u32 val; 341 342 val = ath11k_pcic_read32(ab, WLAON_QFPROM_PWR_CTRL_REG); 343 val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK; 344 ath11k_pcic_write32(ab, WLAON_QFPROM_PWR_CTRL_REG, val); 345 } 346 347 static void ath11k_pci_force_wake(struct ath11k_base *ab) 348 { 349 ath11k_pcic_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1); 350 mdelay(5); 351 } 352 353 static void ath11k_pci_sw_reset(struct ath11k_base *ab, bool power_on) 354 { 355 mdelay(100); 356 357 if (power_on) { 358 ath11k_pci_enable_ltssm(ab); 359 ath11k_pci_clear_all_intrs(ab); 360 ath11k_pci_set_wlaon_pwr_ctrl(ab); 361 if (ab->hw_params.fix_l1ss) 362 ath11k_pci_fix_l1ss(ab); 363 } 364 365 ath11k_mhi_clear_vector(ab); 366 ath11k_pci_clear_dbg_registers(ab); 367 ath11k_pci_soc_global_reset(ab); 368 ath11k_mhi_set_mhictrl_reset(ab); 369 } 370 371 static void ath11k_pci_init_qmi_ce_config(struct ath11k_base *ab) 372 { 373 struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg; 374 375 cfg->tgt_ce = ab->hw_params.target_ce_config; 376 cfg->tgt_ce_len = ab->hw_params.target_ce_count; 377 378 cfg->svc_to_ce_map = ab->hw_params.svc_to_ce_map; 379 cfg->svc_to_ce_map_len = ab->hw_params.svc_to_ce_map_len; 380 ab->qmi.service_ins_id = ab->hw_params.qmi_service_ins_id; 381 382 ath11k_ce_get_shadow_config(ab, &cfg->shadow_reg_v2, 383 &cfg->shadow_reg_v2_len); 384 } 385 386 static void ath11k_pci_msi_config(struct ath11k_pci *ab_pci, bool enable) 387 { 388 struct pci_dev *dev = ab_pci->pdev; 389 u16 control; 390 391 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); 392 393 if (enable) 394 control |= PCI_MSI_FLAGS_ENABLE; 395 else 396 control &= ~PCI_MSI_FLAGS_ENABLE; 397 398 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); 399 } 400 401 static void ath11k_pci_msi_enable(struct ath11k_pci *ab_pci) 402 { 403 ath11k_pci_msi_config(ab_pci, true); 404 } 405 406 static void ath11k_pci_msi_disable(struct ath11k_pci *ab_pci) 407 { 408 ath11k_pci_msi_config(ab_pci, false); 409 } 410 411 static int ath11k_pci_alloc_msi(struct ath11k_pci *ab_pci) 412 { 413 struct ath11k_base *ab = ab_pci->ab; 414 const struct ath11k_msi_config *msi_config = ab->pci.msi.config; 415 struct pci_dev *pci_dev = ab_pci->pdev; 416 struct msi_desc *msi_desc; 417 int num_vectors; 418 int ret; 419 420 num_vectors = pci_alloc_irq_vectors(pci_dev, 421 msi_config->total_vectors, 422 msi_config->total_vectors, 423 PCI_IRQ_MSI); 424 if (num_vectors == msi_config->total_vectors) { 425 set_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags); 426 } else { 427 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev, 428 1, 429 1, 430 PCI_IRQ_MSI); 431 if (num_vectors < 0) { 432 ret = -EINVAL; 433 goto reset_msi_config; 434 } 435 clear_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags); 436 ab->pci.msi.config = &msi_config_one_msi; 437 ath11k_dbg(ab, ATH11K_DBG_PCI, "request one msi vector\n"); 438 } 439 ath11k_info(ab, "MSI vectors: %d\n", num_vectors); 440 441 ath11k_pci_msi_disable(ab_pci); 442 443 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq); 444 if (!msi_desc) { 445 ath11k_err(ab, "msi_desc is NULL!\n"); 446 ret = -EINVAL; 447 goto free_msi_vector; 448 } 449 450 ab->pci.msi.ep_base_data = msi_desc->msg.data; 451 452 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO, 453 &ab->pci.msi.addr_lo); 454 455 if (msi_desc->pci.msi_attrib.is_64) { 456 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI, 457 &ab->pci.msi.addr_hi); 458 } else { 459 ab->pci.msi.addr_hi = 0; 460 } 461 462 ath11k_dbg(ab, ATH11K_DBG_PCI, "msi base data is %d\n", ab->pci.msi.ep_base_data); 463 464 return 0; 465 466 free_msi_vector: 467 pci_free_irq_vectors(ab_pci->pdev); 468 469 reset_msi_config: 470 return ret; 471 } 472 473 static void ath11k_pci_free_msi(struct ath11k_pci *ab_pci) 474 { 475 pci_free_irq_vectors(ab_pci->pdev); 476 } 477 478 static int ath11k_pci_config_msi_data(struct ath11k_pci *ab_pci) 479 { 480 struct msi_desc *msi_desc; 481 482 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq); 483 if (!msi_desc) { 484 ath11k_err(ab_pci->ab, "msi_desc is NULL!\n"); 485 pci_free_irq_vectors(ab_pci->pdev); 486 return -EINVAL; 487 } 488 489 ab_pci->ab->pci.msi.ep_base_data = msi_desc->msg.data; 490 491 ath11k_dbg(ab_pci->ab, ATH11K_DBG_PCI, "after request_irq msi_ep_base_data %d\n", 492 ab_pci->ab->pci.msi.ep_base_data); 493 494 return 0; 495 } 496 497 static int ath11k_pci_claim(struct ath11k_pci *ab_pci, struct pci_dev *pdev) 498 { 499 struct ath11k_base *ab = ab_pci->ab; 500 u16 device_id; 501 int ret = 0; 502 503 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id); 504 if (device_id != ab_pci->dev_id) { 505 ath11k_err(ab, "pci device id mismatch: 0x%x 0x%x\n", 506 device_id, ab_pci->dev_id); 507 ret = -EIO; 508 goto out; 509 } 510 511 ret = pci_assign_resource(pdev, ATH11K_PCI_BAR_NUM); 512 if (ret) { 513 ath11k_err(ab, "failed to assign pci resource: %d\n", ret); 514 goto out; 515 } 516 517 ret = pci_enable_device(pdev); 518 if (ret) { 519 ath11k_err(ab, "failed to enable pci device: %d\n", ret); 520 goto out; 521 } 522 523 ret = pci_request_region(pdev, ATH11K_PCI_BAR_NUM, "ath11k_pci"); 524 if (ret) { 525 ath11k_err(ab, "failed to request pci region: %d\n", ret); 526 goto disable_device; 527 } 528 529 ret = dma_set_mask_and_coherent(&pdev->dev, 530 DMA_BIT_MASK(ATH11K_PCI_DMA_MASK)); 531 if (ret) { 532 ath11k_err(ab, "failed to set pci dma mask to %d: %d\n", 533 ATH11K_PCI_DMA_MASK, ret); 534 goto release_region; 535 } 536 537 pci_set_master(pdev); 538 539 ab->mem_len = pci_resource_len(pdev, ATH11K_PCI_BAR_NUM); 540 ab->mem = pci_iomap(pdev, ATH11K_PCI_BAR_NUM, 0); 541 if (!ab->mem) { 542 ath11k_err(ab, "failed to map pci bar %d\n", ATH11K_PCI_BAR_NUM); 543 ret = -EIO; 544 goto release_region; 545 } 546 547 ab->mem_ce = ab->mem; 548 549 ath11k_dbg(ab, ATH11K_DBG_BOOT, "pci_mem 0x%p\n", ab->mem); 550 return 0; 551 552 release_region: 553 pci_release_region(pdev, ATH11K_PCI_BAR_NUM); 554 disable_device: 555 pci_disable_device(pdev); 556 out: 557 return ret; 558 } 559 560 static void ath11k_pci_free_region(struct ath11k_pci *ab_pci) 561 { 562 struct ath11k_base *ab = ab_pci->ab; 563 struct pci_dev *pci_dev = ab_pci->pdev; 564 565 pci_iounmap(pci_dev, ab->mem); 566 ab->mem = NULL; 567 pci_release_region(pci_dev, ATH11K_PCI_BAR_NUM); 568 if (pci_is_enabled(pci_dev)) 569 pci_disable_device(pci_dev); 570 } 571 572 static void ath11k_pci_aspm_disable(struct ath11k_pci *ab_pci) 573 { 574 struct ath11k_base *ab = ab_pci->ab; 575 576 pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL, 577 &ab_pci->link_ctl); 578 579 ath11k_dbg(ab, ATH11K_DBG_PCI, "link_ctl 0x%04x L0s %d L1 %d\n", 580 ab_pci->link_ctl, 581 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S), 582 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1)); 583 584 /* disable L0s and L1 */ 585 pcie_capability_clear_word(ab_pci->pdev, PCI_EXP_LNKCTL, 586 PCI_EXP_LNKCTL_ASPMC); 587 588 set_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags); 589 } 590 591 static void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci) 592 { 593 if (test_and_clear_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags)) 594 pcie_capability_clear_and_set_word(ab_pci->pdev, PCI_EXP_LNKCTL, 595 PCI_EXP_LNKCTL_ASPMC, 596 ab_pci->link_ctl & 597 PCI_EXP_LNKCTL_ASPMC); 598 } 599 600 static int ath11k_pci_power_up(struct ath11k_base *ab) 601 { 602 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 603 int ret; 604 605 ab_pci->register_window = 0; 606 clear_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags); 607 ath11k_pci_sw_reset(ab_pci->ab, true); 608 609 /* Disable ASPM during firmware download due to problems switching 610 * to AMSS state. 611 */ 612 ath11k_pci_aspm_disable(ab_pci); 613 614 ath11k_pci_msi_enable(ab_pci); 615 616 ret = ath11k_mhi_start(ab_pci); 617 if (ret) { 618 ath11k_err(ab, "failed to start mhi: %d\n", ret); 619 return ret; 620 } 621 622 if (ab->hw_params.static_window_map) 623 ath11k_pci_select_static_window(ab_pci); 624 625 return 0; 626 } 627 628 static void ath11k_pci_power_down(struct ath11k_base *ab) 629 { 630 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 631 632 /* restore aspm in case firmware bootup fails */ 633 ath11k_pci_aspm_restore(ab_pci); 634 635 ath11k_pci_force_wake(ab_pci->ab); 636 637 ath11k_pci_msi_disable(ab_pci); 638 639 ath11k_mhi_stop(ab_pci); 640 clear_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags); 641 ath11k_pci_sw_reset(ab_pci->ab, false); 642 } 643 644 static int ath11k_pci_hif_suspend(struct ath11k_base *ab) 645 { 646 struct ath11k_pci *ar_pci = ath11k_pci_priv(ab); 647 648 return ath11k_mhi_suspend(ar_pci); 649 } 650 651 static int ath11k_pci_hif_resume(struct ath11k_base *ab) 652 { 653 struct ath11k_pci *ar_pci = ath11k_pci_priv(ab); 654 655 return ath11k_mhi_resume(ar_pci); 656 } 657 658 static void ath11k_pci_hif_ce_irq_enable(struct ath11k_base *ab) 659 { 660 ath11k_pcic_ce_irqs_enable(ab); 661 } 662 663 static void ath11k_pci_hif_ce_irq_disable(struct ath11k_base *ab) 664 { 665 ath11k_pcic_ce_irq_disable_sync(ab); 666 } 667 668 static int ath11k_pci_start(struct ath11k_base *ab) 669 { 670 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 671 672 /* TODO: for now don't restore ASPM in case of single MSI 673 * vector as MHI register reading in M2 causes system hang. 674 */ 675 if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags)) 676 ath11k_pci_aspm_restore(ab_pci); 677 else 678 ath11k_info(ab, "leaving PCI ASPM disabled to avoid MHI M2 problems\n"); 679 680 ath11k_pcic_start(ab); 681 682 return 0; 683 } 684 685 static const struct ath11k_hif_ops ath11k_pci_hif_ops = { 686 .start = ath11k_pci_start, 687 .stop = ath11k_pcic_stop, 688 .read32 = ath11k_pcic_read32, 689 .write32 = ath11k_pcic_write32, 690 .read = ath11k_pcic_read, 691 .power_down = ath11k_pci_power_down, 692 .power_up = ath11k_pci_power_up, 693 .suspend = ath11k_pci_hif_suspend, 694 .resume = ath11k_pci_hif_resume, 695 .irq_enable = ath11k_pcic_ext_irq_enable, 696 .irq_disable = ath11k_pcic_ext_irq_disable, 697 .get_msi_address = ath11k_pcic_get_msi_address, 698 .get_user_msi_vector = ath11k_pcic_get_user_msi_assignment, 699 .map_service_to_pipe = ath11k_pcic_map_service_to_pipe, 700 .ce_irq_enable = ath11k_pci_hif_ce_irq_enable, 701 .ce_irq_disable = ath11k_pci_hif_ce_irq_disable, 702 .get_ce_msi_idx = ath11k_pcic_get_ce_msi_idx, 703 }; 704 705 static void ath11k_pci_read_hw_version(struct ath11k_base *ab, u32 *major, u32 *minor) 706 { 707 u32 soc_hw_version; 708 709 soc_hw_version = ath11k_pcic_read32(ab, TCSR_SOC_HW_VERSION); 710 *major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK, 711 soc_hw_version); 712 *minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK, 713 soc_hw_version); 714 715 ath11k_dbg(ab, ATH11K_DBG_PCI, "tcsr_soc_hw_version major %d minor %d\n", 716 *major, *minor); 717 } 718 719 static int ath11k_pci_set_irq_affinity_hint(struct ath11k_pci *ab_pci, 720 const struct cpumask *m) 721 { 722 if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab_pci->ab->dev_flags)) 723 return 0; 724 725 return irq_set_affinity_hint(ab_pci->pdev->irq, m); 726 } 727 728 static int ath11k_pci_probe(struct pci_dev *pdev, 729 const struct pci_device_id *pci_dev) 730 { 731 struct ath11k_base *ab; 732 struct ath11k_pci *ab_pci; 733 u32 soc_hw_version_major, soc_hw_version_minor, addr; 734 const struct ath11k_pci_ops *pci_ops; 735 int ret; 736 737 ab = ath11k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH11K_BUS_PCI); 738 739 if (!ab) { 740 dev_err(&pdev->dev, "failed to allocate ath11k base\n"); 741 return -ENOMEM; 742 } 743 744 ab->dev = &pdev->dev; 745 pci_set_drvdata(pdev, ab); 746 ab_pci = ath11k_pci_priv(ab); 747 ab_pci->dev_id = pci_dev->device; 748 ab_pci->ab = ab; 749 ab_pci->pdev = pdev; 750 ab->hif.ops = &ath11k_pci_hif_ops; 751 ab->fw_mode = ATH11K_FIRMWARE_MODE_NORMAL; 752 pci_set_drvdata(pdev, ab); 753 spin_lock_init(&ab_pci->window_lock); 754 755 /* Set fixed_mem_region to true for platforms support reserved memory 756 * from DT. If memory is reserved from DT for FW, ath11k driver need not 757 * allocate memory. 758 */ 759 ret = of_property_read_u32(ab->dev->of_node, "memory-region", &addr); 760 if (!ret) 761 set_bit(ATH11K_FLAG_FIXED_MEM_RGN, &ab->dev_flags); 762 763 ret = ath11k_pci_claim(ab_pci, pdev); 764 if (ret) { 765 ath11k_err(ab, "failed to claim device: %d\n", ret); 766 goto err_free_core; 767 } 768 769 ath11k_dbg(ab, ATH11K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n", 770 pdev->vendor, pdev->device, 771 pdev->subsystem_vendor, pdev->subsystem_device); 772 773 ab->id.vendor = pdev->vendor; 774 ab->id.device = pdev->device; 775 ab->id.subsystem_vendor = pdev->subsystem_vendor; 776 ab->id.subsystem_device = pdev->subsystem_device; 777 778 switch (pci_dev->device) { 779 case QCA6390_DEVICE_ID: 780 ath11k_pci_read_hw_version(ab, &soc_hw_version_major, 781 &soc_hw_version_minor); 782 switch (soc_hw_version_major) { 783 case 2: 784 ab->hw_rev = ATH11K_HW_QCA6390_HW20; 785 break; 786 default: 787 dev_err(&pdev->dev, "Unsupported QCA6390 SOC hardware version: %d %d\n", 788 soc_hw_version_major, soc_hw_version_minor); 789 ret = -EOPNOTSUPP; 790 goto err_pci_free_region; 791 } 792 793 pci_ops = &ath11k_pci_ops_qca6390; 794 break; 795 case QCN9074_DEVICE_ID: 796 pci_ops = &ath11k_pci_ops_qcn9074; 797 ab->hw_rev = ATH11K_HW_QCN9074_HW10; 798 break; 799 case WCN6855_DEVICE_ID: 800 ab->id.bdf_search = ATH11K_BDF_SEARCH_BUS_AND_BOARD; 801 ath11k_pci_read_hw_version(ab, &soc_hw_version_major, 802 &soc_hw_version_minor); 803 switch (soc_hw_version_major) { 804 case 2: 805 switch (soc_hw_version_minor) { 806 case 0x00: 807 case 0x01: 808 ab->hw_rev = ATH11K_HW_WCN6855_HW20; 809 break; 810 case 0x10: 811 case 0x11: 812 ab->hw_rev = ATH11K_HW_WCN6855_HW21; 813 break; 814 default: 815 goto unsupported_wcn6855_soc; 816 } 817 break; 818 default: 819 unsupported_wcn6855_soc: 820 dev_err(&pdev->dev, "Unsupported WCN6855 SOC hardware version: %d %d\n", 821 soc_hw_version_major, soc_hw_version_minor); 822 ret = -EOPNOTSUPP; 823 goto err_pci_free_region; 824 } 825 826 pci_ops = &ath11k_pci_ops_qca6390; 827 break; 828 default: 829 dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n", 830 pci_dev->device); 831 ret = -EOPNOTSUPP; 832 goto err_pci_free_region; 833 } 834 835 ret = ath11k_pcic_register_pci_ops(ab, pci_ops); 836 if (ret) { 837 ath11k_err(ab, "failed to register PCI ops: %d\n", ret); 838 goto err_pci_free_region; 839 } 840 841 ret = ath11k_pcic_init_msi_config(ab); 842 if (ret) { 843 ath11k_err(ab, "failed to init msi config: %d\n", ret); 844 goto err_pci_free_region; 845 } 846 847 ret = ath11k_pci_alloc_msi(ab_pci); 848 if (ret) { 849 ath11k_err(ab, "failed to enable msi: %d\n", ret); 850 goto err_pci_free_region; 851 } 852 853 ret = ath11k_core_pre_init(ab); 854 if (ret) 855 goto err_pci_disable_msi; 856 857 ret = ath11k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0)); 858 if (ret) { 859 ath11k_err(ab, "failed to set irq affinity %d\n", ret); 860 goto err_pci_disable_msi; 861 } 862 863 ret = ath11k_mhi_register(ab_pci); 864 if (ret) { 865 ath11k_err(ab, "failed to register mhi: %d\n", ret); 866 goto err_irq_affinity_cleanup; 867 } 868 869 ret = ath11k_hal_srng_init(ab); 870 if (ret) 871 goto err_mhi_unregister; 872 873 ret = ath11k_ce_alloc_pipes(ab); 874 if (ret) { 875 ath11k_err(ab, "failed to allocate ce pipes: %d\n", ret); 876 goto err_hal_srng_deinit; 877 } 878 879 ath11k_pci_init_qmi_ce_config(ab); 880 881 ret = ath11k_pcic_config_irq(ab); 882 if (ret) { 883 ath11k_err(ab, "failed to config irq: %d\n", ret); 884 goto err_ce_free; 885 } 886 887 /* kernel may allocate a dummy vector before request_irq and 888 * then allocate a real vector when request_irq is called. 889 * So get msi_data here again to avoid spurious interrupt 890 * as msi_data will configured to srngs. 891 */ 892 ret = ath11k_pci_config_msi_data(ab_pci); 893 if (ret) { 894 ath11k_err(ab, "failed to config msi_data: %d\n", ret); 895 goto err_free_irq; 896 } 897 898 ret = ath11k_core_init(ab); 899 if (ret) { 900 ath11k_err(ab, "failed to init core: %d\n", ret); 901 goto err_free_irq; 902 } 903 ath11k_qmi_fwreset_from_cold_boot(ab); 904 return 0; 905 906 err_free_irq: 907 ath11k_pcic_free_irq(ab); 908 909 err_ce_free: 910 ath11k_ce_free_pipes(ab); 911 912 err_hal_srng_deinit: 913 ath11k_hal_srng_deinit(ab); 914 915 err_mhi_unregister: 916 ath11k_mhi_unregister(ab_pci); 917 918 err_irq_affinity_cleanup: 919 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL); 920 921 err_pci_disable_msi: 922 ath11k_pci_free_msi(ab_pci); 923 924 err_pci_free_region: 925 ath11k_pci_free_region(ab_pci); 926 927 err_free_core: 928 ath11k_core_free(ab); 929 930 return ret; 931 } 932 933 static void ath11k_pci_remove(struct pci_dev *pdev) 934 { 935 struct ath11k_base *ab = pci_get_drvdata(pdev); 936 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 937 938 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL); 939 940 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) { 941 ath11k_pci_power_down(ab); 942 ath11k_debugfs_soc_destroy(ab); 943 ath11k_qmi_deinit_service(ab); 944 goto qmi_fail; 945 } 946 947 set_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags); 948 949 ath11k_core_deinit(ab); 950 951 qmi_fail: 952 ath11k_mhi_unregister(ab_pci); 953 954 ath11k_pcic_free_irq(ab); 955 ath11k_pci_free_msi(ab_pci); 956 ath11k_pci_free_region(ab_pci); 957 958 ath11k_hal_srng_deinit(ab); 959 ath11k_ce_free_pipes(ab); 960 ath11k_core_free(ab); 961 } 962 963 static void ath11k_pci_shutdown(struct pci_dev *pdev) 964 { 965 struct ath11k_base *ab = pci_get_drvdata(pdev); 966 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 967 968 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL); 969 ath11k_pci_power_down(ab); 970 } 971 972 static __maybe_unused int ath11k_pci_pm_suspend(struct device *dev) 973 { 974 struct ath11k_base *ab = dev_get_drvdata(dev); 975 int ret; 976 977 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) { 978 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot skipping pci suspend as qmi is not initialised\n"); 979 return 0; 980 } 981 982 ret = ath11k_core_suspend(ab); 983 if (ret) 984 ath11k_warn(ab, "failed to suspend core: %d\n", ret); 985 986 return 0; 987 } 988 989 static __maybe_unused int ath11k_pci_pm_resume(struct device *dev) 990 { 991 struct ath11k_base *ab = dev_get_drvdata(dev); 992 int ret; 993 994 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) { 995 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot skipping pci resume as qmi is not initialised\n"); 996 return 0; 997 } 998 999 ret = ath11k_core_resume(ab); 1000 if (ret) 1001 ath11k_warn(ab, "failed to resume core: %d\n", ret); 1002 1003 return ret; 1004 } 1005 1006 static SIMPLE_DEV_PM_OPS(ath11k_pci_pm_ops, 1007 ath11k_pci_pm_suspend, 1008 ath11k_pci_pm_resume); 1009 1010 static struct pci_driver ath11k_pci_driver = { 1011 .name = "ath11k_pci", 1012 .id_table = ath11k_pci_id_table, 1013 .probe = ath11k_pci_probe, 1014 .remove = ath11k_pci_remove, 1015 .shutdown = ath11k_pci_shutdown, 1016 #ifdef CONFIG_PM 1017 .driver.pm = &ath11k_pci_pm_ops, 1018 #endif 1019 }; 1020 1021 static int ath11k_pci_init(void) 1022 { 1023 int ret; 1024 1025 ret = pci_register_driver(&ath11k_pci_driver); 1026 if (ret) 1027 pr_err("failed to register ath11k pci driver: %d\n", 1028 ret); 1029 1030 return ret; 1031 } 1032 module_init(ath11k_pci_init); 1033 1034 static void ath11k_pci_exit(void) 1035 { 1036 pci_unregister_driver(&ath11k_pci_driver); 1037 } 1038 1039 module_exit(ath11k_pci_exit); 1040 1041 MODULE_DESCRIPTION("Driver support for Qualcomm Technologies PCIe 802.11ax WLAN devices"); 1042 MODULE_LICENSE("Dual BSD/GPL"); 1043 1044 /* firmware files */ 1045 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/*"); 1046 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCN9074/hw1.0/*"); 1047 MODULE_FIRMWARE(ATH11K_FW_DIR "/WCN6855/hw2.0/*"); 1048 MODULE_FIRMWARE(ATH11K_FW_DIR "/WCN6855/hw2.1/*"); 1049