1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/msi.h> 8 #include <linux/pci.h> 9 10 #include "pci.h" 11 #include "core.h" 12 #include "hif.h" 13 #include "mhi.h" 14 #include "debug.h" 15 16 #define ATH11K_PCI_BAR_NUM 0 17 #define ATH11K_PCI_DMA_MASK 32 18 19 #define ATH11K_PCI_IRQ_CE0_OFFSET 3 20 21 #define WINDOW_ENABLE_BIT 0x40000000 22 #define WINDOW_REG_ADDRESS 0x310c 23 #define WINDOW_VALUE_MASK GENMASK(24, 19) 24 #define WINDOW_START 0x80000 25 #define WINDOW_RANGE_MASK GENMASK(18, 0) 26 27 #define QCA6390_DEVICE_ID 0x1101 28 29 static const struct pci_device_id ath11k_pci_id_table[] = { 30 { PCI_VDEVICE(QCOM, QCA6390_DEVICE_ID) }, 31 {0} 32 }; 33 34 MODULE_DEVICE_TABLE(pci, ath11k_pci_id_table); 35 36 static const struct ath11k_bus_params ath11k_pci_bus_params = { 37 .mhi_support = true, 38 .m3_fw_support = true, 39 .fixed_bdf_addr = false, 40 .fixed_mem_region = false, 41 }; 42 43 static const struct ath11k_msi_config msi_config = { 44 .total_vectors = 32, 45 .total_users = 4, 46 .users = (struct ath11k_msi_user[]) { 47 { .name = "MHI", .num_vectors = 3, .base_vector = 0 }, 48 { .name = "CE", .num_vectors = 10, .base_vector = 3 }, 49 { .name = "WAKE", .num_vectors = 1, .base_vector = 13 }, 50 { .name = "DP", .num_vectors = 18, .base_vector = 14 }, 51 }, 52 }; 53 54 static const char *irq_name[ATH11K_IRQ_NUM_MAX] = { 55 "bhi", 56 "mhi-er0", 57 "mhi-er1", 58 "ce0", 59 "ce1", 60 "ce2", 61 "ce3", 62 "ce4", 63 "ce5", 64 "ce6", 65 "ce7", 66 "ce8", 67 "ce9", 68 "ce10", 69 "ce11", 70 "host2wbm-desc-feed", 71 "host2reo-re-injection", 72 "host2reo-command", 73 "host2rxdma-monitor-ring3", 74 "host2rxdma-monitor-ring2", 75 "host2rxdma-monitor-ring1", 76 "reo2ost-exception", 77 "wbm2host-rx-release", 78 "reo2host-status", 79 "reo2host-destination-ring4", 80 "reo2host-destination-ring3", 81 "reo2host-destination-ring2", 82 "reo2host-destination-ring1", 83 "rxdma2host-monitor-destination-mac3", 84 "rxdma2host-monitor-destination-mac2", 85 "rxdma2host-monitor-destination-mac1", 86 "ppdu-end-interrupts-mac3", 87 "ppdu-end-interrupts-mac2", 88 "ppdu-end-interrupts-mac1", 89 "rxdma2host-monitor-status-ring-mac3", 90 "rxdma2host-monitor-status-ring-mac2", 91 "rxdma2host-monitor-status-ring-mac1", 92 "host2rxdma-host-buf-ring-mac3", 93 "host2rxdma-host-buf-ring-mac2", 94 "host2rxdma-host-buf-ring-mac1", 95 "rxdma2host-destination-ring-mac3", 96 "rxdma2host-destination-ring-mac2", 97 "rxdma2host-destination-ring-mac1", 98 "host2tcl-input-ring4", 99 "host2tcl-input-ring3", 100 "host2tcl-input-ring2", 101 "host2tcl-input-ring1", 102 "wbm2host-tx-completions-ring3", 103 "wbm2host-tx-completions-ring2", 104 "wbm2host-tx-completions-ring1", 105 "tcl2host-status-ring", 106 }; 107 108 static inline void ath11k_pci_select_window(struct ath11k_pci *ab_pci, u32 offset) 109 { 110 struct ath11k_base *ab = ab_pci->ab; 111 112 u32 window = FIELD_GET(WINDOW_VALUE_MASK, offset); 113 114 lockdep_assert_held(&ab_pci->window_lock); 115 116 if (window != ab_pci->register_window) { 117 iowrite32(WINDOW_ENABLE_BIT | window, 118 ab->mem + WINDOW_REG_ADDRESS); 119 ab_pci->register_window = window; 120 } 121 } 122 123 void ath11k_pci_write32(struct ath11k_base *ab, u32 offset, u32 value) 124 { 125 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 126 127 if (offset < WINDOW_START) { 128 iowrite32(value, ab->mem + offset); 129 } else { 130 spin_lock_bh(&ab_pci->window_lock); 131 ath11k_pci_select_window(ab_pci, offset); 132 iowrite32(value, ab->mem + WINDOW_START + (offset & WINDOW_RANGE_MASK)); 133 spin_unlock_bh(&ab_pci->window_lock); 134 } 135 } 136 137 u32 ath11k_pci_read32(struct ath11k_base *ab, u32 offset) 138 { 139 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 140 u32 val; 141 142 if (offset < WINDOW_START) { 143 val = ioread32(ab->mem + offset); 144 } else { 145 spin_lock_bh(&ab_pci->window_lock); 146 ath11k_pci_select_window(ab_pci, offset); 147 val = ioread32(ab->mem + WINDOW_START + (offset & WINDOW_RANGE_MASK)); 148 spin_unlock_bh(&ab_pci->window_lock); 149 } 150 151 return val; 152 } 153 154 static void ath11k_pci_soc_global_reset(struct ath11k_base *ab) 155 { 156 u32 val, delay; 157 158 val = ath11k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET); 159 160 val |= PCIE_SOC_GLOBAL_RESET_V; 161 162 ath11k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 163 164 /* TODO: exact time to sleep is uncertain */ 165 delay = 10; 166 mdelay(delay); 167 168 /* Need to toggle V bit back otherwise stuck in reset status */ 169 val &= ~PCIE_SOC_GLOBAL_RESET_V; 170 171 ath11k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 172 173 mdelay(delay); 174 175 val = ath11k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET); 176 if (val == 0xffffffff) 177 ath11k_warn(ab, "link down error during global reset\n"); 178 } 179 180 static void ath11k_pci_clear_dbg_registers(struct ath11k_base *ab) 181 { 182 u32 val; 183 184 /* read cookie */ 185 val = ath11k_pci_read32(ab, PCIE_Q6_COOKIE_ADDR); 186 ath11k_dbg(ab, ATH11K_DBG_PCI, "cookie:0x%x\n", val); 187 188 val = ath11k_pci_read32(ab, WLAON_WARM_SW_ENTRY); 189 ath11k_dbg(ab, ATH11K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val); 190 191 /* TODO: exact time to sleep is uncertain */ 192 mdelay(10); 193 194 /* write 0 to WLAON_WARM_SW_ENTRY to prevent Q6 from 195 * continuing warm path and entering dead loop. 196 */ 197 ath11k_pci_write32(ab, WLAON_WARM_SW_ENTRY, 0); 198 mdelay(10); 199 200 val = ath11k_pci_read32(ab, WLAON_WARM_SW_ENTRY); 201 ath11k_dbg(ab, ATH11K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val); 202 203 /* A read clear register. clear the register to prevent 204 * Q6 from entering wrong code path. 205 */ 206 val = ath11k_pci_read32(ab, WLAON_SOC_RESET_CAUSE_REG); 207 ath11k_dbg(ab, ATH11K_DBG_PCI, "soc reset cause:%d\n", val); 208 } 209 210 static void ath11k_pci_force_wake(struct ath11k_base *ab) 211 { 212 ath11k_pci_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1); 213 mdelay(5); 214 } 215 216 static void ath11k_pci_sw_reset(struct ath11k_base *ab) 217 { 218 ath11k_pci_soc_global_reset(ab); 219 ath11k_mhi_clear_vector(ab); 220 ath11k_pci_soc_global_reset(ab); 221 ath11k_mhi_set_mhictrl_reset(ab); 222 ath11k_pci_clear_dbg_registers(ab); 223 } 224 225 int ath11k_pci_get_msi_irq(struct device *dev, unsigned int vector) 226 { 227 struct pci_dev *pci_dev = to_pci_dev(dev); 228 229 return pci_irq_vector(pci_dev, vector); 230 } 231 232 static void ath11k_pci_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo, 233 u32 *msi_addr_hi) 234 { 235 struct pci_dev *pci_dev = to_pci_dev(ab->dev); 236 237 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO, 238 msi_addr_lo); 239 240 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI, 241 msi_addr_hi); 242 } 243 244 int ath11k_pci_get_user_msi_assignment(struct ath11k_pci *ab_pci, char *user_name, 245 int *num_vectors, u32 *user_base_data, 246 u32 *base_vector) 247 { 248 struct ath11k_base *ab = ab_pci->ab; 249 int idx; 250 251 for (idx = 0; idx < msi_config.total_users; idx++) { 252 if (strcmp(user_name, msi_config.users[idx].name) == 0) { 253 *num_vectors = msi_config.users[idx].num_vectors; 254 *user_base_data = msi_config.users[idx].base_vector 255 + ab_pci->msi_ep_base_data; 256 *base_vector = msi_config.users[idx].base_vector; 257 258 ath11k_dbg(ab, ATH11K_DBG_PCI, "Assign MSI to user: %s, num_vectors: %d, user_base_data: %u, base_vector: %u\n", 259 user_name, *num_vectors, *user_base_data, 260 *base_vector); 261 262 return 0; 263 } 264 } 265 266 ath11k_err(ab, "Failed to find MSI assignment for %s!\n", user_name); 267 268 return -EINVAL; 269 } 270 271 static int ath11k_get_user_msi_assignment(struct ath11k_base *ab, char *user_name, 272 int *num_vectors, u32 *user_base_data, 273 u32 *base_vector) 274 { 275 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 276 277 return ath11k_pci_get_user_msi_assignment(ab_pci, user_name, 278 num_vectors, user_base_data, 279 base_vector); 280 } 281 282 static void ath11k_pci_free_ext_irq(struct ath11k_base *ab) 283 { 284 int i, j; 285 286 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 287 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 288 289 for (j = 0; j < irq_grp->num_irq; j++) 290 free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp); 291 292 netif_napi_del(&irq_grp->napi); 293 } 294 } 295 296 static void ath11k_pci_free_irq(struct ath11k_base *ab) 297 { 298 int i, irq_idx; 299 300 for (i = 0; i < ab->hw_params.ce_count; i++) { 301 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 302 continue; 303 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i; 304 free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]); 305 } 306 307 ath11k_pci_free_ext_irq(ab); 308 } 309 310 static void ath11k_pci_ce_irq_enable(struct ath11k_base *ab, u16 ce_id) 311 { 312 u32 irq_idx; 313 314 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_id; 315 enable_irq(ab->irq_num[irq_idx]); 316 } 317 318 static void ath11k_pci_ce_irq_disable(struct ath11k_base *ab, u16 ce_id) 319 { 320 u32 irq_idx; 321 322 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_id; 323 disable_irq_nosync(ab->irq_num[irq_idx]); 324 } 325 326 static void ath11k_pci_ce_irqs_disable(struct ath11k_base *ab) 327 { 328 int i; 329 330 for (i = 0; i < ab->hw_params.ce_count; i++) { 331 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 332 continue; 333 ath11k_pci_ce_irq_disable(ab, i); 334 } 335 } 336 337 static void ath11k_pci_sync_ce_irqs(struct ath11k_base *ab) 338 { 339 int i; 340 int irq_idx; 341 342 for (i = 0; i < ab->hw_params.ce_count; i++) { 343 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 344 continue; 345 346 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i; 347 synchronize_irq(ab->irq_num[irq_idx]); 348 } 349 } 350 351 static void ath11k_pci_ce_tasklet(unsigned long data) 352 { 353 struct ath11k_ce_pipe *ce_pipe = (struct ath11k_ce_pipe *)data; 354 355 ath11k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num); 356 357 ath11k_pci_ce_irq_enable(ce_pipe->ab, ce_pipe->pipe_num); 358 } 359 360 static irqreturn_t ath11k_pci_ce_interrupt_handler(int irq, void *arg) 361 { 362 struct ath11k_ce_pipe *ce_pipe = arg; 363 364 ath11k_pci_ce_irq_disable(ce_pipe->ab, ce_pipe->pipe_num); 365 tasklet_schedule(&ce_pipe->intr_tq); 366 367 return IRQ_HANDLED; 368 } 369 370 static void ath11k_pci_ext_grp_disable(struct ath11k_ext_irq_grp *irq_grp) 371 { 372 int i; 373 374 for (i = 0; i < irq_grp->num_irq; i++) 375 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 376 } 377 378 static void __ath11k_pci_ext_irq_disable(struct ath11k_base *sc) 379 { 380 int i; 381 382 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 383 struct ath11k_ext_irq_grp *irq_grp = &sc->ext_irq_grp[i]; 384 385 ath11k_pci_ext_grp_disable(irq_grp); 386 387 napi_synchronize(&irq_grp->napi); 388 napi_disable(&irq_grp->napi); 389 } 390 } 391 392 static void ath11k_pci_ext_grp_enable(struct ath11k_ext_irq_grp *irq_grp) 393 { 394 int i; 395 396 for (i = 0; i < irq_grp->num_irq; i++) 397 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 398 } 399 400 static void ath11k_pci_ext_irq_enable(struct ath11k_base *ab) 401 { 402 int i; 403 404 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 405 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 406 407 napi_enable(&irq_grp->napi); 408 ath11k_pci_ext_grp_enable(irq_grp); 409 } 410 } 411 412 static void ath11k_pci_sync_ext_irqs(struct ath11k_base *ab) 413 { 414 int i, j, irq_idx; 415 416 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 417 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 418 419 for (j = 0; j < irq_grp->num_irq; j++) { 420 irq_idx = irq_grp->irqs[j]; 421 synchronize_irq(ab->irq_num[irq_idx]); 422 } 423 } 424 } 425 426 static void ath11k_pci_ext_irq_disable(struct ath11k_base *ab) 427 { 428 __ath11k_pci_ext_irq_disable(ab); 429 ath11k_pci_sync_ext_irqs(ab); 430 } 431 432 static int ath11k_pci_ext_grp_napi_poll(struct napi_struct *napi, int budget) 433 { 434 struct ath11k_ext_irq_grp *irq_grp = container_of(napi, 435 struct ath11k_ext_irq_grp, 436 napi); 437 struct ath11k_base *ab = irq_grp->ab; 438 int work_done; 439 440 work_done = ath11k_dp_service_srng(ab, irq_grp, budget); 441 if (work_done < budget) { 442 napi_complete_done(napi, work_done); 443 ath11k_pci_ext_grp_enable(irq_grp); 444 } 445 446 if (work_done > budget) 447 work_done = budget; 448 449 return work_done; 450 } 451 452 static irqreturn_t ath11k_pci_ext_interrupt_handler(int irq, void *arg) 453 { 454 struct ath11k_ext_irq_grp *irq_grp = arg; 455 456 ath11k_dbg(irq_grp->ab, ATH11K_DBG_PCI, "ext irq:%d\n", irq); 457 458 ath11k_pci_ext_grp_disable(irq_grp); 459 460 napi_schedule(&irq_grp->napi); 461 462 return IRQ_HANDLED; 463 } 464 465 static int ath11k_pci_ext_irq_config(struct ath11k_base *ab) 466 { 467 int i, j, ret, num_vectors = 0; 468 u32 user_base_data = 0, base_vector = 0; 469 470 ret = ath11k_pci_get_user_msi_assignment(ath11k_pci_priv(ab), "DP", 471 &num_vectors, 472 &user_base_data, 473 &base_vector); 474 if (ret < 0) 475 return ret; 476 477 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 478 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 479 u32 num_irq = 0; 480 481 irq_grp->ab = ab; 482 irq_grp->grp_id = i; 483 init_dummy_netdev(&irq_grp->napi_ndev); 484 netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi, 485 ath11k_pci_ext_grp_napi_poll, NAPI_POLL_WEIGHT); 486 487 if (ab->hw_params.ring_mask->tx[i] || 488 ab->hw_params.ring_mask->rx[i] || 489 ab->hw_params.ring_mask->rx_err[i] || 490 ab->hw_params.ring_mask->rx_wbm_rel[i] || 491 ab->hw_params.ring_mask->reo_status[i] || 492 ab->hw_params.ring_mask->rxdma2host[i] || 493 ab->hw_params.ring_mask->host2rxdma[i] || 494 ab->hw_params.ring_mask->rx_mon_status[i]) { 495 num_irq = 1; 496 } 497 498 irq_grp->num_irq = num_irq; 499 irq_grp->irqs[0] = base_vector + i; 500 501 for (j = 0; j < irq_grp->num_irq; j++) { 502 int irq_idx = irq_grp->irqs[j]; 503 int vector = (i % num_vectors) + base_vector; 504 int irq = ath11k_pci_get_msi_irq(ab->dev, vector); 505 506 ab->irq_num[irq_idx] = irq; 507 508 ath11k_dbg(ab, ATH11K_DBG_PCI, 509 "irq:%d group:%d\n", irq, i); 510 ret = request_irq(irq, ath11k_pci_ext_interrupt_handler, 511 IRQF_SHARED, 512 "DP_EXT_IRQ", irq_grp); 513 if (ret) { 514 ath11k_err(ab, "failed request irq %d: %d\n", 515 vector, ret); 516 return ret; 517 } 518 519 disable_irq_nosync(ab->irq_num[irq_idx]); 520 } 521 } 522 523 return 0; 524 } 525 526 static int ath11k_pci_config_irq(struct ath11k_base *ab) 527 { 528 struct ath11k_ce_pipe *ce_pipe; 529 u32 msi_data_start; 530 u32 msi_data_count; 531 u32 msi_irq_start; 532 unsigned int msi_data; 533 int irq, i, ret, irq_idx; 534 535 ret = ath11k_pci_get_user_msi_assignment(ath11k_pci_priv(ab), 536 "CE", &msi_data_count, 537 &msi_data_start, &msi_irq_start); 538 if (ret) 539 return ret; 540 541 /* Configure CE irqs */ 542 for (i = 0; i < ab->hw_params.ce_count; i++) { 543 msi_data = (i % msi_data_count) + msi_irq_start; 544 irq = ath11k_pci_get_msi_irq(ab->dev, msi_data); 545 ce_pipe = &ab->ce.ce_pipe[i]; 546 547 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 548 continue; 549 550 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i; 551 552 tasklet_init(&ce_pipe->intr_tq, ath11k_pci_ce_tasklet, 553 (unsigned long)ce_pipe); 554 555 ret = request_irq(irq, ath11k_pci_ce_interrupt_handler, 556 IRQF_SHARED, irq_name[irq_idx], 557 ce_pipe); 558 if (ret) { 559 ath11k_err(ab, "failed to request irq %d: %d\n", 560 irq_idx, ret); 561 return ret; 562 } 563 564 ab->irq_num[irq_idx] = irq; 565 ath11k_pci_ce_irq_disable(ab, i); 566 } 567 568 ret = ath11k_pci_ext_irq_config(ab); 569 if (ret) 570 return ret; 571 572 return 0; 573 } 574 575 static void ath11k_pci_init_qmi_ce_config(struct ath11k_base *ab) 576 { 577 struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg; 578 579 cfg->tgt_ce = ab->hw_params.target_ce_config; 580 cfg->tgt_ce_len = ab->hw_params.target_ce_count; 581 582 cfg->svc_to_ce_map = ab->hw_params.svc_to_ce_map; 583 cfg->svc_to_ce_map_len = ab->hw_params.svc_to_ce_map_len; 584 ab->qmi.service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390; 585 } 586 587 static void ath11k_pci_ce_irqs_enable(struct ath11k_base *ab) 588 { 589 int i; 590 591 for (i = 0; i < ab->hw_params.ce_count; i++) { 592 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 593 continue; 594 ath11k_pci_ce_irq_enable(ab, i); 595 } 596 } 597 598 static int ath11k_pci_enable_msi(struct ath11k_pci *ab_pci) 599 { 600 struct ath11k_base *ab = ab_pci->ab; 601 struct msi_desc *msi_desc; 602 int num_vectors; 603 int ret; 604 605 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev, 606 msi_config.total_vectors, 607 msi_config.total_vectors, 608 PCI_IRQ_MSI); 609 if (num_vectors != msi_config.total_vectors) { 610 ath11k_err(ab, "failed to get %d MSI vectors, only %d available", 611 msi_config.total_vectors, num_vectors); 612 613 if (num_vectors >= 0) 614 return -EINVAL; 615 else 616 return num_vectors; 617 } 618 619 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq); 620 if (!msi_desc) { 621 ath11k_err(ab, "msi_desc is NULL!\n"); 622 ret = -EINVAL; 623 goto free_msi_vector; 624 } 625 626 ab_pci->msi_ep_base_data = msi_desc->msg.data; 627 628 ath11k_dbg(ab, ATH11K_DBG_PCI, "msi base data is %d\n", ab_pci->msi_ep_base_data); 629 630 return 0; 631 632 free_msi_vector: 633 pci_free_irq_vectors(ab_pci->pdev); 634 635 return ret; 636 } 637 638 static void ath11k_pci_disable_msi(struct ath11k_pci *ab_pci) 639 { 640 pci_free_irq_vectors(ab_pci->pdev); 641 } 642 643 static int ath11k_pci_claim(struct ath11k_pci *ab_pci, struct pci_dev *pdev) 644 { 645 struct ath11k_base *ab = ab_pci->ab; 646 u16 device_id; 647 int ret = 0; 648 649 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id); 650 if (device_id != ab_pci->dev_id) { 651 ath11k_err(ab, "pci device id mismatch: 0x%x 0x%x\n", 652 device_id, ab_pci->dev_id); 653 ret = -EIO; 654 goto out; 655 } 656 657 ret = pci_assign_resource(pdev, ATH11K_PCI_BAR_NUM); 658 if (ret) { 659 ath11k_err(ab, "failed to assign pci resource: %d\n", ret); 660 goto out; 661 } 662 663 ret = pci_enable_device(pdev); 664 if (ret) { 665 ath11k_err(ab, "failed to enable pci device: %d\n", ret); 666 goto out; 667 } 668 669 ret = pci_request_region(pdev, ATH11K_PCI_BAR_NUM, "ath11k_pci"); 670 if (ret) { 671 ath11k_err(ab, "failed to request pci region: %d\n", ret); 672 goto disable_device; 673 } 674 675 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(ATH11K_PCI_DMA_MASK)); 676 if (ret) { 677 ath11k_err(ab, "failed to set pci dma mask to %d: %d\n", 678 ATH11K_PCI_DMA_MASK, ret); 679 goto release_region; 680 } 681 682 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(ATH11K_PCI_DMA_MASK)); 683 if (ret) { 684 ath11k_err(ab, "failed to set pci consistent dma mask to %d: %d\n", 685 ATH11K_PCI_DMA_MASK, ret); 686 goto release_region; 687 } 688 689 pci_set_master(pdev); 690 691 ab->mem_len = pci_resource_len(pdev, ATH11K_PCI_BAR_NUM); 692 ab->mem = pci_iomap(pdev, ATH11K_PCI_BAR_NUM, 0); 693 if (!ab->mem) { 694 ath11k_err(ab, "failed to map pci bar %d\n", ATH11K_PCI_BAR_NUM); 695 ret = -EIO; 696 goto clear_master; 697 } 698 699 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot pci_mem 0x%pK\n", ab->mem); 700 return 0; 701 702 clear_master: 703 pci_clear_master(pdev); 704 release_region: 705 pci_release_region(pdev, ATH11K_PCI_BAR_NUM); 706 disable_device: 707 pci_disable_device(pdev); 708 out: 709 return ret; 710 } 711 712 static void ath11k_pci_free_region(struct ath11k_pci *ab_pci) 713 { 714 struct ath11k_base *ab = ab_pci->ab; 715 struct pci_dev *pci_dev = ab_pci->pdev; 716 717 pci_iounmap(pci_dev, ab->mem); 718 ab->mem = NULL; 719 pci_clear_master(pci_dev); 720 pci_release_region(pci_dev, ATH11K_PCI_BAR_NUM); 721 if (pci_is_enabled(pci_dev)) 722 pci_disable_device(pci_dev); 723 } 724 725 static int ath11k_pci_power_up(struct ath11k_base *ab) 726 { 727 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 728 int ret; 729 730 ath11k_pci_sw_reset(ab_pci->ab); 731 732 ret = ath11k_mhi_start(ab_pci); 733 if (ret) { 734 ath11k_err(ab, "failed to start mhi: %d\n", ret); 735 return ret; 736 } 737 738 return 0; 739 } 740 741 static void ath11k_pci_power_down(struct ath11k_base *ab) 742 { 743 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 744 745 ath11k_mhi_stop(ab_pci); 746 ath11k_pci_force_wake(ab_pci->ab); 747 ath11k_pci_sw_reset(ab_pci->ab); 748 } 749 750 static void ath11k_pci_kill_tasklets(struct ath11k_base *ab) 751 { 752 int i; 753 754 for (i = 0; i < ab->hw_params.ce_count; i++) { 755 struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i]; 756 757 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 758 continue; 759 760 tasklet_kill(&ce_pipe->intr_tq); 761 } 762 } 763 764 static void ath11k_pci_stop(struct ath11k_base *ab) 765 { 766 ath11k_pci_ce_irqs_disable(ab); 767 ath11k_pci_sync_ce_irqs(ab); 768 ath11k_pci_kill_tasklets(ab); 769 ath11k_ce_cleanup_pipes(ab); 770 } 771 772 static int ath11k_pci_start(struct ath11k_base *ab) 773 { 774 ath11k_pci_ce_irqs_enable(ab); 775 ath11k_ce_rx_post_buf(ab); 776 777 return 0; 778 } 779 780 static int ath11k_pci_map_service_to_pipe(struct ath11k_base *ab, u16 service_id, 781 u8 *ul_pipe, u8 *dl_pipe) 782 { 783 const struct service_to_pipe *entry; 784 bool ul_set = false, dl_set = false; 785 int i; 786 787 for (i = 0; i < ab->hw_params.svc_to_ce_map_len; i++) { 788 entry = &ab->hw_params.svc_to_ce_map[i]; 789 790 if (__le32_to_cpu(entry->service_id) != service_id) 791 continue; 792 793 switch (__le32_to_cpu(entry->pipedir)) { 794 case PIPEDIR_NONE: 795 break; 796 case PIPEDIR_IN: 797 WARN_ON(dl_set); 798 *dl_pipe = __le32_to_cpu(entry->pipenum); 799 dl_set = true; 800 break; 801 case PIPEDIR_OUT: 802 WARN_ON(ul_set); 803 *ul_pipe = __le32_to_cpu(entry->pipenum); 804 ul_set = true; 805 break; 806 case PIPEDIR_INOUT: 807 WARN_ON(dl_set); 808 WARN_ON(ul_set); 809 *dl_pipe = __le32_to_cpu(entry->pipenum); 810 *ul_pipe = __le32_to_cpu(entry->pipenum); 811 dl_set = true; 812 ul_set = true; 813 break; 814 } 815 } 816 817 if (WARN_ON(!ul_set || !dl_set)) 818 return -ENOENT; 819 820 return 0; 821 } 822 823 static const struct ath11k_hif_ops ath11k_pci_hif_ops = { 824 .start = ath11k_pci_start, 825 .stop = ath11k_pci_stop, 826 .read32 = ath11k_pci_read32, 827 .write32 = ath11k_pci_write32, 828 .power_down = ath11k_pci_power_down, 829 .power_up = ath11k_pci_power_up, 830 .irq_enable = ath11k_pci_ext_irq_enable, 831 .irq_disable = ath11k_pci_ext_irq_disable, 832 .get_msi_address = ath11k_pci_get_msi_address, 833 .get_user_msi_vector = ath11k_get_user_msi_assignment, 834 .map_service_to_pipe = ath11k_pci_map_service_to_pipe, 835 }; 836 837 static int ath11k_pci_probe(struct pci_dev *pdev, 838 const struct pci_device_id *pci_dev) 839 { 840 struct ath11k_base *ab; 841 struct ath11k_pci *ab_pci; 842 enum ath11k_hw_rev hw_rev; 843 int ret; 844 845 dev_warn(&pdev->dev, "WARNING: ath11k PCI support is experimental!\n"); 846 847 switch (pci_dev->device) { 848 case QCA6390_DEVICE_ID: 849 hw_rev = ATH11K_HW_QCA6390_HW20; 850 break; 851 default: 852 dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n", 853 pci_dev->device); 854 return -ENOTSUPP; 855 } 856 857 ab = ath11k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH11K_BUS_PCI, 858 &ath11k_pci_bus_params); 859 if (!ab) { 860 dev_err(&pdev->dev, "failed to allocate ath11k base\n"); 861 return -ENOMEM; 862 } 863 864 ab->dev = &pdev->dev; 865 ab->hw_rev = hw_rev; 866 pci_set_drvdata(pdev, ab); 867 ab_pci = ath11k_pci_priv(ab); 868 ab_pci->dev_id = pci_dev->device; 869 ab_pci->ab = ab; 870 ab_pci->pdev = pdev; 871 ab->hif.ops = &ath11k_pci_hif_ops; 872 pci_set_drvdata(pdev, ab); 873 spin_lock_init(&ab_pci->window_lock); 874 875 ret = ath11k_pci_claim(ab_pci, pdev); 876 if (ret) { 877 ath11k_err(ab, "failed to claim device: %d\n", ret); 878 goto err_free_core; 879 } 880 881 ret = ath11k_pci_enable_msi(ab_pci); 882 if (ret) { 883 ath11k_err(ab, "failed to enable msi: %d\n", ret); 884 goto err_pci_free_region; 885 } 886 887 ret = ath11k_core_pre_init(ab); 888 if (ret) 889 goto err_pci_disable_msi; 890 891 ret = ath11k_mhi_register(ab_pci); 892 if (ret) { 893 ath11k_err(ab, "failed to register mhi: %d\n", ret); 894 goto err_pci_disable_msi; 895 } 896 897 ret = ath11k_hal_srng_init(ab); 898 if (ret) 899 goto err_mhi_unregister; 900 901 ret = ath11k_ce_alloc_pipes(ab); 902 if (ret) { 903 ath11k_err(ab, "failed to allocate ce pipes: %d\n", ret); 904 goto err_hal_srng_deinit; 905 } 906 907 ath11k_pci_init_qmi_ce_config(ab); 908 909 ret = ath11k_pci_config_irq(ab); 910 if (ret) { 911 ath11k_err(ab, "failed to config irq: %d\n", ret); 912 goto err_ce_free; 913 } 914 915 ret = ath11k_core_init(ab); 916 if (ret) { 917 ath11k_err(ab, "failed to init core: %d\n", ret); 918 goto err_free_irq; 919 } 920 return 0; 921 922 err_free_irq: 923 ath11k_pci_free_irq(ab); 924 925 err_ce_free: 926 ath11k_ce_free_pipes(ab); 927 928 err_hal_srng_deinit: 929 ath11k_hal_srng_deinit(ab); 930 931 err_mhi_unregister: 932 ath11k_mhi_unregister(ab_pci); 933 934 err_pci_disable_msi: 935 ath11k_pci_disable_msi(ab_pci); 936 937 err_pci_free_region: 938 ath11k_pci_free_region(ab_pci); 939 940 err_free_core: 941 ath11k_core_free(ab); 942 943 return ret; 944 } 945 946 static void ath11k_pci_remove(struct pci_dev *pdev) 947 { 948 struct ath11k_base *ab = pci_get_drvdata(pdev); 949 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 950 951 set_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags); 952 ath11k_mhi_unregister(ab_pci); 953 ath11k_pci_disable_msi(ab_pci); 954 ath11k_pci_free_region(ab_pci); 955 ath11k_pci_free_irq(ab); 956 ath11k_core_free(ab); 957 } 958 959 static void ath11k_pci_shutdown(struct pci_dev *pdev) 960 { 961 struct ath11k_base *ab = pci_get_drvdata(pdev); 962 963 ath11k_pci_power_down(ab); 964 } 965 966 static struct pci_driver ath11k_pci_driver = { 967 .name = "ath11k_pci", 968 .id_table = ath11k_pci_id_table, 969 .probe = ath11k_pci_probe, 970 .remove = ath11k_pci_remove, 971 .shutdown = ath11k_pci_shutdown, 972 }; 973 974 static int ath11k_pci_init(void) 975 { 976 int ret; 977 978 ret = pci_register_driver(&ath11k_pci_driver); 979 if (ret) 980 pr_err("failed to register ath11k pci driver: %d\n", 981 ret); 982 983 return ret; 984 } 985 module_init(ath11k_pci_init); 986 987 static void ath11k_pci_exit(void) 988 { 989 pci_unregister_driver(&ath11k_pci_driver); 990 } 991 992 module_exit(ath11k_pci_exit); 993 994 MODULE_DESCRIPTION("Driver support for Qualcomm Technologies 802.11ax WLAN PCIe devices"); 995 MODULE_LICENSE("Dual BSD/GPL"); 996