1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/module.h> 8 #include <linux/msi.h> 9 #include <linux/pci.h> 10 #include <linux/of.h> 11 12 #include "pci.h" 13 #include "core.h" 14 #include "hif.h" 15 #include "mhi.h" 16 #include "debug.h" 17 #include "pcic.h" 18 19 #define ATH11K_PCI_BAR_NUM 0 20 #define ATH11K_PCI_DMA_MASK 32 21 22 #define TCSR_SOC_HW_VERSION 0x0224 23 #define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(11, 8) 24 #define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 0) 25 26 #define QCA6390_DEVICE_ID 0x1101 27 #define QCN9074_DEVICE_ID 0x1104 28 #define WCN6855_DEVICE_ID 0x1103 29 30 static const struct pci_device_id ath11k_pci_id_table[] = { 31 { PCI_VDEVICE(QCOM, QCA6390_DEVICE_ID) }, 32 { PCI_VDEVICE(QCOM, WCN6855_DEVICE_ID) }, 33 { PCI_VDEVICE(QCOM, QCN9074_DEVICE_ID) }, 34 {0} 35 }; 36 37 MODULE_DEVICE_TABLE(pci, ath11k_pci_id_table); 38 39 static int ath11k_pci_bus_wake_up(struct ath11k_base *ab) 40 { 41 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 42 43 return mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev); 44 } 45 46 static void ath11k_pci_bus_release(struct ath11k_base *ab) 47 { 48 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 49 50 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev); 51 } 52 53 static u32 ath11k_pci_get_window_start(struct ath11k_base *ab, u32 offset) 54 { 55 if (!ab->hw_params.static_window_map) 56 return ATH11K_PCI_WINDOW_START; 57 58 if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < ATH11K_PCI_WINDOW_RANGE_MASK) 59 /* if offset lies within DP register range, use 3rd window */ 60 return 3 * ATH11K_PCI_WINDOW_START; 61 else if ((offset ^ HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(ab)) < 62 ATH11K_PCI_WINDOW_RANGE_MASK) 63 /* if offset lies within CE register range, use 2nd window */ 64 return 2 * ATH11K_PCI_WINDOW_START; 65 else 66 return ATH11K_PCI_WINDOW_START; 67 } 68 69 static inline void ath11k_pci_select_window(struct ath11k_pci *ab_pci, u32 offset) 70 { 71 struct ath11k_base *ab = ab_pci->ab; 72 73 u32 window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, offset); 74 75 lockdep_assert_held(&ab_pci->window_lock); 76 77 if (window != ab_pci->register_window) { 78 iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window, 79 ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS); 80 ioread32(ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS); 81 ab_pci->register_window = window; 82 } 83 } 84 85 static void 86 ath11k_pci_window_write32(struct ath11k_base *ab, u32 offset, u32 value) 87 { 88 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 89 u32 window_start; 90 91 window_start = ath11k_pci_get_window_start(ab, offset); 92 93 if (window_start == ATH11K_PCI_WINDOW_START) { 94 spin_lock_bh(&ab_pci->window_lock); 95 ath11k_pci_select_window(ab_pci, offset); 96 iowrite32(value, ab->mem + window_start + 97 (offset & ATH11K_PCI_WINDOW_RANGE_MASK)); 98 spin_unlock_bh(&ab_pci->window_lock); 99 } else { 100 iowrite32(value, ab->mem + window_start + 101 (offset & ATH11K_PCI_WINDOW_RANGE_MASK)); 102 } 103 } 104 105 static u32 ath11k_pci_window_read32(struct ath11k_base *ab, u32 offset) 106 { 107 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 108 u32 window_start, val; 109 110 window_start = ath11k_pci_get_window_start(ab, offset); 111 112 if (window_start == ATH11K_PCI_WINDOW_START) { 113 spin_lock_bh(&ab_pci->window_lock); 114 ath11k_pci_select_window(ab_pci, offset); 115 val = ioread32(ab->mem + window_start + 116 (offset & ATH11K_PCI_WINDOW_RANGE_MASK)); 117 spin_unlock_bh(&ab_pci->window_lock); 118 } else { 119 val = ioread32(ab->mem + window_start + 120 (offset & ATH11K_PCI_WINDOW_RANGE_MASK)); 121 } 122 123 return val; 124 } 125 126 int ath11k_pci_get_msi_irq(struct ath11k_base *ab, unsigned int vector) 127 { 128 struct pci_dev *pci_dev = to_pci_dev(ab->dev); 129 130 return pci_irq_vector(pci_dev, vector); 131 } 132 133 static const struct ath11k_pci_ops ath11k_pci_ops_qca6390 = { 134 .wakeup = ath11k_pci_bus_wake_up, 135 .release = ath11k_pci_bus_release, 136 .get_msi_irq = ath11k_pci_get_msi_irq, 137 .window_write32 = ath11k_pci_window_write32, 138 .window_read32 = ath11k_pci_window_read32, 139 }; 140 141 static const struct ath11k_pci_ops ath11k_pci_ops_qcn9074 = { 142 .wakeup = NULL, 143 .release = NULL, 144 .get_msi_irq = ath11k_pci_get_msi_irq, 145 .window_write32 = ath11k_pci_window_write32, 146 .window_read32 = ath11k_pci_window_read32, 147 }; 148 149 static const struct ath11k_msi_config msi_config_one_msi = { 150 .total_vectors = 1, 151 .total_users = 4, 152 .users = (struct ath11k_msi_user[]) { 153 { .name = "MHI", .num_vectors = 3, .base_vector = 0 }, 154 { .name = "CE", .num_vectors = 1, .base_vector = 0 }, 155 { .name = "WAKE", .num_vectors = 1, .base_vector = 0 }, 156 { .name = "DP", .num_vectors = 1, .base_vector = 0 }, 157 }, 158 }; 159 160 static inline void ath11k_pci_select_static_window(struct ath11k_pci *ab_pci) 161 { 162 u32 umac_window; 163 u32 ce_window; 164 u32 window; 165 166 umac_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_SEQ_WCSS_UMAC_OFFSET); 167 ce_window = FIELD_GET(ATH11K_PCI_WINDOW_VALUE_MASK, HAL_CE_WFSS_CE_REG_BASE); 168 window = (umac_window << 12) | (ce_window << 6); 169 170 iowrite32(ATH11K_PCI_WINDOW_ENABLE_BIT | window, 171 ab_pci->ab->mem + ATH11K_PCI_WINDOW_REG_ADDRESS); 172 } 173 174 static void ath11k_pci_soc_global_reset(struct ath11k_base *ab) 175 { 176 u32 val, delay; 177 178 val = ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET); 179 180 val |= PCIE_SOC_GLOBAL_RESET_V; 181 182 ath11k_pcic_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 183 184 /* TODO: exact time to sleep is uncertain */ 185 delay = 10; 186 mdelay(delay); 187 188 /* Need to toggle V bit back otherwise stuck in reset status */ 189 val &= ~PCIE_SOC_GLOBAL_RESET_V; 190 191 ath11k_pcic_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 192 193 mdelay(delay); 194 195 val = ath11k_pcic_read32(ab, PCIE_SOC_GLOBAL_RESET); 196 if (val == 0xffffffff) 197 ath11k_warn(ab, "link down error during global reset\n"); 198 } 199 200 static void ath11k_pci_clear_dbg_registers(struct ath11k_base *ab) 201 { 202 u32 val; 203 204 /* read cookie */ 205 val = ath11k_pcic_read32(ab, PCIE_Q6_COOKIE_ADDR); 206 ath11k_dbg(ab, ATH11K_DBG_PCI, "cookie:0x%x\n", val); 207 208 val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY); 209 ath11k_dbg(ab, ATH11K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val); 210 211 /* TODO: exact time to sleep is uncertain */ 212 mdelay(10); 213 214 /* write 0 to WLAON_WARM_SW_ENTRY to prevent Q6 from 215 * continuing warm path and entering dead loop. 216 */ 217 ath11k_pcic_write32(ab, WLAON_WARM_SW_ENTRY, 0); 218 mdelay(10); 219 220 val = ath11k_pcic_read32(ab, WLAON_WARM_SW_ENTRY); 221 ath11k_dbg(ab, ATH11K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val); 222 223 /* A read clear register. clear the register to prevent 224 * Q6 from entering wrong code path. 225 */ 226 val = ath11k_pcic_read32(ab, WLAON_SOC_RESET_CAUSE_REG); 227 ath11k_dbg(ab, ATH11K_DBG_PCI, "soc reset cause:%d\n", val); 228 } 229 230 static int ath11k_pci_set_link_reg(struct ath11k_base *ab, 231 u32 offset, u32 value, u32 mask) 232 { 233 u32 v; 234 int i; 235 236 v = ath11k_pcic_read32(ab, offset); 237 if ((v & mask) == value) 238 return 0; 239 240 for (i = 0; i < 10; i++) { 241 ath11k_pcic_write32(ab, offset, (v & ~mask) | value); 242 243 v = ath11k_pcic_read32(ab, offset); 244 if ((v & mask) == value) 245 return 0; 246 247 mdelay(2); 248 } 249 250 ath11k_warn(ab, "failed to set pcie link register 0x%08x: 0x%08x != 0x%08x\n", 251 offset, v & mask, value); 252 253 return -ETIMEDOUT; 254 } 255 256 static int ath11k_pci_fix_l1ss(struct ath11k_base *ab) 257 { 258 int ret; 259 260 ret = ath11k_pci_set_link_reg(ab, 261 PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(ab), 262 PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL, 263 PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK); 264 if (ret) { 265 ath11k_warn(ab, "failed to set sysclk: %d\n", ret); 266 return ret; 267 } 268 269 ret = ath11k_pci_set_link_reg(ab, 270 PCIE_PCS_OSC_DTCT_CONFIG1_REG(ab), 271 PCIE_PCS_OSC_DTCT_CONFIG1_VAL, 272 PCIE_PCS_OSC_DTCT_CONFIG_MSK); 273 if (ret) { 274 ath11k_warn(ab, "failed to set dtct config1 error: %d\n", ret); 275 return ret; 276 } 277 278 ret = ath11k_pci_set_link_reg(ab, 279 PCIE_PCS_OSC_DTCT_CONFIG2_REG(ab), 280 PCIE_PCS_OSC_DTCT_CONFIG2_VAL, 281 PCIE_PCS_OSC_DTCT_CONFIG_MSK); 282 if (ret) { 283 ath11k_warn(ab, "failed to set dtct config2: %d\n", ret); 284 return ret; 285 } 286 287 ret = ath11k_pci_set_link_reg(ab, 288 PCIE_PCS_OSC_DTCT_CONFIG4_REG(ab), 289 PCIE_PCS_OSC_DTCT_CONFIG4_VAL, 290 PCIE_PCS_OSC_DTCT_CONFIG_MSK); 291 if (ret) { 292 ath11k_warn(ab, "failed to set dtct config4: %d\n", ret); 293 return ret; 294 } 295 296 return 0; 297 } 298 299 static void ath11k_pci_enable_ltssm(struct ath11k_base *ab) 300 { 301 u32 val; 302 int i; 303 304 val = ath11k_pcic_read32(ab, PCIE_PCIE_PARF_LTSSM); 305 306 /* PCIE link seems very unstable after the Hot Reset*/ 307 for (i = 0; val != PARM_LTSSM_VALUE && i < 5; i++) { 308 if (val == 0xffffffff) 309 mdelay(5); 310 311 ath11k_pcic_write32(ab, PCIE_PCIE_PARF_LTSSM, PARM_LTSSM_VALUE); 312 val = ath11k_pcic_read32(ab, PCIE_PCIE_PARF_LTSSM); 313 } 314 315 ath11k_dbg(ab, ATH11K_DBG_PCI, "pci ltssm 0x%x\n", val); 316 317 val = ath11k_pcic_read32(ab, GCC_GCC_PCIE_HOT_RST); 318 val |= GCC_GCC_PCIE_HOT_RST_VAL; 319 ath11k_pcic_write32(ab, GCC_GCC_PCIE_HOT_RST, val); 320 val = ath11k_pcic_read32(ab, GCC_GCC_PCIE_HOT_RST); 321 322 ath11k_dbg(ab, ATH11K_DBG_PCI, "pci pcie_hot_rst 0x%x\n", val); 323 324 mdelay(5); 325 } 326 327 static void ath11k_pci_clear_all_intrs(struct ath11k_base *ab) 328 { 329 /* This is a WAR for PCIE Hotreset. 330 * When target receive Hotreset, but will set the interrupt. 331 * So when download SBL again, SBL will open Interrupt and 332 * receive it, and crash immediately. 333 */ 334 ath11k_pcic_write32(ab, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL); 335 } 336 337 static void ath11k_pci_set_wlaon_pwr_ctrl(struct ath11k_base *ab) 338 { 339 u32 val; 340 341 val = ath11k_pcic_read32(ab, WLAON_QFPROM_PWR_CTRL_REG); 342 val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK; 343 ath11k_pcic_write32(ab, WLAON_QFPROM_PWR_CTRL_REG, val); 344 } 345 346 static void ath11k_pci_force_wake(struct ath11k_base *ab) 347 { 348 ath11k_pcic_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1); 349 mdelay(5); 350 } 351 352 static void ath11k_pci_sw_reset(struct ath11k_base *ab, bool power_on) 353 { 354 mdelay(100); 355 356 if (power_on) { 357 ath11k_pci_enable_ltssm(ab); 358 ath11k_pci_clear_all_intrs(ab); 359 ath11k_pci_set_wlaon_pwr_ctrl(ab); 360 if (ab->hw_params.fix_l1ss) 361 ath11k_pci_fix_l1ss(ab); 362 } 363 364 ath11k_mhi_clear_vector(ab); 365 ath11k_pci_clear_dbg_registers(ab); 366 ath11k_pci_soc_global_reset(ab); 367 ath11k_mhi_set_mhictrl_reset(ab); 368 } 369 370 static void ath11k_pci_init_qmi_ce_config(struct ath11k_base *ab) 371 { 372 struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg; 373 374 cfg->tgt_ce = ab->hw_params.target_ce_config; 375 cfg->tgt_ce_len = ab->hw_params.target_ce_count; 376 377 cfg->svc_to_ce_map = ab->hw_params.svc_to_ce_map; 378 cfg->svc_to_ce_map_len = ab->hw_params.svc_to_ce_map_len; 379 ab->qmi.service_ins_id = ab->hw_params.qmi_service_ins_id; 380 381 ath11k_ce_get_shadow_config(ab, &cfg->shadow_reg_v2, 382 &cfg->shadow_reg_v2_len); 383 } 384 385 static void ath11k_pci_msi_config(struct ath11k_pci *ab_pci, bool enable) 386 { 387 struct pci_dev *dev = ab_pci->pdev; 388 u16 control; 389 390 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control); 391 392 if (enable) 393 control |= PCI_MSI_FLAGS_ENABLE; 394 else 395 control &= ~PCI_MSI_FLAGS_ENABLE; 396 397 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control); 398 } 399 400 static void ath11k_pci_msi_enable(struct ath11k_pci *ab_pci) 401 { 402 ath11k_pci_msi_config(ab_pci, true); 403 } 404 405 static void ath11k_pci_msi_disable(struct ath11k_pci *ab_pci) 406 { 407 ath11k_pci_msi_config(ab_pci, false); 408 } 409 410 static int ath11k_pci_alloc_msi(struct ath11k_pci *ab_pci) 411 { 412 struct ath11k_base *ab = ab_pci->ab; 413 const struct ath11k_msi_config *msi_config = ab->pci.msi.config; 414 struct pci_dev *pci_dev = ab_pci->pdev; 415 struct msi_desc *msi_desc; 416 int num_vectors; 417 int ret; 418 419 num_vectors = pci_alloc_irq_vectors(pci_dev, 420 msi_config->total_vectors, 421 msi_config->total_vectors, 422 PCI_IRQ_MSI); 423 if (num_vectors == msi_config->total_vectors) { 424 set_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags); 425 } else { 426 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev, 427 1, 428 1, 429 PCI_IRQ_MSI); 430 if (num_vectors < 0) { 431 ret = -EINVAL; 432 goto reset_msi_config; 433 } 434 clear_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags); 435 ab->pci.msi.config = &msi_config_one_msi; 436 ath11k_dbg(ab, ATH11K_DBG_PCI, "request MSI one vector\n"); 437 } 438 ath11k_info(ab, "MSI vectors: %d\n", num_vectors); 439 440 ath11k_pci_msi_disable(ab_pci); 441 442 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq); 443 if (!msi_desc) { 444 ath11k_err(ab, "msi_desc is NULL!\n"); 445 ret = -EINVAL; 446 goto free_msi_vector; 447 } 448 449 ab->pci.msi.ep_base_data = msi_desc->msg.data; 450 451 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO, 452 &ab->pci.msi.addr_lo); 453 454 if (msi_desc->pci.msi_attrib.is_64) { 455 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI, 456 &ab->pci.msi.addr_hi); 457 } else { 458 ab->pci.msi.addr_hi = 0; 459 } 460 461 ath11k_dbg(ab, ATH11K_DBG_PCI, "msi base data is %d\n", ab->pci.msi.ep_base_data); 462 463 return 0; 464 465 free_msi_vector: 466 pci_free_irq_vectors(ab_pci->pdev); 467 468 reset_msi_config: 469 return ret; 470 } 471 472 static void ath11k_pci_free_msi(struct ath11k_pci *ab_pci) 473 { 474 pci_free_irq_vectors(ab_pci->pdev); 475 } 476 477 static int ath11k_pci_config_msi_data(struct ath11k_pci *ab_pci) 478 { 479 struct msi_desc *msi_desc; 480 481 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq); 482 if (!msi_desc) { 483 ath11k_err(ab_pci->ab, "msi_desc is NULL!\n"); 484 pci_free_irq_vectors(ab_pci->pdev); 485 return -EINVAL; 486 } 487 488 ab_pci->ab->pci.msi.ep_base_data = msi_desc->msg.data; 489 490 ath11k_dbg(ab_pci->ab, ATH11K_DBG_PCI, "pci after request_irq msi_ep_base_data %d\n", 491 ab_pci->ab->pci.msi.ep_base_data); 492 493 return 0; 494 } 495 496 static int ath11k_pci_claim(struct ath11k_pci *ab_pci, struct pci_dev *pdev) 497 { 498 struct ath11k_base *ab = ab_pci->ab; 499 u16 device_id; 500 int ret = 0; 501 502 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id); 503 if (device_id != ab_pci->dev_id) { 504 ath11k_err(ab, "pci device id mismatch: 0x%x 0x%x\n", 505 device_id, ab_pci->dev_id); 506 ret = -EIO; 507 goto out; 508 } 509 510 ret = pci_assign_resource(pdev, ATH11K_PCI_BAR_NUM); 511 if (ret) { 512 ath11k_err(ab, "failed to assign pci resource: %d\n", ret); 513 goto out; 514 } 515 516 ret = pci_enable_device(pdev); 517 if (ret) { 518 ath11k_err(ab, "failed to enable pci device: %d\n", ret); 519 goto out; 520 } 521 522 ret = pci_request_region(pdev, ATH11K_PCI_BAR_NUM, "ath11k_pci"); 523 if (ret) { 524 ath11k_err(ab, "failed to request pci region: %d\n", ret); 525 goto disable_device; 526 } 527 528 ret = dma_set_mask_and_coherent(&pdev->dev, 529 DMA_BIT_MASK(ATH11K_PCI_DMA_MASK)); 530 if (ret) { 531 ath11k_err(ab, "failed to set pci dma mask to %d: %d\n", 532 ATH11K_PCI_DMA_MASK, ret); 533 goto release_region; 534 } 535 536 pci_set_master(pdev); 537 538 ab->mem_len = pci_resource_len(pdev, ATH11K_PCI_BAR_NUM); 539 ab->mem = pci_iomap(pdev, ATH11K_PCI_BAR_NUM, 0); 540 if (!ab->mem) { 541 ath11k_err(ab, "failed to map pci bar %d\n", ATH11K_PCI_BAR_NUM); 542 ret = -EIO; 543 goto clear_master; 544 } 545 546 ab->mem_ce = ab->mem; 547 548 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot pci_mem 0x%pK\n", ab->mem); 549 return 0; 550 551 clear_master: 552 pci_clear_master(pdev); 553 release_region: 554 pci_release_region(pdev, ATH11K_PCI_BAR_NUM); 555 disable_device: 556 pci_disable_device(pdev); 557 out: 558 return ret; 559 } 560 561 static void ath11k_pci_free_region(struct ath11k_pci *ab_pci) 562 { 563 struct ath11k_base *ab = ab_pci->ab; 564 struct pci_dev *pci_dev = ab_pci->pdev; 565 566 pci_iounmap(pci_dev, ab->mem); 567 ab->mem = NULL; 568 pci_clear_master(pci_dev); 569 pci_release_region(pci_dev, ATH11K_PCI_BAR_NUM); 570 if (pci_is_enabled(pci_dev)) 571 pci_disable_device(pci_dev); 572 } 573 574 static void ath11k_pci_aspm_disable(struct ath11k_pci *ab_pci) 575 { 576 struct ath11k_base *ab = ab_pci->ab; 577 578 pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL, 579 &ab_pci->link_ctl); 580 581 ath11k_dbg(ab, ATH11K_DBG_PCI, "pci link_ctl 0x%04x L0s %d L1 %d\n", 582 ab_pci->link_ctl, 583 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S), 584 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1)); 585 586 /* disable L0s and L1 */ 587 pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL, 588 ab_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC); 589 590 set_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags); 591 } 592 593 static void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci) 594 { 595 if (test_and_clear_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags)) 596 pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL, 597 ab_pci->link_ctl); 598 } 599 600 static int ath11k_pci_power_up(struct ath11k_base *ab) 601 { 602 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 603 int ret; 604 605 ab_pci->register_window = 0; 606 clear_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags); 607 ath11k_pci_sw_reset(ab_pci->ab, true); 608 609 /* Disable ASPM during firmware download due to problems switching 610 * to AMSS state. 611 */ 612 ath11k_pci_aspm_disable(ab_pci); 613 614 ath11k_pci_msi_enable(ab_pci); 615 616 ret = ath11k_mhi_start(ab_pci); 617 if (ret) { 618 ath11k_err(ab, "failed to start mhi: %d\n", ret); 619 return ret; 620 } 621 622 if (ab->hw_params.static_window_map) 623 ath11k_pci_select_static_window(ab_pci); 624 625 return 0; 626 } 627 628 static void ath11k_pci_power_down(struct ath11k_base *ab) 629 { 630 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 631 632 /* restore aspm in case firmware bootup fails */ 633 ath11k_pci_aspm_restore(ab_pci); 634 635 ath11k_pci_force_wake(ab_pci->ab); 636 637 ath11k_pci_msi_disable(ab_pci); 638 639 ath11k_mhi_stop(ab_pci); 640 clear_bit(ATH11K_FLAG_DEVICE_INIT_DONE, &ab->dev_flags); 641 ath11k_pci_sw_reset(ab_pci->ab, false); 642 } 643 644 static int ath11k_pci_hif_suspend(struct ath11k_base *ab) 645 { 646 struct ath11k_pci *ar_pci = ath11k_pci_priv(ab); 647 648 return ath11k_mhi_suspend(ar_pci); 649 } 650 651 static int ath11k_pci_hif_resume(struct ath11k_base *ab) 652 { 653 struct ath11k_pci *ar_pci = ath11k_pci_priv(ab); 654 655 return ath11k_mhi_resume(ar_pci); 656 } 657 658 static void ath11k_pci_hif_ce_irq_enable(struct ath11k_base *ab) 659 { 660 ath11k_pcic_ce_irqs_enable(ab); 661 } 662 663 static void ath11k_pci_hif_ce_irq_disable(struct ath11k_base *ab) 664 { 665 ath11k_pcic_ce_irq_disable_sync(ab); 666 } 667 668 static int ath11k_pci_start(struct ath11k_base *ab) 669 { 670 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 671 672 /* TODO: for now don't restore ASPM in case of single MSI 673 * vector as MHI register reading in M2 causes system hang. 674 */ 675 if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags)) 676 ath11k_pci_aspm_restore(ab_pci); 677 else 678 ath11k_info(ab, "leaving PCI ASPM disabled to avoid MHI M2 problems\n"); 679 680 ath11k_pcic_start(ab); 681 682 return 0; 683 } 684 685 static const struct ath11k_hif_ops ath11k_pci_hif_ops = { 686 .start = ath11k_pci_start, 687 .stop = ath11k_pcic_stop, 688 .read32 = ath11k_pcic_read32, 689 .write32 = ath11k_pcic_write32, 690 .read = ath11k_pcic_read, 691 .power_down = ath11k_pci_power_down, 692 .power_up = ath11k_pci_power_up, 693 .suspend = ath11k_pci_hif_suspend, 694 .resume = ath11k_pci_hif_resume, 695 .irq_enable = ath11k_pcic_ext_irq_enable, 696 .irq_disable = ath11k_pcic_ext_irq_disable, 697 .get_msi_address = ath11k_pcic_get_msi_address, 698 .get_user_msi_vector = ath11k_pcic_get_user_msi_assignment, 699 .map_service_to_pipe = ath11k_pcic_map_service_to_pipe, 700 .ce_irq_enable = ath11k_pci_hif_ce_irq_enable, 701 .ce_irq_disable = ath11k_pci_hif_ce_irq_disable, 702 .get_ce_msi_idx = ath11k_pcic_get_ce_msi_idx, 703 }; 704 705 static void ath11k_pci_read_hw_version(struct ath11k_base *ab, u32 *major, u32 *minor) 706 { 707 u32 soc_hw_version; 708 709 soc_hw_version = ath11k_pcic_read32(ab, TCSR_SOC_HW_VERSION); 710 *major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK, 711 soc_hw_version); 712 *minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK, 713 soc_hw_version); 714 715 ath11k_dbg(ab, ATH11K_DBG_PCI, "pci tcsr_soc_hw_version major %d minor %d\n", 716 *major, *minor); 717 } 718 719 static int ath11k_pci_set_irq_affinity_hint(struct ath11k_pci *ab_pci, 720 const struct cpumask *m) 721 { 722 if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab_pci->ab->dev_flags)) 723 return 0; 724 725 return irq_set_affinity_hint(ab_pci->pdev->irq, m); 726 } 727 728 static int ath11k_pci_probe(struct pci_dev *pdev, 729 const struct pci_device_id *pci_dev) 730 { 731 struct ath11k_base *ab; 732 struct ath11k_pci *ab_pci; 733 u32 soc_hw_version_major, soc_hw_version_minor, addr; 734 const struct ath11k_pci_ops *pci_ops; 735 int ret; 736 737 ab = ath11k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH11K_BUS_PCI); 738 739 if (!ab) { 740 dev_err(&pdev->dev, "failed to allocate ath11k base\n"); 741 return -ENOMEM; 742 } 743 744 ab->dev = &pdev->dev; 745 pci_set_drvdata(pdev, ab); 746 ab_pci = ath11k_pci_priv(ab); 747 ab_pci->dev_id = pci_dev->device; 748 ab_pci->ab = ab; 749 ab_pci->pdev = pdev; 750 ab->hif.ops = &ath11k_pci_hif_ops; 751 pci_set_drvdata(pdev, ab); 752 spin_lock_init(&ab_pci->window_lock); 753 754 /* Set fixed_mem_region to true for platforms support reserved memory 755 * from DT. If memory is reserved from DT for FW, ath11k driver need not 756 * allocate memory. 757 */ 758 ret = of_property_read_u32(ab->dev->of_node, "memory-region", &addr); 759 if (!ret) 760 set_bit(ATH11K_FLAG_FIXED_MEM_RGN, &ab->dev_flags); 761 762 ret = ath11k_pci_claim(ab_pci, pdev); 763 if (ret) { 764 ath11k_err(ab, "failed to claim device: %d\n", ret); 765 goto err_free_core; 766 } 767 768 ath11k_dbg(ab, ATH11K_DBG_BOOT, "pci probe %04x:%04x %04x:%04x\n", 769 pdev->vendor, pdev->device, 770 pdev->subsystem_vendor, pdev->subsystem_device); 771 772 ab->id.vendor = pdev->vendor; 773 ab->id.device = pdev->device; 774 ab->id.subsystem_vendor = pdev->subsystem_vendor; 775 ab->id.subsystem_device = pdev->subsystem_device; 776 777 switch (pci_dev->device) { 778 case QCA6390_DEVICE_ID: 779 ath11k_pci_read_hw_version(ab, &soc_hw_version_major, 780 &soc_hw_version_minor); 781 switch (soc_hw_version_major) { 782 case 2: 783 ab->hw_rev = ATH11K_HW_QCA6390_HW20; 784 break; 785 default: 786 dev_err(&pdev->dev, "Unsupported QCA6390 SOC hardware version: %d %d\n", 787 soc_hw_version_major, soc_hw_version_minor); 788 ret = -EOPNOTSUPP; 789 goto err_pci_free_region; 790 } 791 792 pci_ops = &ath11k_pci_ops_qca6390; 793 break; 794 case QCN9074_DEVICE_ID: 795 pci_ops = &ath11k_pci_ops_qcn9074; 796 ab->hw_rev = ATH11K_HW_QCN9074_HW10; 797 break; 798 case WCN6855_DEVICE_ID: 799 ab->id.bdf_search = ATH11K_BDF_SEARCH_BUS_AND_BOARD; 800 ath11k_pci_read_hw_version(ab, &soc_hw_version_major, 801 &soc_hw_version_minor); 802 switch (soc_hw_version_major) { 803 case 2: 804 switch (soc_hw_version_minor) { 805 case 0x00: 806 case 0x01: 807 ab->hw_rev = ATH11K_HW_WCN6855_HW20; 808 break; 809 case 0x10: 810 case 0x11: 811 ab->hw_rev = ATH11K_HW_WCN6855_HW21; 812 break; 813 default: 814 goto unsupported_wcn6855_soc; 815 } 816 break; 817 default: 818 unsupported_wcn6855_soc: 819 dev_err(&pdev->dev, "Unsupported WCN6855 SOC hardware version: %d %d\n", 820 soc_hw_version_major, soc_hw_version_minor); 821 ret = -EOPNOTSUPP; 822 goto err_pci_free_region; 823 } 824 825 pci_ops = &ath11k_pci_ops_qca6390; 826 break; 827 default: 828 dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n", 829 pci_dev->device); 830 ret = -EOPNOTSUPP; 831 goto err_pci_free_region; 832 } 833 834 ret = ath11k_pcic_register_pci_ops(ab, pci_ops); 835 if (ret) { 836 ath11k_err(ab, "failed to register PCI ops: %d\n", ret); 837 goto err_pci_free_region; 838 } 839 840 ret = ath11k_pcic_init_msi_config(ab); 841 if (ret) { 842 ath11k_err(ab, "failed to init msi config: %d\n", ret); 843 goto err_pci_free_region; 844 } 845 846 ret = ath11k_pci_alloc_msi(ab_pci); 847 if (ret) { 848 ath11k_err(ab, "failed to enable msi: %d\n", ret); 849 goto err_pci_free_region; 850 } 851 852 ret = ath11k_core_pre_init(ab); 853 if (ret) 854 goto err_pci_disable_msi; 855 856 ret = ath11k_mhi_register(ab_pci); 857 if (ret) { 858 ath11k_err(ab, "failed to register mhi: %d\n", ret); 859 goto err_pci_disable_msi; 860 } 861 862 ret = ath11k_hal_srng_init(ab); 863 if (ret) 864 goto err_mhi_unregister; 865 866 ret = ath11k_ce_alloc_pipes(ab); 867 if (ret) { 868 ath11k_err(ab, "failed to allocate ce pipes: %d\n", ret); 869 goto err_hal_srng_deinit; 870 } 871 872 ath11k_pci_init_qmi_ce_config(ab); 873 874 ret = ath11k_pcic_config_irq(ab); 875 if (ret) { 876 ath11k_err(ab, "failed to config irq: %d\n", ret); 877 goto err_ce_free; 878 } 879 880 ret = ath11k_pci_set_irq_affinity_hint(ab_pci, cpumask_of(0)); 881 if (ret) { 882 ath11k_err(ab, "failed to set irq affinity %d\n", ret); 883 goto err_free_irq; 884 } 885 886 /* kernel may allocate a dummy vector before request_irq and 887 * then allocate a real vector when request_irq is called. 888 * So get msi_data here again to avoid spurious interrupt 889 * as msi_data will configured to srngs. 890 */ 891 ret = ath11k_pci_config_msi_data(ab_pci); 892 if (ret) { 893 ath11k_err(ab, "failed to config msi_data: %d\n", ret); 894 goto err_irq_affinity_cleanup; 895 } 896 897 ret = ath11k_core_init(ab); 898 if (ret) { 899 ath11k_err(ab, "failed to init core: %d\n", ret); 900 goto err_irq_affinity_cleanup; 901 } 902 return 0; 903 904 err_irq_affinity_cleanup: 905 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL); 906 907 err_free_irq: 908 ath11k_pcic_free_irq(ab); 909 910 err_ce_free: 911 ath11k_ce_free_pipes(ab); 912 913 err_hal_srng_deinit: 914 ath11k_hal_srng_deinit(ab); 915 916 err_mhi_unregister: 917 ath11k_mhi_unregister(ab_pci); 918 919 err_pci_disable_msi: 920 ath11k_pci_free_msi(ab_pci); 921 922 err_pci_free_region: 923 ath11k_pci_free_region(ab_pci); 924 925 err_free_core: 926 ath11k_core_free(ab); 927 928 return ret; 929 } 930 931 static void ath11k_pci_remove(struct pci_dev *pdev) 932 { 933 struct ath11k_base *ab = pci_get_drvdata(pdev); 934 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 935 936 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL); 937 938 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) { 939 ath11k_pci_power_down(ab); 940 ath11k_debugfs_soc_destroy(ab); 941 ath11k_qmi_deinit_service(ab); 942 goto qmi_fail; 943 } 944 945 set_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags); 946 947 ath11k_core_deinit(ab); 948 949 qmi_fail: 950 ath11k_mhi_unregister(ab_pci); 951 952 ath11k_pcic_free_irq(ab); 953 ath11k_pci_free_msi(ab_pci); 954 ath11k_pci_free_region(ab_pci); 955 956 ath11k_hal_srng_deinit(ab); 957 ath11k_ce_free_pipes(ab); 958 ath11k_core_free(ab); 959 } 960 961 static void ath11k_pci_shutdown(struct pci_dev *pdev) 962 { 963 struct ath11k_base *ab = pci_get_drvdata(pdev); 964 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 965 966 ath11k_pci_set_irq_affinity_hint(ab_pci, NULL); 967 ath11k_pci_power_down(ab); 968 } 969 970 static __maybe_unused int ath11k_pci_pm_suspend(struct device *dev) 971 { 972 struct ath11k_base *ab = dev_get_drvdata(dev); 973 int ret; 974 975 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) { 976 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot skipping pci suspend as qmi is not initialised\n"); 977 return 0; 978 } 979 980 ret = ath11k_core_suspend(ab); 981 if (ret) 982 ath11k_warn(ab, "failed to suspend core: %d\n", ret); 983 984 return 0; 985 } 986 987 static __maybe_unused int ath11k_pci_pm_resume(struct device *dev) 988 { 989 struct ath11k_base *ab = dev_get_drvdata(dev); 990 int ret; 991 992 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) { 993 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot skipping pci resume as qmi is not initialised\n"); 994 return 0; 995 } 996 997 ret = ath11k_core_resume(ab); 998 if (ret) 999 ath11k_warn(ab, "failed to resume core: %d\n", ret); 1000 1001 return ret; 1002 } 1003 1004 static SIMPLE_DEV_PM_OPS(ath11k_pci_pm_ops, 1005 ath11k_pci_pm_suspend, 1006 ath11k_pci_pm_resume); 1007 1008 static struct pci_driver ath11k_pci_driver = { 1009 .name = "ath11k_pci", 1010 .id_table = ath11k_pci_id_table, 1011 .probe = ath11k_pci_probe, 1012 .remove = ath11k_pci_remove, 1013 .shutdown = ath11k_pci_shutdown, 1014 #ifdef CONFIG_PM 1015 .driver.pm = &ath11k_pci_pm_ops, 1016 #endif 1017 }; 1018 1019 static int ath11k_pci_init(void) 1020 { 1021 int ret; 1022 1023 ret = pci_register_driver(&ath11k_pci_driver); 1024 if (ret) 1025 pr_err("failed to register ath11k pci driver: %d\n", 1026 ret); 1027 1028 return ret; 1029 } 1030 module_init(ath11k_pci_init); 1031 1032 static void ath11k_pci_exit(void) 1033 { 1034 pci_unregister_driver(&ath11k_pci_driver); 1035 } 1036 1037 module_exit(ath11k_pci_exit); 1038 1039 MODULE_DESCRIPTION("Driver support for Qualcomm Technologies 802.11ax WLAN PCIe devices"); 1040 MODULE_LICENSE("Dual BSD/GPL"); 1041 1042 /* QCA639x 2.0 firmware files */ 1043 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/" ATH11K_BOARD_API2_FILE); 1044 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/" ATH11K_AMSS_FILE); 1045 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/" ATH11K_M3_FILE); 1046