1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/msi.h> 8 #include <linux/pci.h> 9 10 #include "pci.h" 11 #include "core.h" 12 #include "hif.h" 13 #include "mhi.h" 14 #include "debug.h" 15 16 #define ATH11K_PCI_BAR_NUM 0 17 #define ATH11K_PCI_DMA_MASK 32 18 19 #define ATH11K_PCI_IRQ_CE0_OFFSET 3 20 21 #define WINDOW_ENABLE_BIT 0x40000000 22 #define WINDOW_REG_ADDRESS 0x310c 23 #define WINDOW_VALUE_MASK GENMASK(24, 19) 24 #define WINDOW_START 0x80000 25 #define WINDOW_RANGE_MASK GENMASK(18, 0) 26 27 #define TCSR_SOC_HW_VERSION 0x0224 28 #define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(16, 8) 29 #define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 0) 30 31 /* BAR0 + 4k is always accessible, and no 32 * need to force wakeup. 33 * 4K - 32 = 0xFE0 34 */ 35 #define ACCESS_ALWAYS_OFF 0xFE0 36 37 #define QCA6390_DEVICE_ID 0x1101 38 39 static const struct pci_device_id ath11k_pci_id_table[] = { 40 { PCI_VDEVICE(QCOM, QCA6390_DEVICE_ID) }, 41 {0} 42 }; 43 44 MODULE_DEVICE_TABLE(pci, ath11k_pci_id_table); 45 46 static const struct ath11k_bus_params ath11k_pci_bus_params = { 47 .mhi_support = true, 48 .m3_fw_support = true, 49 .fixed_bdf_addr = false, 50 .fixed_mem_region = false, 51 }; 52 53 static const struct ath11k_msi_config msi_config = { 54 .total_vectors = 32, 55 .total_users = 4, 56 .users = (struct ath11k_msi_user[]) { 57 { .name = "MHI", .num_vectors = 3, .base_vector = 0 }, 58 { .name = "CE", .num_vectors = 10, .base_vector = 3 }, 59 { .name = "WAKE", .num_vectors = 1, .base_vector = 13 }, 60 { .name = "DP", .num_vectors = 18, .base_vector = 14 }, 61 }, 62 }; 63 64 static const char *irq_name[ATH11K_IRQ_NUM_MAX] = { 65 "bhi", 66 "mhi-er0", 67 "mhi-er1", 68 "ce0", 69 "ce1", 70 "ce2", 71 "ce3", 72 "ce4", 73 "ce5", 74 "ce6", 75 "ce7", 76 "ce8", 77 "ce9", 78 "ce10", 79 "ce11", 80 "host2wbm-desc-feed", 81 "host2reo-re-injection", 82 "host2reo-command", 83 "host2rxdma-monitor-ring3", 84 "host2rxdma-monitor-ring2", 85 "host2rxdma-monitor-ring1", 86 "reo2ost-exception", 87 "wbm2host-rx-release", 88 "reo2host-status", 89 "reo2host-destination-ring4", 90 "reo2host-destination-ring3", 91 "reo2host-destination-ring2", 92 "reo2host-destination-ring1", 93 "rxdma2host-monitor-destination-mac3", 94 "rxdma2host-monitor-destination-mac2", 95 "rxdma2host-monitor-destination-mac1", 96 "ppdu-end-interrupts-mac3", 97 "ppdu-end-interrupts-mac2", 98 "ppdu-end-interrupts-mac1", 99 "rxdma2host-monitor-status-ring-mac3", 100 "rxdma2host-monitor-status-ring-mac2", 101 "rxdma2host-monitor-status-ring-mac1", 102 "host2rxdma-host-buf-ring-mac3", 103 "host2rxdma-host-buf-ring-mac2", 104 "host2rxdma-host-buf-ring-mac1", 105 "rxdma2host-destination-ring-mac3", 106 "rxdma2host-destination-ring-mac2", 107 "rxdma2host-destination-ring-mac1", 108 "host2tcl-input-ring4", 109 "host2tcl-input-ring3", 110 "host2tcl-input-ring2", 111 "host2tcl-input-ring1", 112 "wbm2host-tx-completions-ring3", 113 "wbm2host-tx-completions-ring2", 114 "wbm2host-tx-completions-ring1", 115 "tcl2host-status-ring", 116 }; 117 118 static inline void ath11k_pci_select_window(struct ath11k_pci *ab_pci, u32 offset) 119 { 120 struct ath11k_base *ab = ab_pci->ab; 121 122 u32 window = FIELD_GET(WINDOW_VALUE_MASK, offset); 123 124 lockdep_assert_held(&ab_pci->window_lock); 125 126 if (window != ab_pci->register_window) { 127 iowrite32(WINDOW_ENABLE_BIT | window, 128 ab->mem + WINDOW_REG_ADDRESS); 129 ab_pci->register_window = window; 130 } 131 } 132 133 void ath11k_pci_write32(struct ath11k_base *ab, u32 offset, u32 value) 134 { 135 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 136 137 /* for offset beyond BAR + 4K - 32, may 138 * need to wakeup MHI to access. 139 */ 140 if (test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 141 offset >= ACCESS_ALWAYS_OFF) 142 mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev); 143 144 if (offset < WINDOW_START) { 145 iowrite32(value, ab->mem + offset); 146 } else { 147 spin_lock_bh(&ab_pci->window_lock); 148 ath11k_pci_select_window(ab_pci, offset); 149 iowrite32(value, ab->mem + WINDOW_START + (offset & WINDOW_RANGE_MASK)); 150 spin_unlock_bh(&ab_pci->window_lock); 151 } 152 153 if (test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 154 offset >= ACCESS_ALWAYS_OFF) 155 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev); 156 } 157 158 u32 ath11k_pci_read32(struct ath11k_base *ab, u32 offset) 159 { 160 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 161 u32 val; 162 163 /* for offset beyond BAR + 4K - 32, may 164 * need to wakeup MHI to access. 165 */ 166 if (test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 167 offset >= ACCESS_ALWAYS_OFF) 168 mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev); 169 170 if (offset < WINDOW_START) { 171 val = ioread32(ab->mem + offset); 172 } else { 173 spin_lock_bh(&ab_pci->window_lock); 174 ath11k_pci_select_window(ab_pci, offset); 175 val = ioread32(ab->mem + WINDOW_START + (offset & WINDOW_RANGE_MASK)); 176 spin_unlock_bh(&ab_pci->window_lock); 177 } 178 179 if (test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 180 offset >= ACCESS_ALWAYS_OFF) 181 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev); 182 183 return val; 184 } 185 186 static void ath11k_pci_soc_global_reset(struct ath11k_base *ab) 187 { 188 u32 val, delay; 189 190 val = ath11k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET); 191 192 val |= PCIE_SOC_GLOBAL_RESET_V; 193 194 ath11k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 195 196 /* TODO: exact time to sleep is uncertain */ 197 delay = 10; 198 mdelay(delay); 199 200 /* Need to toggle V bit back otherwise stuck in reset status */ 201 val &= ~PCIE_SOC_GLOBAL_RESET_V; 202 203 ath11k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 204 205 mdelay(delay); 206 207 val = ath11k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET); 208 if (val == 0xffffffff) 209 ath11k_warn(ab, "link down error during global reset\n"); 210 } 211 212 static void ath11k_pci_clear_dbg_registers(struct ath11k_base *ab) 213 { 214 u32 val; 215 216 /* read cookie */ 217 val = ath11k_pci_read32(ab, PCIE_Q6_COOKIE_ADDR); 218 ath11k_dbg(ab, ATH11K_DBG_PCI, "cookie:0x%x\n", val); 219 220 val = ath11k_pci_read32(ab, WLAON_WARM_SW_ENTRY); 221 ath11k_dbg(ab, ATH11K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val); 222 223 /* TODO: exact time to sleep is uncertain */ 224 mdelay(10); 225 226 /* write 0 to WLAON_WARM_SW_ENTRY to prevent Q6 from 227 * continuing warm path and entering dead loop. 228 */ 229 ath11k_pci_write32(ab, WLAON_WARM_SW_ENTRY, 0); 230 mdelay(10); 231 232 val = ath11k_pci_read32(ab, WLAON_WARM_SW_ENTRY); 233 ath11k_dbg(ab, ATH11K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val); 234 235 /* A read clear register. clear the register to prevent 236 * Q6 from entering wrong code path. 237 */ 238 val = ath11k_pci_read32(ab, WLAON_SOC_RESET_CAUSE_REG); 239 ath11k_dbg(ab, ATH11K_DBG_PCI, "soc reset cause:%d\n", val); 240 } 241 242 static void ath11k_pci_force_wake(struct ath11k_base *ab) 243 { 244 ath11k_pci_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1); 245 mdelay(5); 246 } 247 248 static void ath11k_pci_sw_reset(struct ath11k_base *ab) 249 { 250 ath11k_pci_soc_global_reset(ab); 251 ath11k_mhi_clear_vector(ab); 252 ath11k_pci_soc_global_reset(ab); 253 ath11k_mhi_set_mhictrl_reset(ab); 254 ath11k_pci_clear_dbg_registers(ab); 255 } 256 257 int ath11k_pci_get_msi_irq(struct device *dev, unsigned int vector) 258 { 259 struct pci_dev *pci_dev = to_pci_dev(dev); 260 261 return pci_irq_vector(pci_dev, vector); 262 } 263 264 static void ath11k_pci_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo, 265 u32 *msi_addr_hi) 266 { 267 struct pci_dev *pci_dev = to_pci_dev(ab->dev); 268 269 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO, 270 msi_addr_lo); 271 272 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI, 273 msi_addr_hi); 274 } 275 276 int ath11k_pci_get_user_msi_assignment(struct ath11k_pci *ab_pci, char *user_name, 277 int *num_vectors, u32 *user_base_data, 278 u32 *base_vector) 279 { 280 struct ath11k_base *ab = ab_pci->ab; 281 int idx; 282 283 for (idx = 0; idx < msi_config.total_users; idx++) { 284 if (strcmp(user_name, msi_config.users[idx].name) == 0) { 285 *num_vectors = msi_config.users[idx].num_vectors; 286 *user_base_data = msi_config.users[idx].base_vector 287 + ab_pci->msi_ep_base_data; 288 *base_vector = msi_config.users[idx].base_vector; 289 290 ath11k_dbg(ab, ATH11K_DBG_PCI, "Assign MSI to user: %s, num_vectors: %d, user_base_data: %u, base_vector: %u\n", 291 user_name, *num_vectors, *user_base_data, 292 *base_vector); 293 294 return 0; 295 } 296 } 297 298 ath11k_err(ab, "Failed to find MSI assignment for %s!\n", user_name); 299 300 return -EINVAL; 301 } 302 303 static int ath11k_get_user_msi_assignment(struct ath11k_base *ab, char *user_name, 304 int *num_vectors, u32 *user_base_data, 305 u32 *base_vector) 306 { 307 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 308 309 return ath11k_pci_get_user_msi_assignment(ab_pci, user_name, 310 num_vectors, user_base_data, 311 base_vector); 312 } 313 314 static void ath11k_pci_free_ext_irq(struct ath11k_base *ab) 315 { 316 int i, j; 317 318 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 319 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 320 321 for (j = 0; j < irq_grp->num_irq; j++) 322 free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp); 323 324 netif_napi_del(&irq_grp->napi); 325 } 326 } 327 328 static void ath11k_pci_free_irq(struct ath11k_base *ab) 329 { 330 int i, irq_idx; 331 332 for (i = 0; i < ab->hw_params.ce_count; i++) { 333 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 334 continue; 335 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i; 336 free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]); 337 } 338 339 ath11k_pci_free_ext_irq(ab); 340 } 341 342 static void ath11k_pci_ce_irq_enable(struct ath11k_base *ab, u16 ce_id) 343 { 344 u32 irq_idx; 345 346 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_id; 347 enable_irq(ab->irq_num[irq_idx]); 348 } 349 350 static void ath11k_pci_ce_irq_disable(struct ath11k_base *ab, u16 ce_id) 351 { 352 u32 irq_idx; 353 354 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_id; 355 disable_irq_nosync(ab->irq_num[irq_idx]); 356 } 357 358 static void ath11k_pci_ce_irqs_disable(struct ath11k_base *ab) 359 { 360 int i; 361 362 for (i = 0; i < ab->hw_params.ce_count; i++) { 363 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 364 continue; 365 ath11k_pci_ce_irq_disable(ab, i); 366 } 367 } 368 369 static void ath11k_pci_sync_ce_irqs(struct ath11k_base *ab) 370 { 371 int i; 372 int irq_idx; 373 374 for (i = 0; i < ab->hw_params.ce_count; i++) { 375 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 376 continue; 377 378 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i; 379 synchronize_irq(ab->irq_num[irq_idx]); 380 } 381 } 382 383 static void ath11k_pci_ce_tasklet(unsigned long data) 384 { 385 struct ath11k_ce_pipe *ce_pipe = (struct ath11k_ce_pipe *)data; 386 387 ath11k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num); 388 389 ath11k_pci_ce_irq_enable(ce_pipe->ab, ce_pipe->pipe_num); 390 } 391 392 static irqreturn_t ath11k_pci_ce_interrupt_handler(int irq, void *arg) 393 { 394 struct ath11k_ce_pipe *ce_pipe = arg; 395 396 ath11k_pci_ce_irq_disable(ce_pipe->ab, ce_pipe->pipe_num); 397 tasklet_schedule(&ce_pipe->intr_tq); 398 399 return IRQ_HANDLED; 400 } 401 402 static void ath11k_pci_ext_grp_disable(struct ath11k_ext_irq_grp *irq_grp) 403 { 404 int i; 405 406 for (i = 0; i < irq_grp->num_irq; i++) 407 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 408 } 409 410 static void __ath11k_pci_ext_irq_disable(struct ath11k_base *sc) 411 { 412 int i; 413 414 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 415 struct ath11k_ext_irq_grp *irq_grp = &sc->ext_irq_grp[i]; 416 417 ath11k_pci_ext_grp_disable(irq_grp); 418 419 napi_synchronize(&irq_grp->napi); 420 napi_disable(&irq_grp->napi); 421 } 422 } 423 424 static void ath11k_pci_ext_grp_enable(struct ath11k_ext_irq_grp *irq_grp) 425 { 426 int i; 427 428 for (i = 0; i < irq_grp->num_irq; i++) 429 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 430 } 431 432 static void ath11k_pci_ext_irq_enable(struct ath11k_base *ab) 433 { 434 int i; 435 436 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 437 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 438 439 napi_enable(&irq_grp->napi); 440 ath11k_pci_ext_grp_enable(irq_grp); 441 } 442 } 443 444 static void ath11k_pci_sync_ext_irqs(struct ath11k_base *ab) 445 { 446 int i, j, irq_idx; 447 448 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 449 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 450 451 for (j = 0; j < irq_grp->num_irq; j++) { 452 irq_idx = irq_grp->irqs[j]; 453 synchronize_irq(ab->irq_num[irq_idx]); 454 } 455 } 456 } 457 458 static void ath11k_pci_ext_irq_disable(struct ath11k_base *ab) 459 { 460 __ath11k_pci_ext_irq_disable(ab); 461 ath11k_pci_sync_ext_irqs(ab); 462 } 463 464 static int ath11k_pci_ext_grp_napi_poll(struct napi_struct *napi, int budget) 465 { 466 struct ath11k_ext_irq_grp *irq_grp = container_of(napi, 467 struct ath11k_ext_irq_grp, 468 napi); 469 struct ath11k_base *ab = irq_grp->ab; 470 int work_done; 471 472 work_done = ath11k_dp_service_srng(ab, irq_grp, budget); 473 if (work_done < budget) { 474 napi_complete_done(napi, work_done); 475 ath11k_pci_ext_grp_enable(irq_grp); 476 } 477 478 if (work_done > budget) 479 work_done = budget; 480 481 return work_done; 482 } 483 484 static irqreturn_t ath11k_pci_ext_interrupt_handler(int irq, void *arg) 485 { 486 struct ath11k_ext_irq_grp *irq_grp = arg; 487 488 ath11k_dbg(irq_grp->ab, ATH11K_DBG_PCI, "ext irq:%d\n", irq); 489 490 ath11k_pci_ext_grp_disable(irq_grp); 491 492 napi_schedule(&irq_grp->napi); 493 494 return IRQ_HANDLED; 495 } 496 497 static int ath11k_pci_ext_irq_config(struct ath11k_base *ab) 498 { 499 int i, j, ret, num_vectors = 0; 500 u32 user_base_data = 0, base_vector = 0; 501 502 ret = ath11k_pci_get_user_msi_assignment(ath11k_pci_priv(ab), "DP", 503 &num_vectors, 504 &user_base_data, 505 &base_vector); 506 if (ret < 0) 507 return ret; 508 509 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 510 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 511 u32 num_irq = 0; 512 513 irq_grp->ab = ab; 514 irq_grp->grp_id = i; 515 init_dummy_netdev(&irq_grp->napi_ndev); 516 netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi, 517 ath11k_pci_ext_grp_napi_poll, NAPI_POLL_WEIGHT); 518 519 if (ab->hw_params.ring_mask->tx[i] || 520 ab->hw_params.ring_mask->rx[i] || 521 ab->hw_params.ring_mask->rx_err[i] || 522 ab->hw_params.ring_mask->rx_wbm_rel[i] || 523 ab->hw_params.ring_mask->reo_status[i] || 524 ab->hw_params.ring_mask->rxdma2host[i] || 525 ab->hw_params.ring_mask->host2rxdma[i] || 526 ab->hw_params.ring_mask->rx_mon_status[i]) { 527 num_irq = 1; 528 } 529 530 irq_grp->num_irq = num_irq; 531 irq_grp->irqs[0] = base_vector + i; 532 533 for (j = 0; j < irq_grp->num_irq; j++) { 534 int irq_idx = irq_grp->irqs[j]; 535 int vector = (i % num_vectors) + base_vector; 536 int irq = ath11k_pci_get_msi_irq(ab->dev, vector); 537 538 ab->irq_num[irq_idx] = irq; 539 540 ath11k_dbg(ab, ATH11K_DBG_PCI, 541 "irq:%d group:%d\n", irq, i); 542 ret = request_irq(irq, ath11k_pci_ext_interrupt_handler, 543 IRQF_SHARED, 544 "DP_EXT_IRQ", irq_grp); 545 if (ret) { 546 ath11k_err(ab, "failed request irq %d: %d\n", 547 vector, ret); 548 return ret; 549 } 550 551 disable_irq_nosync(ab->irq_num[irq_idx]); 552 } 553 } 554 555 return 0; 556 } 557 558 static int ath11k_pci_config_irq(struct ath11k_base *ab) 559 { 560 struct ath11k_ce_pipe *ce_pipe; 561 u32 msi_data_start; 562 u32 msi_data_count; 563 u32 msi_irq_start; 564 unsigned int msi_data; 565 int irq, i, ret, irq_idx; 566 567 ret = ath11k_pci_get_user_msi_assignment(ath11k_pci_priv(ab), 568 "CE", &msi_data_count, 569 &msi_data_start, &msi_irq_start); 570 if (ret) 571 return ret; 572 573 /* Configure CE irqs */ 574 for (i = 0; i < ab->hw_params.ce_count; i++) { 575 msi_data = (i % msi_data_count) + msi_irq_start; 576 irq = ath11k_pci_get_msi_irq(ab->dev, msi_data); 577 ce_pipe = &ab->ce.ce_pipe[i]; 578 579 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 580 continue; 581 582 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i; 583 584 tasklet_init(&ce_pipe->intr_tq, ath11k_pci_ce_tasklet, 585 (unsigned long)ce_pipe); 586 587 ret = request_irq(irq, ath11k_pci_ce_interrupt_handler, 588 IRQF_SHARED, irq_name[irq_idx], 589 ce_pipe); 590 if (ret) { 591 ath11k_err(ab, "failed to request irq %d: %d\n", 592 irq_idx, ret); 593 return ret; 594 } 595 596 ab->irq_num[irq_idx] = irq; 597 ath11k_pci_ce_irq_disable(ab, i); 598 } 599 600 ret = ath11k_pci_ext_irq_config(ab); 601 if (ret) 602 return ret; 603 604 return 0; 605 } 606 607 static void ath11k_pci_init_qmi_ce_config(struct ath11k_base *ab) 608 { 609 struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg; 610 611 cfg->tgt_ce = ab->hw_params.target_ce_config; 612 cfg->tgt_ce_len = ab->hw_params.target_ce_count; 613 614 cfg->svc_to_ce_map = ab->hw_params.svc_to_ce_map; 615 cfg->svc_to_ce_map_len = ab->hw_params.svc_to_ce_map_len; 616 ab->qmi.service_ins_id = ATH11K_QMI_WLFW_SERVICE_INS_ID_V01_QCA6390; 617 618 ath11k_ce_get_shadow_config(ab, &cfg->shadow_reg_v2, 619 &cfg->shadow_reg_v2_len); 620 } 621 622 static void ath11k_pci_ce_irqs_enable(struct ath11k_base *ab) 623 { 624 int i; 625 626 for (i = 0; i < ab->hw_params.ce_count; i++) { 627 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 628 continue; 629 ath11k_pci_ce_irq_enable(ab, i); 630 } 631 } 632 633 static int ath11k_pci_enable_msi(struct ath11k_pci *ab_pci) 634 { 635 struct ath11k_base *ab = ab_pci->ab; 636 struct msi_desc *msi_desc; 637 int num_vectors; 638 int ret; 639 640 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev, 641 msi_config.total_vectors, 642 msi_config.total_vectors, 643 PCI_IRQ_MSI); 644 if (num_vectors != msi_config.total_vectors) { 645 ath11k_err(ab, "failed to get %d MSI vectors, only %d available", 646 msi_config.total_vectors, num_vectors); 647 648 if (num_vectors >= 0) 649 return -EINVAL; 650 else 651 return num_vectors; 652 } 653 654 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq); 655 if (!msi_desc) { 656 ath11k_err(ab, "msi_desc is NULL!\n"); 657 ret = -EINVAL; 658 goto free_msi_vector; 659 } 660 661 ab_pci->msi_ep_base_data = msi_desc->msg.data; 662 663 ath11k_dbg(ab, ATH11K_DBG_PCI, "msi base data is %d\n", ab_pci->msi_ep_base_data); 664 665 return 0; 666 667 free_msi_vector: 668 pci_free_irq_vectors(ab_pci->pdev); 669 670 return ret; 671 } 672 673 static void ath11k_pci_disable_msi(struct ath11k_pci *ab_pci) 674 { 675 pci_free_irq_vectors(ab_pci->pdev); 676 } 677 678 static int ath11k_pci_claim(struct ath11k_pci *ab_pci, struct pci_dev *pdev) 679 { 680 struct ath11k_base *ab = ab_pci->ab; 681 u16 device_id; 682 int ret = 0; 683 684 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id); 685 if (device_id != ab_pci->dev_id) { 686 ath11k_err(ab, "pci device id mismatch: 0x%x 0x%x\n", 687 device_id, ab_pci->dev_id); 688 ret = -EIO; 689 goto out; 690 } 691 692 ret = pci_assign_resource(pdev, ATH11K_PCI_BAR_NUM); 693 if (ret) { 694 ath11k_err(ab, "failed to assign pci resource: %d\n", ret); 695 goto out; 696 } 697 698 ret = pci_enable_device(pdev); 699 if (ret) { 700 ath11k_err(ab, "failed to enable pci device: %d\n", ret); 701 goto out; 702 } 703 704 ret = pci_request_region(pdev, ATH11K_PCI_BAR_NUM, "ath11k_pci"); 705 if (ret) { 706 ath11k_err(ab, "failed to request pci region: %d\n", ret); 707 goto disable_device; 708 } 709 710 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(ATH11K_PCI_DMA_MASK)); 711 if (ret) { 712 ath11k_err(ab, "failed to set pci dma mask to %d: %d\n", 713 ATH11K_PCI_DMA_MASK, ret); 714 goto release_region; 715 } 716 717 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(ATH11K_PCI_DMA_MASK)); 718 if (ret) { 719 ath11k_err(ab, "failed to set pci consistent dma mask to %d: %d\n", 720 ATH11K_PCI_DMA_MASK, ret); 721 goto release_region; 722 } 723 724 pci_set_master(pdev); 725 726 ab->mem_len = pci_resource_len(pdev, ATH11K_PCI_BAR_NUM); 727 ab->mem = pci_iomap(pdev, ATH11K_PCI_BAR_NUM, 0); 728 if (!ab->mem) { 729 ath11k_err(ab, "failed to map pci bar %d\n", ATH11K_PCI_BAR_NUM); 730 ret = -EIO; 731 goto clear_master; 732 } 733 734 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot pci_mem 0x%pK\n", ab->mem); 735 return 0; 736 737 clear_master: 738 pci_clear_master(pdev); 739 release_region: 740 pci_release_region(pdev, ATH11K_PCI_BAR_NUM); 741 disable_device: 742 pci_disable_device(pdev); 743 out: 744 return ret; 745 } 746 747 static void ath11k_pci_free_region(struct ath11k_pci *ab_pci) 748 { 749 struct ath11k_base *ab = ab_pci->ab; 750 struct pci_dev *pci_dev = ab_pci->pdev; 751 752 pci_iounmap(pci_dev, ab->mem); 753 ab->mem = NULL; 754 pci_clear_master(pci_dev); 755 pci_release_region(pci_dev, ATH11K_PCI_BAR_NUM); 756 if (pci_is_enabled(pci_dev)) 757 pci_disable_device(pci_dev); 758 } 759 760 static int ath11k_pci_power_up(struct ath11k_base *ab) 761 { 762 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 763 int ret; 764 765 ab_pci->register_window = 0; 766 clear_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags); 767 ath11k_pci_sw_reset(ab_pci->ab); 768 769 ret = ath11k_mhi_start(ab_pci); 770 if (ret) { 771 ath11k_err(ab, "failed to start mhi: %d\n", ret); 772 return ret; 773 } 774 775 return 0; 776 } 777 778 static void ath11k_pci_power_down(struct ath11k_base *ab) 779 { 780 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 781 782 ath11k_mhi_stop(ab_pci); 783 clear_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags); 784 ath11k_pci_force_wake(ab_pci->ab); 785 ath11k_pci_sw_reset(ab_pci->ab); 786 } 787 788 static void ath11k_pci_kill_tasklets(struct ath11k_base *ab) 789 { 790 int i; 791 792 for (i = 0; i < ab->hw_params.ce_count; i++) { 793 struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i]; 794 795 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 796 continue; 797 798 tasklet_kill(&ce_pipe->intr_tq); 799 } 800 } 801 802 static void ath11k_pci_stop(struct ath11k_base *ab) 803 { 804 ath11k_pci_ce_irqs_disable(ab); 805 ath11k_pci_sync_ce_irqs(ab); 806 ath11k_pci_kill_tasklets(ab); 807 ath11k_ce_cleanup_pipes(ab); 808 } 809 810 static int ath11k_pci_start(struct ath11k_base *ab) 811 { 812 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 813 814 set_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags); 815 816 ath11k_pci_ce_irqs_enable(ab); 817 ath11k_ce_rx_post_buf(ab); 818 819 return 0; 820 } 821 822 static int ath11k_pci_map_service_to_pipe(struct ath11k_base *ab, u16 service_id, 823 u8 *ul_pipe, u8 *dl_pipe) 824 { 825 const struct service_to_pipe *entry; 826 bool ul_set = false, dl_set = false; 827 int i; 828 829 for (i = 0; i < ab->hw_params.svc_to_ce_map_len; i++) { 830 entry = &ab->hw_params.svc_to_ce_map[i]; 831 832 if (__le32_to_cpu(entry->service_id) != service_id) 833 continue; 834 835 switch (__le32_to_cpu(entry->pipedir)) { 836 case PIPEDIR_NONE: 837 break; 838 case PIPEDIR_IN: 839 WARN_ON(dl_set); 840 *dl_pipe = __le32_to_cpu(entry->pipenum); 841 dl_set = true; 842 break; 843 case PIPEDIR_OUT: 844 WARN_ON(ul_set); 845 *ul_pipe = __le32_to_cpu(entry->pipenum); 846 ul_set = true; 847 break; 848 case PIPEDIR_INOUT: 849 WARN_ON(dl_set); 850 WARN_ON(ul_set); 851 *dl_pipe = __le32_to_cpu(entry->pipenum); 852 *ul_pipe = __le32_to_cpu(entry->pipenum); 853 dl_set = true; 854 ul_set = true; 855 break; 856 } 857 } 858 859 if (WARN_ON(!ul_set || !dl_set)) 860 return -ENOENT; 861 862 return 0; 863 } 864 865 static const struct ath11k_hif_ops ath11k_pci_hif_ops = { 866 .start = ath11k_pci_start, 867 .stop = ath11k_pci_stop, 868 .read32 = ath11k_pci_read32, 869 .write32 = ath11k_pci_write32, 870 .power_down = ath11k_pci_power_down, 871 .power_up = ath11k_pci_power_up, 872 .irq_enable = ath11k_pci_ext_irq_enable, 873 .irq_disable = ath11k_pci_ext_irq_disable, 874 .get_msi_address = ath11k_pci_get_msi_address, 875 .get_user_msi_vector = ath11k_get_user_msi_assignment, 876 .map_service_to_pipe = ath11k_pci_map_service_to_pipe, 877 }; 878 879 static int ath11k_pci_probe(struct pci_dev *pdev, 880 const struct pci_device_id *pci_dev) 881 { 882 struct ath11k_base *ab; 883 struct ath11k_pci *ab_pci; 884 u32 soc_hw_version, soc_hw_version_major, soc_hw_version_minor; 885 int ret; 886 887 dev_warn(&pdev->dev, "WARNING: ath11k PCI support is experimental!\n"); 888 889 ab = ath11k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH11K_BUS_PCI, 890 &ath11k_pci_bus_params); 891 if (!ab) { 892 dev_err(&pdev->dev, "failed to allocate ath11k base\n"); 893 return -ENOMEM; 894 } 895 896 ab->dev = &pdev->dev; 897 pci_set_drvdata(pdev, ab); 898 ab_pci = ath11k_pci_priv(ab); 899 ab_pci->dev_id = pci_dev->device; 900 ab_pci->ab = ab; 901 ab_pci->pdev = pdev; 902 ab->hif.ops = &ath11k_pci_hif_ops; 903 pci_set_drvdata(pdev, ab); 904 spin_lock_init(&ab_pci->window_lock); 905 906 ret = ath11k_pci_claim(ab_pci, pdev); 907 if (ret) { 908 ath11k_err(ab, "failed to claim device: %d\n", ret); 909 goto err_free_core; 910 } 911 912 switch (pci_dev->device) { 913 case QCA6390_DEVICE_ID: 914 soc_hw_version = ath11k_pci_read32(ab, TCSR_SOC_HW_VERSION); 915 soc_hw_version_major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK, 916 soc_hw_version); 917 soc_hw_version_minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK, 918 soc_hw_version); 919 920 ath11k_dbg(ab, ATH11K_DBG_PCI, "pci tcsr_soc_hw_version major %d minor %d\n", 921 soc_hw_version_major, soc_hw_version_minor); 922 923 switch (soc_hw_version_major) { 924 case 2: 925 ab->hw_rev = ATH11K_HW_QCA6390_HW20; 926 break; 927 default: 928 dev_err(&pdev->dev, "Unsupported QCA6390 SOC hardware version: %d %d\n", 929 soc_hw_version_major, soc_hw_version_minor); 930 ret = -EOPNOTSUPP; 931 goto err_pci_free_region; 932 } 933 break; 934 default: 935 dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n", 936 pci_dev->device); 937 ret = -EOPNOTSUPP; 938 goto err_pci_free_region; 939 } 940 941 ret = ath11k_pci_enable_msi(ab_pci); 942 if (ret) { 943 ath11k_err(ab, "failed to enable msi: %d\n", ret); 944 goto err_pci_free_region; 945 } 946 947 ret = ath11k_core_pre_init(ab); 948 if (ret) 949 goto err_pci_disable_msi; 950 951 ret = ath11k_mhi_register(ab_pci); 952 if (ret) { 953 ath11k_err(ab, "failed to register mhi: %d\n", ret); 954 goto err_pci_disable_msi; 955 } 956 957 ret = ath11k_hal_srng_init(ab); 958 if (ret) 959 goto err_mhi_unregister; 960 961 ret = ath11k_ce_alloc_pipes(ab); 962 if (ret) { 963 ath11k_err(ab, "failed to allocate ce pipes: %d\n", ret); 964 goto err_hal_srng_deinit; 965 } 966 967 ath11k_pci_init_qmi_ce_config(ab); 968 969 ret = ath11k_pci_config_irq(ab); 970 if (ret) { 971 ath11k_err(ab, "failed to config irq: %d\n", ret); 972 goto err_ce_free; 973 } 974 975 ret = ath11k_core_init(ab); 976 if (ret) { 977 ath11k_err(ab, "failed to init core: %d\n", ret); 978 goto err_free_irq; 979 } 980 return 0; 981 982 err_free_irq: 983 ath11k_pci_free_irq(ab); 984 985 err_ce_free: 986 ath11k_ce_free_pipes(ab); 987 988 err_hal_srng_deinit: 989 ath11k_hal_srng_deinit(ab); 990 991 err_mhi_unregister: 992 ath11k_mhi_unregister(ab_pci); 993 994 err_pci_disable_msi: 995 ath11k_pci_disable_msi(ab_pci); 996 997 err_pci_free_region: 998 ath11k_pci_free_region(ab_pci); 999 1000 err_free_core: 1001 ath11k_core_free(ab); 1002 1003 return ret; 1004 } 1005 1006 static void ath11k_pci_remove(struct pci_dev *pdev) 1007 { 1008 struct ath11k_base *ab = pci_get_drvdata(pdev); 1009 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 1010 1011 set_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags); 1012 1013 ath11k_core_deinit(ab); 1014 1015 ath11k_mhi_unregister(ab_pci); 1016 1017 ath11k_pci_free_irq(ab); 1018 ath11k_pci_disable_msi(ab_pci); 1019 ath11k_pci_free_region(ab_pci); 1020 1021 ath11k_hal_srng_deinit(ab); 1022 ath11k_ce_free_pipes(ab); 1023 ath11k_core_free(ab); 1024 } 1025 1026 static void ath11k_pci_shutdown(struct pci_dev *pdev) 1027 { 1028 struct ath11k_base *ab = pci_get_drvdata(pdev); 1029 1030 ath11k_pci_power_down(ab); 1031 } 1032 1033 static struct pci_driver ath11k_pci_driver = { 1034 .name = "ath11k_pci", 1035 .id_table = ath11k_pci_id_table, 1036 .probe = ath11k_pci_probe, 1037 .remove = ath11k_pci_remove, 1038 .shutdown = ath11k_pci_shutdown, 1039 }; 1040 1041 static int ath11k_pci_init(void) 1042 { 1043 int ret; 1044 1045 ret = pci_register_driver(&ath11k_pci_driver); 1046 if (ret) 1047 pr_err("failed to register ath11k pci driver: %d\n", 1048 ret); 1049 1050 return ret; 1051 } 1052 module_init(ath11k_pci_init); 1053 1054 static void ath11k_pci_exit(void) 1055 { 1056 pci_unregister_driver(&ath11k_pci_driver); 1057 } 1058 1059 module_exit(ath11k_pci_exit); 1060 1061 MODULE_DESCRIPTION("Driver support for Qualcomm Technologies 802.11ax WLAN PCIe devices"); 1062 MODULE_LICENSE("Dual BSD/GPL"); 1063