1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2019-2020 The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/module.h> 7 #include <linux/msi.h> 8 #include <linux/pci.h> 9 10 #include "pci.h" 11 #include "core.h" 12 #include "hif.h" 13 #include "mhi.h" 14 #include "debug.h" 15 16 #define ATH11K_PCI_BAR_NUM 0 17 #define ATH11K_PCI_DMA_MASK 32 18 19 #define ATH11K_PCI_IRQ_CE0_OFFSET 3 20 21 #define WINDOW_ENABLE_BIT 0x40000000 22 #define WINDOW_REG_ADDRESS 0x310c 23 #define WINDOW_VALUE_MASK GENMASK(24, 19) 24 #define WINDOW_START 0x80000 25 #define WINDOW_RANGE_MASK GENMASK(18, 0) 26 27 #define TCSR_SOC_HW_VERSION 0x0224 28 #define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(16, 8) 29 #define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 0) 30 31 /* BAR0 + 4k is always accessible, and no 32 * need to force wakeup. 33 * 4K - 32 = 0xFE0 34 */ 35 #define ACCESS_ALWAYS_OFF 0xFE0 36 37 #define QCA6390_DEVICE_ID 0x1101 38 #define QCN9074_DEVICE_ID 0x1104 39 40 static const struct pci_device_id ath11k_pci_id_table[] = { 41 { PCI_VDEVICE(QCOM, QCA6390_DEVICE_ID) }, 42 /* TODO: add QCN9074_DEVICE_ID) once firmware issues are resolved */ 43 {0} 44 }; 45 46 MODULE_DEVICE_TABLE(pci, ath11k_pci_id_table); 47 48 static const struct ath11k_bus_params ath11k_pci_bus_params = { 49 .mhi_support = true, 50 .m3_fw_support = true, 51 .fixed_bdf_addr = false, 52 .fixed_mem_region = false, 53 }; 54 55 static const struct ath11k_msi_config ath11k_msi_config[] = { 56 { 57 .total_vectors = 32, 58 .total_users = 4, 59 .users = (struct ath11k_msi_user[]) { 60 { .name = "MHI", .num_vectors = 3, .base_vector = 0 }, 61 { .name = "CE", .num_vectors = 10, .base_vector = 3 }, 62 { .name = "WAKE", .num_vectors = 1, .base_vector = 13 }, 63 { .name = "DP", .num_vectors = 18, .base_vector = 14 }, 64 }, 65 }, 66 { 67 .total_vectors = 16, 68 .total_users = 3, 69 .users = (struct ath11k_msi_user[]) { 70 { .name = "MHI", .num_vectors = 3, .base_vector = 0 }, 71 { .name = "CE", .num_vectors = 5, .base_vector = 3 }, 72 { .name = "DP", .num_vectors = 8, .base_vector = 8 }, 73 }, 74 }, 75 }; 76 77 static const char *irq_name[ATH11K_IRQ_NUM_MAX] = { 78 "bhi", 79 "mhi-er0", 80 "mhi-er1", 81 "ce0", 82 "ce1", 83 "ce2", 84 "ce3", 85 "ce4", 86 "ce5", 87 "ce6", 88 "ce7", 89 "ce8", 90 "ce9", 91 "ce10", 92 "ce11", 93 "host2wbm-desc-feed", 94 "host2reo-re-injection", 95 "host2reo-command", 96 "host2rxdma-monitor-ring3", 97 "host2rxdma-monitor-ring2", 98 "host2rxdma-monitor-ring1", 99 "reo2ost-exception", 100 "wbm2host-rx-release", 101 "reo2host-status", 102 "reo2host-destination-ring4", 103 "reo2host-destination-ring3", 104 "reo2host-destination-ring2", 105 "reo2host-destination-ring1", 106 "rxdma2host-monitor-destination-mac3", 107 "rxdma2host-monitor-destination-mac2", 108 "rxdma2host-monitor-destination-mac1", 109 "ppdu-end-interrupts-mac3", 110 "ppdu-end-interrupts-mac2", 111 "ppdu-end-interrupts-mac1", 112 "rxdma2host-monitor-status-ring-mac3", 113 "rxdma2host-monitor-status-ring-mac2", 114 "rxdma2host-monitor-status-ring-mac1", 115 "host2rxdma-host-buf-ring-mac3", 116 "host2rxdma-host-buf-ring-mac2", 117 "host2rxdma-host-buf-ring-mac1", 118 "rxdma2host-destination-ring-mac3", 119 "rxdma2host-destination-ring-mac2", 120 "rxdma2host-destination-ring-mac1", 121 "host2tcl-input-ring4", 122 "host2tcl-input-ring3", 123 "host2tcl-input-ring2", 124 "host2tcl-input-ring1", 125 "wbm2host-tx-completions-ring3", 126 "wbm2host-tx-completions-ring2", 127 "wbm2host-tx-completions-ring1", 128 "tcl2host-status-ring", 129 }; 130 131 static inline void ath11k_pci_select_window(struct ath11k_pci *ab_pci, u32 offset) 132 { 133 struct ath11k_base *ab = ab_pci->ab; 134 135 u32 window = FIELD_GET(WINDOW_VALUE_MASK, offset); 136 137 lockdep_assert_held(&ab_pci->window_lock); 138 139 if (window != ab_pci->register_window) { 140 iowrite32(WINDOW_ENABLE_BIT | window, 141 ab->mem + WINDOW_REG_ADDRESS); 142 ioread32(ab->mem + WINDOW_REG_ADDRESS); 143 ab_pci->register_window = window; 144 } 145 } 146 147 static inline void ath11k_pci_select_static_window(struct ath11k_pci *ab_pci) 148 { 149 u32 umac_window = FIELD_GET(WINDOW_VALUE_MASK, HAL_SEQ_WCSS_UMAC_OFFSET); 150 u32 ce_window = FIELD_GET(WINDOW_VALUE_MASK, HAL_CE_WFSS_CE_REG_BASE); 151 u32 window; 152 153 window = (umac_window << 12) | (ce_window << 6); 154 155 iowrite32(WINDOW_ENABLE_BIT | window, ab_pci->ab->mem + WINDOW_REG_ADDRESS); 156 } 157 158 static inline u32 ath11k_pci_get_window_start(struct ath11k_base *ab, 159 u32 offset) 160 { 161 u32 window_start; 162 163 /* If offset lies within DP register range, use 3rd window */ 164 if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < WINDOW_RANGE_MASK) 165 window_start = 3 * WINDOW_START; 166 /* If offset lies within CE register range, use 2nd window */ 167 else if ((offset ^ HAL_CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK) 168 window_start = 2 * WINDOW_START; 169 else 170 window_start = WINDOW_START; 171 172 return window_start; 173 } 174 175 void ath11k_pci_write32(struct ath11k_base *ab, u32 offset, u32 value) 176 { 177 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 178 u32 window_start; 179 180 /* for offset beyond BAR + 4K - 32, may 181 * need to wakeup MHI to access. 182 */ 183 if (test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 184 offset >= ACCESS_ALWAYS_OFF) 185 mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev); 186 187 if (offset < WINDOW_START) { 188 iowrite32(value, ab->mem + offset); 189 } else { 190 if (ab->bus_params.static_window_map) 191 window_start = ath11k_pci_get_window_start(ab, offset); 192 else 193 window_start = WINDOW_START; 194 195 if (window_start == WINDOW_START) { 196 spin_lock_bh(&ab_pci->window_lock); 197 ath11k_pci_select_window(ab_pci, offset); 198 iowrite32(value, ab->mem + window_start + 199 (offset & WINDOW_RANGE_MASK)); 200 spin_unlock_bh(&ab_pci->window_lock); 201 } else { 202 iowrite32(value, ab->mem + window_start + 203 (offset & WINDOW_RANGE_MASK)); 204 } 205 } 206 207 if (test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 208 offset >= ACCESS_ALWAYS_OFF) 209 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev); 210 } 211 212 u32 ath11k_pci_read32(struct ath11k_base *ab, u32 offset) 213 { 214 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 215 u32 val, window_start; 216 217 /* for offset beyond BAR + 4K - 32, may 218 * need to wakeup MHI to access. 219 */ 220 if (test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 221 offset >= ACCESS_ALWAYS_OFF) 222 mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev); 223 224 if (offset < WINDOW_START) { 225 val = ioread32(ab->mem + offset); 226 } else { 227 if (ab->bus_params.static_window_map) 228 window_start = ath11k_pci_get_window_start(ab, offset); 229 else 230 window_start = WINDOW_START; 231 232 if (window_start == WINDOW_START) { 233 spin_lock_bh(&ab_pci->window_lock); 234 ath11k_pci_select_window(ab_pci, offset); 235 val = ioread32(ab->mem + window_start + 236 (offset & WINDOW_RANGE_MASK)); 237 spin_unlock_bh(&ab_pci->window_lock); 238 } else { 239 val = ioread32(ab->mem + window_start + 240 (offset & WINDOW_RANGE_MASK)); 241 } 242 } 243 244 if (test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) && 245 offset >= ACCESS_ALWAYS_OFF) 246 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev); 247 248 return val; 249 } 250 251 static void ath11k_pci_soc_global_reset(struct ath11k_base *ab) 252 { 253 u32 val, delay; 254 255 val = ath11k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET); 256 257 val |= PCIE_SOC_GLOBAL_RESET_V; 258 259 ath11k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 260 261 /* TODO: exact time to sleep is uncertain */ 262 delay = 10; 263 mdelay(delay); 264 265 /* Need to toggle V bit back otherwise stuck in reset status */ 266 val &= ~PCIE_SOC_GLOBAL_RESET_V; 267 268 ath11k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val); 269 270 mdelay(delay); 271 272 val = ath11k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET); 273 if (val == 0xffffffff) 274 ath11k_warn(ab, "link down error during global reset\n"); 275 } 276 277 static void ath11k_pci_clear_dbg_registers(struct ath11k_base *ab) 278 { 279 u32 val; 280 281 /* read cookie */ 282 val = ath11k_pci_read32(ab, PCIE_Q6_COOKIE_ADDR); 283 ath11k_dbg(ab, ATH11K_DBG_PCI, "cookie:0x%x\n", val); 284 285 val = ath11k_pci_read32(ab, WLAON_WARM_SW_ENTRY); 286 ath11k_dbg(ab, ATH11K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val); 287 288 /* TODO: exact time to sleep is uncertain */ 289 mdelay(10); 290 291 /* write 0 to WLAON_WARM_SW_ENTRY to prevent Q6 from 292 * continuing warm path and entering dead loop. 293 */ 294 ath11k_pci_write32(ab, WLAON_WARM_SW_ENTRY, 0); 295 mdelay(10); 296 297 val = ath11k_pci_read32(ab, WLAON_WARM_SW_ENTRY); 298 ath11k_dbg(ab, ATH11K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val); 299 300 /* A read clear register. clear the register to prevent 301 * Q6 from entering wrong code path. 302 */ 303 val = ath11k_pci_read32(ab, WLAON_SOC_RESET_CAUSE_REG); 304 ath11k_dbg(ab, ATH11K_DBG_PCI, "soc reset cause:%d\n", val); 305 } 306 307 static int ath11k_pci_set_link_reg(struct ath11k_base *ab, 308 u32 offset, u32 value, u32 mask) 309 { 310 u32 v; 311 int i; 312 313 v = ath11k_pci_read32(ab, offset); 314 if ((v & mask) == value) 315 return 0; 316 317 for (i = 0; i < 10; i++) { 318 ath11k_pci_write32(ab, offset, (v & ~mask) | value); 319 320 v = ath11k_pci_read32(ab, offset); 321 if ((v & mask) == value) 322 return 0; 323 324 mdelay(2); 325 } 326 327 ath11k_warn(ab, "failed to set pcie link register 0x%08x: 0x%08x != 0x%08x\n", 328 offset, v & mask, value); 329 330 return -ETIMEDOUT; 331 } 332 333 static int ath11k_pci_fix_l1ss(struct ath11k_base *ab) 334 { 335 int ret; 336 337 ret = ath11k_pci_set_link_reg(ab, 338 PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(ab), 339 PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL, 340 PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK); 341 if (ret) { 342 ath11k_warn(ab, "failed to set sysclk: %d\n", ret); 343 return ret; 344 } 345 346 ret = ath11k_pci_set_link_reg(ab, 347 PCIE_PCS_OSC_DTCT_CONFIG1_REG(ab), 348 PCIE_PCS_OSC_DTCT_CONFIG1_VAL, 349 PCIE_PCS_OSC_DTCT_CONFIG_MSK); 350 if (ret) { 351 ath11k_warn(ab, "failed to set dtct config1 error: %d\n", ret); 352 return ret; 353 } 354 355 ret = ath11k_pci_set_link_reg(ab, 356 PCIE_PCS_OSC_DTCT_CONFIG2_REG(ab), 357 PCIE_PCS_OSC_DTCT_CONFIG2_VAL, 358 PCIE_PCS_OSC_DTCT_CONFIG_MSK); 359 if (ret) { 360 ath11k_warn(ab, "failed to set dtct config2: %d\n", ret); 361 return ret; 362 } 363 364 ret = ath11k_pci_set_link_reg(ab, 365 PCIE_PCS_OSC_DTCT_CONFIG4_REG(ab), 366 PCIE_PCS_OSC_DTCT_CONFIG4_VAL, 367 PCIE_PCS_OSC_DTCT_CONFIG_MSK); 368 if (ret) { 369 ath11k_warn(ab, "failed to set dtct config4: %d\n", ret); 370 return ret; 371 } 372 373 return 0; 374 } 375 376 static void ath11k_pci_enable_ltssm(struct ath11k_base *ab) 377 { 378 u32 val; 379 int i; 380 381 val = ath11k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM); 382 383 /* PCIE link seems very unstable after the Hot Reset*/ 384 for (i = 0; val != PARM_LTSSM_VALUE && i < 5; i++) { 385 if (val == 0xffffffff) 386 mdelay(5); 387 388 ath11k_pci_write32(ab, PCIE_PCIE_PARF_LTSSM, PARM_LTSSM_VALUE); 389 val = ath11k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM); 390 } 391 392 ath11k_dbg(ab, ATH11K_DBG_PCI, "pci ltssm 0x%x\n", val); 393 394 val = ath11k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST); 395 val |= GCC_GCC_PCIE_HOT_RST_VAL; 396 ath11k_pci_write32(ab, GCC_GCC_PCIE_HOT_RST, val); 397 val = ath11k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST); 398 399 ath11k_dbg(ab, ATH11K_DBG_PCI, "pci pcie_hot_rst 0x%x\n", val); 400 401 mdelay(5); 402 } 403 404 static void ath11k_pci_clear_all_intrs(struct ath11k_base *ab) 405 { 406 /* This is a WAR for PCIE Hotreset. 407 * When target receive Hotreset, but will set the interrupt. 408 * So when download SBL again, SBL will open Interrupt and 409 * receive it, and crash immediately. 410 */ 411 ath11k_pci_write32(ab, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL); 412 } 413 414 static void ath11k_pci_set_wlaon_pwr_ctrl(struct ath11k_base *ab) 415 { 416 u32 val; 417 418 val = ath11k_pci_read32(ab, WLAON_QFPROM_PWR_CTRL_REG); 419 val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK; 420 ath11k_pci_write32(ab, WLAON_QFPROM_PWR_CTRL_REG, val); 421 } 422 423 static void ath11k_pci_force_wake(struct ath11k_base *ab) 424 { 425 ath11k_pci_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1); 426 mdelay(5); 427 } 428 429 static void ath11k_pci_sw_reset(struct ath11k_base *ab, bool power_on) 430 { 431 if (power_on) { 432 ath11k_pci_enable_ltssm(ab); 433 ath11k_pci_clear_all_intrs(ab); 434 ath11k_pci_set_wlaon_pwr_ctrl(ab); 435 ath11k_pci_fix_l1ss(ab); 436 } 437 438 ath11k_mhi_clear_vector(ab); 439 ath11k_pci_soc_global_reset(ab); 440 ath11k_mhi_set_mhictrl_reset(ab); 441 ath11k_pci_clear_dbg_registers(ab); 442 } 443 444 int ath11k_pci_get_msi_irq(struct device *dev, unsigned int vector) 445 { 446 struct pci_dev *pci_dev = to_pci_dev(dev); 447 448 return pci_irq_vector(pci_dev, vector); 449 } 450 451 static void ath11k_pci_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo, 452 u32 *msi_addr_hi) 453 { 454 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 455 struct pci_dev *pci_dev = to_pci_dev(ab->dev); 456 457 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO, 458 msi_addr_lo); 459 460 if (test_bit(ATH11K_PCI_FLAG_IS_MSI_64, &ab_pci->flags)) { 461 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI, 462 msi_addr_hi); 463 } else { 464 *msi_addr_hi = 0; 465 } 466 } 467 468 int ath11k_pci_get_user_msi_assignment(struct ath11k_pci *ab_pci, char *user_name, 469 int *num_vectors, u32 *user_base_data, 470 u32 *base_vector) 471 { 472 struct ath11k_base *ab = ab_pci->ab; 473 const struct ath11k_msi_config *msi_config = ab_pci->msi_config; 474 int idx; 475 476 for (idx = 0; idx < msi_config->total_users; idx++) { 477 if (strcmp(user_name, msi_config->users[idx].name) == 0) { 478 *num_vectors = msi_config->users[idx].num_vectors; 479 *user_base_data = msi_config->users[idx].base_vector 480 + ab_pci->msi_ep_base_data; 481 *base_vector = msi_config->users[idx].base_vector; 482 483 ath11k_dbg(ab, ATH11K_DBG_PCI, "Assign MSI to user: %s, num_vectors: %d, user_base_data: %u, base_vector: %u\n", 484 user_name, *num_vectors, *user_base_data, 485 *base_vector); 486 487 return 0; 488 } 489 } 490 491 ath11k_err(ab, "Failed to find MSI assignment for %s!\n", user_name); 492 493 return -EINVAL; 494 } 495 496 static void ath11k_pci_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id, 497 u32 *msi_idx) 498 { 499 u32 i, msi_data_idx; 500 501 for (i = 0, msi_data_idx = 0; i < ab->hw_params.ce_count; i++) { 502 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 503 continue; 504 505 if (ce_id == i) 506 break; 507 508 msi_data_idx++; 509 } 510 *msi_idx = msi_data_idx; 511 } 512 513 static int ath11k_get_user_msi_assignment(struct ath11k_base *ab, char *user_name, 514 int *num_vectors, u32 *user_base_data, 515 u32 *base_vector) 516 { 517 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 518 519 return ath11k_pci_get_user_msi_assignment(ab_pci, user_name, 520 num_vectors, user_base_data, 521 base_vector); 522 } 523 524 static void ath11k_pci_free_ext_irq(struct ath11k_base *ab) 525 { 526 int i, j; 527 528 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 529 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 530 531 for (j = 0; j < irq_grp->num_irq; j++) 532 free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp); 533 534 netif_napi_del(&irq_grp->napi); 535 } 536 } 537 538 static void ath11k_pci_free_irq(struct ath11k_base *ab) 539 { 540 int i, irq_idx; 541 542 for (i = 0; i < ab->hw_params.ce_count; i++) { 543 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 544 continue; 545 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i; 546 free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]); 547 } 548 549 ath11k_pci_free_ext_irq(ab); 550 } 551 552 static void ath11k_pci_ce_irq_enable(struct ath11k_base *ab, u16 ce_id) 553 { 554 u32 irq_idx; 555 556 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_id; 557 enable_irq(ab->irq_num[irq_idx]); 558 } 559 560 static void ath11k_pci_ce_irq_disable(struct ath11k_base *ab, u16 ce_id) 561 { 562 u32 irq_idx; 563 564 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_id; 565 disable_irq_nosync(ab->irq_num[irq_idx]); 566 } 567 568 static void ath11k_pci_ce_irqs_disable(struct ath11k_base *ab) 569 { 570 int i; 571 572 for (i = 0; i < ab->hw_params.ce_count; i++) { 573 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 574 continue; 575 ath11k_pci_ce_irq_disable(ab, i); 576 } 577 } 578 579 static void ath11k_pci_sync_ce_irqs(struct ath11k_base *ab) 580 { 581 int i; 582 int irq_idx; 583 584 for (i = 0; i < ab->hw_params.ce_count; i++) { 585 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 586 continue; 587 588 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i; 589 synchronize_irq(ab->irq_num[irq_idx]); 590 } 591 } 592 593 static void ath11k_pci_ce_tasklet(struct tasklet_struct *t) 594 { 595 struct ath11k_ce_pipe *ce_pipe = from_tasklet(ce_pipe, t, intr_tq); 596 597 ath11k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num); 598 599 ath11k_pci_ce_irq_enable(ce_pipe->ab, ce_pipe->pipe_num); 600 } 601 602 static irqreturn_t ath11k_pci_ce_interrupt_handler(int irq, void *arg) 603 { 604 struct ath11k_ce_pipe *ce_pipe = arg; 605 606 /* last interrupt received for this CE */ 607 ce_pipe->timestamp = jiffies; 608 609 ath11k_pci_ce_irq_disable(ce_pipe->ab, ce_pipe->pipe_num); 610 tasklet_schedule(&ce_pipe->intr_tq); 611 612 return IRQ_HANDLED; 613 } 614 615 static void ath11k_pci_ext_grp_disable(struct ath11k_ext_irq_grp *irq_grp) 616 { 617 int i; 618 619 for (i = 0; i < irq_grp->num_irq; i++) 620 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 621 } 622 623 static void __ath11k_pci_ext_irq_disable(struct ath11k_base *sc) 624 { 625 int i; 626 627 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 628 struct ath11k_ext_irq_grp *irq_grp = &sc->ext_irq_grp[i]; 629 630 ath11k_pci_ext_grp_disable(irq_grp); 631 632 napi_synchronize(&irq_grp->napi); 633 napi_disable(&irq_grp->napi); 634 } 635 } 636 637 static void ath11k_pci_ext_grp_enable(struct ath11k_ext_irq_grp *irq_grp) 638 { 639 int i; 640 641 for (i = 0; i < irq_grp->num_irq; i++) 642 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]); 643 } 644 645 static void ath11k_pci_ext_irq_enable(struct ath11k_base *ab) 646 { 647 int i; 648 649 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 650 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 651 652 napi_enable(&irq_grp->napi); 653 ath11k_pci_ext_grp_enable(irq_grp); 654 } 655 } 656 657 static void ath11k_pci_sync_ext_irqs(struct ath11k_base *ab) 658 { 659 int i, j, irq_idx; 660 661 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 662 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 663 664 for (j = 0; j < irq_grp->num_irq; j++) { 665 irq_idx = irq_grp->irqs[j]; 666 synchronize_irq(ab->irq_num[irq_idx]); 667 } 668 } 669 } 670 671 static void ath11k_pci_ext_irq_disable(struct ath11k_base *ab) 672 { 673 __ath11k_pci_ext_irq_disable(ab); 674 ath11k_pci_sync_ext_irqs(ab); 675 } 676 677 static int ath11k_pci_ext_grp_napi_poll(struct napi_struct *napi, int budget) 678 { 679 struct ath11k_ext_irq_grp *irq_grp = container_of(napi, 680 struct ath11k_ext_irq_grp, 681 napi); 682 struct ath11k_base *ab = irq_grp->ab; 683 int work_done; 684 685 work_done = ath11k_dp_service_srng(ab, irq_grp, budget); 686 if (work_done < budget) { 687 napi_complete_done(napi, work_done); 688 ath11k_pci_ext_grp_enable(irq_grp); 689 } 690 691 if (work_done > budget) 692 work_done = budget; 693 694 return work_done; 695 } 696 697 static irqreturn_t ath11k_pci_ext_interrupt_handler(int irq, void *arg) 698 { 699 struct ath11k_ext_irq_grp *irq_grp = arg; 700 701 ath11k_dbg(irq_grp->ab, ATH11K_DBG_PCI, "ext irq:%d\n", irq); 702 703 /* last interrupt received for this group */ 704 irq_grp->timestamp = jiffies; 705 706 ath11k_pci_ext_grp_disable(irq_grp); 707 708 napi_schedule(&irq_grp->napi); 709 710 return IRQ_HANDLED; 711 } 712 713 static int ath11k_pci_ext_irq_config(struct ath11k_base *ab) 714 { 715 int i, j, ret, num_vectors = 0; 716 u32 user_base_data = 0, base_vector = 0, base_idx; 717 718 base_idx = ATH11K_PCI_IRQ_CE0_OFFSET + CE_COUNT_MAX; 719 ret = ath11k_pci_get_user_msi_assignment(ath11k_pci_priv(ab), "DP", 720 &num_vectors, 721 &user_base_data, 722 &base_vector); 723 if (ret < 0) 724 return ret; 725 726 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) { 727 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i]; 728 u32 num_irq = 0; 729 730 irq_grp->ab = ab; 731 irq_grp->grp_id = i; 732 init_dummy_netdev(&irq_grp->napi_ndev); 733 netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi, 734 ath11k_pci_ext_grp_napi_poll, NAPI_POLL_WEIGHT); 735 736 if (ab->hw_params.ring_mask->tx[i] || 737 ab->hw_params.ring_mask->rx[i] || 738 ab->hw_params.ring_mask->rx_err[i] || 739 ab->hw_params.ring_mask->rx_wbm_rel[i] || 740 ab->hw_params.ring_mask->reo_status[i] || 741 ab->hw_params.ring_mask->rxdma2host[i] || 742 ab->hw_params.ring_mask->host2rxdma[i] || 743 ab->hw_params.ring_mask->rx_mon_status[i]) { 744 num_irq = 1; 745 } 746 747 irq_grp->num_irq = num_irq; 748 irq_grp->irqs[0] = base_idx + i; 749 750 for (j = 0; j < irq_grp->num_irq; j++) { 751 int irq_idx = irq_grp->irqs[j]; 752 int vector = (i % num_vectors) + base_vector; 753 int irq = ath11k_pci_get_msi_irq(ab->dev, vector); 754 755 ab->irq_num[irq_idx] = irq; 756 757 ath11k_dbg(ab, ATH11K_DBG_PCI, 758 "irq:%d group:%d\n", irq, i); 759 760 irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY); 761 ret = request_irq(irq, ath11k_pci_ext_interrupt_handler, 762 IRQF_SHARED, 763 "DP_EXT_IRQ", irq_grp); 764 if (ret) { 765 ath11k_err(ab, "failed request irq %d: %d\n", 766 vector, ret); 767 return ret; 768 } 769 770 disable_irq_nosync(ab->irq_num[irq_idx]); 771 } 772 } 773 774 return 0; 775 } 776 777 static int ath11k_pci_config_irq(struct ath11k_base *ab) 778 { 779 struct ath11k_ce_pipe *ce_pipe; 780 u32 msi_data_start; 781 u32 msi_data_count, msi_data_idx; 782 u32 msi_irq_start; 783 unsigned int msi_data; 784 int irq, i, ret, irq_idx; 785 786 ret = ath11k_pci_get_user_msi_assignment(ath11k_pci_priv(ab), 787 "CE", &msi_data_count, 788 &msi_data_start, &msi_irq_start); 789 if (ret) 790 return ret; 791 792 /* Configure CE irqs */ 793 for (i = 0, msi_data_idx = 0; i < ab->hw_params.ce_count; i++) { 794 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 795 continue; 796 797 msi_data = (msi_data_idx % msi_data_count) + msi_irq_start; 798 irq = ath11k_pci_get_msi_irq(ab->dev, msi_data); 799 ce_pipe = &ab->ce.ce_pipe[i]; 800 801 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i; 802 803 tasklet_setup(&ce_pipe->intr_tq, ath11k_pci_ce_tasklet); 804 805 ret = request_irq(irq, ath11k_pci_ce_interrupt_handler, 806 IRQF_SHARED, irq_name[irq_idx], 807 ce_pipe); 808 if (ret) { 809 ath11k_err(ab, "failed to request irq %d: %d\n", 810 irq_idx, ret); 811 return ret; 812 } 813 814 ab->irq_num[irq_idx] = irq; 815 msi_data_idx++; 816 817 ath11k_pci_ce_irq_disable(ab, i); 818 } 819 820 ret = ath11k_pci_ext_irq_config(ab); 821 if (ret) 822 return ret; 823 824 return 0; 825 } 826 827 static void ath11k_pci_init_qmi_ce_config(struct ath11k_base *ab) 828 { 829 struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg; 830 831 cfg->tgt_ce = ab->hw_params.target_ce_config; 832 cfg->tgt_ce_len = ab->hw_params.target_ce_count; 833 834 cfg->svc_to_ce_map = ab->hw_params.svc_to_ce_map; 835 cfg->svc_to_ce_map_len = ab->hw_params.svc_to_ce_map_len; 836 ab->qmi.service_ins_id = ab->hw_params.qmi_service_ins_id; 837 838 ath11k_ce_get_shadow_config(ab, &cfg->shadow_reg_v2, 839 &cfg->shadow_reg_v2_len); 840 } 841 842 static void ath11k_pci_ce_irqs_enable(struct ath11k_base *ab) 843 { 844 int i; 845 846 for (i = 0; i < ab->hw_params.ce_count; i++) { 847 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 848 continue; 849 ath11k_pci_ce_irq_enable(ab, i); 850 } 851 } 852 853 static int ath11k_pci_enable_msi(struct ath11k_pci *ab_pci) 854 { 855 struct ath11k_base *ab = ab_pci->ab; 856 const struct ath11k_msi_config *msi_config = ab_pci->msi_config; 857 struct msi_desc *msi_desc; 858 int num_vectors; 859 int ret; 860 861 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev, 862 msi_config->total_vectors, 863 msi_config->total_vectors, 864 PCI_IRQ_MSI); 865 if (num_vectors != msi_config->total_vectors) { 866 ath11k_err(ab, "failed to get %d MSI vectors, only %d available", 867 msi_config->total_vectors, num_vectors); 868 869 if (num_vectors >= 0) 870 return -EINVAL; 871 else 872 return num_vectors; 873 } 874 875 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq); 876 if (!msi_desc) { 877 ath11k_err(ab, "msi_desc is NULL!\n"); 878 ret = -EINVAL; 879 goto free_msi_vector; 880 } 881 882 ab_pci->msi_ep_base_data = msi_desc->msg.data; 883 if (msi_desc->msi_attrib.is_64) 884 set_bit(ATH11K_PCI_FLAG_IS_MSI_64, &ab_pci->flags); 885 886 ath11k_dbg(ab, ATH11K_DBG_PCI, "msi base data is %d\n", ab_pci->msi_ep_base_data); 887 888 return 0; 889 890 free_msi_vector: 891 pci_free_irq_vectors(ab_pci->pdev); 892 893 return ret; 894 } 895 896 static void ath11k_pci_disable_msi(struct ath11k_pci *ab_pci) 897 { 898 pci_free_irq_vectors(ab_pci->pdev); 899 } 900 901 static int ath11k_pci_claim(struct ath11k_pci *ab_pci, struct pci_dev *pdev) 902 { 903 struct ath11k_base *ab = ab_pci->ab; 904 u16 device_id; 905 int ret = 0; 906 907 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id); 908 if (device_id != ab_pci->dev_id) { 909 ath11k_err(ab, "pci device id mismatch: 0x%x 0x%x\n", 910 device_id, ab_pci->dev_id); 911 ret = -EIO; 912 goto out; 913 } 914 915 ret = pci_assign_resource(pdev, ATH11K_PCI_BAR_NUM); 916 if (ret) { 917 ath11k_err(ab, "failed to assign pci resource: %d\n", ret); 918 goto out; 919 } 920 921 ret = pci_enable_device(pdev); 922 if (ret) { 923 ath11k_err(ab, "failed to enable pci device: %d\n", ret); 924 goto out; 925 } 926 927 ret = pci_request_region(pdev, ATH11K_PCI_BAR_NUM, "ath11k_pci"); 928 if (ret) { 929 ath11k_err(ab, "failed to request pci region: %d\n", ret); 930 goto disable_device; 931 } 932 933 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(ATH11K_PCI_DMA_MASK)); 934 if (ret) { 935 ath11k_err(ab, "failed to set pci dma mask to %d: %d\n", 936 ATH11K_PCI_DMA_MASK, ret); 937 goto release_region; 938 } 939 940 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(ATH11K_PCI_DMA_MASK)); 941 if (ret) { 942 ath11k_err(ab, "failed to set pci consistent dma mask to %d: %d\n", 943 ATH11K_PCI_DMA_MASK, ret); 944 goto release_region; 945 } 946 947 pci_set_master(pdev); 948 949 ab->mem_len = pci_resource_len(pdev, ATH11K_PCI_BAR_NUM); 950 ab->mem = pci_iomap(pdev, ATH11K_PCI_BAR_NUM, 0); 951 if (!ab->mem) { 952 ath11k_err(ab, "failed to map pci bar %d\n", ATH11K_PCI_BAR_NUM); 953 ret = -EIO; 954 goto clear_master; 955 } 956 957 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot pci_mem 0x%pK\n", ab->mem); 958 return 0; 959 960 clear_master: 961 pci_clear_master(pdev); 962 release_region: 963 pci_release_region(pdev, ATH11K_PCI_BAR_NUM); 964 disable_device: 965 pci_disable_device(pdev); 966 out: 967 return ret; 968 } 969 970 static void ath11k_pci_free_region(struct ath11k_pci *ab_pci) 971 { 972 struct ath11k_base *ab = ab_pci->ab; 973 struct pci_dev *pci_dev = ab_pci->pdev; 974 975 pci_iounmap(pci_dev, ab->mem); 976 ab->mem = NULL; 977 pci_clear_master(pci_dev); 978 pci_release_region(pci_dev, ATH11K_PCI_BAR_NUM); 979 if (pci_is_enabled(pci_dev)) 980 pci_disable_device(pci_dev); 981 } 982 983 static void ath11k_pci_aspm_disable(struct ath11k_pci *ab_pci) 984 { 985 struct ath11k_base *ab = ab_pci->ab; 986 987 pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL, 988 &ab_pci->link_ctl); 989 990 ath11k_dbg(ab, ATH11K_DBG_PCI, "pci link_ctl 0x%04x L0s %d L1 %d\n", 991 ab_pci->link_ctl, 992 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S), 993 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1)); 994 995 /* disable L0s and L1 */ 996 pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL, 997 ab_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC); 998 999 set_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags); 1000 } 1001 1002 static void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci) 1003 { 1004 if (test_and_clear_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags)) 1005 pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL, 1006 ab_pci->link_ctl); 1007 } 1008 1009 static int ath11k_pci_power_up(struct ath11k_base *ab) 1010 { 1011 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 1012 int ret; 1013 1014 ab_pci->register_window = 0; 1015 clear_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags); 1016 ath11k_pci_sw_reset(ab_pci->ab, true); 1017 1018 /* Disable ASPM during firmware download due to problems switching 1019 * to AMSS state. 1020 */ 1021 ath11k_pci_aspm_disable(ab_pci); 1022 1023 ret = ath11k_mhi_start(ab_pci); 1024 if (ret) { 1025 ath11k_err(ab, "failed to start mhi: %d\n", ret); 1026 return ret; 1027 } 1028 1029 if (ab->bus_params.static_window_map) 1030 ath11k_pci_select_static_window(ab_pci); 1031 1032 return 0; 1033 } 1034 1035 static void ath11k_pci_power_down(struct ath11k_base *ab) 1036 { 1037 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 1038 1039 /* restore aspm in case firmware bootup fails */ 1040 ath11k_pci_aspm_restore(ab_pci); 1041 1042 ath11k_pci_force_wake(ab_pci->ab); 1043 ath11k_mhi_stop(ab_pci); 1044 clear_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags); 1045 ath11k_pci_sw_reset(ab_pci->ab, false); 1046 } 1047 1048 static int ath11k_pci_hif_suspend(struct ath11k_base *ab) 1049 { 1050 struct ath11k_pci *ar_pci = ath11k_pci_priv(ab); 1051 1052 ath11k_mhi_suspend(ar_pci); 1053 1054 return 0; 1055 } 1056 1057 static int ath11k_pci_hif_resume(struct ath11k_base *ab) 1058 { 1059 struct ath11k_pci *ar_pci = ath11k_pci_priv(ab); 1060 1061 ath11k_mhi_resume(ar_pci); 1062 1063 return 0; 1064 } 1065 1066 static void ath11k_pci_kill_tasklets(struct ath11k_base *ab) 1067 { 1068 int i; 1069 1070 for (i = 0; i < ab->hw_params.ce_count; i++) { 1071 struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i]; 1072 1073 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR) 1074 continue; 1075 1076 tasklet_kill(&ce_pipe->intr_tq); 1077 } 1078 } 1079 1080 static void ath11k_pci_ce_irq_disable_sync(struct ath11k_base *ab) 1081 { 1082 ath11k_pci_ce_irqs_disable(ab); 1083 ath11k_pci_sync_ce_irqs(ab); 1084 ath11k_pci_kill_tasklets(ab); 1085 } 1086 1087 static void ath11k_pci_stop(struct ath11k_base *ab) 1088 { 1089 ath11k_pci_ce_irq_disable_sync(ab); 1090 ath11k_ce_cleanup_pipes(ab); 1091 } 1092 1093 static int ath11k_pci_start(struct ath11k_base *ab) 1094 { 1095 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 1096 1097 set_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags); 1098 1099 ath11k_pci_aspm_restore(ab_pci); 1100 1101 ath11k_pci_ce_irqs_enable(ab); 1102 ath11k_ce_rx_post_buf(ab); 1103 1104 return 0; 1105 } 1106 1107 static void ath11k_pci_hif_ce_irq_enable(struct ath11k_base *ab) 1108 { 1109 ath11k_pci_ce_irqs_enable(ab); 1110 } 1111 1112 static void ath11k_pci_hif_ce_irq_disable(struct ath11k_base *ab) 1113 { 1114 ath11k_pci_ce_irq_disable_sync(ab); 1115 } 1116 1117 static int ath11k_pci_map_service_to_pipe(struct ath11k_base *ab, u16 service_id, 1118 u8 *ul_pipe, u8 *dl_pipe) 1119 { 1120 const struct service_to_pipe *entry; 1121 bool ul_set = false, dl_set = false; 1122 int i; 1123 1124 for (i = 0; i < ab->hw_params.svc_to_ce_map_len; i++) { 1125 entry = &ab->hw_params.svc_to_ce_map[i]; 1126 1127 if (__le32_to_cpu(entry->service_id) != service_id) 1128 continue; 1129 1130 switch (__le32_to_cpu(entry->pipedir)) { 1131 case PIPEDIR_NONE: 1132 break; 1133 case PIPEDIR_IN: 1134 WARN_ON(dl_set); 1135 *dl_pipe = __le32_to_cpu(entry->pipenum); 1136 dl_set = true; 1137 break; 1138 case PIPEDIR_OUT: 1139 WARN_ON(ul_set); 1140 *ul_pipe = __le32_to_cpu(entry->pipenum); 1141 ul_set = true; 1142 break; 1143 case PIPEDIR_INOUT: 1144 WARN_ON(dl_set); 1145 WARN_ON(ul_set); 1146 *dl_pipe = __le32_to_cpu(entry->pipenum); 1147 *ul_pipe = __le32_to_cpu(entry->pipenum); 1148 dl_set = true; 1149 ul_set = true; 1150 break; 1151 } 1152 } 1153 1154 if (WARN_ON(!ul_set || !dl_set)) 1155 return -ENOENT; 1156 1157 return 0; 1158 } 1159 1160 static const struct ath11k_hif_ops ath11k_pci_hif_ops = { 1161 .start = ath11k_pci_start, 1162 .stop = ath11k_pci_stop, 1163 .read32 = ath11k_pci_read32, 1164 .write32 = ath11k_pci_write32, 1165 .power_down = ath11k_pci_power_down, 1166 .power_up = ath11k_pci_power_up, 1167 .suspend = ath11k_pci_hif_suspend, 1168 .resume = ath11k_pci_hif_resume, 1169 .irq_enable = ath11k_pci_ext_irq_enable, 1170 .irq_disable = ath11k_pci_ext_irq_disable, 1171 .get_msi_address = ath11k_pci_get_msi_address, 1172 .get_user_msi_vector = ath11k_get_user_msi_assignment, 1173 .map_service_to_pipe = ath11k_pci_map_service_to_pipe, 1174 .ce_irq_enable = ath11k_pci_hif_ce_irq_enable, 1175 .ce_irq_disable = ath11k_pci_hif_ce_irq_disable, 1176 .get_ce_msi_idx = ath11k_pci_get_ce_msi_idx, 1177 }; 1178 1179 static int ath11k_pci_probe(struct pci_dev *pdev, 1180 const struct pci_device_id *pci_dev) 1181 { 1182 struct ath11k_base *ab; 1183 struct ath11k_pci *ab_pci; 1184 u32 soc_hw_version, soc_hw_version_major, soc_hw_version_minor; 1185 int ret; 1186 1187 ab = ath11k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH11K_BUS_PCI, 1188 &ath11k_pci_bus_params); 1189 if (!ab) { 1190 dev_err(&pdev->dev, "failed to allocate ath11k base\n"); 1191 return -ENOMEM; 1192 } 1193 1194 ab->dev = &pdev->dev; 1195 pci_set_drvdata(pdev, ab); 1196 ab_pci = ath11k_pci_priv(ab); 1197 ab_pci->dev_id = pci_dev->device; 1198 ab_pci->ab = ab; 1199 ab_pci->pdev = pdev; 1200 ab->hif.ops = &ath11k_pci_hif_ops; 1201 pci_set_drvdata(pdev, ab); 1202 spin_lock_init(&ab_pci->window_lock); 1203 1204 ret = ath11k_pci_claim(ab_pci, pdev); 1205 if (ret) { 1206 ath11k_err(ab, "failed to claim device: %d\n", ret); 1207 goto err_free_core; 1208 } 1209 1210 switch (pci_dev->device) { 1211 case QCA6390_DEVICE_ID: 1212 soc_hw_version = ath11k_pci_read32(ab, TCSR_SOC_HW_VERSION); 1213 soc_hw_version_major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK, 1214 soc_hw_version); 1215 soc_hw_version_minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK, 1216 soc_hw_version); 1217 1218 ath11k_dbg(ab, ATH11K_DBG_PCI, "pci tcsr_soc_hw_version major %d minor %d\n", 1219 soc_hw_version_major, soc_hw_version_minor); 1220 1221 switch (soc_hw_version_major) { 1222 case 2: 1223 ab->hw_rev = ATH11K_HW_QCA6390_HW20; 1224 break; 1225 default: 1226 dev_err(&pdev->dev, "Unsupported QCA6390 SOC hardware version: %d %d\n", 1227 soc_hw_version_major, soc_hw_version_minor); 1228 ret = -EOPNOTSUPP; 1229 goto err_pci_free_region; 1230 } 1231 ab_pci->msi_config = &ath11k_msi_config[0]; 1232 break; 1233 case QCN9074_DEVICE_ID: 1234 ab_pci->msi_config = &ath11k_msi_config[1]; 1235 ab->bus_params.static_window_map = true; 1236 ab->hw_rev = ATH11K_HW_QCN9074_HW10; 1237 break; 1238 default: 1239 dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n", 1240 pci_dev->device); 1241 ret = -EOPNOTSUPP; 1242 goto err_pci_free_region; 1243 } 1244 1245 ret = ath11k_pci_enable_msi(ab_pci); 1246 if (ret) { 1247 ath11k_err(ab, "failed to enable msi: %d\n", ret); 1248 goto err_pci_free_region; 1249 } 1250 1251 ret = ath11k_core_pre_init(ab); 1252 if (ret) 1253 goto err_pci_disable_msi; 1254 1255 ret = ath11k_mhi_register(ab_pci); 1256 if (ret) { 1257 ath11k_err(ab, "failed to register mhi: %d\n", ret); 1258 goto err_pci_disable_msi; 1259 } 1260 1261 ret = ath11k_hal_srng_init(ab); 1262 if (ret) 1263 goto err_mhi_unregister; 1264 1265 ret = ath11k_ce_alloc_pipes(ab); 1266 if (ret) { 1267 ath11k_err(ab, "failed to allocate ce pipes: %d\n", ret); 1268 goto err_hal_srng_deinit; 1269 } 1270 1271 ath11k_pci_init_qmi_ce_config(ab); 1272 1273 ret = ath11k_pci_config_irq(ab); 1274 if (ret) { 1275 ath11k_err(ab, "failed to config irq: %d\n", ret); 1276 goto err_ce_free; 1277 } 1278 1279 ret = ath11k_core_init(ab); 1280 if (ret) { 1281 ath11k_err(ab, "failed to init core: %d\n", ret); 1282 goto err_free_irq; 1283 } 1284 return 0; 1285 1286 err_free_irq: 1287 ath11k_pci_free_irq(ab); 1288 1289 err_ce_free: 1290 ath11k_ce_free_pipes(ab); 1291 1292 err_hal_srng_deinit: 1293 ath11k_hal_srng_deinit(ab); 1294 1295 err_mhi_unregister: 1296 ath11k_mhi_unregister(ab_pci); 1297 1298 err_pci_disable_msi: 1299 ath11k_pci_disable_msi(ab_pci); 1300 1301 err_pci_free_region: 1302 ath11k_pci_free_region(ab_pci); 1303 1304 err_free_core: 1305 ath11k_core_free(ab); 1306 1307 return ret; 1308 } 1309 1310 static void ath11k_pci_remove(struct pci_dev *pdev) 1311 { 1312 struct ath11k_base *ab = pci_get_drvdata(pdev); 1313 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab); 1314 1315 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) { 1316 ath11k_pci_power_down(ab); 1317 ath11k_debugfs_soc_destroy(ab); 1318 ath11k_qmi_deinit_service(ab); 1319 goto qmi_fail; 1320 } 1321 1322 set_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags); 1323 1324 ath11k_core_deinit(ab); 1325 1326 qmi_fail: 1327 ath11k_mhi_unregister(ab_pci); 1328 1329 ath11k_pci_free_irq(ab); 1330 ath11k_pci_disable_msi(ab_pci); 1331 ath11k_pci_free_region(ab_pci); 1332 1333 ath11k_hal_srng_deinit(ab); 1334 ath11k_ce_free_pipes(ab); 1335 ath11k_core_free(ab); 1336 } 1337 1338 static void ath11k_pci_shutdown(struct pci_dev *pdev) 1339 { 1340 struct ath11k_base *ab = pci_get_drvdata(pdev); 1341 1342 ath11k_pci_power_down(ab); 1343 } 1344 1345 static __maybe_unused int ath11k_pci_pm_suspend(struct device *dev) 1346 { 1347 struct ath11k_base *ab = dev_get_drvdata(dev); 1348 int ret; 1349 1350 ret = ath11k_core_suspend(ab); 1351 if (ret) 1352 ath11k_warn(ab, "failed to suspend core: %d\n", ret); 1353 1354 return ret; 1355 } 1356 1357 static __maybe_unused int ath11k_pci_pm_resume(struct device *dev) 1358 { 1359 struct ath11k_base *ab = dev_get_drvdata(dev); 1360 int ret; 1361 1362 ret = ath11k_core_resume(ab); 1363 if (ret) 1364 ath11k_warn(ab, "failed to resume core: %d\n", ret); 1365 1366 return ret; 1367 } 1368 1369 static SIMPLE_DEV_PM_OPS(ath11k_pci_pm_ops, 1370 ath11k_pci_pm_suspend, 1371 ath11k_pci_pm_resume); 1372 1373 static struct pci_driver ath11k_pci_driver = { 1374 .name = "ath11k_pci", 1375 .id_table = ath11k_pci_id_table, 1376 .probe = ath11k_pci_probe, 1377 .remove = ath11k_pci_remove, 1378 .shutdown = ath11k_pci_shutdown, 1379 #ifdef CONFIG_PM 1380 .driver.pm = &ath11k_pci_pm_ops, 1381 #endif 1382 }; 1383 1384 static int ath11k_pci_init(void) 1385 { 1386 int ret; 1387 1388 ret = pci_register_driver(&ath11k_pci_driver); 1389 if (ret) 1390 pr_err("failed to register ath11k pci driver: %d\n", 1391 ret); 1392 1393 return ret; 1394 } 1395 module_init(ath11k_pci_init); 1396 1397 static void ath11k_pci_exit(void) 1398 { 1399 pci_unregister_driver(&ath11k_pci_driver); 1400 } 1401 1402 module_exit(ath11k_pci_exit); 1403 1404 MODULE_DESCRIPTION("Driver support for Qualcomm Technologies 802.11ax WLAN PCIe devices"); 1405 MODULE_LICENSE("Dual BSD/GPL"); 1406 1407 /* QCA639x 2.0 firmware files */ 1408 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/" ATH11K_BOARD_API2_FILE); 1409 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/" ATH11K_AMSS_FILE); 1410 MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/" ATH11K_M3_FILE); 1411