1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* Copyright (c) 2020 The Linux Foundation. All rights reserved. */ 3 4 #include <linux/msi.h> 5 #include <linux/pci.h> 6 #include <linux/of.h> 7 #include <linux/of_address.h> 8 #include <linux/ioport.h> 9 10 #include "core.h" 11 #include "debug.h" 12 #include "mhi.h" 13 #include "pci.h" 14 15 #define MHI_TIMEOUT_DEFAULT_MS 90000 16 #define RDDM_DUMP_SIZE 0x420000 17 18 static struct mhi_channel_config ath11k_mhi_channels_qca6390[] = { 19 { 20 .num = 0, 21 .name = "LOOPBACK", 22 .num_elements = 32, 23 .event_ring = 0, 24 .dir = DMA_TO_DEVICE, 25 .ee_mask = 0x4, 26 .pollcfg = 0, 27 .doorbell = MHI_DB_BRST_DISABLE, 28 .lpm_notify = false, 29 .offload_channel = false, 30 .doorbell_mode_switch = false, 31 .auto_queue = false, 32 }, 33 { 34 .num = 1, 35 .name = "LOOPBACK", 36 .num_elements = 32, 37 .event_ring = 0, 38 .dir = DMA_FROM_DEVICE, 39 .ee_mask = 0x4, 40 .pollcfg = 0, 41 .doorbell = MHI_DB_BRST_DISABLE, 42 .lpm_notify = false, 43 .offload_channel = false, 44 .doorbell_mode_switch = false, 45 .auto_queue = false, 46 }, 47 { 48 .num = 20, 49 .name = "IPCR", 50 .num_elements = 64, 51 .event_ring = 1, 52 .dir = DMA_TO_DEVICE, 53 .ee_mask = 0x4, 54 .pollcfg = 0, 55 .doorbell = MHI_DB_BRST_DISABLE, 56 .lpm_notify = false, 57 .offload_channel = false, 58 .doorbell_mode_switch = false, 59 .auto_queue = false, 60 }, 61 { 62 .num = 21, 63 .name = "IPCR", 64 .num_elements = 64, 65 .event_ring = 1, 66 .dir = DMA_FROM_DEVICE, 67 .ee_mask = 0x4, 68 .pollcfg = 0, 69 .doorbell = MHI_DB_BRST_DISABLE, 70 .lpm_notify = false, 71 .offload_channel = false, 72 .doorbell_mode_switch = false, 73 .auto_queue = true, 74 }, 75 }; 76 77 static struct mhi_event_config ath11k_mhi_events_qca6390[] = { 78 { 79 .num_elements = 32, 80 .irq_moderation_ms = 0, 81 .irq = 1, 82 .mode = MHI_DB_BRST_DISABLE, 83 .data_type = MHI_ER_CTRL, 84 .hardware_event = false, 85 .client_managed = false, 86 .offload_channel = false, 87 }, 88 { 89 .num_elements = 256, 90 .irq_moderation_ms = 1, 91 .irq = 2, 92 .mode = MHI_DB_BRST_DISABLE, 93 .priority = 1, 94 .hardware_event = false, 95 .client_managed = false, 96 .offload_channel = false, 97 }, 98 }; 99 100 static struct mhi_controller_config ath11k_mhi_config_qca6390 = { 101 .max_channels = 128, 102 .timeout_ms = 2000, 103 .use_bounce_buf = false, 104 .buf_len = 0, 105 .num_channels = ARRAY_SIZE(ath11k_mhi_channels_qca6390), 106 .ch_cfg = ath11k_mhi_channels_qca6390, 107 .num_events = ARRAY_SIZE(ath11k_mhi_events_qca6390), 108 .event_cfg = ath11k_mhi_events_qca6390, 109 }; 110 111 static struct mhi_channel_config ath11k_mhi_channels_qcn9074[] = { 112 { 113 .num = 0, 114 .name = "LOOPBACK", 115 .num_elements = 32, 116 .event_ring = 1, 117 .dir = DMA_TO_DEVICE, 118 .ee_mask = 0x14, 119 .pollcfg = 0, 120 .doorbell = MHI_DB_BRST_DISABLE, 121 .lpm_notify = false, 122 .offload_channel = false, 123 .doorbell_mode_switch = false, 124 .auto_queue = false, 125 }, 126 { 127 .num = 1, 128 .name = "LOOPBACK", 129 .num_elements = 32, 130 .event_ring = 1, 131 .dir = DMA_FROM_DEVICE, 132 .ee_mask = 0x14, 133 .pollcfg = 0, 134 .doorbell = MHI_DB_BRST_DISABLE, 135 .lpm_notify = false, 136 .offload_channel = false, 137 .doorbell_mode_switch = false, 138 .auto_queue = false, 139 }, 140 { 141 .num = 20, 142 .name = "IPCR", 143 .num_elements = 32, 144 .event_ring = 1, 145 .dir = DMA_TO_DEVICE, 146 .ee_mask = 0x14, 147 .pollcfg = 0, 148 .doorbell = MHI_DB_BRST_DISABLE, 149 .lpm_notify = false, 150 .offload_channel = false, 151 .doorbell_mode_switch = false, 152 .auto_queue = false, 153 }, 154 { 155 .num = 21, 156 .name = "IPCR", 157 .num_elements = 32, 158 .event_ring = 1, 159 .dir = DMA_FROM_DEVICE, 160 .ee_mask = 0x14, 161 .pollcfg = 0, 162 .doorbell = MHI_DB_BRST_DISABLE, 163 .lpm_notify = false, 164 .offload_channel = false, 165 .doorbell_mode_switch = false, 166 .auto_queue = true, 167 }, 168 }; 169 170 static struct mhi_event_config ath11k_mhi_events_qcn9074[] = { 171 { 172 .num_elements = 32, 173 .irq_moderation_ms = 0, 174 .irq = 1, 175 .data_type = MHI_ER_CTRL, 176 .mode = MHI_DB_BRST_DISABLE, 177 .hardware_event = false, 178 .client_managed = false, 179 .offload_channel = false, 180 }, 181 { 182 .num_elements = 256, 183 .irq_moderation_ms = 1, 184 .irq = 2, 185 .mode = MHI_DB_BRST_DISABLE, 186 .priority = 1, 187 .hardware_event = false, 188 .client_managed = false, 189 .offload_channel = false, 190 }, 191 }; 192 193 static struct mhi_controller_config ath11k_mhi_config_qcn9074 = { 194 .max_channels = 30, 195 .timeout_ms = 10000, 196 .use_bounce_buf = false, 197 .buf_len = 0, 198 .num_channels = ARRAY_SIZE(ath11k_mhi_channels_qcn9074), 199 .ch_cfg = ath11k_mhi_channels_qcn9074, 200 .num_events = ARRAY_SIZE(ath11k_mhi_events_qcn9074), 201 .event_cfg = ath11k_mhi_events_qcn9074, 202 }; 203 204 void ath11k_mhi_set_mhictrl_reset(struct ath11k_base *ab) 205 { 206 u32 val; 207 208 val = ath11k_pci_read32(ab, MHISTATUS); 209 210 ath11k_dbg(ab, ATH11K_DBG_PCI, "MHISTATUS 0x%x\n", val); 211 212 /* Observed on QCA6390 that after SOC_GLOBAL_RESET, MHISTATUS 213 * has SYSERR bit set and thus need to set MHICTRL_RESET 214 * to clear SYSERR. 215 */ 216 ath11k_pci_write32(ab, MHICTRL, MHICTRL_RESET_MASK); 217 218 mdelay(10); 219 } 220 221 static void ath11k_mhi_reset_txvecdb(struct ath11k_base *ab) 222 { 223 ath11k_pci_write32(ab, PCIE_TXVECDB, 0); 224 } 225 226 static void ath11k_mhi_reset_txvecstatus(struct ath11k_base *ab) 227 { 228 ath11k_pci_write32(ab, PCIE_TXVECSTATUS, 0); 229 } 230 231 static void ath11k_mhi_reset_rxvecdb(struct ath11k_base *ab) 232 { 233 ath11k_pci_write32(ab, PCIE_RXVECDB, 0); 234 } 235 236 static void ath11k_mhi_reset_rxvecstatus(struct ath11k_base *ab) 237 { 238 ath11k_pci_write32(ab, PCIE_RXVECSTATUS, 0); 239 } 240 241 void ath11k_mhi_clear_vector(struct ath11k_base *ab) 242 { 243 ath11k_mhi_reset_txvecdb(ab); 244 ath11k_mhi_reset_txvecstatus(ab); 245 ath11k_mhi_reset_rxvecdb(ab); 246 ath11k_mhi_reset_rxvecstatus(ab); 247 } 248 249 static int ath11k_mhi_get_msi(struct ath11k_pci *ab_pci) 250 { 251 struct ath11k_base *ab = ab_pci->ab; 252 u32 user_base_data, base_vector; 253 int ret, num_vectors, i; 254 int *irq; 255 unsigned int msi_data; 256 257 ret = ath11k_pci_get_user_msi_assignment(ab_pci, 258 "MHI", &num_vectors, 259 &user_base_data, &base_vector); 260 if (ret) 261 return ret; 262 263 ath11k_dbg(ab, ATH11K_DBG_PCI, "Number of assigned MSI for MHI is %d, base vector is %d\n", 264 num_vectors, base_vector); 265 266 irq = kcalloc(num_vectors, sizeof(int), GFP_KERNEL); 267 if (!irq) 268 return -ENOMEM; 269 270 for (i = 0; i < num_vectors; i++) { 271 msi_data = base_vector; 272 273 if (test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 274 msi_data += i; 275 276 irq[i] = ath11k_pci_get_msi_irq(ab->dev, 277 msi_data); 278 } 279 280 ab_pci->mhi_ctrl->irq = irq; 281 ab_pci->mhi_ctrl->nr_irqs = num_vectors; 282 283 return 0; 284 } 285 286 static int ath11k_mhi_op_runtime_get(struct mhi_controller *mhi_cntrl) 287 { 288 return 0; 289 } 290 291 static void ath11k_mhi_op_runtime_put(struct mhi_controller *mhi_cntrl) 292 { 293 } 294 295 static void ath11k_mhi_op_status_cb(struct mhi_controller *mhi_cntrl, 296 enum mhi_callback cb) 297 { 298 struct ath11k_base *ab = dev_get_drvdata(mhi_cntrl->cntrl_dev); 299 300 switch (cb) { 301 case MHI_CB_SYS_ERROR: 302 ath11k_warn(ab, "firmware crashed: MHI_CB_SYS_ERROR\n"); 303 break; 304 default: 305 break; 306 } 307 } 308 309 static int ath11k_mhi_op_read_reg(struct mhi_controller *mhi_cntrl, 310 void __iomem *addr, 311 u32 *out) 312 { 313 *out = readl(addr); 314 315 return 0; 316 } 317 318 static void ath11k_mhi_op_write_reg(struct mhi_controller *mhi_cntrl, 319 void __iomem *addr, 320 u32 val) 321 { 322 writel(val, addr); 323 } 324 325 static int ath11k_mhi_read_addr_from_dt(struct mhi_controller *mhi_ctrl) 326 { 327 struct device_node *np; 328 struct resource res; 329 int ret; 330 331 np = of_find_node_by_type(NULL, "memory"); 332 if (!np) 333 return -ENOENT; 334 335 ret = of_address_to_resource(np, 0, &res); 336 of_node_put(np); 337 if (ret) 338 return ret; 339 340 mhi_ctrl->iova_start = res.start + 0x1000000; 341 mhi_ctrl->iova_stop = res.end; 342 343 return 0; 344 } 345 346 int ath11k_mhi_register(struct ath11k_pci *ab_pci) 347 { 348 struct ath11k_base *ab = ab_pci->ab; 349 struct mhi_controller *mhi_ctrl; 350 struct mhi_controller_config *ath11k_mhi_config; 351 int ret; 352 353 mhi_ctrl = mhi_alloc_controller(); 354 if (!mhi_ctrl) 355 return -ENOMEM; 356 357 ath11k_core_create_firmware_path(ab, ATH11K_AMSS_FILE, 358 ab_pci->amss_path, 359 sizeof(ab_pci->amss_path)); 360 361 ab_pci->mhi_ctrl = mhi_ctrl; 362 mhi_ctrl->cntrl_dev = ab->dev; 363 mhi_ctrl->fw_image = ab_pci->amss_path; 364 mhi_ctrl->regs = ab->mem; 365 mhi_ctrl->reg_len = ab->mem_len; 366 367 ret = ath11k_mhi_get_msi(ab_pci); 368 if (ret) { 369 ath11k_err(ab, "failed to get msi for mhi\n"); 370 mhi_free_controller(mhi_ctrl); 371 return ret; 372 } 373 374 if (!test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 375 mhi_ctrl->irq_flags = IRQF_SHARED | IRQF_NOBALANCING; 376 377 if (test_bit(ATH11K_FLAG_FIXED_MEM_RGN, &ab->dev_flags)) { 378 ret = ath11k_mhi_read_addr_from_dt(mhi_ctrl); 379 if (ret < 0) 380 return ret; 381 } else { 382 mhi_ctrl->iova_start = 0; 383 mhi_ctrl->iova_stop = 0xFFFFFFFF; 384 } 385 386 mhi_ctrl->rddm_size = RDDM_DUMP_SIZE; 387 mhi_ctrl->sbl_size = SZ_512K; 388 mhi_ctrl->seg_len = SZ_512K; 389 mhi_ctrl->fbc_download = true; 390 mhi_ctrl->runtime_get = ath11k_mhi_op_runtime_get; 391 mhi_ctrl->runtime_put = ath11k_mhi_op_runtime_put; 392 mhi_ctrl->status_cb = ath11k_mhi_op_status_cb; 393 mhi_ctrl->read_reg = ath11k_mhi_op_read_reg; 394 mhi_ctrl->write_reg = ath11k_mhi_op_write_reg; 395 396 switch (ab->hw_rev) { 397 case ATH11K_HW_QCN9074_HW10: 398 ath11k_mhi_config = &ath11k_mhi_config_qcn9074; 399 break; 400 case ATH11K_HW_QCA6390_HW20: 401 case ATH11K_HW_WCN6855_HW20: 402 case ATH11K_HW_WCN6855_HW21: 403 ath11k_mhi_config = &ath11k_mhi_config_qca6390; 404 break; 405 default: 406 ath11k_err(ab, "failed assign mhi_config for unknown hw rev %d\n", 407 ab->hw_rev); 408 mhi_free_controller(mhi_ctrl); 409 return -EINVAL; 410 } 411 412 ret = mhi_register_controller(mhi_ctrl, ath11k_mhi_config); 413 if (ret) { 414 ath11k_err(ab, "failed to register to mhi bus, err = %d\n", ret); 415 mhi_free_controller(mhi_ctrl); 416 return ret; 417 } 418 419 return 0; 420 } 421 422 void ath11k_mhi_unregister(struct ath11k_pci *ab_pci) 423 { 424 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl; 425 426 mhi_unregister_controller(mhi_ctrl); 427 kfree(mhi_ctrl->irq); 428 mhi_free_controller(mhi_ctrl); 429 } 430 431 static char *ath11k_mhi_state_to_str(enum ath11k_mhi_state mhi_state) 432 { 433 switch (mhi_state) { 434 case ATH11K_MHI_INIT: 435 return "INIT"; 436 case ATH11K_MHI_DEINIT: 437 return "DEINIT"; 438 case ATH11K_MHI_POWER_ON: 439 return "POWER_ON"; 440 case ATH11K_MHI_POWER_OFF: 441 return "POWER_OFF"; 442 case ATH11K_MHI_FORCE_POWER_OFF: 443 return "FORCE_POWER_OFF"; 444 case ATH11K_MHI_SUSPEND: 445 return "SUSPEND"; 446 case ATH11K_MHI_RESUME: 447 return "RESUME"; 448 case ATH11K_MHI_TRIGGER_RDDM: 449 return "TRIGGER_RDDM"; 450 case ATH11K_MHI_RDDM_DONE: 451 return "RDDM_DONE"; 452 default: 453 return "UNKNOWN"; 454 } 455 }; 456 457 static void ath11k_mhi_set_state_bit(struct ath11k_pci *ab_pci, 458 enum ath11k_mhi_state mhi_state) 459 { 460 struct ath11k_base *ab = ab_pci->ab; 461 462 switch (mhi_state) { 463 case ATH11K_MHI_INIT: 464 set_bit(ATH11K_MHI_INIT, &ab_pci->mhi_state); 465 break; 466 case ATH11K_MHI_DEINIT: 467 clear_bit(ATH11K_MHI_INIT, &ab_pci->mhi_state); 468 break; 469 case ATH11K_MHI_POWER_ON: 470 set_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state); 471 break; 472 case ATH11K_MHI_POWER_OFF: 473 case ATH11K_MHI_FORCE_POWER_OFF: 474 clear_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state); 475 clear_bit(ATH11K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state); 476 clear_bit(ATH11K_MHI_RDDM_DONE, &ab_pci->mhi_state); 477 break; 478 case ATH11K_MHI_SUSPEND: 479 set_bit(ATH11K_MHI_SUSPEND, &ab_pci->mhi_state); 480 break; 481 case ATH11K_MHI_RESUME: 482 clear_bit(ATH11K_MHI_SUSPEND, &ab_pci->mhi_state); 483 break; 484 case ATH11K_MHI_TRIGGER_RDDM: 485 set_bit(ATH11K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state); 486 break; 487 case ATH11K_MHI_RDDM_DONE: 488 set_bit(ATH11K_MHI_RDDM_DONE, &ab_pci->mhi_state); 489 break; 490 default: 491 ath11k_err(ab, "unhandled mhi state (%d)\n", mhi_state); 492 } 493 } 494 495 static int ath11k_mhi_check_state_bit(struct ath11k_pci *ab_pci, 496 enum ath11k_mhi_state mhi_state) 497 { 498 struct ath11k_base *ab = ab_pci->ab; 499 500 switch (mhi_state) { 501 case ATH11K_MHI_INIT: 502 if (!test_bit(ATH11K_MHI_INIT, &ab_pci->mhi_state)) 503 return 0; 504 break; 505 case ATH11K_MHI_DEINIT: 506 case ATH11K_MHI_POWER_ON: 507 if (test_bit(ATH11K_MHI_INIT, &ab_pci->mhi_state) && 508 !test_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state)) 509 return 0; 510 break; 511 case ATH11K_MHI_FORCE_POWER_OFF: 512 if (test_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state)) 513 return 0; 514 break; 515 case ATH11K_MHI_POWER_OFF: 516 case ATH11K_MHI_SUSPEND: 517 if (test_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state) && 518 !test_bit(ATH11K_MHI_SUSPEND, &ab_pci->mhi_state)) 519 return 0; 520 break; 521 case ATH11K_MHI_RESUME: 522 if (test_bit(ATH11K_MHI_SUSPEND, &ab_pci->mhi_state)) 523 return 0; 524 break; 525 case ATH11K_MHI_TRIGGER_RDDM: 526 if (test_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state) && 527 !test_bit(ATH11K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state)) 528 return 0; 529 break; 530 case ATH11K_MHI_RDDM_DONE: 531 return 0; 532 default: 533 ath11k_err(ab, "unhandled mhi state: %s(%d)\n", 534 ath11k_mhi_state_to_str(mhi_state), mhi_state); 535 } 536 537 ath11k_err(ab, "failed to set mhi state %s(%d) in current mhi state (0x%lx)\n", 538 ath11k_mhi_state_to_str(mhi_state), mhi_state, 539 ab_pci->mhi_state); 540 541 return -EINVAL; 542 } 543 544 static int ath11k_mhi_set_state(struct ath11k_pci *ab_pci, 545 enum ath11k_mhi_state mhi_state) 546 { 547 struct ath11k_base *ab = ab_pci->ab; 548 int ret; 549 550 ret = ath11k_mhi_check_state_bit(ab_pci, mhi_state); 551 if (ret) 552 goto out; 553 554 ath11k_dbg(ab, ATH11K_DBG_PCI, "setting mhi state: %s(%d)\n", 555 ath11k_mhi_state_to_str(mhi_state), mhi_state); 556 557 switch (mhi_state) { 558 case ATH11K_MHI_INIT: 559 ret = mhi_prepare_for_power_up(ab_pci->mhi_ctrl); 560 break; 561 case ATH11K_MHI_DEINIT: 562 mhi_unprepare_after_power_down(ab_pci->mhi_ctrl); 563 ret = 0; 564 break; 565 case ATH11K_MHI_POWER_ON: 566 ret = mhi_sync_power_up(ab_pci->mhi_ctrl); 567 break; 568 case ATH11K_MHI_POWER_OFF: 569 mhi_power_down(ab_pci->mhi_ctrl, true); 570 ret = 0; 571 break; 572 case ATH11K_MHI_FORCE_POWER_OFF: 573 mhi_power_down(ab_pci->mhi_ctrl, false); 574 ret = 0; 575 break; 576 case ATH11K_MHI_SUSPEND: 577 ret = mhi_pm_suspend(ab_pci->mhi_ctrl); 578 break; 579 case ATH11K_MHI_RESUME: 580 /* Do force MHI resume as some devices like QCA6390, WCN6855 581 * are not in M3 state but they are functional. So just ignore 582 * the MHI state while resuming. 583 */ 584 ret = mhi_pm_resume_force(ab_pci->mhi_ctrl); 585 break; 586 case ATH11K_MHI_TRIGGER_RDDM: 587 ret = mhi_force_rddm_mode(ab_pci->mhi_ctrl); 588 break; 589 case ATH11K_MHI_RDDM_DONE: 590 break; 591 default: 592 ath11k_err(ab, "unhandled MHI state (%d)\n", mhi_state); 593 ret = -EINVAL; 594 } 595 596 if (ret) 597 goto out; 598 599 ath11k_mhi_set_state_bit(ab_pci, mhi_state); 600 601 return 0; 602 603 out: 604 ath11k_err(ab, "failed to set mhi state: %s(%d)\n", 605 ath11k_mhi_state_to_str(mhi_state), mhi_state); 606 return ret; 607 } 608 609 int ath11k_mhi_start(struct ath11k_pci *ab_pci) 610 { 611 int ret; 612 613 ab_pci->mhi_ctrl->timeout_ms = MHI_TIMEOUT_DEFAULT_MS; 614 615 ret = ath11k_mhi_set_state(ab_pci, ATH11K_MHI_INIT); 616 if (ret) 617 goto out; 618 619 ret = ath11k_mhi_set_state(ab_pci, ATH11K_MHI_POWER_ON); 620 if (ret) 621 goto out; 622 623 return 0; 624 625 out: 626 return ret; 627 } 628 629 void ath11k_mhi_stop(struct ath11k_pci *ab_pci) 630 { 631 ath11k_mhi_set_state(ab_pci, ATH11K_MHI_POWER_OFF); 632 ath11k_mhi_set_state(ab_pci, ATH11K_MHI_DEINIT); 633 } 634 635 void ath11k_mhi_suspend(struct ath11k_pci *ab_pci) 636 { 637 ath11k_mhi_set_state(ab_pci, ATH11K_MHI_SUSPEND); 638 } 639 640 void ath11k_mhi_resume(struct ath11k_pci *ab_pci) 641 { 642 ath11k_mhi_set_state(ab_pci, ATH11K_MHI_RESUME); 643 } 644