1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/types.h> 7 #include <linux/bitops.h> 8 #include <linux/bitfield.h> 9 10 #include "core.h" 11 #include "ce.h" 12 #include "hif.h" 13 #include "hal.h" 14 #include "hw.h" 15 16 /* Map from pdev index to hw mac index */ 17 static u8 ath11k_hw_ipq8074_mac_from_pdev_id(int pdev_idx) 18 { 19 switch (pdev_idx) { 20 case 0: 21 return 0; 22 case 1: 23 return 2; 24 case 2: 25 return 1; 26 default: 27 return ATH11K_INVALID_HW_MAC_ID; 28 } 29 } 30 31 static u8 ath11k_hw_ipq6018_mac_from_pdev_id(int pdev_idx) 32 { 33 return pdev_idx; 34 } 35 36 static void ath11k_hw_ipq8074_tx_mesh_enable(struct ath11k_base *ab, 37 struct hal_tcl_data_cmd *tcl_cmd) 38 { 39 tcl_cmd->info2 |= FIELD_PREP(HAL_IPQ8074_TCL_DATA_CMD_INFO2_MESH_ENABLE, 40 true); 41 } 42 43 static void ath11k_hw_qcn9074_tx_mesh_enable(struct ath11k_base *ab, 44 struct hal_tcl_data_cmd *tcl_cmd) 45 { 46 tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE, 47 true); 48 } 49 50 static void ath11k_hw_wcn6855_tx_mesh_enable(struct ath11k_base *ab, 51 struct hal_tcl_data_cmd *tcl_cmd) 52 { 53 tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE, 54 true); 55 } 56 57 static void ath11k_init_wmi_config_qca6390(struct ath11k_base *ab, 58 struct target_resource_config *config) 59 { 60 config->num_vdevs = 4; 61 config->num_peers = 16; 62 config->num_tids = 32; 63 64 config->num_offload_peers = 3; 65 config->num_offload_reorder_buffs = 3; 66 config->num_peer_keys = TARGET_NUM_PEER_KEYS; 67 config->ast_skid_limit = TARGET_AST_SKID_LIMIT; 68 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 69 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 70 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; 71 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI; 72 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; 73 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; 74 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; 75 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS; 76 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV; 77 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV; 78 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES; 79 config->num_mcast_groups = 0; 80 config->num_mcast_table_elems = 0; 81 config->mcast2ucast_mode = 0; 82 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE; 83 config->num_wds_entries = 0; 84 config->dma_burst_size = 0; 85 config->rx_skip_defrag_timeout_dup_detection_check = 0; 86 config->vow_config = TARGET_VOW_CONFIG; 87 config->gtk_offload_max_vdev = 2; 88 config->num_msdu_desc = 0x400; 89 config->beacon_tx_offload_max_vdev = 2; 90 config->rx_batchmode = TARGET_RX_BATCHMODE; 91 92 config->peer_map_unmap_v2_support = 0; 93 config->use_pdev_id = 1; 94 config->max_frag_entries = 0xa; 95 config->num_tdls_vdevs = 0x1; 96 config->num_tdls_conn_table_entries = 8; 97 config->beacon_tx_offload_max_vdev = 0x2; 98 config->num_multicast_filter_entries = 0x20; 99 config->num_wow_filters = 0x16; 100 config->num_keep_alive_pattern = 0; 101 config->flag1 |= WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64; 102 } 103 104 static void ath11k_hw_ipq8074_reo_setup(struct ath11k_base *ab) 105 { 106 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; 107 u32 val; 108 /* Each hash entry uses three bits to map to a particular ring. */ 109 u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 | 110 HAL_HASH_ROUTING_RING_SW2 << 3 | 111 HAL_HASH_ROUTING_RING_SW3 << 6 | 112 HAL_HASH_ROUTING_RING_SW4 << 9 | 113 HAL_HASH_ROUTING_RING_SW1 << 12 | 114 HAL_HASH_ROUTING_RING_SW2 << 15 | 115 HAL_HASH_ROUTING_RING_SW3 << 18 | 116 HAL_HASH_ROUTING_RING_SW4 << 21; 117 118 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); 119 120 val &= ~HAL_REO1_GEN_ENABLE_FRAG_DST_RING; 121 val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_FRAG_DST_RING, 122 HAL_SRNG_RING_ID_REO2SW1) | 123 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) | 124 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1); 125 ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); 126 127 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab), 128 HAL_DEFAULT_REO_TIMEOUT_USEC); 129 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab), 130 HAL_DEFAULT_REO_TIMEOUT_USEC); 131 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab), 132 HAL_DEFAULT_REO_TIMEOUT_USEC); 133 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab), 134 HAL_DEFAULT_REO_TIMEOUT_USEC); 135 136 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0, 137 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 138 ring_hash_map)); 139 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1, 140 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 141 ring_hash_map)); 142 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, 143 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 144 ring_hash_map)); 145 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, 146 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 147 ring_hash_map)); 148 } 149 150 static void ath11k_init_wmi_config_ipq8074(struct ath11k_base *ab, 151 struct target_resource_config *config) 152 { 153 config->num_vdevs = ab->num_radios * TARGET_NUM_VDEVS; 154 155 if (ab->num_radios == 2) { 156 config->num_peers = TARGET_NUM_PEERS(DBS); 157 config->num_tids = TARGET_NUM_TIDS(DBS); 158 } else if (ab->num_radios == 3) { 159 config->num_peers = TARGET_NUM_PEERS(DBS_SBS); 160 config->num_tids = TARGET_NUM_TIDS(DBS_SBS); 161 } else { 162 /* Control should not reach here */ 163 config->num_peers = TARGET_NUM_PEERS(SINGLE); 164 config->num_tids = TARGET_NUM_TIDS(SINGLE); 165 } 166 config->num_offload_peers = TARGET_NUM_OFFLD_PEERS; 167 config->num_offload_reorder_buffs = TARGET_NUM_OFFLD_REORDER_BUFFS; 168 config->num_peer_keys = TARGET_NUM_PEER_KEYS; 169 config->ast_skid_limit = TARGET_AST_SKID_LIMIT; 170 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 171 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 172 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; 173 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI; 174 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; 175 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; 176 177 if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) 178 config->rx_decap_mode = TARGET_DECAP_MODE_RAW; 179 else 180 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; 181 182 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS; 183 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV; 184 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV; 185 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES; 186 config->num_mcast_groups = TARGET_NUM_MCAST_GROUPS; 187 config->num_mcast_table_elems = TARGET_NUM_MCAST_TABLE_ELEMS; 188 config->mcast2ucast_mode = TARGET_MCAST2UCAST_MODE; 189 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE; 190 config->num_wds_entries = TARGET_NUM_WDS_ENTRIES; 191 config->dma_burst_size = TARGET_DMA_BURST_SIZE; 192 config->rx_skip_defrag_timeout_dup_detection_check = 193 TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK; 194 config->vow_config = TARGET_VOW_CONFIG; 195 config->gtk_offload_max_vdev = TARGET_GTK_OFFLOAD_MAX_VDEV; 196 config->num_msdu_desc = TARGET_NUM_MSDU_DESC; 197 config->beacon_tx_offload_max_vdev = ab->num_radios * TARGET_MAX_BCN_OFFLD; 198 config->rx_batchmode = TARGET_RX_BATCHMODE; 199 config->peer_map_unmap_v2_support = 1; 200 config->twt_ap_pdev_count = ab->num_radios; 201 config->twt_ap_sta_count = 1000; 202 config->flag1 |= WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64; 203 } 204 205 static int ath11k_hw_mac_id_to_pdev_id_ipq8074(struct ath11k_hw_params *hw, 206 int mac_id) 207 { 208 return mac_id; 209 } 210 211 static int ath11k_hw_mac_id_to_srng_id_ipq8074(struct ath11k_hw_params *hw, 212 int mac_id) 213 { 214 return 0; 215 } 216 217 static int ath11k_hw_mac_id_to_pdev_id_qca6390(struct ath11k_hw_params *hw, 218 int mac_id) 219 { 220 return 0; 221 } 222 223 static int ath11k_hw_mac_id_to_srng_id_qca6390(struct ath11k_hw_params *hw, 224 int mac_id) 225 { 226 return mac_id; 227 } 228 229 static bool ath11k_hw_ipq8074_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 230 { 231 return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU, 232 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 233 } 234 235 static bool ath11k_hw_ipq8074_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 236 { 237 return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU, 238 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 239 } 240 241 static u8 ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 242 { 243 return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING, 244 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 245 } 246 247 static u8 *ath11k_hw_ipq8074_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 248 { 249 return desc->u.ipq8074.hdr_status; 250 } 251 252 static bool ath11k_hw_ipq8074_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 253 { 254 return __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1) & 255 RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID; 256 } 257 258 static u32 ath11k_hw_ipq8074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 259 { 260 return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE, 261 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2)); 262 } 263 264 static u8 ath11k_hw_ipq8074_rx_desc_get_decap_type(struct hal_rx_desc *desc) 265 { 266 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 267 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2)); 268 } 269 270 static u8 ath11k_hw_ipq8074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 271 { 272 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 273 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2)); 274 } 275 276 static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 277 { 278 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID, 279 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 280 } 281 282 static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 283 { 284 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID, 285 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 286 } 287 288 static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 289 { 290 return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM, 291 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 292 } 293 294 static u16 ath11k_hw_ipq8074_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 295 { 296 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 297 __le32_to_cpu(desc->u.ipq8074.msdu_start.info1)); 298 } 299 300 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 301 { 302 return FIELD_GET(RX_MSDU_START_INFO3_SGI, 303 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 304 } 305 306 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 307 { 308 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 309 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 310 } 311 312 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 313 { 314 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 315 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 316 } 317 318 static u32 ath11k_hw_ipq8074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 319 { 320 return __le32_to_cpu(desc->u.ipq8074.msdu_start.phy_meta_data); 321 } 322 323 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 324 { 325 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 326 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 327 } 328 329 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 330 { 331 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 332 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 333 } 334 335 static u8 ath11k_hw_ipq8074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 336 { 337 return FIELD_GET(RX_MPDU_START_INFO2_TID, 338 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2)); 339 } 340 341 static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 342 { 343 return __le16_to_cpu(desc->u.ipq8074.mpdu_start.sw_peer_id); 344 } 345 346 static void ath11k_hw_ipq8074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 347 struct hal_rx_desc *ldesc) 348 { 349 memcpy((u8 *)&fdesc->u.ipq8074.msdu_end, (u8 *)&ldesc->u.ipq8074.msdu_end, 350 sizeof(struct rx_msdu_end_ipq8074)); 351 memcpy((u8 *)&fdesc->u.ipq8074.attention, (u8 *)&ldesc->u.ipq8074.attention, 352 sizeof(struct rx_attention)); 353 memcpy((u8 *)&fdesc->u.ipq8074.mpdu_end, (u8 *)&ldesc->u.ipq8074.mpdu_end, 354 sizeof(struct rx_mpdu_end)); 355 } 356 357 static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 358 { 359 return FIELD_GET(HAL_TLV_HDR_TAG, 360 __le32_to_cpu(desc->u.ipq8074.mpdu_start_tag)); 361 } 362 363 static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 364 { 365 return __le16_to_cpu(desc->u.ipq8074.mpdu_start.phy_ppdu_id); 366 } 367 368 static void ath11k_hw_ipq8074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 369 { 370 u32 info = __le32_to_cpu(desc->u.ipq8074.msdu_start.info1); 371 372 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 373 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 374 375 desc->u.ipq8074.msdu_start.info1 = __cpu_to_le32(info); 376 } 377 378 static bool ath11k_hw_ipq8074_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc) 379 { 380 return __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1) & 381 RX_MPDU_START_INFO1_MAC_ADDR2_VALID; 382 } 383 384 static u8 *ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc) 385 { 386 return desc->u.ipq8074.mpdu_start.addr2; 387 } 388 389 static 390 struct rx_attention *ath11k_hw_ipq8074_rx_desc_get_attention(struct hal_rx_desc *desc) 391 { 392 return &desc->u.ipq8074.attention; 393 } 394 395 static u8 *ath11k_hw_ipq8074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 396 { 397 return &desc->u.ipq8074.msdu_payload[0]; 398 } 399 400 static bool ath11k_hw_qcn9074_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 401 { 402 return !!FIELD_GET(RX_MSDU_END_INFO4_FIRST_MSDU, 403 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 404 } 405 406 static bool ath11k_hw_qcn9074_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 407 { 408 return !!FIELD_GET(RX_MSDU_END_INFO4_LAST_MSDU, 409 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 410 } 411 412 static u8 ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 413 { 414 return FIELD_GET(RX_MSDU_END_INFO4_L3_HDR_PADDING, 415 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 416 } 417 418 static u8 *ath11k_hw_qcn9074_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 419 { 420 return desc->u.qcn9074.hdr_status; 421 } 422 423 static bool ath11k_hw_qcn9074_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 424 { 425 return __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11) & 426 RX_MPDU_START_INFO11_ENCRYPT_INFO_VALID; 427 } 428 429 static u32 ath11k_hw_qcn9074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 430 { 431 return FIELD_GET(RX_MPDU_START_INFO9_ENC_TYPE, 432 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9)); 433 } 434 435 static u8 ath11k_hw_qcn9074_rx_desc_get_decap_type(struct hal_rx_desc *desc) 436 { 437 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 438 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2)); 439 } 440 441 static u8 ath11k_hw_qcn9074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 442 { 443 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 444 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2)); 445 } 446 447 static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 448 { 449 return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_CTRL_VALID, 450 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 451 } 452 453 static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 454 { 455 return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_FCTRL_VALID, 456 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 457 } 458 459 static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 460 { 461 return FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_NUM, 462 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 463 } 464 465 static u16 ath11k_hw_qcn9074_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 466 { 467 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 468 __le32_to_cpu(desc->u.qcn9074.msdu_start.info1)); 469 } 470 471 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 472 { 473 return FIELD_GET(RX_MSDU_START_INFO3_SGI, 474 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 475 } 476 477 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 478 { 479 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 480 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 481 } 482 483 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 484 { 485 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 486 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 487 } 488 489 static u32 ath11k_hw_qcn9074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 490 { 491 return __le32_to_cpu(desc->u.qcn9074.msdu_start.phy_meta_data); 492 } 493 494 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 495 { 496 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 497 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 498 } 499 500 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 501 { 502 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 503 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 504 } 505 506 static u8 ath11k_hw_qcn9074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 507 { 508 return FIELD_GET(RX_MPDU_START_INFO9_TID, 509 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9)); 510 } 511 512 static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 513 { 514 return __le16_to_cpu(desc->u.qcn9074.mpdu_start.sw_peer_id); 515 } 516 517 static void ath11k_hw_qcn9074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 518 struct hal_rx_desc *ldesc) 519 { 520 memcpy((u8 *)&fdesc->u.qcn9074.msdu_end, (u8 *)&ldesc->u.qcn9074.msdu_end, 521 sizeof(struct rx_msdu_end_qcn9074)); 522 memcpy((u8 *)&fdesc->u.qcn9074.attention, (u8 *)&ldesc->u.qcn9074.attention, 523 sizeof(struct rx_attention)); 524 memcpy((u8 *)&fdesc->u.qcn9074.mpdu_end, (u8 *)&ldesc->u.qcn9074.mpdu_end, 525 sizeof(struct rx_mpdu_end)); 526 } 527 528 static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 529 { 530 return FIELD_GET(HAL_TLV_HDR_TAG, 531 __le32_to_cpu(desc->u.qcn9074.mpdu_start_tag)); 532 } 533 534 static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 535 { 536 return __le16_to_cpu(desc->u.qcn9074.mpdu_start.phy_ppdu_id); 537 } 538 539 static void ath11k_hw_qcn9074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 540 { 541 u32 info = __le32_to_cpu(desc->u.qcn9074.msdu_start.info1); 542 543 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 544 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 545 546 desc->u.qcn9074.msdu_start.info1 = __cpu_to_le32(info); 547 } 548 549 static 550 struct rx_attention *ath11k_hw_qcn9074_rx_desc_get_attention(struct hal_rx_desc *desc) 551 { 552 return &desc->u.qcn9074.attention; 553 } 554 555 static u8 *ath11k_hw_qcn9074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 556 { 557 return &desc->u.qcn9074.msdu_payload[0]; 558 } 559 560 static bool ath11k_hw_ipq9074_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc) 561 { 562 return __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11) & 563 RX_MPDU_START_INFO11_MAC_ADDR2_VALID; 564 } 565 566 static u8 *ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc) 567 { 568 return desc->u.qcn9074.mpdu_start.addr2; 569 } 570 571 static bool ath11k_hw_wcn6855_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 572 { 573 return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU_WCN6855, 574 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2)); 575 } 576 577 static bool ath11k_hw_wcn6855_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 578 { 579 return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU_WCN6855, 580 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2)); 581 } 582 583 static u8 ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 584 { 585 return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING, 586 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2)); 587 } 588 589 static u8 *ath11k_hw_wcn6855_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 590 { 591 return desc->u.wcn6855.hdr_status; 592 } 593 594 static bool ath11k_hw_wcn6855_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 595 { 596 return __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1) & 597 RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID; 598 } 599 600 static u32 ath11k_hw_wcn6855_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 601 { 602 return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE, 603 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info2)); 604 } 605 606 static u8 ath11k_hw_wcn6855_rx_desc_get_decap_type(struct hal_rx_desc *desc) 607 { 608 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 609 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2)); 610 } 611 612 static u8 ath11k_hw_wcn6855_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 613 { 614 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 615 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2)); 616 } 617 618 static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 619 { 620 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID, 621 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1)); 622 } 623 624 static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 625 { 626 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID, 627 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1)); 628 } 629 630 static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 631 { 632 return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM, 633 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1)); 634 } 635 636 static u16 ath11k_hw_wcn6855_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 637 { 638 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 639 __le32_to_cpu(desc->u.wcn6855.msdu_start.info1)); 640 } 641 642 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 643 { 644 return FIELD_GET(RX_MSDU_START_INFO3_SGI, 645 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 646 } 647 648 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 649 { 650 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 651 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 652 } 653 654 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 655 { 656 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 657 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 658 } 659 660 static u32 ath11k_hw_wcn6855_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 661 { 662 return __le32_to_cpu(desc->u.wcn6855.msdu_start.phy_meta_data); 663 } 664 665 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 666 { 667 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 668 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 669 } 670 671 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 672 { 673 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 674 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 675 } 676 677 static u8 ath11k_hw_wcn6855_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 678 { 679 return FIELD_GET(RX_MPDU_START_INFO2_TID_WCN6855, 680 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info2)); 681 } 682 683 static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 684 { 685 return __le16_to_cpu(desc->u.wcn6855.mpdu_start.sw_peer_id); 686 } 687 688 static void ath11k_hw_wcn6855_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 689 struct hal_rx_desc *ldesc) 690 { 691 memcpy((u8 *)&fdesc->u.wcn6855.msdu_end, (u8 *)&ldesc->u.wcn6855.msdu_end, 692 sizeof(struct rx_msdu_end_wcn6855)); 693 memcpy((u8 *)&fdesc->u.wcn6855.attention, (u8 *)&ldesc->u.wcn6855.attention, 694 sizeof(struct rx_attention)); 695 memcpy((u8 *)&fdesc->u.wcn6855.mpdu_end, (u8 *)&ldesc->u.wcn6855.mpdu_end, 696 sizeof(struct rx_mpdu_end)); 697 } 698 699 static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 700 { 701 return FIELD_GET(HAL_TLV_HDR_TAG, 702 __le32_to_cpu(desc->u.wcn6855.mpdu_start_tag)); 703 } 704 705 static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 706 { 707 return __le16_to_cpu(desc->u.wcn6855.mpdu_start.phy_ppdu_id); 708 } 709 710 static void ath11k_hw_wcn6855_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 711 { 712 u32 info = __le32_to_cpu(desc->u.wcn6855.msdu_start.info1); 713 714 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 715 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 716 717 desc->u.wcn6855.msdu_start.info1 = __cpu_to_le32(info); 718 } 719 720 static 721 struct rx_attention *ath11k_hw_wcn6855_rx_desc_get_attention(struct hal_rx_desc *desc) 722 { 723 return &desc->u.wcn6855.attention; 724 } 725 726 static u8 *ath11k_hw_wcn6855_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 727 { 728 return &desc->u.wcn6855.msdu_payload[0]; 729 } 730 731 static bool ath11k_hw_wcn6855_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc) 732 { 733 return __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1) & 734 RX_MPDU_START_INFO1_MAC_ADDR2_VALID; 735 } 736 737 static u8 *ath11k_hw_wcn6855_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc) 738 { 739 return desc->u.wcn6855.mpdu_start.addr2; 740 } 741 742 static void ath11k_hw_wcn6855_reo_setup(struct ath11k_base *ab) 743 { 744 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; 745 u32 val; 746 /* Each hash entry uses four bits to map to a particular ring. */ 747 u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 | 748 HAL_HASH_ROUTING_RING_SW2 << 4 | 749 HAL_HASH_ROUTING_RING_SW3 << 8 | 750 HAL_HASH_ROUTING_RING_SW4 << 12 | 751 HAL_HASH_ROUTING_RING_SW1 << 16 | 752 HAL_HASH_ROUTING_RING_SW2 << 20 | 753 HAL_HASH_ROUTING_RING_SW3 << 24 | 754 HAL_HASH_ROUTING_RING_SW4 << 28; 755 756 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); 757 val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) | 758 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1); 759 ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); 760 761 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_MISC_CTL); 762 val &= ~HAL_REO1_MISC_CTL_FRAGMENT_DST_RING; 763 val |= FIELD_PREP(HAL_REO1_MISC_CTL_FRAGMENT_DST_RING, HAL_SRNG_RING_ID_REO2SW1); 764 ath11k_hif_write32(ab, reo_base + HAL_REO1_MISC_CTL, val); 765 766 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab), 767 HAL_DEFAULT_REO_TIMEOUT_USEC); 768 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab), 769 HAL_DEFAULT_REO_TIMEOUT_USEC); 770 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab), 771 HAL_DEFAULT_REO_TIMEOUT_USEC); 772 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab), 773 HAL_DEFAULT_REO_TIMEOUT_USEC); 774 775 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, 776 ring_hash_map); 777 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, 778 ring_hash_map); 779 } 780 781 static u16 ath11k_hw_ipq8074_mpdu_info_get_peerid(u8 *tlv_data) 782 { 783 u16 peer_id = 0; 784 struct hal_rx_mpdu_info *mpdu_info = 785 (struct hal_rx_mpdu_info *)tlv_data; 786 787 peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID, 788 __le32_to_cpu(mpdu_info->info0)); 789 790 return peer_id; 791 } 792 793 static u16 ath11k_hw_wcn6855_mpdu_info_get_peerid(u8 *tlv_data) 794 { 795 u16 peer_id = 0; 796 struct hal_rx_mpdu_info_wcn6855 *mpdu_info = 797 (struct hal_rx_mpdu_info_wcn6855 *)tlv_data; 798 799 peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID_WCN6855, 800 __le32_to_cpu(mpdu_info->info0)); 801 return peer_id; 802 } 803 804 const struct ath11k_hw_ops ipq8074_ops = { 805 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 806 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 807 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 808 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 809 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 810 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 811 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 812 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 813 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 814 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 815 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 816 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 817 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 818 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 819 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 820 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 821 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 822 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 823 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 824 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 825 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 826 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 827 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 828 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 829 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 830 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 831 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 832 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 833 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 834 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 835 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 836 .reo_setup = ath11k_hw_ipq8074_reo_setup, 837 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 838 .rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid, 839 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2, 840 }; 841 842 const struct ath11k_hw_ops ipq6018_ops = { 843 .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 844 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 845 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 846 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 847 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 848 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 849 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 850 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 851 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 852 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 853 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 854 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 855 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 856 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 857 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 858 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 859 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 860 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 861 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 862 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 863 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 864 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 865 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 866 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 867 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 868 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 869 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 870 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 871 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 872 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 873 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 874 .reo_setup = ath11k_hw_ipq8074_reo_setup, 875 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 876 .rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid, 877 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2, 878 }; 879 880 const struct ath11k_hw_ops qca6390_ops = { 881 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 882 .wmi_init_config = ath11k_init_wmi_config_qca6390, 883 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390, 884 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390, 885 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 886 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 887 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 888 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 889 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 890 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 891 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 892 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 893 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 894 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 895 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 896 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 897 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 898 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 899 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 900 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 901 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 902 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 903 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 904 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 905 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 906 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 907 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 908 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 909 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 910 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 911 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 912 .reo_setup = ath11k_hw_ipq8074_reo_setup, 913 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 914 .rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid, 915 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2, 916 }; 917 918 const struct ath11k_hw_ops qcn9074_ops = { 919 .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 920 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 921 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 922 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 923 .tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable, 924 .rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu, 925 .rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu, 926 .rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes, 927 .rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status, 928 .rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid, 929 .rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type, 930 .rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type, 931 .rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl, 932 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld, 933 .rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid, 934 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no, 935 .rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len, 936 .rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi, 937 .rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs, 938 .rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw, 939 .rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq, 940 .rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type, 941 .rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss, 942 .rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid, 943 .rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id, 944 .rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end, 945 .rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag, 946 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id, 947 .rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len, 948 .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention, 949 .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload, 950 .reo_setup = ath11k_hw_ipq8074_reo_setup, 951 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 952 .rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid, 953 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2, 954 }; 955 956 const struct ath11k_hw_ops wcn6855_ops = { 957 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 958 .wmi_init_config = ath11k_init_wmi_config_qca6390, 959 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390, 960 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390, 961 .tx_mesh_enable = ath11k_hw_wcn6855_tx_mesh_enable, 962 .rx_desc_get_first_msdu = ath11k_hw_wcn6855_rx_desc_get_first_msdu, 963 .rx_desc_get_last_msdu = ath11k_hw_wcn6855_rx_desc_get_last_msdu, 964 .rx_desc_get_l3_pad_bytes = ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes, 965 .rx_desc_get_hdr_status = ath11k_hw_wcn6855_rx_desc_get_hdr_status, 966 .rx_desc_encrypt_valid = ath11k_hw_wcn6855_rx_desc_encrypt_valid, 967 .rx_desc_get_encrypt_type = ath11k_hw_wcn6855_rx_desc_get_encrypt_type, 968 .rx_desc_get_decap_type = ath11k_hw_wcn6855_rx_desc_get_decap_type, 969 .rx_desc_get_mesh_ctl = ath11k_hw_wcn6855_rx_desc_get_mesh_ctl, 970 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld, 971 .rx_desc_get_mpdu_fc_valid = ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid, 972 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no, 973 .rx_desc_get_msdu_len = ath11k_hw_wcn6855_rx_desc_get_msdu_len, 974 .rx_desc_get_msdu_sgi = ath11k_hw_wcn6855_rx_desc_get_msdu_sgi, 975 .rx_desc_get_msdu_rate_mcs = ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs, 976 .rx_desc_get_msdu_rx_bw = ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw, 977 .rx_desc_get_msdu_freq = ath11k_hw_wcn6855_rx_desc_get_msdu_freq, 978 .rx_desc_get_msdu_pkt_type = ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type, 979 .rx_desc_get_msdu_nss = ath11k_hw_wcn6855_rx_desc_get_msdu_nss, 980 .rx_desc_get_mpdu_tid = ath11k_hw_wcn6855_rx_desc_get_mpdu_tid, 981 .rx_desc_get_mpdu_peer_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id, 982 .rx_desc_copy_attn_end_tlv = ath11k_hw_wcn6855_rx_desc_copy_attn_end, 983 .rx_desc_get_mpdu_start_tag = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag, 984 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id, 985 .rx_desc_set_msdu_len = ath11k_hw_wcn6855_rx_desc_set_msdu_len, 986 .rx_desc_get_attention = ath11k_hw_wcn6855_rx_desc_get_attention, 987 .rx_desc_get_msdu_payload = ath11k_hw_wcn6855_rx_desc_get_msdu_payload, 988 .reo_setup = ath11k_hw_wcn6855_reo_setup, 989 .mpdu_info_get_peerid = ath11k_hw_wcn6855_mpdu_info_get_peerid, 990 .rx_desc_mac_addr2_valid = ath11k_hw_wcn6855_rx_desc_mac_addr2_valid, 991 .rx_desc_mpdu_start_addr2 = ath11k_hw_wcn6855_rx_desc_mpdu_start_addr2, 992 }; 993 994 #define ATH11K_TX_RING_MASK_0 0x1 995 #define ATH11K_TX_RING_MASK_1 0x2 996 #define ATH11K_TX_RING_MASK_2 0x4 997 998 #define ATH11K_RX_RING_MASK_0 0x1 999 #define ATH11K_RX_RING_MASK_1 0x2 1000 #define ATH11K_RX_RING_MASK_2 0x4 1001 #define ATH11K_RX_RING_MASK_3 0x8 1002 1003 #define ATH11K_RX_ERR_RING_MASK_0 0x1 1004 1005 #define ATH11K_RX_WBM_REL_RING_MASK_0 0x1 1006 1007 #define ATH11K_REO_STATUS_RING_MASK_0 0x1 1008 1009 #define ATH11K_RXDMA2HOST_RING_MASK_0 0x1 1010 #define ATH11K_RXDMA2HOST_RING_MASK_1 0x2 1011 #define ATH11K_RXDMA2HOST_RING_MASK_2 0x4 1012 1013 #define ATH11K_HOST2RXDMA_RING_MASK_0 0x1 1014 #define ATH11K_HOST2RXDMA_RING_MASK_1 0x2 1015 #define ATH11K_HOST2RXDMA_RING_MASK_2 0x4 1016 1017 #define ATH11K_RX_MON_STATUS_RING_MASK_0 0x1 1018 #define ATH11K_RX_MON_STATUS_RING_MASK_1 0x2 1019 #define ATH11K_RX_MON_STATUS_RING_MASK_2 0x4 1020 1021 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074 = { 1022 .tx = { 1023 ATH11K_TX_RING_MASK_0, 1024 ATH11K_TX_RING_MASK_1, 1025 ATH11K_TX_RING_MASK_2, 1026 }, 1027 .rx_mon_status = { 1028 0, 0, 0, 0, 1029 ATH11K_RX_MON_STATUS_RING_MASK_0, 1030 ATH11K_RX_MON_STATUS_RING_MASK_1, 1031 ATH11K_RX_MON_STATUS_RING_MASK_2, 1032 }, 1033 .rx = { 1034 0, 0, 0, 0, 0, 0, 0, 1035 ATH11K_RX_RING_MASK_0, 1036 ATH11K_RX_RING_MASK_1, 1037 ATH11K_RX_RING_MASK_2, 1038 ATH11K_RX_RING_MASK_3, 1039 }, 1040 .rx_err = { 1041 ATH11K_RX_ERR_RING_MASK_0, 1042 }, 1043 .rx_wbm_rel = { 1044 ATH11K_RX_WBM_REL_RING_MASK_0, 1045 }, 1046 .reo_status = { 1047 ATH11K_REO_STATUS_RING_MASK_0, 1048 }, 1049 .rxdma2host = { 1050 ATH11K_RXDMA2HOST_RING_MASK_0, 1051 ATH11K_RXDMA2HOST_RING_MASK_1, 1052 ATH11K_RXDMA2HOST_RING_MASK_2, 1053 }, 1054 .host2rxdma = { 1055 ATH11K_HOST2RXDMA_RING_MASK_0, 1056 ATH11K_HOST2RXDMA_RING_MASK_1, 1057 ATH11K_HOST2RXDMA_RING_MASK_2, 1058 }, 1059 }; 1060 1061 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390 = { 1062 .tx = { 1063 ATH11K_TX_RING_MASK_0, 1064 ATH11K_TX_RING_MASK_1, 1065 ATH11K_TX_RING_MASK_2, 1066 }, 1067 .rx_mon_status = { 1068 0, 0, 0, 0, 1069 ATH11K_RX_MON_STATUS_RING_MASK_0, 1070 ATH11K_RX_MON_STATUS_RING_MASK_1, 1071 ATH11K_RX_MON_STATUS_RING_MASK_2, 1072 }, 1073 .rx = { 1074 0, 0, 0, 0, 0, 0, 0, 1075 ATH11K_RX_RING_MASK_0, 1076 ATH11K_RX_RING_MASK_1, 1077 ATH11K_RX_RING_MASK_2, 1078 ATH11K_RX_RING_MASK_3, 1079 }, 1080 .rx_err = { 1081 ATH11K_RX_ERR_RING_MASK_0, 1082 }, 1083 .rx_wbm_rel = { 1084 ATH11K_RX_WBM_REL_RING_MASK_0, 1085 }, 1086 .reo_status = { 1087 ATH11K_REO_STATUS_RING_MASK_0, 1088 }, 1089 .rxdma2host = { 1090 ATH11K_RXDMA2HOST_RING_MASK_0, 1091 ATH11K_RXDMA2HOST_RING_MASK_1, 1092 ATH11K_RXDMA2HOST_RING_MASK_2, 1093 }, 1094 .host2rxdma = { 1095 }, 1096 }; 1097 1098 /* Target firmware's Copy Engine configuration. */ 1099 const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq8074[] = { 1100 /* CE0: host->target HTC control and raw streams */ 1101 { 1102 .pipenum = __cpu_to_le32(0), 1103 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1104 .nentries = __cpu_to_le32(32), 1105 .nbytes_max = __cpu_to_le32(2048), 1106 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1107 .reserved = __cpu_to_le32(0), 1108 }, 1109 1110 /* CE1: target->host HTT + HTC control */ 1111 { 1112 .pipenum = __cpu_to_le32(1), 1113 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1114 .nentries = __cpu_to_le32(32), 1115 .nbytes_max = __cpu_to_le32(2048), 1116 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1117 .reserved = __cpu_to_le32(0), 1118 }, 1119 1120 /* CE2: target->host WMI */ 1121 { 1122 .pipenum = __cpu_to_le32(2), 1123 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1124 .nentries = __cpu_to_le32(32), 1125 .nbytes_max = __cpu_to_le32(2048), 1126 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1127 .reserved = __cpu_to_le32(0), 1128 }, 1129 1130 /* CE3: host->target WMI */ 1131 { 1132 .pipenum = __cpu_to_le32(3), 1133 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1134 .nentries = __cpu_to_le32(32), 1135 .nbytes_max = __cpu_to_le32(2048), 1136 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1137 .reserved = __cpu_to_le32(0), 1138 }, 1139 1140 /* CE4: host->target HTT */ 1141 { 1142 .pipenum = __cpu_to_le32(4), 1143 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1144 .nentries = __cpu_to_le32(256), 1145 .nbytes_max = __cpu_to_le32(256), 1146 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1147 .reserved = __cpu_to_le32(0), 1148 }, 1149 1150 /* CE5: target->host Pktlog */ 1151 { 1152 .pipenum = __cpu_to_le32(5), 1153 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1154 .nentries = __cpu_to_le32(32), 1155 .nbytes_max = __cpu_to_le32(2048), 1156 .flags = __cpu_to_le32(0), 1157 .reserved = __cpu_to_le32(0), 1158 }, 1159 1160 /* CE6: Reserved for target autonomous hif_memcpy */ 1161 { 1162 .pipenum = __cpu_to_le32(6), 1163 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1164 .nentries = __cpu_to_le32(32), 1165 .nbytes_max = __cpu_to_le32(65535), 1166 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1167 .reserved = __cpu_to_le32(0), 1168 }, 1169 1170 /* CE7 used only by Host */ 1171 { 1172 .pipenum = __cpu_to_le32(7), 1173 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1174 .nentries = __cpu_to_le32(32), 1175 .nbytes_max = __cpu_to_le32(2048), 1176 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1177 .reserved = __cpu_to_le32(0), 1178 }, 1179 1180 /* CE8 target->host used only by IPA */ 1181 { 1182 .pipenum = __cpu_to_le32(8), 1183 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1184 .nentries = __cpu_to_le32(32), 1185 .nbytes_max = __cpu_to_le32(65535), 1186 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1187 .reserved = __cpu_to_le32(0), 1188 }, 1189 1190 /* CE9 host->target HTT */ 1191 { 1192 .pipenum = __cpu_to_le32(9), 1193 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1194 .nentries = __cpu_to_le32(32), 1195 .nbytes_max = __cpu_to_le32(2048), 1196 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1197 .reserved = __cpu_to_le32(0), 1198 }, 1199 1200 /* CE10 target->host HTT */ 1201 { 1202 .pipenum = __cpu_to_le32(10), 1203 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 1204 .nentries = __cpu_to_le32(0), 1205 .nbytes_max = __cpu_to_le32(0), 1206 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1207 .reserved = __cpu_to_le32(0), 1208 }, 1209 1210 /* CE11 Not used */ 1211 }; 1212 1213 /* Map from service/endpoint to Copy Engine. 1214 * This table is derived from the CE_PCI TABLE, above. 1215 * It is passed to the Target at startup for use by firmware. 1216 */ 1217 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq8074[] = { 1218 { 1219 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1220 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1221 .pipenum = __cpu_to_le32(3), 1222 }, 1223 { 1224 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1225 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1226 .pipenum = __cpu_to_le32(2), 1227 }, 1228 { 1229 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1230 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1231 .pipenum = __cpu_to_le32(3), 1232 }, 1233 { 1234 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1235 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1236 .pipenum = __cpu_to_le32(2), 1237 }, 1238 { 1239 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1240 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1241 .pipenum = __cpu_to_le32(3), 1242 }, 1243 { 1244 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1245 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1246 .pipenum = __cpu_to_le32(2), 1247 }, 1248 { 1249 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1250 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1251 .pipenum = __cpu_to_le32(3), 1252 }, 1253 { 1254 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1255 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1256 .pipenum = __cpu_to_le32(2), 1257 }, 1258 { 1259 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1260 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1261 .pipenum = __cpu_to_le32(3), 1262 }, 1263 { 1264 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1265 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1266 .pipenum = __cpu_to_le32(2), 1267 }, 1268 { 1269 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1270 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1271 .pipenum = __cpu_to_le32(7), 1272 }, 1273 { 1274 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1275 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1276 .pipenum = __cpu_to_le32(2), 1277 }, 1278 { 1279 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2), 1280 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1281 .pipenum = __cpu_to_le32(9), 1282 }, 1283 { 1284 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2), 1285 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1286 .pipenum = __cpu_to_le32(2), 1287 }, 1288 { 1289 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1290 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1291 .pipenum = __cpu_to_le32(0), 1292 }, 1293 { 1294 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1295 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1296 .pipenum = __cpu_to_le32(1), 1297 }, 1298 { /* not used */ 1299 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1300 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1301 .pipenum = __cpu_to_le32(0), 1302 }, 1303 { /* not used */ 1304 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1305 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1306 .pipenum = __cpu_to_le32(1), 1307 }, 1308 { 1309 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1310 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1311 .pipenum = __cpu_to_le32(4), 1312 }, 1313 { 1314 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1315 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1316 .pipenum = __cpu_to_le32(1), 1317 }, 1318 { 1319 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 1320 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1321 .pipenum = __cpu_to_le32(5), 1322 }, 1323 1324 /* (Additions here) */ 1325 1326 { /* terminator entry */ } 1327 }; 1328 1329 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq6018[] = { 1330 { 1331 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1332 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1333 .pipenum = __cpu_to_le32(3), 1334 }, 1335 { 1336 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1337 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1338 .pipenum = __cpu_to_le32(2), 1339 }, 1340 { 1341 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1342 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1343 .pipenum = __cpu_to_le32(3), 1344 }, 1345 { 1346 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1347 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1348 .pipenum = __cpu_to_le32(2), 1349 }, 1350 { 1351 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1352 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1353 .pipenum = __cpu_to_le32(3), 1354 }, 1355 { 1356 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1357 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1358 .pipenum = __cpu_to_le32(2), 1359 }, 1360 { 1361 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1362 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1363 .pipenum = __cpu_to_le32(3), 1364 }, 1365 { 1366 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1367 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1368 .pipenum = __cpu_to_le32(2), 1369 }, 1370 { 1371 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1372 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1373 .pipenum = __cpu_to_le32(3), 1374 }, 1375 { 1376 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1377 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1378 .pipenum = __cpu_to_le32(2), 1379 }, 1380 { 1381 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1382 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1383 .pipenum = __cpu_to_le32(7), 1384 }, 1385 { 1386 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1387 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1388 .pipenum = __cpu_to_le32(2), 1389 }, 1390 { 1391 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1392 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1393 .pipenum = __cpu_to_le32(0), 1394 }, 1395 { 1396 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1397 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1398 .pipenum = __cpu_to_le32(1), 1399 }, 1400 { /* not used */ 1401 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1402 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1403 .pipenum = __cpu_to_le32(0), 1404 }, 1405 { /* not used */ 1406 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1407 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1408 .pipenum = __cpu_to_le32(1), 1409 }, 1410 { 1411 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1412 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1413 .pipenum = __cpu_to_le32(4), 1414 }, 1415 { 1416 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1417 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1418 .pipenum = __cpu_to_le32(1), 1419 }, 1420 { 1421 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 1422 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1423 .pipenum = __cpu_to_le32(5), 1424 }, 1425 1426 /* (Additions here) */ 1427 1428 { /* terminator entry */ } 1429 }; 1430 1431 /* Target firmware's Copy Engine configuration. */ 1432 const struct ce_pipe_config ath11k_target_ce_config_wlan_qca6390[] = { 1433 /* CE0: host->target HTC control and raw streams */ 1434 { 1435 .pipenum = __cpu_to_le32(0), 1436 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1437 .nentries = __cpu_to_le32(32), 1438 .nbytes_max = __cpu_to_le32(2048), 1439 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1440 .reserved = __cpu_to_le32(0), 1441 }, 1442 1443 /* CE1: target->host HTT + HTC control */ 1444 { 1445 .pipenum = __cpu_to_le32(1), 1446 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1447 .nentries = __cpu_to_le32(32), 1448 .nbytes_max = __cpu_to_le32(2048), 1449 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1450 .reserved = __cpu_to_le32(0), 1451 }, 1452 1453 /* CE2: target->host WMI */ 1454 { 1455 .pipenum = __cpu_to_le32(2), 1456 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1457 .nentries = __cpu_to_le32(32), 1458 .nbytes_max = __cpu_to_le32(2048), 1459 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1460 .reserved = __cpu_to_le32(0), 1461 }, 1462 1463 /* CE3: host->target WMI */ 1464 { 1465 .pipenum = __cpu_to_le32(3), 1466 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1467 .nentries = __cpu_to_le32(32), 1468 .nbytes_max = __cpu_to_le32(2048), 1469 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1470 .reserved = __cpu_to_le32(0), 1471 }, 1472 1473 /* CE4: host->target HTT */ 1474 { 1475 .pipenum = __cpu_to_le32(4), 1476 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1477 .nentries = __cpu_to_le32(256), 1478 .nbytes_max = __cpu_to_le32(256), 1479 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1480 .reserved = __cpu_to_le32(0), 1481 }, 1482 1483 /* CE5: target->host Pktlog */ 1484 { 1485 .pipenum = __cpu_to_le32(5), 1486 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1487 .nentries = __cpu_to_le32(32), 1488 .nbytes_max = __cpu_to_le32(2048), 1489 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1490 .reserved = __cpu_to_le32(0), 1491 }, 1492 1493 /* CE6: Reserved for target autonomous hif_memcpy */ 1494 { 1495 .pipenum = __cpu_to_le32(6), 1496 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1497 .nentries = __cpu_to_le32(32), 1498 .nbytes_max = __cpu_to_le32(16384), 1499 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1500 .reserved = __cpu_to_le32(0), 1501 }, 1502 1503 /* CE7 used only by Host */ 1504 { 1505 .pipenum = __cpu_to_le32(7), 1506 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 1507 .nentries = __cpu_to_le32(0), 1508 .nbytes_max = __cpu_to_le32(0), 1509 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1510 .reserved = __cpu_to_le32(0), 1511 }, 1512 1513 /* CE8 target->host used only by IPA */ 1514 { 1515 .pipenum = __cpu_to_le32(8), 1516 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1517 .nentries = __cpu_to_le32(32), 1518 .nbytes_max = __cpu_to_le32(16384), 1519 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1520 .reserved = __cpu_to_le32(0), 1521 }, 1522 /* CE 9, 10, 11 are used by MHI driver */ 1523 }; 1524 1525 /* Map from service/endpoint to Copy Engine. 1526 * This table is derived from the CE_PCI TABLE, above. 1527 * It is passed to the Target at startup for use by firmware. 1528 */ 1529 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qca6390[] = { 1530 { 1531 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1532 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1533 __cpu_to_le32(3), 1534 }, 1535 { 1536 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1537 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1538 __cpu_to_le32(2), 1539 }, 1540 { 1541 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1542 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1543 __cpu_to_le32(3), 1544 }, 1545 { 1546 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1547 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1548 __cpu_to_le32(2), 1549 }, 1550 { 1551 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1552 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1553 __cpu_to_le32(3), 1554 }, 1555 { 1556 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1557 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1558 __cpu_to_le32(2), 1559 }, 1560 { 1561 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1562 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1563 __cpu_to_le32(3), 1564 }, 1565 { 1566 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1567 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1568 __cpu_to_le32(2), 1569 }, 1570 { 1571 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1572 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1573 __cpu_to_le32(3), 1574 }, 1575 { 1576 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1577 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1578 __cpu_to_le32(2), 1579 }, 1580 { 1581 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1582 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1583 __cpu_to_le32(0), 1584 }, 1585 { 1586 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1587 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1588 __cpu_to_le32(2), 1589 }, 1590 { 1591 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1592 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1593 __cpu_to_le32(4), 1594 }, 1595 { 1596 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1597 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1598 __cpu_to_le32(1), 1599 }, 1600 1601 /* (Additions here) */ 1602 1603 { /* must be last */ 1604 __cpu_to_le32(0), 1605 __cpu_to_le32(0), 1606 __cpu_to_le32(0), 1607 }, 1608 }; 1609 1610 /* Target firmware's Copy Engine configuration. */ 1611 const struct ce_pipe_config ath11k_target_ce_config_wlan_qcn9074[] = { 1612 /* CE0: host->target HTC control and raw streams */ 1613 { 1614 .pipenum = __cpu_to_le32(0), 1615 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1616 .nentries = __cpu_to_le32(32), 1617 .nbytes_max = __cpu_to_le32(2048), 1618 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1619 .reserved = __cpu_to_le32(0), 1620 }, 1621 1622 /* CE1: target->host HTT + HTC control */ 1623 { 1624 .pipenum = __cpu_to_le32(1), 1625 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1626 .nentries = __cpu_to_le32(32), 1627 .nbytes_max = __cpu_to_le32(2048), 1628 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1629 .reserved = __cpu_to_le32(0), 1630 }, 1631 1632 /* CE2: target->host WMI */ 1633 { 1634 .pipenum = __cpu_to_le32(2), 1635 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1636 .nentries = __cpu_to_le32(32), 1637 .nbytes_max = __cpu_to_le32(2048), 1638 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1639 .reserved = __cpu_to_le32(0), 1640 }, 1641 1642 /* CE3: host->target WMI */ 1643 { 1644 .pipenum = __cpu_to_le32(3), 1645 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1646 .nentries = __cpu_to_le32(32), 1647 .nbytes_max = __cpu_to_le32(2048), 1648 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1649 .reserved = __cpu_to_le32(0), 1650 }, 1651 1652 /* CE4: host->target HTT */ 1653 { 1654 .pipenum = __cpu_to_le32(4), 1655 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1656 .nentries = __cpu_to_le32(256), 1657 .nbytes_max = __cpu_to_le32(256), 1658 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1659 .reserved = __cpu_to_le32(0), 1660 }, 1661 1662 /* CE5: target->host Pktlog */ 1663 { 1664 .pipenum = __cpu_to_le32(5), 1665 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1666 .nentries = __cpu_to_le32(32), 1667 .nbytes_max = __cpu_to_le32(2048), 1668 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1669 .reserved = __cpu_to_le32(0), 1670 }, 1671 1672 /* CE6: Reserved for target autonomous hif_memcpy */ 1673 { 1674 .pipenum = __cpu_to_le32(6), 1675 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1676 .nentries = __cpu_to_le32(32), 1677 .nbytes_max = __cpu_to_le32(16384), 1678 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1679 .reserved = __cpu_to_le32(0), 1680 }, 1681 1682 /* CE7 used only by Host */ 1683 { 1684 .pipenum = __cpu_to_le32(7), 1685 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 1686 .nentries = __cpu_to_le32(0), 1687 .nbytes_max = __cpu_to_le32(0), 1688 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1689 .reserved = __cpu_to_le32(0), 1690 }, 1691 1692 /* CE8 target->host used only by IPA */ 1693 { 1694 .pipenum = __cpu_to_le32(8), 1695 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1696 .nentries = __cpu_to_le32(32), 1697 .nbytes_max = __cpu_to_le32(16384), 1698 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1699 .reserved = __cpu_to_le32(0), 1700 }, 1701 /* CE 9, 10, 11 are used by MHI driver */ 1702 }; 1703 1704 /* Map from service/endpoint to Copy Engine. 1705 * This table is derived from the CE_PCI TABLE, above. 1706 * It is passed to the Target at startup for use by firmware. 1707 */ 1708 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qcn9074[] = { 1709 { 1710 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1711 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1712 __cpu_to_le32(3), 1713 }, 1714 { 1715 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1716 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1717 __cpu_to_le32(2), 1718 }, 1719 { 1720 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1721 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1722 __cpu_to_le32(3), 1723 }, 1724 { 1725 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1726 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1727 __cpu_to_le32(2), 1728 }, 1729 { 1730 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1731 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1732 __cpu_to_le32(3), 1733 }, 1734 { 1735 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1736 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1737 __cpu_to_le32(2), 1738 }, 1739 { 1740 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1741 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1742 __cpu_to_le32(3), 1743 }, 1744 { 1745 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1746 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1747 __cpu_to_le32(2), 1748 }, 1749 { 1750 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1751 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1752 __cpu_to_le32(3), 1753 }, 1754 { 1755 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1756 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1757 __cpu_to_le32(2), 1758 }, 1759 { 1760 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1761 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1762 __cpu_to_le32(0), 1763 }, 1764 { 1765 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1766 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1767 __cpu_to_le32(1), 1768 }, 1769 { 1770 __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1771 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1772 __cpu_to_le32(0), 1773 }, 1774 { 1775 __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1776 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1777 __cpu_to_le32(1), 1778 }, 1779 { 1780 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1781 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1782 __cpu_to_le32(4), 1783 }, 1784 { 1785 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1786 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1787 __cpu_to_le32(1), 1788 }, 1789 { 1790 __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 1791 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1792 __cpu_to_le32(5), 1793 }, 1794 1795 /* (Additions here) */ 1796 1797 { /* must be last */ 1798 __cpu_to_le32(0), 1799 __cpu_to_le32(0), 1800 __cpu_to_le32(0), 1801 }, 1802 }; 1803 1804 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qcn9074 = { 1805 .tx = { 1806 ATH11K_TX_RING_MASK_0, 1807 ATH11K_TX_RING_MASK_1, 1808 ATH11K_TX_RING_MASK_2, 1809 }, 1810 .rx_mon_status = { 1811 0, 0, 0, 1812 ATH11K_RX_MON_STATUS_RING_MASK_0, 1813 ATH11K_RX_MON_STATUS_RING_MASK_1, 1814 ATH11K_RX_MON_STATUS_RING_MASK_2, 1815 }, 1816 .rx = { 1817 0, 0, 0, 0, 1818 ATH11K_RX_RING_MASK_0, 1819 ATH11K_RX_RING_MASK_1, 1820 ATH11K_RX_RING_MASK_2, 1821 ATH11K_RX_RING_MASK_3, 1822 }, 1823 .rx_err = { 1824 0, 0, 0, 1825 ATH11K_RX_ERR_RING_MASK_0, 1826 }, 1827 .rx_wbm_rel = { 1828 0, 0, 0, 1829 ATH11K_RX_WBM_REL_RING_MASK_0, 1830 }, 1831 .reo_status = { 1832 0, 0, 0, 1833 ATH11K_REO_STATUS_RING_MASK_0, 1834 }, 1835 .rxdma2host = { 1836 0, 0, 0, 1837 ATH11K_RXDMA2HOST_RING_MASK_0, 1838 }, 1839 .host2rxdma = { 1840 0, 0, 0, 1841 ATH11K_HOST2RXDMA_RING_MASK_0, 1842 }, 1843 }; 1844 1845 const struct ath11k_hw_regs ipq8074_regs = { 1846 /* SW2TCL(x) R0 ring configuration address */ 1847 .hal_tcl1_ring_base_lsb = 0x00000510, 1848 .hal_tcl1_ring_base_msb = 0x00000514, 1849 .hal_tcl1_ring_id = 0x00000518, 1850 .hal_tcl1_ring_misc = 0x00000520, 1851 .hal_tcl1_ring_tp_addr_lsb = 0x0000052c, 1852 .hal_tcl1_ring_tp_addr_msb = 0x00000530, 1853 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000540, 1854 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000544, 1855 .hal_tcl1_ring_msi1_base_lsb = 0x00000558, 1856 .hal_tcl1_ring_msi1_base_msb = 0x0000055c, 1857 .hal_tcl1_ring_msi1_data = 0x00000560, 1858 .hal_tcl2_ring_base_lsb = 0x00000568, 1859 .hal_tcl_ring_base_lsb = 0x00000618, 1860 1861 /* TCL STATUS ring address */ 1862 .hal_tcl_status_ring_base_lsb = 0x00000720, 1863 1864 /* REO2SW(x) R0 ring configuration address */ 1865 .hal_reo1_ring_base_lsb = 0x0000029c, 1866 .hal_reo1_ring_base_msb = 0x000002a0, 1867 .hal_reo1_ring_id = 0x000002a4, 1868 .hal_reo1_ring_misc = 0x000002ac, 1869 .hal_reo1_ring_hp_addr_lsb = 0x000002b0, 1870 .hal_reo1_ring_hp_addr_msb = 0x000002b4, 1871 .hal_reo1_ring_producer_int_setup = 0x000002c0, 1872 .hal_reo1_ring_msi1_base_lsb = 0x000002e4, 1873 .hal_reo1_ring_msi1_base_msb = 0x000002e8, 1874 .hal_reo1_ring_msi1_data = 0x000002ec, 1875 .hal_reo2_ring_base_lsb = 0x000002f4, 1876 .hal_reo1_aging_thresh_ix_0 = 0x00000564, 1877 .hal_reo1_aging_thresh_ix_1 = 0x00000568, 1878 .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 1879 .hal_reo1_aging_thresh_ix_3 = 0x00000570, 1880 1881 /* REO2SW(x) R2 ring pointers (head/tail) address */ 1882 .hal_reo1_ring_hp = 0x00003038, 1883 .hal_reo1_ring_tp = 0x0000303c, 1884 .hal_reo2_ring_hp = 0x00003040, 1885 1886 /* REO2TCL R0 ring configuration address */ 1887 .hal_reo_tcl_ring_base_lsb = 0x000003fc, 1888 .hal_reo_tcl_ring_hp = 0x00003058, 1889 1890 /* REO status address */ 1891 .hal_reo_status_ring_base_lsb = 0x00000504, 1892 .hal_reo_status_hp = 0x00003070, 1893 1894 /* WCSS relative address */ 1895 .hal_seq_wcss_umac_ce0_src_reg = 0x00a00000, 1896 .hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000, 1897 .hal_seq_wcss_umac_ce1_src_reg = 0x00a02000, 1898 .hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000, 1899 1900 /* WBM Idle address */ 1901 .hal_wbm_idle_link_ring_base_lsb = 0x00000860, 1902 .hal_wbm_idle_link_ring_misc = 0x00000870, 1903 1904 /* SW2WBM release address */ 1905 .hal_wbm_release_ring_base_lsb = 0x000001d8, 1906 1907 /* WBM2SW release address */ 1908 .hal_wbm0_release_ring_base_lsb = 0x00000910, 1909 .hal_wbm1_release_ring_base_lsb = 0x00000968, 1910 1911 /* PCIe base address */ 1912 .pcie_qserdes_sysclk_en_sel = 0x0, 1913 .pcie_pcs_osc_dtct_config_base = 0x0, 1914 }; 1915 1916 const struct ath11k_hw_regs qca6390_regs = { 1917 /* SW2TCL(x) R0 ring configuration address */ 1918 .hal_tcl1_ring_base_lsb = 0x00000684, 1919 .hal_tcl1_ring_base_msb = 0x00000688, 1920 .hal_tcl1_ring_id = 0x0000068c, 1921 .hal_tcl1_ring_misc = 0x00000694, 1922 .hal_tcl1_ring_tp_addr_lsb = 0x000006a0, 1923 .hal_tcl1_ring_tp_addr_msb = 0x000006a4, 1924 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006b4, 1925 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006b8, 1926 .hal_tcl1_ring_msi1_base_lsb = 0x000006cc, 1927 .hal_tcl1_ring_msi1_base_msb = 0x000006d0, 1928 .hal_tcl1_ring_msi1_data = 0x000006d4, 1929 .hal_tcl2_ring_base_lsb = 0x000006dc, 1930 .hal_tcl_ring_base_lsb = 0x0000078c, 1931 1932 /* TCL STATUS ring address */ 1933 .hal_tcl_status_ring_base_lsb = 0x00000894, 1934 1935 /* REO2SW(x) R0 ring configuration address */ 1936 .hal_reo1_ring_base_lsb = 0x00000244, 1937 .hal_reo1_ring_base_msb = 0x00000248, 1938 .hal_reo1_ring_id = 0x0000024c, 1939 .hal_reo1_ring_misc = 0x00000254, 1940 .hal_reo1_ring_hp_addr_lsb = 0x00000258, 1941 .hal_reo1_ring_hp_addr_msb = 0x0000025c, 1942 .hal_reo1_ring_producer_int_setup = 0x00000268, 1943 .hal_reo1_ring_msi1_base_lsb = 0x0000028c, 1944 .hal_reo1_ring_msi1_base_msb = 0x00000290, 1945 .hal_reo1_ring_msi1_data = 0x00000294, 1946 .hal_reo2_ring_base_lsb = 0x0000029c, 1947 .hal_reo1_aging_thresh_ix_0 = 0x0000050c, 1948 .hal_reo1_aging_thresh_ix_1 = 0x00000510, 1949 .hal_reo1_aging_thresh_ix_2 = 0x00000514, 1950 .hal_reo1_aging_thresh_ix_3 = 0x00000518, 1951 1952 /* REO2SW(x) R2 ring pointers (head/tail) address */ 1953 .hal_reo1_ring_hp = 0x00003030, 1954 .hal_reo1_ring_tp = 0x00003034, 1955 .hal_reo2_ring_hp = 0x00003038, 1956 1957 /* REO2TCL R0 ring configuration address */ 1958 .hal_reo_tcl_ring_base_lsb = 0x000003a4, 1959 .hal_reo_tcl_ring_hp = 0x00003050, 1960 1961 /* REO status address */ 1962 .hal_reo_status_ring_base_lsb = 0x000004ac, 1963 .hal_reo_status_hp = 0x00003068, 1964 1965 /* WCSS relative address */ 1966 .hal_seq_wcss_umac_ce0_src_reg = 0x00a00000, 1967 .hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000, 1968 .hal_seq_wcss_umac_ce1_src_reg = 0x00a02000, 1969 .hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000, 1970 1971 /* WBM Idle address */ 1972 .hal_wbm_idle_link_ring_base_lsb = 0x00000860, 1973 .hal_wbm_idle_link_ring_misc = 0x00000870, 1974 1975 /* SW2WBM release address */ 1976 .hal_wbm_release_ring_base_lsb = 0x000001d8, 1977 1978 /* WBM2SW release address */ 1979 .hal_wbm0_release_ring_base_lsb = 0x00000910, 1980 .hal_wbm1_release_ring_base_lsb = 0x00000968, 1981 1982 /* PCIe base address */ 1983 .pcie_qserdes_sysclk_en_sel = 0x01e0c0ac, 1984 .pcie_pcs_osc_dtct_config_base = 0x01e0c628, 1985 }; 1986 1987 const struct ath11k_hw_regs qcn9074_regs = { 1988 /* SW2TCL(x) R0 ring configuration address */ 1989 .hal_tcl1_ring_base_lsb = 0x000004f0, 1990 .hal_tcl1_ring_base_msb = 0x000004f4, 1991 .hal_tcl1_ring_id = 0x000004f8, 1992 .hal_tcl1_ring_misc = 0x00000500, 1993 .hal_tcl1_ring_tp_addr_lsb = 0x0000050c, 1994 .hal_tcl1_ring_tp_addr_msb = 0x00000510, 1995 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000520, 1996 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000524, 1997 .hal_tcl1_ring_msi1_base_lsb = 0x00000538, 1998 .hal_tcl1_ring_msi1_base_msb = 0x0000053c, 1999 .hal_tcl1_ring_msi1_data = 0x00000540, 2000 .hal_tcl2_ring_base_lsb = 0x00000548, 2001 .hal_tcl_ring_base_lsb = 0x000005f8, 2002 2003 /* TCL STATUS ring address */ 2004 .hal_tcl_status_ring_base_lsb = 0x00000700, 2005 2006 /* REO2SW(x) R0 ring configuration address */ 2007 .hal_reo1_ring_base_lsb = 0x0000029c, 2008 .hal_reo1_ring_base_msb = 0x000002a0, 2009 .hal_reo1_ring_id = 0x000002a4, 2010 .hal_reo1_ring_misc = 0x000002ac, 2011 .hal_reo1_ring_hp_addr_lsb = 0x000002b0, 2012 .hal_reo1_ring_hp_addr_msb = 0x000002b4, 2013 .hal_reo1_ring_producer_int_setup = 0x000002c0, 2014 .hal_reo1_ring_msi1_base_lsb = 0x000002e4, 2015 .hal_reo1_ring_msi1_base_msb = 0x000002e8, 2016 .hal_reo1_ring_msi1_data = 0x000002ec, 2017 .hal_reo2_ring_base_lsb = 0x000002f4, 2018 .hal_reo1_aging_thresh_ix_0 = 0x00000564, 2019 .hal_reo1_aging_thresh_ix_1 = 0x00000568, 2020 .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 2021 .hal_reo1_aging_thresh_ix_3 = 0x00000570, 2022 2023 /* REO2SW(x) R2 ring pointers (head/tail) address */ 2024 .hal_reo1_ring_hp = 0x00003038, 2025 .hal_reo1_ring_tp = 0x0000303c, 2026 .hal_reo2_ring_hp = 0x00003040, 2027 2028 /* REO2TCL R0 ring configuration address */ 2029 .hal_reo_tcl_ring_base_lsb = 0x000003fc, 2030 .hal_reo_tcl_ring_hp = 0x00003058, 2031 2032 /* REO status address */ 2033 .hal_reo_status_ring_base_lsb = 0x00000504, 2034 .hal_reo_status_hp = 0x00003070, 2035 2036 /* WCSS relative address */ 2037 .hal_seq_wcss_umac_ce0_src_reg = 0x01b80000, 2038 .hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000, 2039 .hal_seq_wcss_umac_ce1_src_reg = 0x01b82000, 2040 .hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000, 2041 2042 /* WBM Idle address */ 2043 .hal_wbm_idle_link_ring_base_lsb = 0x00000874, 2044 .hal_wbm_idle_link_ring_misc = 0x00000884, 2045 2046 /* SW2WBM release address */ 2047 .hal_wbm_release_ring_base_lsb = 0x000001ec, 2048 2049 /* WBM2SW release address */ 2050 .hal_wbm0_release_ring_base_lsb = 0x00000924, 2051 .hal_wbm1_release_ring_base_lsb = 0x0000097c, 2052 2053 /* PCIe base address */ 2054 .pcie_qserdes_sysclk_en_sel = 0x01e0e0a8, 2055 .pcie_pcs_osc_dtct_config_base = 0x01e0f45c, 2056 }; 2057 2058 const struct ath11k_hw_regs wcn6855_regs = { 2059 /* SW2TCL(x) R0 ring configuration address */ 2060 .hal_tcl1_ring_base_lsb = 0x00000690, 2061 .hal_tcl1_ring_base_msb = 0x00000694, 2062 .hal_tcl1_ring_id = 0x00000698, 2063 .hal_tcl1_ring_misc = 0x000006a0, 2064 .hal_tcl1_ring_tp_addr_lsb = 0x000006ac, 2065 .hal_tcl1_ring_tp_addr_msb = 0x000006b0, 2066 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c0, 2067 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c4, 2068 .hal_tcl1_ring_msi1_base_lsb = 0x000006d8, 2069 .hal_tcl1_ring_msi1_base_msb = 0x000006dc, 2070 .hal_tcl1_ring_msi1_data = 0x000006e0, 2071 .hal_tcl2_ring_base_lsb = 0x000006e8, 2072 .hal_tcl_ring_base_lsb = 0x00000798, 2073 2074 /* TCL STATUS ring address */ 2075 .hal_tcl_status_ring_base_lsb = 0x000008a0, 2076 2077 /* REO2SW(x) R0 ring configuration address */ 2078 .hal_reo1_ring_base_lsb = 0x00000244, 2079 .hal_reo1_ring_base_msb = 0x00000248, 2080 .hal_reo1_ring_id = 0x0000024c, 2081 .hal_reo1_ring_misc = 0x00000254, 2082 .hal_reo1_ring_hp_addr_lsb = 0x00000258, 2083 .hal_reo1_ring_hp_addr_msb = 0x0000025c, 2084 .hal_reo1_ring_producer_int_setup = 0x00000268, 2085 .hal_reo1_ring_msi1_base_lsb = 0x0000028c, 2086 .hal_reo1_ring_msi1_base_msb = 0x00000290, 2087 .hal_reo1_ring_msi1_data = 0x00000294, 2088 .hal_reo2_ring_base_lsb = 0x0000029c, 2089 .hal_reo1_aging_thresh_ix_0 = 0x000005bc, 2090 .hal_reo1_aging_thresh_ix_1 = 0x000005c0, 2091 .hal_reo1_aging_thresh_ix_2 = 0x000005c4, 2092 .hal_reo1_aging_thresh_ix_3 = 0x000005c8, 2093 2094 /* REO2SW(x) R2 ring pointers (head/tail) address */ 2095 .hal_reo1_ring_hp = 0x00003030, 2096 .hal_reo1_ring_tp = 0x00003034, 2097 .hal_reo2_ring_hp = 0x00003038, 2098 2099 /* REO2TCL R0 ring configuration address */ 2100 .hal_reo_tcl_ring_base_lsb = 0x00000454, 2101 .hal_reo_tcl_ring_hp = 0x00003060, 2102 2103 /* REO status address */ 2104 .hal_reo_status_ring_base_lsb = 0x0000055c, 2105 .hal_reo_status_hp = 0x00003078, 2106 2107 /* WCSS relative address */ 2108 .hal_seq_wcss_umac_ce0_src_reg = 0x1b80000, 2109 .hal_seq_wcss_umac_ce0_dst_reg = 0x1b81000, 2110 .hal_seq_wcss_umac_ce1_src_reg = 0x1b82000, 2111 .hal_seq_wcss_umac_ce1_dst_reg = 0x1b83000, 2112 2113 /* WBM Idle address */ 2114 .hal_wbm_idle_link_ring_base_lsb = 0x00000870, 2115 .hal_wbm_idle_link_ring_misc = 0x00000880, 2116 2117 /* SW2WBM release address */ 2118 .hal_wbm_release_ring_base_lsb = 0x000001e8, 2119 2120 /* WBM2SW release address */ 2121 .hal_wbm0_release_ring_base_lsb = 0x00000920, 2122 .hal_wbm1_release_ring_base_lsb = 0x00000978, 2123 2124 /* PCIe base address */ 2125 .pcie_qserdes_sysclk_en_sel = 0x01e0c0ac, 2126 .pcie_pcs_osc_dtct_config_base = 0x01e0c628, 2127 }; 2128 2129 const struct ath11k_hw_hal_params ath11k_hw_hal_params_ipq8074 = { 2130 .rx_buf_rbm = HAL_RX_BUF_RBM_SW3_BM, 2131 }; 2132 2133 const struct ath11k_hw_hal_params ath11k_hw_hal_params_qca6390 = { 2134 .rx_buf_rbm = HAL_RX_BUF_RBM_SW1_BM, 2135 }; 2136