1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/types.h> 7 #include <linux/bitops.h> 8 #include <linux/bitfield.h> 9 10 #include "hw.h" 11 #include "core.h" 12 #include "ce.h" 13 #include "hif.h" 14 15 /* Map from pdev index to hw mac index */ 16 static u8 ath11k_hw_ipq8074_mac_from_pdev_id(int pdev_idx) 17 { 18 switch (pdev_idx) { 19 case 0: 20 return 0; 21 case 1: 22 return 2; 23 case 2: 24 return 1; 25 default: 26 return ATH11K_INVALID_HW_MAC_ID; 27 } 28 } 29 30 static u8 ath11k_hw_ipq6018_mac_from_pdev_id(int pdev_idx) 31 { 32 return pdev_idx; 33 } 34 35 static void ath11k_hw_ipq8074_tx_mesh_enable(struct ath11k_base *ab, 36 struct hal_tcl_data_cmd *tcl_cmd) 37 { 38 tcl_cmd->info2 |= FIELD_PREP(HAL_IPQ8074_TCL_DATA_CMD_INFO2_MESH_ENABLE, 39 true); 40 } 41 42 static void ath11k_hw_qcn9074_tx_mesh_enable(struct ath11k_base *ab, 43 struct hal_tcl_data_cmd *tcl_cmd) 44 { 45 tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE, 46 true); 47 } 48 49 static void ath11k_hw_wcn6855_tx_mesh_enable(struct ath11k_base *ab, 50 struct hal_tcl_data_cmd *tcl_cmd) 51 { 52 tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE, 53 true); 54 } 55 56 static void ath11k_init_wmi_config_qca6390(struct ath11k_base *ab, 57 struct target_resource_config *config) 58 { 59 config->num_vdevs = 4; 60 config->num_peers = 16; 61 config->num_tids = 32; 62 63 config->num_offload_peers = 3; 64 config->num_offload_reorder_buffs = 3; 65 config->num_peer_keys = TARGET_NUM_PEER_KEYS; 66 config->ast_skid_limit = TARGET_AST_SKID_LIMIT; 67 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 68 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 69 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; 70 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI; 71 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; 72 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; 73 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; 74 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS; 75 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV; 76 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV; 77 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES; 78 config->num_mcast_groups = 0; 79 config->num_mcast_table_elems = 0; 80 config->mcast2ucast_mode = 0; 81 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE; 82 config->num_wds_entries = 0; 83 config->dma_burst_size = 0; 84 config->rx_skip_defrag_timeout_dup_detection_check = 0; 85 config->vow_config = TARGET_VOW_CONFIG; 86 config->gtk_offload_max_vdev = 2; 87 config->num_msdu_desc = 0x400; 88 config->beacon_tx_offload_max_vdev = 2; 89 config->rx_batchmode = TARGET_RX_BATCHMODE; 90 91 config->peer_map_unmap_v2_support = 0; 92 config->use_pdev_id = 1; 93 config->max_frag_entries = 0xa; 94 config->num_tdls_vdevs = 0x1; 95 config->num_tdls_conn_table_entries = 8; 96 config->beacon_tx_offload_max_vdev = 0x2; 97 config->num_multicast_filter_entries = 0x20; 98 config->num_wow_filters = 0x16; 99 config->num_keep_alive_pattern = 0; 100 } 101 102 static void ath11k_hw_ipq8074_reo_setup(struct ath11k_base *ab) 103 { 104 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; 105 u32 val; 106 /* Each hash entry uses three bits to map to a particular ring. */ 107 u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 | 108 HAL_HASH_ROUTING_RING_SW2 << 3 | 109 HAL_HASH_ROUTING_RING_SW3 << 6 | 110 HAL_HASH_ROUTING_RING_SW4 << 9 | 111 HAL_HASH_ROUTING_RING_SW1 << 12 | 112 HAL_HASH_ROUTING_RING_SW2 << 15 | 113 HAL_HASH_ROUTING_RING_SW3 << 18 | 114 HAL_HASH_ROUTING_RING_SW4 << 21; 115 116 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); 117 118 val &= ~HAL_REO1_GEN_ENABLE_FRAG_DST_RING; 119 val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_FRAG_DST_RING, 120 HAL_SRNG_RING_ID_REO2SW1) | 121 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) | 122 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1); 123 ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); 124 125 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab), 126 HAL_DEFAULT_REO_TIMEOUT_USEC); 127 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab), 128 HAL_DEFAULT_REO_TIMEOUT_USEC); 129 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab), 130 HAL_DEFAULT_REO_TIMEOUT_USEC); 131 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab), 132 HAL_DEFAULT_REO_TIMEOUT_USEC); 133 134 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0, 135 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 136 ring_hash_map)); 137 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1, 138 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 139 ring_hash_map)); 140 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, 141 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 142 ring_hash_map)); 143 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, 144 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 145 ring_hash_map)); 146 } 147 148 static void ath11k_init_wmi_config_ipq8074(struct ath11k_base *ab, 149 struct target_resource_config *config) 150 { 151 config->num_vdevs = ab->num_radios * TARGET_NUM_VDEVS; 152 153 if (ab->num_radios == 2) { 154 config->num_peers = TARGET_NUM_PEERS(DBS); 155 config->num_tids = TARGET_NUM_TIDS(DBS); 156 } else if (ab->num_radios == 3) { 157 config->num_peers = TARGET_NUM_PEERS(DBS_SBS); 158 config->num_tids = TARGET_NUM_TIDS(DBS_SBS); 159 } else { 160 /* Control should not reach here */ 161 config->num_peers = TARGET_NUM_PEERS(SINGLE); 162 config->num_tids = TARGET_NUM_TIDS(SINGLE); 163 } 164 config->num_offload_peers = TARGET_NUM_OFFLD_PEERS; 165 config->num_offload_reorder_buffs = TARGET_NUM_OFFLD_REORDER_BUFFS; 166 config->num_peer_keys = TARGET_NUM_PEER_KEYS; 167 config->ast_skid_limit = TARGET_AST_SKID_LIMIT; 168 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 169 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 170 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; 171 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI; 172 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; 173 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; 174 175 if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) 176 config->rx_decap_mode = TARGET_DECAP_MODE_RAW; 177 else 178 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; 179 180 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS; 181 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV; 182 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV; 183 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES; 184 config->num_mcast_groups = TARGET_NUM_MCAST_GROUPS; 185 config->num_mcast_table_elems = TARGET_NUM_MCAST_TABLE_ELEMS; 186 config->mcast2ucast_mode = TARGET_MCAST2UCAST_MODE; 187 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE; 188 config->num_wds_entries = TARGET_NUM_WDS_ENTRIES; 189 config->dma_burst_size = TARGET_DMA_BURST_SIZE; 190 config->rx_skip_defrag_timeout_dup_detection_check = 191 TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK; 192 config->vow_config = TARGET_VOW_CONFIG; 193 config->gtk_offload_max_vdev = TARGET_GTK_OFFLOAD_MAX_VDEV; 194 config->num_msdu_desc = TARGET_NUM_MSDU_DESC; 195 config->beacon_tx_offload_max_vdev = ab->num_radios * TARGET_MAX_BCN_OFFLD; 196 config->rx_batchmode = TARGET_RX_BATCHMODE; 197 config->peer_map_unmap_v2_support = 1; 198 config->twt_ap_pdev_count = ab->num_radios; 199 config->twt_ap_sta_count = 1000; 200 } 201 202 static int ath11k_hw_mac_id_to_pdev_id_ipq8074(struct ath11k_hw_params *hw, 203 int mac_id) 204 { 205 return mac_id; 206 } 207 208 static int ath11k_hw_mac_id_to_srng_id_ipq8074(struct ath11k_hw_params *hw, 209 int mac_id) 210 { 211 return 0; 212 } 213 214 static int ath11k_hw_mac_id_to_pdev_id_qca6390(struct ath11k_hw_params *hw, 215 int mac_id) 216 { 217 return 0; 218 } 219 220 static int ath11k_hw_mac_id_to_srng_id_qca6390(struct ath11k_hw_params *hw, 221 int mac_id) 222 { 223 return mac_id; 224 } 225 226 static bool ath11k_hw_ipq8074_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 227 { 228 return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU, 229 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 230 } 231 232 static bool ath11k_hw_ipq8074_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 233 { 234 return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU, 235 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 236 } 237 238 static u8 ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 239 { 240 return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING, 241 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 242 } 243 244 static u8 *ath11k_hw_ipq8074_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 245 { 246 return desc->u.ipq8074.hdr_status; 247 } 248 249 static bool ath11k_hw_ipq8074_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 250 { 251 return __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1) & 252 RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID; 253 } 254 255 static u32 ath11k_hw_ipq8074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 256 { 257 return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE, 258 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2)); 259 } 260 261 static u8 ath11k_hw_ipq8074_rx_desc_get_decap_type(struct hal_rx_desc *desc) 262 { 263 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 264 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2)); 265 } 266 267 static u8 ath11k_hw_ipq8074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 268 { 269 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 270 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2)); 271 } 272 273 static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 274 { 275 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID, 276 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 277 } 278 279 static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 280 { 281 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID, 282 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 283 } 284 285 static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 286 { 287 return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM, 288 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 289 } 290 291 static u16 ath11k_hw_ipq8074_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 292 { 293 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 294 __le32_to_cpu(desc->u.ipq8074.msdu_start.info1)); 295 } 296 297 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 298 { 299 return FIELD_GET(RX_MSDU_START_INFO3_SGI, 300 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 301 } 302 303 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 304 { 305 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 306 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 307 } 308 309 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 310 { 311 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 312 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 313 } 314 315 static u32 ath11k_hw_ipq8074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 316 { 317 return __le32_to_cpu(desc->u.ipq8074.msdu_start.phy_meta_data); 318 } 319 320 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 321 { 322 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 323 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 324 } 325 326 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 327 { 328 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 329 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 330 } 331 332 static u8 ath11k_hw_ipq8074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 333 { 334 return FIELD_GET(RX_MPDU_START_INFO2_TID, 335 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2)); 336 } 337 338 static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 339 { 340 return __le16_to_cpu(desc->u.ipq8074.mpdu_start.sw_peer_id); 341 } 342 343 static void ath11k_hw_ipq8074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 344 struct hal_rx_desc *ldesc) 345 { 346 memcpy((u8 *)&fdesc->u.ipq8074.msdu_end, (u8 *)&ldesc->u.ipq8074.msdu_end, 347 sizeof(struct rx_msdu_end_ipq8074)); 348 memcpy((u8 *)&fdesc->u.ipq8074.attention, (u8 *)&ldesc->u.ipq8074.attention, 349 sizeof(struct rx_attention)); 350 memcpy((u8 *)&fdesc->u.ipq8074.mpdu_end, (u8 *)&ldesc->u.ipq8074.mpdu_end, 351 sizeof(struct rx_mpdu_end)); 352 } 353 354 static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 355 { 356 return FIELD_GET(HAL_TLV_HDR_TAG, 357 __le32_to_cpu(desc->u.ipq8074.mpdu_start_tag)); 358 } 359 360 static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 361 { 362 return __le16_to_cpu(desc->u.ipq8074.mpdu_start.phy_ppdu_id); 363 } 364 365 static void ath11k_hw_ipq8074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 366 { 367 u32 info = __le32_to_cpu(desc->u.ipq8074.msdu_start.info1); 368 369 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 370 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 371 372 desc->u.ipq8074.msdu_start.info1 = __cpu_to_le32(info); 373 } 374 375 static 376 struct rx_attention *ath11k_hw_ipq8074_rx_desc_get_attention(struct hal_rx_desc *desc) 377 { 378 return &desc->u.ipq8074.attention; 379 } 380 381 static u8 *ath11k_hw_ipq8074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 382 { 383 return &desc->u.ipq8074.msdu_payload[0]; 384 } 385 386 static bool ath11k_hw_qcn9074_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 387 { 388 return !!FIELD_GET(RX_MSDU_END_INFO4_FIRST_MSDU, 389 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 390 } 391 392 static bool ath11k_hw_qcn9074_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 393 { 394 return !!FIELD_GET(RX_MSDU_END_INFO4_LAST_MSDU, 395 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 396 } 397 398 static u8 ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 399 { 400 return FIELD_GET(RX_MSDU_END_INFO4_L3_HDR_PADDING, 401 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 402 } 403 404 static u8 *ath11k_hw_qcn9074_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 405 { 406 return desc->u.qcn9074.hdr_status; 407 } 408 409 static bool ath11k_hw_qcn9074_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 410 { 411 return __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11) & 412 RX_MPDU_START_INFO11_ENCRYPT_INFO_VALID; 413 } 414 415 static u32 ath11k_hw_qcn9074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 416 { 417 return FIELD_GET(RX_MPDU_START_INFO9_ENC_TYPE, 418 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9)); 419 } 420 421 static u8 ath11k_hw_qcn9074_rx_desc_get_decap_type(struct hal_rx_desc *desc) 422 { 423 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 424 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2)); 425 } 426 427 static u8 ath11k_hw_qcn9074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 428 { 429 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 430 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2)); 431 } 432 433 static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 434 { 435 return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_CTRL_VALID, 436 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 437 } 438 439 static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 440 { 441 return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_FCTRL_VALID, 442 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 443 } 444 445 static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 446 { 447 return FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_NUM, 448 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 449 } 450 451 static u16 ath11k_hw_qcn9074_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 452 { 453 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 454 __le32_to_cpu(desc->u.qcn9074.msdu_start.info1)); 455 } 456 457 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 458 { 459 return FIELD_GET(RX_MSDU_START_INFO3_SGI, 460 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 461 } 462 463 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 464 { 465 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 466 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 467 } 468 469 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 470 { 471 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 472 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 473 } 474 475 static u32 ath11k_hw_qcn9074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 476 { 477 return __le32_to_cpu(desc->u.qcn9074.msdu_start.phy_meta_data); 478 } 479 480 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 481 { 482 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 483 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 484 } 485 486 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 487 { 488 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 489 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 490 } 491 492 static u8 ath11k_hw_qcn9074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 493 { 494 return FIELD_GET(RX_MPDU_START_INFO9_TID, 495 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9)); 496 } 497 498 static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 499 { 500 return __le16_to_cpu(desc->u.qcn9074.mpdu_start.sw_peer_id); 501 } 502 503 static void ath11k_hw_qcn9074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 504 struct hal_rx_desc *ldesc) 505 { 506 memcpy((u8 *)&fdesc->u.qcn9074.msdu_end, (u8 *)&ldesc->u.qcn9074.msdu_end, 507 sizeof(struct rx_msdu_end_qcn9074)); 508 memcpy((u8 *)&fdesc->u.qcn9074.attention, (u8 *)&ldesc->u.qcn9074.attention, 509 sizeof(struct rx_attention)); 510 memcpy((u8 *)&fdesc->u.qcn9074.mpdu_end, (u8 *)&ldesc->u.qcn9074.mpdu_end, 511 sizeof(struct rx_mpdu_end)); 512 } 513 514 static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 515 { 516 return FIELD_GET(HAL_TLV_HDR_TAG, 517 __le32_to_cpu(desc->u.qcn9074.mpdu_start_tag)); 518 } 519 520 static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 521 { 522 return __le16_to_cpu(desc->u.qcn9074.mpdu_start.phy_ppdu_id); 523 } 524 525 static void ath11k_hw_qcn9074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 526 { 527 u32 info = __le32_to_cpu(desc->u.qcn9074.msdu_start.info1); 528 529 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 530 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 531 532 desc->u.qcn9074.msdu_start.info1 = __cpu_to_le32(info); 533 } 534 535 static 536 struct rx_attention *ath11k_hw_qcn9074_rx_desc_get_attention(struct hal_rx_desc *desc) 537 { 538 return &desc->u.qcn9074.attention; 539 } 540 541 static u8 *ath11k_hw_qcn9074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 542 { 543 return &desc->u.qcn9074.msdu_payload[0]; 544 } 545 546 static bool ath11k_hw_wcn6855_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 547 { 548 return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU_WCN6855, 549 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2)); 550 } 551 552 static bool ath11k_hw_wcn6855_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 553 { 554 return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU_WCN6855, 555 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2)); 556 } 557 558 static u8 ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 559 { 560 return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING, 561 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2)); 562 } 563 564 static u8 *ath11k_hw_wcn6855_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 565 { 566 return desc->u.wcn6855.hdr_status; 567 } 568 569 static bool ath11k_hw_wcn6855_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 570 { 571 return __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1) & 572 RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID; 573 } 574 575 static u32 ath11k_hw_wcn6855_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 576 { 577 return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE, 578 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info2)); 579 } 580 581 static u8 ath11k_hw_wcn6855_rx_desc_get_decap_type(struct hal_rx_desc *desc) 582 { 583 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 584 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2)); 585 } 586 587 static u8 ath11k_hw_wcn6855_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 588 { 589 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 590 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2)); 591 } 592 593 static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 594 { 595 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID, 596 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1)); 597 } 598 599 static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 600 { 601 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID, 602 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1)); 603 } 604 605 static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 606 { 607 return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM, 608 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1)); 609 } 610 611 static u16 ath11k_hw_wcn6855_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 612 { 613 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 614 __le32_to_cpu(desc->u.wcn6855.msdu_start.info1)); 615 } 616 617 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 618 { 619 return FIELD_GET(RX_MSDU_START_INFO3_SGI, 620 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 621 } 622 623 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 624 { 625 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 626 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 627 } 628 629 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 630 { 631 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 632 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 633 } 634 635 static u32 ath11k_hw_wcn6855_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 636 { 637 return __le32_to_cpu(desc->u.wcn6855.msdu_start.phy_meta_data); 638 } 639 640 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 641 { 642 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 643 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 644 } 645 646 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 647 { 648 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 649 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 650 } 651 652 static u8 ath11k_hw_wcn6855_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 653 { 654 return FIELD_GET(RX_MPDU_START_INFO2_TID_WCN6855, 655 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info2)); 656 } 657 658 static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 659 { 660 return __le16_to_cpu(desc->u.wcn6855.mpdu_start.sw_peer_id); 661 } 662 663 static void ath11k_hw_wcn6855_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 664 struct hal_rx_desc *ldesc) 665 { 666 memcpy((u8 *)&fdesc->u.wcn6855.msdu_end, (u8 *)&ldesc->u.wcn6855.msdu_end, 667 sizeof(struct rx_msdu_end_wcn6855)); 668 memcpy((u8 *)&fdesc->u.wcn6855.attention, (u8 *)&ldesc->u.wcn6855.attention, 669 sizeof(struct rx_attention)); 670 memcpy((u8 *)&fdesc->u.wcn6855.mpdu_end, (u8 *)&ldesc->u.wcn6855.mpdu_end, 671 sizeof(struct rx_mpdu_end)); 672 } 673 674 static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 675 { 676 return FIELD_GET(HAL_TLV_HDR_TAG, 677 __le32_to_cpu(desc->u.wcn6855.mpdu_start_tag)); 678 } 679 680 static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 681 { 682 return __le16_to_cpu(desc->u.wcn6855.mpdu_start.phy_ppdu_id); 683 } 684 685 static void ath11k_hw_wcn6855_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 686 { 687 u32 info = __le32_to_cpu(desc->u.wcn6855.msdu_start.info1); 688 689 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 690 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 691 692 desc->u.wcn6855.msdu_start.info1 = __cpu_to_le32(info); 693 } 694 695 static 696 struct rx_attention *ath11k_hw_wcn6855_rx_desc_get_attention(struct hal_rx_desc *desc) 697 { 698 return &desc->u.wcn6855.attention; 699 } 700 701 static u8 *ath11k_hw_wcn6855_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 702 { 703 return &desc->u.wcn6855.msdu_payload[0]; 704 } 705 706 static void ath11k_hw_wcn6855_reo_setup(struct ath11k_base *ab) 707 { 708 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; 709 u32 val; 710 /* Each hash entry uses four bits to map to a particular ring. */ 711 u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 | 712 HAL_HASH_ROUTING_RING_SW2 << 4 | 713 HAL_HASH_ROUTING_RING_SW3 << 8 | 714 HAL_HASH_ROUTING_RING_SW4 << 12 | 715 HAL_HASH_ROUTING_RING_SW1 << 16 | 716 HAL_HASH_ROUTING_RING_SW2 << 20 | 717 HAL_HASH_ROUTING_RING_SW3 << 24 | 718 HAL_HASH_ROUTING_RING_SW4 << 28; 719 720 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); 721 val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) | 722 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1); 723 ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); 724 725 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_MISC_CTL); 726 val &= ~HAL_REO1_MISC_CTL_FRAGMENT_DST_RING; 727 val |= FIELD_PREP(HAL_REO1_MISC_CTL_FRAGMENT_DST_RING, HAL_SRNG_RING_ID_REO2SW1); 728 ath11k_hif_write32(ab, reo_base + HAL_REO1_MISC_CTL, val); 729 730 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab), 731 HAL_DEFAULT_REO_TIMEOUT_USEC); 732 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab), 733 HAL_DEFAULT_REO_TIMEOUT_USEC); 734 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab), 735 HAL_DEFAULT_REO_TIMEOUT_USEC); 736 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab), 737 HAL_DEFAULT_REO_TIMEOUT_USEC); 738 739 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, 740 ring_hash_map); 741 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, 742 ring_hash_map); 743 } 744 745 static u16 ath11k_hw_ipq8074_mpdu_info_get_peerid(u8 *tlv_data) 746 { 747 u16 peer_id = 0; 748 struct hal_rx_mpdu_info *mpdu_info = 749 (struct hal_rx_mpdu_info *)tlv_data; 750 751 peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID, 752 __le32_to_cpu(mpdu_info->info0)); 753 754 return peer_id; 755 } 756 757 static u16 ath11k_hw_wcn6855_mpdu_info_get_peerid(u8 *tlv_data) 758 { 759 u16 peer_id = 0; 760 struct hal_rx_mpdu_info_wcn6855 *mpdu_info = 761 (struct hal_rx_mpdu_info_wcn6855 *)tlv_data; 762 763 peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID_WCN6855, 764 __le32_to_cpu(mpdu_info->info0)); 765 return peer_id; 766 } 767 768 const struct ath11k_hw_ops ipq8074_ops = { 769 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 770 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 771 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 772 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 773 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 774 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 775 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 776 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 777 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 778 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 779 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 780 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 781 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 782 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 783 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 784 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 785 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 786 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 787 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 788 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 789 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 790 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 791 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 792 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 793 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 794 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 795 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 796 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 797 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 798 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 799 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 800 .reo_setup = ath11k_hw_ipq8074_reo_setup, 801 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 802 }; 803 804 const struct ath11k_hw_ops ipq6018_ops = { 805 .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 806 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 807 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 808 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 809 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 810 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 811 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 812 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 813 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 814 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 815 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 816 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 817 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 818 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 819 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 820 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 821 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 822 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 823 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 824 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 825 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 826 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 827 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 828 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 829 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 830 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 831 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 832 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 833 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 834 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 835 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 836 .reo_setup = ath11k_hw_ipq8074_reo_setup, 837 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 838 }; 839 840 const struct ath11k_hw_ops qca6390_ops = { 841 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 842 .wmi_init_config = ath11k_init_wmi_config_qca6390, 843 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390, 844 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390, 845 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 846 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 847 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 848 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 849 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 850 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 851 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 852 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 853 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 854 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 855 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 856 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 857 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 858 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 859 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 860 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 861 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 862 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 863 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 864 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 865 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 866 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 867 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 868 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 869 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 870 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 871 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 872 .reo_setup = ath11k_hw_ipq8074_reo_setup, 873 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 874 }; 875 876 const struct ath11k_hw_ops qcn9074_ops = { 877 .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 878 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 879 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 880 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 881 .tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable, 882 .rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu, 883 .rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu, 884 .rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes, 885 .rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status, 886 .rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid, 887 .rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type, 888 .rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type, 889 .rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl, 890 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld, 891 .rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid, 892 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no, 893 .rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len, 894 .rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi, 895 .rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs, 896 .rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw, 897 .rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq, 898 .rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type, 899 .rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss, 900 .rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid, 901 .rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id, 902 .rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end, 903 .rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag, 904 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id, 905 .rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len, 906 .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention, 907 .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload, 908 .reo_setup = ath11k_hw_ipq8074_reo_setup, 909 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 910 }; 911 912 const struct ath11k_hw_ops wcn6855_ops = { 913 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 914 .wmi_init_config = ath11k_init_wmi_config_qca6390, 915 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390, 916 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390, 917 .tx_mesh_enable = ath11k_hw_wcn6855_tx_mesh_enable, 918 .rx_desc_get_first_msdu = ath11k_hw_wcn6855_rx_desc_get_first_msdu, 919 .rx_desc_get_last_msdu = ath11k_hw_wcn6855_rx_desc_get_last_msdu, 920 .rx_desc_get_l3_pad_bytes = ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes, 921 .rx_desc_get_hdr_status = ath11k_hw_wcn6855_rx_desc_get_hdr_status, 922 .rx_desc_encrypt_valid = ath11k_hw_wcn6855_rx_desc_encrypt_valid, 923 .rx_desc_get_encrypt_type = ath11k_hw_wcn6855_rx_desc_get_encrypt_type, 924 .rx_desc_get_decap_type = ath11k_hw_wcn6855_rx_desc_get_decap_type, 925 .rx_desc_get_mesh_ctl = ath11k_hw_wcn6855_rx_desc_get_mesh_ctl, 926 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld, 927 .rx_desc_get_mpdu_fc_valid = ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid, 928 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no, 929 .rx_desc_get_msdu_len = ath11k_hw_wcn6855_rx_desc_get_msdu_len, 930 .rx_desc_get_msdu_sgi = ath11k_hw_wcn6855_rx_desc_get_msdu_sgi, 931 .rx_desc_get_msdu_rate_mcs = ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs, 932 .rx_desc_get_msdu_rx_bw = ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw, 933 .rx_desc_get_msdu_freq = ath11k_hw_wcn6855_rx_desc_get_msdu_freq, 934 .rx_desc_get_msdu_pkt_type = ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type, 935 .rx_desc_get_msdu_nss = ath11k_hw_wcn6855_rx_desc_get_msdu_nss, 936 .rx_desc_get_mpdu_tid = ath11k_hw_wcn6855_rx_desc_get_mpdu_tid, 937 .rx_desc_get_mpdu_peer_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id, 938 .rx_desc_copy_attn_end_tlv = ath11k_hw_wcn6855_rx_desc_copy_attn_end, 939 .rx_desc_get_mpdu_start_tag = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag, 940 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id, 941 .rx_desc_set_msdu_len = ath11k_hw_wcn6855_rx_desc_set_msdu_len, 942 .rx_desc_get_attention = ath11k_hw_wcn6855_rx_desc_get_attention, 943 .rx_desc_get_msdu_payload = ath11k_hw_wcn6855_rx_desc_get_msdu_payload, 944 .reo_setup = ath11k_hw_wcn6855_reo_setup, 945 .mpdu_info_get_peerid = ath11k_hw_wcn6855_mpdu_info_get_peerid, 946 }; 947 948 #define ATH11K_TX_RING_MASK_0 0x1 949 #define ATH11K_TX_RING_MASK_1 0x2 950 #define ATH11K_TX_RING_MASK_2 0x4 951 952 #define ATH11K_RX_RING_MASK_0 0x1 953 #define ATH11K_RX_RING_MASK_1 0x2 954 #define ATH11K_RX_RING_MASK_2 0x4 955 #define ATH11K_RX_RING_MASK_3 0x8 956 957 #define ATH11K_RX_ERR_RING_MASK_0 0x1 958 959 #define ATH11K_RX_WBM_REL_RING_MASK_0 0x1 960 961 #define ATH11K_REO_STATUS_RING_MASK_0 0x1 962 963 #define ATH11K_RXDMA2HOST_RING_MASK_0 0x1 964 #define ATH11K_RXDMA2HOST_RING_MASK_1 0x2 965 #define ATH11K_RXDMA2HOST_RING_MASK_2 0x4 966 967 #define ATH11K_HOST2RXDMA_RING_MASK_0 0x1 968 #define ATH11K_HOST2RXDMA_RING_MASK_1 0x2 969 #define ATH11K_HOST2RXDMA_RING_MASK_2 0x4 970 971 #define ATH11K_RX_MON_STATUS_RING_MASK_0 0x1 972 #define ATH11K_RX_MON_STATUS_RING_MASK_1 0x2 973 #define ATH11K_RX_MON_STATUS_RING_MASK_2 0x4 974 975 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074 = { 976 .tx = { 977 ATH11K_TX_RING_MASK_0, 978 ATH11K_TX_RING_MASK_1, 979 ATH11K_TX_RING_MASK_2, 980 }, 981 .rx_mon_status = { 982 0, 0, 0, 0, 983 ATH11K_RX_MON_STATUS_RING_MASK_0, 984 ATH11K_RX_MON_STATUS_RING_MASK_1, 985 ATH11K_RX_MON_STATUS_RING_MASK_2, 986 }, 987 .rx = { 988 0, 0, 0, 0, 0, 0, 0, 989 ATH11K_RX_RING_MASK_0, 990 ATH11K_RX_RING_MASK_1, 991 ATH11K_RX_RING_MASK_2, 992 ATH11K_RX_RING_MASK_3, 993 }, 994 .rx_err = { 995 ATH11K_RX_ERR_RING_MASK_0, 996 }, 997 .rx_wbm_rel = { 998 ATH11K_RX_WBM_REL_RING_MASK_0, 999 }, 1000 .reo_status = { 1001 ATH11K_REO_STATUS_RING_MASK_0, 1002 }, 1003 .rxdma2host = { 1004 ATH11K_RXDMA2HOST_RING_MASK_0, 1005 ATH11K_RXDMA2HOST_RING_MASK_1, 1006 ATH11K_RXDMA2HOST_RING_MASK_2, 1007 }, 1008 .host2rxdma = { 1009 ATH11K_HOST2RXDMA_RING_MASK_0, 1010 ATH11K_HOST2RXDMA_RING_MASK_1, 1011 ATH11K_HOST2RXDMA_RING_MASK_2, 1012 }, 1013 }; 1014 1015 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390 = { 1016 .tx = { 1017 ATH11K_TX_RING_MASK_0, 1018 ATH11K_TX_RING_MASK_1, 1019 ATH11K_TX_RING_MASK_2, 1020 }, 1021 .rx_mon_status = { 1022 0, 0, 0, 0, 1023 ATH11K_RX_MON_STATUS_RING_MASK_0, 1024 ATH11K_RX_MON_STATUS_RING_MASK_1, 1025 ATH11K_RX_MON_STATUS_RING_MASK_2, 1026 }, 1027 .rx = { 1028 0, 0, 0, 0, 0, 0, 0, 1029 ATH11K_RX_RING_MASK_0, 1030 ATH11K_RX_RING_MASK_1, 1031 ATH11K_RX_RING_MASK_2, 1032 ATH11K_RX_RING_MASK_3, 1033 }, 1034 .rx_err = { 1035 ATH11K_RX_ERR_RING_MASK_0, 1036 }, 1037 .rx_wbm_rel = { 1038 ATH11K_RX_WBM_REL_RING_MASK_0, 1039 }, 1040 .reo_status = { 1041 ATH11K_REO_STATUS_RING_MASK_0, 1042 }, 1043 .rxdma2host = { 1044 ATH11K_RXDMA2HOST_RING_MASK_0, 1045 ATH11K_RXDMA2HOST_RING_MASK_1, 1046 ATH11K_RXDMA2HOST_RING_MASK_2, 1047 }, 1048 .host2rxdma = { 1049 }, 1050 }; 1051 1052 /* Target firmware's Copy Engine configuration. */ 1053 const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq8074[] = { 1054 /* CE0: host->target HTC control and raw streams */ 1055 { 1056 .pipenum = __cpu_to_le32(0), 1057 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1058 .nentries = __cpu_to_le32(32), 1059 .nbytes_max = __cpu_to_le32(2048), 1060 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1061 .reserved = __cpu_to_le32(0), 1062 }, 1063 1064 /* CE1: target->host HTT + HTC control */ 1065 { 1066 .pipenum = __cpu_to_le32(1), 1067 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1068 .nentries = __cpu_to_le32(32), 1069 .nbytes_max = __cpu_to_le32(2048), 1070 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1071 .reserved = __cpu_to_le32(0), 1072 }, 1073 1074 /* CE2: target->host WMI */ 1075 { 1076 .pipenum = __cpu_to_le32(2), 1077 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1078 .nentries = __cpu_to_le32(32), 1079 .nbytes_max = __cpu_to_le32(2048), 1080 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1081 .reserved = __cpu_to_le32(0), 1082 }, 1083 1084 /* CE3: host->target WMI */ 1085 { 1086 .pipenum = __cpu_to_le32(3), 1087 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1088 .nentries = __cpu_to_le32(32), 1089 .nbytes_max = __cpu_to_le32(2048), 1090 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1091 .reserved = __cpu_to_le32(0), 1092 }, 1093 1094 /* CE4: host->target HTT */ 1095 { 1096 .pipenum = __cpu_to_le32(4), 1097 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1098 .nentries = __cpu_to_le32(256), 1099 .nbytes_max = __cpu_to_le32(256), 1100 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1101 .reserved = __cpu_to_le32(0), 1102 }, 1103 1104 /* CE5: target->host Pktlog */ 1105 { 1106 .pipenum = __cpu_to_le32(5), 1107 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1108 .nentries = __cpu_to_le32(32), 1109 .nbytes_max = __cpu_to_le32(2048), 1110 .flags = __cpu_to_le32(0), 1111 .reserved = __cpu_to_le32(0), 1112 }, 1113 1114 /* CE6: Reserved for target autonomous hif_memcpy */ 1115 { 1116 .pipenum = __cpu_to_le32(6), 1117 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1118 .nentries = __cpu_to_le32(32), 1119 .nbytes_max = __cpu_to_le32(65535), 1120 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1121 .reserved = __cpu_to_le32(0), 1122 }, 1123 1124 /* CE7 used only by Host */ 1125 { 1126 .pipenum = __cpu_to_le32(7), 1127 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1128 .nentries = __cpu_to_le32(32), 1129 .nbytes_max = __cpu_to_le32(2048), 1130 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1131 .reserved = __cpu_to_le32(0), 1132 }, 1133 1134 /* CE8 target->host used only by IPA */ 1135 { 1136 .pipenum = __cpu_to_le32(8), 1137 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1138 .nentries = __cpu_to_le32(32), 1139 .nbytes_max = __cpu_to_le32(65535), 1140 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1141 .reserved = __cpu_to_le32(0), 1142 }, 1143 1144 /* CE9 host->target HTT */ 1145 { 1146 .pipenum = __cpu_to_le32(9), 1147 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1148 .nentries = __cpu_to_le32(32), 1149 .nbytes_max = __cpu_to_le32(2048), 1150 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1151 .reserved = __cpu_to_le32(0), 1152 }, 1153 1154 /* CE10 target->host HTT */ 1155 { 1156 .pipenum = __cpu_to_le32(10), 1157 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 1158 .nentries = __cpu_to_le32(0), 1159 .nbytes_max = __cpu_to_le32(0), 1160 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1161 .reserved = __cpu_to_le32(0), 1162 }, 1163 1164 /* CE11 Not used */ 1165 }; 1166 1167 /* Map from service/endpoint to Copy Engine. 1168 * This table is derived from the CE_PCI TABLE, above. 1169 * It is passed to the Target at startup for use by firmware. 1170 */ 1171 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq8074[] = { 1172 { 1173 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1174 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1175 .pipenum = __cpu_to_le32(3), 1176 }, 1177 { 1178 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1179 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1180 .pipenum = __cpu_to_le32(2), 1181 }, 1182 { 1183 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1184 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1185 .pipenum = __cpu_to_le32(3), 1186 }, 1187 { 1188 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1189 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1190 .pipenum = __cpu_to_le32(2), 1191 }, 1192 { 1193 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1194 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1195 .pipenum = __cpu_to_le32(3), 1196 }, 1197 { 1198 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1199 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1200 .pipenum = __cpu_to_le32(2), 1201 }, 1202 { 1203 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1204 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1205 .pipenum = __cpu_to_le32(3), 1206 }, 1207 { 1208 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1209 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1210 .pipenum = __cpu_to_le32(2), 1211 }, 1212 { 1213 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1214 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1215 .pipenum = __cpu_to_le32(3), 1216 }, 1217 { 1218 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1219 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1220 .pipenum = __cpu_to_le32(2), 1221 }, 1222 { 1223 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1224 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1225 .pipenum = __cpu_to_le32(7), 1226 }, 1227 { 1228 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1229 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1230 .pipenum = __cpu_to_le32(2), 1231 }, 1232 { 1233 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2), 1234 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1235 .pipenum = __cpu_to_le32(9), 1236 }, 1237 { 1238 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2), 1239 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1240 .pipenum = __cpu_to_le32(2), 1241 }, 1242 { 1243 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1244 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1245 .pipenum = __cpu_to_le32(0), 1246 }, 1247 { 1248 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1249 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1250 .pipenum = __cpu_to_le32(1), 1251 }, 1252 { /* not used */ 1253 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1254 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1255 .pipenum = __cpu_to_le32(0), 1256 }, 1257 { /* not used */ 1258 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1259 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1260 .pipenum = __cpu_to_le32(1), 1261 }, 1262 { 1263 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1264 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1265 .pipenum = __cpu_to_le32(4), 1266 }, 1267 { 1268 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1269 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1270 .pipenum = __cpu_to_le32(1), 1271 }, 1272 { 1273 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 1274 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1275 .pipenum = __cpu_to_le32(5), 1276 }, 1277 1278 /* (Additions here) */ 1279 1280 { /* terminator entry */ } 1281 }; 1282 1283 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq6018[] = { 1284 { 1285 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1286 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1287 .pipenum = __cpu_to_le32(3), 1288 }, 1289 { 1290 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1291 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1292 .pipenum = __cpu_to_le32(2), 1293 }, 1294 { 1295 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1296 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1297 .pipenum = __cpu_to_le32(3), 1298 }, 1299 { 1300 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1301 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1302 .pipenum = __cpu_to_le32(2), 1303 }, 1304 { 1305 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1306 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1307 .pipenum = __cpu_to_le32(3), 1308 }, 1309 { 1310 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1311 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1312 .pipenum = __cpu_to_le32(2), 1313 }, 1314 { 1315 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1316 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1317 .pipenum = __cpu_to_le32(3), 1318 }, 1319 { 1320 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1321 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1322 .pipenum = __cpu_to_le32(2), 1323 }, 1324 { 1325 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1326 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1327 .pipenum = __cpu_to_le32(3), 1328 }, 1329 { 1330 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1331 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1332 .pipenum = __cpu_to_le32(2), 1333 }, 1334 { 1335 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1336 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1337 .pipenum = __cpu_to_le32(7), 1338 }, 1339 { 1340 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1341 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1342 .pipenum = __cpu_to_le32(2), 1343 }, 1344 { 1345 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1346 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1347 .pipenum = __cpu_to_le32(0), 1348 }, 1349 { 1350 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1351 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1352 .pipenum = __cpu_to_le32(1), 1353 }, 1354 { /* not used */ 1355 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1356 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1357 .pipenum = __cpu_to_le32(0), 1358 }, 1359 { /* not used */ 1360 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1361 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1362 .pipenum = __cpu_to_le32(1), 1363 }, 1364 { 1365 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1366 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1367 .pipenum = __cpu_to_le32(4), 1368 }, 1369 { 1370 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1371 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1372 .pipenum = __cpu_to_le32(1), 1373 }, 1374 { 1375 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 1376 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1377 .pipenum = __cpu_to_le32(5), 1378 }, 1379 1380 /* (Additions here) */ 1381 1382 { /* terminator entry */ } 1383 }; 1384 1385 /* Target firmware's Copy Engine configuration. */ 1386 const struct ce_pipe_config ath11k_target_ce_config_wlan_qca6390[] = { 1387 /* CE0: host->target HTC control and raw streams */ 1388 { 1389 .pipenum = __cpu_to_le32(0), 1390 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1391 .nentries = __cpu_to_le32(32), 1392 .nbytes_max = __cpu_to_le32(2048), 1393 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1394 .reserved = __cpu_to_le32(0), 1395 }, 1396 1397 /* CE1: target->host HTT + HTC control */ 1398 { 1399 .pipenum = __cpu_to_le32(1), 1400 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1401 .nentries = __cpu_to_le32(32), 1402 .nbytes_max = __cpu_to_le32(2048), 1403 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1404 .reserved = __cpu_to_le32(0), 1405 }, 1406 1407 /* CE2: target->host WMI */ 1408 { 1409 .pipenum = __cpu_to_le32(2), 1410 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1411 .nentries = __cpu_to_le32(32), 1412 .nbytes_max = __cpu_to_le32(2048), 1413 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1414 .reserved = __cpu_to_le32(0), 1415 }, 1416 1417 /* CE3: host->target WMI */ 1418 { 1419 .pipenum = __cpu_to_le32(3), 1420 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1421 .nentries = __cpu_to_le32(32), 1422 .nbytes_max = __cpu_to_le32(2048), 1423 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1424 .reserved = __cpu_to_le32(0), 1425 }, 1426 1427 /* CE4: host->target HTT */ 1428 { 1429 .pipenum = __cpu_to_le32(4), 1430 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1431 .nentries = __cpu_to_le32(256), 1432 .nbytes_max = __cpu_to_le32(256), 1433 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1434 .reserved = __cpu_to_le32(0), 1435 }, 1436 1437 /* CE5: target->host Pktlog */ 1438 { 1439 .pipenum = __cpu_to_le32(5), 1440 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1441 .nentries = __cpu_to_le32(32), 1442 .nbytes_max = __cpu_to_le32(2048), 1443 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1444 .reserved = __cpu_to_le32(0), 1445 }, 1446 1447 /* CE6: Reserved for target autonomous hif_memcpy */ 1448 { 1449 .pipenum = __cpu_to_le32(6), 1450 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1451 .nentries = __cpu_to_le32(32), 1452 .nbytes_max = __cpu_to_le32(16384), 1453 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1454 .reserved = __cpu_to_le32(0), 1455 }, 1456 1457 /* CE7 used only by Host */ 1458 { 1459 .pipenum = __cpu_to_le32(7), 1460 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 1461 .nentries = __cpu_to_le32(0), 1462 .nbytes_max = __cpu_to_le32(0), 1463 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1464 .reserved = __cpu_to_le32(0), 1465 }, 1466 1467 /* CE8 target->host used only by IPA */ 1468 { 1469 .pipenum = __cpu_to_le32(8), 1470 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1471 .nentries = __cpu_to_le32(32), 1472 .nbytes_max = __cpu_to_le32(16384), 1473 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1474 .reserved = __cpu_to_le32(0), 1475 }, 1476 /* CE 9, 10, 11 are used by MHI driver */ 1477 }; 1478 1479 /* Map from service/endpoint to Copy Engine. 1480 * This table is derived from the CE_PCI TABLE, above. 1481 * It is passed to the Target at startup for use by firmware. 1482 */ 1483 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qca6390[] = { 1484 { 1485 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1486 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1487 __cpu_to_le32(3), 1488 }, 1489 { 1490 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1491 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1492 __cpu_to_le32(2), 1493 }, 1494 { 1495 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1496 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1497 __cpu_to_le32(3), 1498 }, 1499 { 1500 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1501 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1502 __cpu_to_le32(2), 1503 }, 1504 { 1505 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1506 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1507 __cpu_to_le32(3), 1508 }, 1509 { 1510 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1511 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1512 __cpu_to_le32(2), 1513 }, 1514 { 1515 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1516 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1517 __cpu_to_le32(3), 1518 }, 1519 { 1520 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1521 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1522 __cpu_to_le32(2), 1523 }, 1524 { 1525 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1526 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1527 __cpu_to_le32(3), 1528 }, 1529 { 1530 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1531 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1532 __cpu_to_le32(2), 1533 }, 1534 { 1535 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1536 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1537 __cpu_to_le32(0), 1538 }, 1539 { 1540 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1541 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1542 __cpu_to_le32(2), 1543 }, 1544 { 1545 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1546 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1547 __cpu_to_le32(4), 1548 }, 1549 { 1550 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1551 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1552 __cpu_to_le32(1), 1553 }, 1554 1555 /* (Additions here) */ 1556 1557 { /* must be last */ 1558 __cpu_to_le32(0), 1559 __cpu_to_le32(0), 1560 __cpu_to_le32(0), 1561 }, 1562 }; 1563 1564 /* Target firmware's Copy Engine configuration. */ 1565 const struct ce_pipe_config ath11k_target_ce_config_wlan_qcn9074[] = { 1566 /* CE0: host->target HTC control and raw streams */ 1567 { 1568 .pipenum = __cpu_to_le32(0), 1569 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1570 .nentries = __cpu_to_le32(32), 1571 .nbytes_max = __cpu_to_le32(2048), 1572 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1573 .reserved = __cpu_to_le32(0), 1574 }, 1575 1576 /* CE1: target->host HTT + HTC control */ 1577 { 1578 .pipenum = __cpu_to_le32(1), 1579 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1580 .nentries = __cpu_to_le32(32), 1581 .nbytes_max = __cpu_to_le32(2048), 1582 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1583 .reserved = __cpu_to_le32(0), 1584 }, 1585 1586 /* CE2: target->host WMI */ 1587 { 1588 .pipenum = __cpu_to_le32(2), 1589 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1590 .nentries = __cpu_to_le32(32), 1591 .nbytes_max = __cpu_to_le32(2048), 1592 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1593 .reserved = __cpu_to_le32(0), 1594 }, 1595 1596 /* CE3: host->target WMI */ 1597 { 1598 .pipenum = __cpu_to_le32(3), 1599 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1600 .nentries = __cpu_to_le32(32), 1601 .nbytes_max = __cpu_to_le32(2048), 1602 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1603 .reserved = __cpu_to_le32(0), 1604 }, 1605 1606 /* CE4: host->target HTT */ 1607 { 1608 .pipenum = __cpu_to_le32(4), 1609 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1610 .nentries = __cpu_to_le32(256), 1611 .nbytes_max = __cpu_to_le32(256), 1612 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1613 .reserved = __cpu_to_le32(0), 1614 }, 1615 1616 /* CE5: target->host Pktlog */ 1617 { 1618 .pipenum = __cpu_to_le32(5), 1619 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1620 .nentries = __cpu_to_le32(32), 1621 .nbytes_max = __cpu_to_le32(2048), 1622 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1623 .reserved = __cpu_to_le32(0), 1624 }, 1625 1626 /* CE6: Reserved for target autonomous hif_memcpy */ 1627 { 1628 .pipenum = __cpu_to_le32(6), 1629 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1630 .nentries = __cpu_to_le32(32), 1631 .nbytes_max = __cpu_to_le32(16384), 1632 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1633 .reserved = __cpu_to_le32(0), 1634 }, 1635 1636 /* CE7 used only by Host */ 1637 { 1638 .pipenum = __cpu_to_le32(7), 1639 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 1640 .nentries = __cpu_to_le32(0), 1641 .nbytes_max = __cpu_to_le32(0), 1642 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1643 .reserved = __cpu_to_le32(0), 1644 }, 1645 1646 /* CE8 target->host used only by IPA */ 1647 { 1648 .pipenum = __cpu_to_le32(8), 1649 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1650 .nentries = __cpu_to_le32(32), 1651 .nbytes_max = __cpu_to_le32(16384), 1652 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1653 .reserved = __cpu_to_le32(0), 1654 }, 1655 /* CE 9, 10, 11 are used by MHI driver */ 1656 }; 1657 1658 /* Map from service/endpoint to Copy Engine. 1659 * This table is derived from the CE_PCI TABLE, above. 1660 * It is passed to the Target at startup for use by firmware. 1661 */ 1662 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qcn9074[] = { 1663 { 1664 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1665 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1666 __cpu_to_le32(3), 1667 }, 1668 { 1669 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1670 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1671 __cpu_to_le32(2), 1672 }, 1673 { 1674 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1675 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1676 __cpu_to_le32(3), 1677 }, 1678 { 1679 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1680 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1681 __cpu_to_le32(2), 1682 }, 1683 { 1684 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1685 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1686 __cpu_to_le32(3), 1687 }, 1688 { 1689 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1690 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1691 __cpu_to_le32(2), 1692 }, 1693 { 1694 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1695 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1696 __cpu_to_le32(3), 1697 }, 1698 { 1699 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1700 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1701 __cpu_to_le32(2), 1702 }, 1703 { 1704 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1705 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1706 __cpu_to_le32(3), 1707 }, 1708 { 1709 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1710 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1711 __cpu_to_le32(2), 1712 }, 1713 { 1714 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1715 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1716 __cpu_to_le32(0), 1717 }, 1718 { 1719 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1720 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1721 __cpu_to_le32(1), 1722 }, 1723 { 1724 __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1725 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1726 __cpu_to_le32(0), 1727 }, 1728 { 1729 __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1730 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1731 __cpu_to_le32(1), 1732 }, 1733 { 1734 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1735 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1736 __cpu_to_le32(4), 1737 }, 1738 { 1739 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1740 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1741 __cpu_to_le32(1), 1742 }, 1743 { 1744 __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 1745 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1746 __cpu_to_le32(5), 1747 }, 1748 1749 /* (Additions here) */ 1750 1751 { /* must be last */ 1752 __cpu_to_le32(0), 1753 __cpu_to_le32(0), 1754 __cpu_to_le32(0), 1755 }, 1756 }; 1757 1758 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qcn9074 = { 1759 .tx = { 1760 ATH11K_TX_RING_MASK_0, 1761 ATH11K_TX_RING_MASK_1, 1762 ATH11K_TX_RING_MASK_2, 1763 }, 1764 .rx_mon_status = { 1765 0, 0, 0, 1766 ATH11K_RX_MON_STATUS_RING_MASK_0, 1767 ATH11K_RX_MON_STATUS_RING_MASK_1, 1768 ATH11K_RX_MON_STATUS_RING_MASK_2, 1769 }, 1770 .rx = { 1771 0, 0, 0, 0, 1772 ATH11K_RX_RING_MASK_0, 1773 ATH11K_RX_RING_MASK_1, 1774 ATH11K_RX_RING_MASK_2, 1775 ATH11K_RX_RING_MASK_3, 1776 }, 1777 .rx_err = { 1778 0, 0, 0, 1779 ATH11K_RX_ERR_RING_MASK_0, 1780 }, 1781 .rx_wbm_rel = { 1782 0, 0, 0, 1783 ATH11K_RX_WBM_REL_RING_MASK_0, 1784 }, 1785 .reo_status = { 1786 0, 0, 0, 1787 ATH11K_REO_STATUS_RING_MASK_0, 1788 }, 1789 .rxdma2host = { 1790 0, 0, 0, 1791 ATH11K_RXDMA2HOST_RING_MASK_0, 1792 }, 1793 .host2rxdma = { 1794 0, 0, 0, 1795 ATH11K_HOST2RXDMA_RING_MASK_0, 1796 }, 1797 }; 1798 1799 const struct ath11k_hw_regs ipq8074_regs = { 1800 /* SW2TCL(x) R0 ring configuration address */ 1801 .hal_tcl1_ring_base_lsb = 0x00000510, 1802 .hal_tcl1_ring_base_msb = 0x00000514, 1803 .hal_tcl1_ring_id = 0x00000518, 1804 .hal_tcl1_ring_misc = 0x00000520, 1805 .hal_tcl1_ring_tp_addr_lsb = 0x0000052c, 1806 .hal_tcl1_ring_tp_addr_msb = 0x00000530, 1807 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000540, 1808 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000544, 1809 .hal_tcl1_ring_msi1_base_lsb = 0x00000558, 1810 .hal_tcl1_ring_msi1_base_msb = 0x0000055c, 1811 .hal_tcl1_ring_msi1_data = 0x00000560, 1812 .hal_tcl2_ring_base_lsb = 0x00000568, 1813 .hal_tcl_ring_base_lsb = 0x00000618, 1814 1815 /* TCL STATUS ring address */ 1816 .hal_tcl_status_ring_base_lsb = 0x00000720, 1817 1818 /* REO2SW(x) R0 ring configuration address */ 1819 .hal_reo1_ring_base_lsb = 0x0000029c, 1820 .hal_reo1_ring_base_msb = 0x000002a0, 1821 .hal_reo1_ring_id = 0x000002a4, 1822 .hal_reo1_ring_misc = 0x000002ac, 1823 .hal_reo1_ring_hp_addr_lsb = 0x000002b0, 1824 .hal_reo1_ring_hp_addr_msb = 0x000002b4, 1825 .hal_reo1_ring_producer_int_setup = 0x000002c0, 1826 .hal_reo1_ring_msi1_base_lsb = 0x000002e4, 1827 .hal_reo1_ring_msi1_base_msb = 0x000002e8, 1828 .hal_reo1_ring_msi1_data = 0x000002ec, 1829 .hal_reo2_ring_base_lsb = 0x000002f4, 1830 .hal_reo1_aging_thresh_ix_0 = 0x00000564, 1831 .hal_reo1_aging_thresh_ix_1 = 0x00000568, 1832 .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 1833 .hal_reo1_aging_thresh_ix_3 = 0x00000570, 1834 1835 /* REO2SW(x) R2 ring pointers (head/tail) address */ 1836 .hal_reo1_ring_hp = 0x00003038, 1837 .hal_reo1_ring_tp = 0x0000303c, 1838 .hal_reo2_ring_hp = 0x00003040, 1839 1840 /* REO2TCL R0 ring configuration address */ 1841 .hal_reo_tcl_ring_base_lsb = 0x000003fc, 1842 .hal_reo_tcl_ring_hp = 0x00003058, 1843 1844 /* REO status address */ 1845 .hal_reo_status_ring_base_lsb = 0x00000504, 1846 .hal_reo_status_hp = 0x00003070, 1847 1848 /* WCSS relative address */ 1849 .hal_seq_wcss_umac_ce0_src_reg = 0x00a00000, 1850 .hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000, 1851 .hal_seq_wcss_umac_ce1_src_reg = 0x00a02000, 1852 .hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000, 1853 1854 /* WBM Idle address */ 1855 .hal_wbm_idle_link_ring_base_lsb = 0x00000860, 1856 .hal_wbm_idle_link_ring_misc = 0x00000870, 1857 1858 /* SW2WBM release address */ 1859 .hal_wbm_release_ring_base_lsb = 0x000001d8, 1860 1861 /* WBM2SW release address */ 1862 .hal_wbm0_release_ring_base_lsb = 0x00000910, 1863 .hal_wbm1_release_ring_base_lsb = 0x00000968, 1864 1865 /* PCIe base address */ 1866 .pcie_qserdes_sysclk_en_sel = 0x0, 1867 .pcie_pcs_osc_dtct_config_base = 0x0, 1868 }; 1869 1870 const struct ath11k_hw_regs qca6390_regs = { 1871 /* SW2TCL(x) R0 ring configuration address */ 1872 .hal_tcl1_ring_base_lsb = 0x00000684, 1873 .hal_tcl1_ring_base_msb = 0x00000688, 1874 .hal_tcl1_ring_id = 0x0000068c, 1875 .hal_tcl1_ring_misc = 0x00000694, 1876 .hal_tcl1_ring_tp_addr_lsb = 0x000006a0, 1877 .hal_tcl1_ring_tp_addr_msb = 0x000006a4, 1878 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006b4, 1879 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006b8, 1880 .hal_tcl1_ring_msi1_base_lsb = 0x000006cc, 1881 .hal_tcl1_ring_msi1_base_msb = 0x000006d0, 1882 .hal_tcl1_ring_msi1_data = 0x000006d4, 1883 .hal_tcl2_ring_base_lsb = 0x000006dc, 1884 .hal_tcl_ring_base_lsb = 0x0000078c, 1885 1886 /* TCL STATUS ring address */ 1887 .hal_tcl_status_ring_base_lsb = 0x00000894, 1888 1889 /* REO2SW(x) R0 ring configuration address */ 1890 .hal_reo1_ring_base_lsb = 0x00000244, 1891 .hal_reo1_ring_base_msb = 0x00000248, 1892 .hal_reo1_ring_id = 0x0000024c, 1893 .hal_reo1_ring_misc = 0x00000254, 1894 .hal_reo1_ring_hp_addr_lsb = 0x00000258, 1895 .hal_reo1_ring_hp_addr_msb = 0x0000025c, 1896 .hal_reo1_ring_producer_int_setup = 0x00000268, 1897 .hal_reo1_ring_msi1_base_lsb = 0x0000028c, 1898 .hal_reo1_ring_msi1_base_msb = 0x00000290, 1899 .hal_reo1_ring_msi1_data = 0x00000294, 1900 .hal_reo2_ring_base_lsb = 0x0000029c, 1901 .hal_reo1_aging_thresh_ix_0 = 0x0000050c, 1902 .hal_reo1_aging_thresh_ix_1 = 0x00000510, 1903 .hal_reo1_aging_thresh_ix_2 = 0x00000514, 1904 .hal_reo1_aging_thresh_ix_3 = 0x00000518, 1905 1906 /* REO2SW(x) R2 ring pointers (head/tail) address */ 1907 .hal_reo1_ring_hp = 0x00003030, 1908 .hal_reo1_ring_tp = 0x00003034, 1909 .hal_reo2_ring_hp = 0x00003038, 1910 1911 /* REO2TCL R0 ring configuration address */ 1912 .hal_reo_tcl_ring_base_lsb = 0x000003a4, 1913 .hal_reo_tcl_ring_hp = 0x00003050, 1914 1915 /* REO status address */ 1916 .hal_reo_status_ring_base_lsb = 0x000004ac, 1917 .hal_reo_status_hp = 0x00003068, 1918 1919 /* WCSS relative address */ 1920 .hal_seq_wcss_umac_ce0_src_reg = 0x00a00000, 1921 .hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000, 1922 .hal_seq_wcss_umac_ce1_src_reg = 0x00a02000, 1923 .hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000, 1924 1925 /* WBM Idle address */ 1926 .hal_wbm_idle_link_ring_base_lsb = 0x00000860, 1927 .hal_wbm_idle_link_ring_misc = 0x00000870, 1928 1929 /* SW2WBM release address */ 1930 .hal_wbm_release_ring_base_lsb = 0x000001d8, 1931 1932 /* WBM2SW release address */ 1933 .hal_wbm0_release_ring_base_lsb = 0x00000910, 1934 .hal_wbm1_release_ring_base_lsb = 0x00000968, 1935 1936 /* PCIe base address */ 1937 .pcie_qserdes_sysclk_en_sel = 0x01e0c0ac, 1938 .pcie_pcs_osc_dtct_config_base = 0x01e0c628, 1939 }; 1940 1941 const struct ath11k_hw_regs qcn9074_regs = { 1942 /* SW2TCL(x) R0 ring configuration address */ 1943 .hal_tcl1_ring_base_lsb = 0x000004f0, 1944 .hal_tcl1_ring_base_msb = 0x000004f4, 1945 .hal_tcl1_ring_id = 0x000004f8, 1946 .hal_tcl1_ring_misc = 0x00000500, 1947 .hal_tcl1_ring_tp_addr_lsb = 0x0000050c, 1948 .hal_tcl1_ring_tp_addr_msb = 0x00000510, 1949 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000520, 1950 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000524, 1951 .hal_tcl1_ring_msi1_base_lsb = 0x00000538, 1952 .hal_tcl1_ring_msi1_base_msb = 0x0000053c, 1953 .hal_tcl1_ring_msi1_data = 0x00000540, 1954 .hal_tcl2_ring_base_lsb = 0x00000548, 1955 .hal_tcl_ring_base_lsb = 0x000005f8, 1956 1957 /* TCL STATUS ring address */ 1958 .hal_tcl_status_ring_base_lsb = 0x00000700, 1959 1960 /* REO2SW(x) R0 ring configuration address */ 1961 .hal_reo1_ring_base_lsb = 0x0000029c, 1962 .hal_reo1_ring_base_msb = 0x000002a0, 1963 .hal_reo1_ring_id = 0x000002a4, 1964 .hal_reo1_ring_misc = 0x000002ac, 1965 .hal_reo1_ring_hp_addr_lsb = 0x000002b0, 1966 .hal_reo1_ring_hp_addr_msb = 0x000002b4, 1967 .hal_reo1_ring_producer_int_setup = 0x000002c0, 1968 .hal_reo1_ring_msi1_base_lsb = 0x000002e4, 1969 .hal_reo1_ring_msi1_base_msb = 0x000002e8, 1970 .hal_reo1_ring_msi1_data = 0x000002ec, 1971 .hal_reo2_ring_base_lsb = 0x000002f4, 1972 .hal_reo1_aging_thresh_ix_0 = 0x00000564, 1973 .hal_reo1_aging_thresh_ix_1 = 0x00000568, 1974 .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 1975 .hal_reo1_aging_thresh_ix_3 = 0x00000570, 1976 1977 /* REO2SW(x) R2 ring pointers (head/tail) address */ 1978 .hal_reo1_ring_hp = 0x00003038, 1979 .hal_reo1_ring_tp = 0x0000303c, 1980 .hal_reo2_ring_hp = 0x00003040, 1981 1982 /* REO2TCL R0 ring configuration address */ 1983 .hal_reo_tcl_ring_base_lsb = 0x000003fc, 1984 .hal_reo_tcl_ring_hp = 0x00003058, 1985 1986 /* REO status address */ 1987 .hal_reo_status_ring_base_lsb = 0x00000504, 1988 .hal_reo_status_hp = 0x00003070, 1989 1990 /* WCSS relative address */ 1991 .hal_seq_wcss_umac_ce0_src_reg = 0x01b80000, 1992 .hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000, 1993 .hal_seq_wcss_umac_ce1_src_reg = 0x01b82000, 1994 .hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000, 1995 1996 /* WBM Idle address */ 1997 .hal_wbm_idle_link_ring_base_lsb = 0x00000874, 1998 .hal_wbm_idle_link_ring_misc = 0x00000884, 1999 2000 /* SW2WBM release address */ 2001 .hal_wbm_release_ring_base_lsb = 0x000001ec, 2002 2003 /* WBM2SW release address */ 2004 .hal_wbm0_release_ring_base_lsb = 0x00000924, 2005 .hal_wbm1_release_ring_base_lsb = 0x0000097c, 2006 2007 /* PCIe base address */ 2008 .pcie_qserdes_sysclk_en_sel = 0x01e0e0a8, 2009 .pcie_pcs_osc_dtct_config_base = 0x01e0f45c, 2010 }; 2011 2012 const struct ath11k_hw_regs wcn6855_regs = { 2013 /* SW2TCL(x) R0 ring configuration address */ 2014 .hal_tcl1_ring_base_lsb = 0x00000690, 2015 .hal_tcl1_ring_base_msb = 0x00000694, 2016 .hal_tcl1_ring_id = 0x00000698, 2017 .hal_tcl1_ring_misc = 0x000006a0, 2018 .hal_tcl1_ring_tp_addr_lsb = 0x000006ac, 2019 .hal_tcl1_ring_tp_addr_msb = 0x000006b0, 2020 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c0, 2021 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c4, 2022 .hal_tcl1_ring_msi1_base_lsb = 0x000006d8, 2023 .hal_tcl1_ring_msi1_base_msb = 0x000006dc, 2024 .hal_tcl1_ring_msi1_data = 0x000006e0, 2025 .hal_tcl2_ring_base_lsb = 0x000006e8, 2026 .hal_tcl_ring_base_lsb = 0x00000798, 2027 2028 /* TCL STATUS ring address */ 2029 .hal_tcl_status_ring_base_lsb = 0x000008a0, 2030 2031 /* REO2SW(x) R0 ring configuration address */ 2032 .hal_reo1_ring_base_lsb = 0x00000244, 2033 .hal_reo1_ring_base_msb = 0x00000248, 2034 .hal_reo1_ring_id = 0x0000024c, 2035 .hal_reo1_ring_misc = 0x00000254, 2036 .hal_reo1_ring_hp_addr_lsb = 0x00000258, 2037 .hal_reo1_ring_hp_addr_msb = 0x0000025c, 2038 .hal_reo1_ring_producer_int_setup = 0x00000268, 2039 .hal_reo1_ring_msi1_base_lsb = 0x0000028c, 2040 .hal_reo1_ring_msi1_base_msb = 0x00000290, 2041 .hal_reo1_ring_msi1_data = 0x00000294, 2042 .hal_reo2_ring_base_lsb = 0x0000029c, 2043 .hal_reo1_aging_thresh_ix_0 = 0x000005bc, 2044 .hal_reo1_aging_thresh_ix_1 = 0x000005c0, 2045 .hal_reo1_aging_thresh_ix_2 = 0x000005c4, 2046 .hal_reo1_aging_thresh_ix_3 = 0x000005c8, 2047 2048 /* REO2SW(x) R2 ring pointers (head/tail) address */ 2049 .hal_reo1_ring_hp = 0x00003030, 2050 .hal_reo1_ring_tp = 0x00003034, 2051 .hal_reo2_ring_hp = 0x00003038, 2052 2053 /* REO2TCL R0 ring configuration address */ 2054 .hal_reo_tcl_ring_base_lsb = 0x00000454, 2055 .hal_reo_tcl_ring_hp = 0x00003060, 2056 2057 /* REO status address */ 2058 .hal_reo_status_ring_base_lsb = 0x0000055c, 2059 .hal_reo_status_hp = 0x00003078, 2060 2061 /* WCSS relative address */ 2062 .hal_seq_wcss_umac_ce0_src_reg = 0x1b80000, 2063 .hal_seq_wcss_umac_ce0_dst_reg = 0x1b81000, 2064 .hal_seq_wcss_umac_ce1_src_reg = 0x1b82000, 2065 .hal_seq_wcss_umac_ce1_dst_reg = 0x1b83000, 2066 2067 /* WBM Idle address */ 2068 .hal_wbm_idle_link_ring_base_lsb = 0x00000870, 2069 .hal_wbm_idle_link_ring_misc = 0x00000880, 2070 2071 /* SW2WBM release address */ 2072 .hal_wbm_release_ring_base_lsb = 0x000001e8, 2073 2074 /* WBM2SW release address */ 2075 .hal_wbm0_release_ring_base_lsb = 0x00000920, 2076 .hal_wbm1_release_ring_base_lsb = 0x00000978, 2077 2078 /* PCIe base address */ 2079 .pcie_qserdes_sysclk_en_sel = 0x01e0c0ac, 2080 .pcie_pcs_osc_dtct_config_base = 0x01e0c628, 2081 }; 2082