1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/types.h> 7 #include <linux/bitops.h> 8 #include <linux/bitfield.h> 9 10 #include "hw.h" 11 #include "core.h" 12 #include "ce.h" 13 14 /* Map from pdev index to hw mac index */ 15 static u8 ath11k_hw_ipq8074_mac_from_pdev_id(int pdev_idx) 16 { 17 switch (pdev_idx) { 18 case 0: 19 return 0; 20 case 1: 21 return 2; 22 case 2: 23 return 1; 24 default: 25 return ATH11K_INVALID_HW_MAC_ID; 26 } 27 } 28 29 static u8 ath11k_hw_ipq6018_mac_from_pdev_id(int pdev_idx) 30 { 31 return pdev_idx; 32 } 33 34 static void ath11k_init_wmi_config_qca6390(struct ath11k_base *ab, 35 struct target_resource_config *config) 36 { 37 config->num_vdevs = 4; 38 config->num_peers = 16; 39 config->num_tids = 32; 40 41 config->num_offload_peers = 3; 42 config->num_offload_reorder_buffs = 3; 43 config->num_peer_keys = TARGET_NUM_PEER_KEYS; 44 config->ast_skid_limit = TARGET_AST_SKID_LIMIT; 45 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 46 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 47 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; 48 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI; 49 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; 50 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; 51 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; 52 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS; 53 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV; 54 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV; 55 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES; 56 config->num_mcast_groups = 0; 57 config->num_mcast_table_elems = 0; 58 config->mcast2ucast_mode = 0; 59 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE; 60 config->num_wds_entries = 0; 61 config->dma_burst_size = 0; 62 config->rx_skip_defrag_timeout_dup_detection_check = 0; 63 config->vow_config = TARGET_VOW_CONFIG; 64 config->gtk_offload_max_vdev = 2; 65 config->num_msdu_desc = 0x400; 66 config->beacon_tx_offload_max_vdev = 2; 67 config->rx_batchmode = TARGET_RX_BATCHMODE; 68 69 config->peer_map_unmap_v2_support = 0; 70 config->use_pdev_id = 1; 71 config->max_frag_entries = 0xa; 72 config->num_tdls_vdevs = 0x1; 73 config->num_tdls_conn_table_entries = 8; 74 config->beacon_tx_offload_max_vdev = 0x2; 75 config->num_multicast_filter_entries = 0x20; 76 config->num_wow_filters = 0x16; 77 config->num_keep_alive_pattern = 0; 78 } 79 80 static void ath11k_init_wmi_config_ipq8074(struct ath11k_base *ab, 81 struct target_resource_config *config) 82 { 83 config->num_vdevs = ab->num_radios * TARGET_NUM_VDEVS; 84 85 if (ab->num_radios == 2) { 86 config->num_peers = TARGET_NUM_PEERS(DBS); 87 config->num_tids = TARGET_NUM_TIDS(DBS); 88 } else if (ab->num_radios == 3) { 89 config->num_peers = TARGET_NUM_PEERS(DBS_SBS); 90 config->num_tids = TARGET_NUM_TIDS(DBS_SBS); 91 } else { 92 /* Control should not reach here */ 93 config->num_peers = TARGET_NUM_PEERS(SINGLE); 94 config->num_tids = TARGET_NUM_TIDS(SINGLE); 95 } 96 config->num_offload_peers = TARGET_NUM_OFFLD_PEERS; 97 config->num_offload_reorder_buffs = TARGET_NUM_OFFLD_REORDER_BUFFS; 98 config->num_peer_keys = TARGET_NUM_PEER_KEYS; 99 config->ast_skid_limit = TARGET_AST_SKID_LIMIT; 100 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 101 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 102 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; 103 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI; 104 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; 105 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; 106 107 if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) 108 config->rx_decap_mode = TARGET_DECAP_MODE_RAW; 109 else 110 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; 111 112 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS; 113 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV; 114 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV; 115 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES; 116 config->num_mcast_groups = TARGET_NUM_MCAST_GROUPS; 117 config->num_mcast_table_elems = TARGET_NUM_MCAST_TABLE_ELEMS; 118 config->mcast2ucast_mode = TARGET_MCAST2UCAST_MODE; 119 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE; 120 config->num_wds_entries = TARGET_NUM_WDS_ENTRIES; 121 config->dma_burst_size = TARGET_DMA_BURST_SIZE; 122 config->rx_skip_defrag_timeout_dup_detection_check = 123 TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK; 124 config->vow_config = TARGET_VOW_CONFIG; 125 config->gtk_offload_max_vdev = TARGET_GTK_OFFLOAD_MAX_VDEV; 126 config->num_msdu_desc = TARGET_NUM_MSDU_DESC; 127 config->beacon_tx_offload_max_vdev = ab->num_radios * TARGET_MAX_BCN_OFFLD; 128 config->rx_batchmode = TARGET_RX_BATCHMODE; 129 config->peer_map_unmap_v2_support = 1; 130 config->twt_ap_pdev_count = 2; 131 config->twt_ap_sta_count = 1000; 132 } 133 134 static int ath11k_hw_mac_id_to_pdev_id_ipq8074(struct ath11k_hw_params *hw, 135 int mac_id) 136 { 137 return mac_id; 138 } 139 140 static int ath11k_hw_mac_id_to_srng_id_ipq8074(struct ath11k_hw_params *hw, 141 int mac_id) 142 { 143 return 0; 144 } 145 146 static int ath11k_hw_mac_id_to_pdev_id_qca6390(struct ath11k_hw_params *hw, 147 int mac_id) 148 { 149 return 0; 150 } 151 152 static int ath11k_hw_mac_id_to_srng_id_qca6390(struct ath11k_hw_params *hw, 153 int mac_id) 154 { 155 return mac_id; 156 } 157 158 const struct ath11k_hw_ops ipq8074_ops = { 159 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 160 .wmi_init_config = ath11k_init_wmi_config_qca6390, 161 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 162 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 163 }; 164 165 const struct ath11k_hw_ops ipq6018_ops = { 166 .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 167 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 168 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 169 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 170 }; 171 172 const struct ath11k_hw_ops qca6390_ops = { 173 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 174 .wmi_init_config = ath11k_init_wmi_config_qca6390, 175 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390, 176 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390, 177 }; 178 179 #define ATH11K_TX_RING_MASK_0 0x1 180 #define ATH11K_TX_RING_MASK_1 0x2 181 #define ATH11K_TX_RING_MASK_2 0x4 182 183 #define ATH11K_RX_RING_MASK_0 0x1 184 #define ATH11K_RX_RING_MASK_1 0x2 185 #define ATH11K_RX_RING_MASK_2 0x4 186 #define ATH11K_RX_RING_MASK_3 0x8 187 188 #define ATH11K_RX_ERR_RING_MASK_0 0x1 189 190 #define ATH11K_RX_WBM_REL_RING_MASK_0 0x1 191 192 #define ATH11K_REO_STATUS_RING_MASK_0 0x1 193 194 #define ATH11K_RXDMA2HOST_RING_MASK_0 0x1 195 #define ATH11K_RXDMA2HOST_RING_MASK_1 0x2 196 #define ATH11K_RXDMA2HOST_RING_MASK_2 0x4 197 198 #define ATH11K_HOST2RXDMA_RING_MASK_0 0x1 199 #define ATH11K_HOST2RXDMA_RING_MASK_1 0x2 200 #define ATH11K_HOST2RXDMA_RING_MASK_2 0x4 201 202 #define ATH11K_RX_MON_STATUS_RING_MASK_0 0x1 203 #define ATH11K_RX_MON_STATUS_RING_MASK_1 0x2 204 #define ATH11K_RX_MON_STATUS_RING_MASK_2 0x4 205 206 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074 = { 207 .tx = { 208 ATH11K_TX_RING_MASK_0, 209 ATH11K_TX_RING_MASK_1, 210 ATH11K_TX_RING_MASK_2, 211 }, 212 .rx_mon_status = { 213 0, 0, 0, 0, 214 ATH11K_RX_MON_STATUS_RING_MASK_0, 215 ATH11K_RX_MON_STATUS_RING_MASK_1, 216 ATH11K_RX_MON_STATUS_RING_MASK_2, 217 }, 218 .rx = { 219 0, 0, 0, 0, 0, 0, 0, 220 ATH11K_RX_RING_MASK_0, 221 ATH11K_RX_RING_MASK_1, 222 ATH11K_RX_RING_MASK_2, 223 ATH11K_RX_RING_MASK_3, 224 }, 225 .rx_err = { 226 ATH11K_RX_ERR_RING_MASK_0, 227 }, 228 .rx_wbm_rel = { 229 ATH11K_RX_WBM_REL_RING_MASK_0, 230 }, 231 .reo_status = { 232 ATH11K_REO_STATUS_RING_MASK_0, 233 }, 234 .rxdma2host = { 235 ATH11K_RXDMA2HOST_RING_MASK_0, 236 ATH11K_RXDMA2HOST_RING_MASK_1, 237 ATH11K_RXDMA2HOST_RING_MASK_2, 238 }, 239 .host2rxdma = { 240 ATH11K_HOST2RXDMA_RING_MASK_0, 241 ATH11K_HOST2RXDMA_RING_MASK_1, 242 ATH11K_HOST2RXDMA_RING_MASK_2, 243 }, 244 }; 245 246 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390 = { 247 .tx = { 248 ATH11K_TX_RING_MASK_0, 249 ATH11K_TX_RING_MASK_1, 250 ATH11K_TX_RING_MASK_2, 251 }, 252 .rx_mon_status = { 253 0, 0, 0, 0, 254 ATH11K_RX_MON_STATUS_RING_MASK_0, 255 ATH11K_RX_MON_STATUS_RING_MASK_1, 256 ATH11K_RX_MON_STATUS_RING_MASK_2, 257 }, 258 .rx = { 259 0, 0, 0, 0, 0, 0, 0, 260 ATH11K_RX_RING_MASK_0, 261 ATH11K_RX_RING_MASK_1, 262 ATH11K_RX_RING_MASK_2, 263 ATH11K_RX_RING_MASK_3, 264 }, 265 .rx_err = { 266 ATH11K_RX_ERR_RING_MASK_0, 267 }, 268 .rx_wbm_rel = { 269 ATH11K_RX_WBM_REL_RING_MASK_0, 270 }, 271 .reo_status = { 272 ATH11K_REO_STATUS_RING_MASK_0, 273 }, 274 .rxdma2host = { 275 ATH11K_RXDMA2HOST_RING_MASK_0, 276 ATH11K_RXDMA2HOST_RING_MASK_1, 277 ATH11K_RXDMA2HOST_RING_MASK_2, 278 }, 279 .host2rxdma = { 280 }, 281 }; 282 283 /* Target firmware's Copy Engine configuration. */ 284 const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq8074[] = { 285 /* CE0: host->target HTC control and raw streams */ 286 { 287 .pipenum = __cpu_to_le32(0), 288 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 289 .nentries = __cpu_to_le32(32), 290 .nbytes_max = __cpu_to_le32(2048), 291 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 292 .reserved = __cpu_to_le32(0), 293 }, 294 295 /* CE1: target->host HTT + HTC control */ 296 { 297 .pipenum = __cpu_to_le32(1), 298 .pipedir = __cpu_to_le32(PIPEDIR_IN), 299 .nentries = __cpu_to_le32(32), 300 .nbytes_max = __cpu_to_le32(2048), 301 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 302 .reserved = __cpu_to_le32(0), 303 }, 304 305 /* CE2: target->host WMI */ 306 { 307 .pipenum = __cpu_to_le32(2), 308 .pipedir = __cpu_to_le32(PIPEDIR_IN), 309 .nentries = __cpu_to_le32(32), 310 .nbytes_max = __cpu_to_le32(2048), 311 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 312 .reserved = __cpu_to_le32(0), 313 }, 314 315 /* CE3: host->target WMI */ 316 { 317 .pipenum = __cpu_to_le32(3), 318 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 319 .nentries = __cpu_to_le32(32), 320 .nbytes_max = __cpu_to_le32(2048), 321 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 322 .reserved = __cpu_to_le32(0), 323 }, 324 325 /* CE4: host->target HTT */ 326 { 327 .pipenum = __cpu_to_le32(4), 328 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 329 .nentries = __cpu_to_le32(256), 330 .nbytes_max = __cpu_to_le32(256), 331 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 332 .reserved = __cpu_to_le32(0), 333 }, 334 335 /* CE5: target->host Pktlog */ 336 { 337 .pipenum = __cpu_to_le32(5), 338 .pipedir = __cpu_to_le32(PIPEDIR_IN), 339 .nentries = __cpu_to_le32(32), 340 .nbytes_max = __cpu_to_le32(2048), 341 .flags = __cpu_to_le32(0), 342 .reserved = __cpu_to_le32(0), 343 }, 344 345 /* CE6: Reserved for target autonomous hif_memcpy */ 346 { 347 .pipenum = __cpu_to_le32(6), 348 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 349 .nentries = __cpu_to_le32(32), 350 .nbytes_max = __cpu_to_le32(65535), 351 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 352 .reserved = __cpu_to_le32(0), 353 }, 354 355 /* CE7 used only by Host */ 356 { 357 .pipenum = __cpu_to_le32(7), 358 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 359 .nentries = __cpu_to_le32(32), 360 .nbytes_max = __cpu_to_le32(2048), 361 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 362 .reserved = __cpu_to_le32(0), 363 }, 364 365 /* CE8 target->host used only by IPA */ 366 { 367 .pipenum = __cpu_to_le32(8), 368 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 369 .nentries = __cpu_to_le32(32), 370 .nbytes_max = __cpu_to_le32(65535), 371 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 372 .reserved = __cpu_to_le32(0), 373 }, 374 375 /* CE9 host->target HTT */ 376 { 377 .pipenum = __cpu_to_le32(9), 378 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 379 .nentries = __cpu_to_le32(32), 380 .nbytes_max = __cpu_to_le32(2048), 381 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 382 .reserved = __cpu_to_le32(0), 383 }, 384 385 /* CE10 target->host HTT */ 386 { 387 .pipenum = __cpu_to_le32(10), 388 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 389 .nentries = __cpu_to_le32(0), 390 .nbytes_max = __cpu_to_le32(0), 391 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 392 .reserved = __cpu_to_le32(0), 393 }, 394 395 /* CE11 Not used */ 396 }; 397 398 /* Map from service/endpoint to Copy Engine. 399 * This table is derived from the CE_PCI TABLE, above. 400 * It is passed to the Target at startup for use by firmware. 401 */ 402 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq8074[] = { 403 { 404 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 405 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 406 .pipenum = __cpu_to_le32(3), 407 }, 408 { 409 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 410 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 411 .pipenum = __cpu_to_le32(2), 412 }, 413 { 414 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 415 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 416 .pipenum = __cpu_to_le32(3), 417 }, 418 { 419 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 420 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 421 .pipenum = __cpu_to_le32(2), 422 }, 423 { 424 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 425 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 426 .pipenum = __cpu_to_le32(3), 427 }, 428 { 429 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 430 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 431 .pipenum = __cpu_to_le32(2), 432 }, 433 { 434 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 435 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 436 .pipenum = __cpu_to_le32(3), 437 }, 438 { 439 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 440 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 441 .pipenum = __cpu_to_le32(2), 442 }, 443 { 444 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 445 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 446 .pipenum = __cpu_to_le32(3), 447 }, 448 { 449 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 450 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 451 .pipenum = __cpu_to_le32(2), 452 }, 453 { 454 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 455 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 456 .pipenum = __cpu_to_le32(7), 457 }, 458 { 459 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 460 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 461 .pipenum = __cpu_to_le32(2), 462 }, 463 { 464 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2), 465 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 466 .pipenum = __cpu_to_le32(9), 467 }, 468 { 469 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2), 470 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 471 .pipenum = __cpu_to_le32(2), 472 }, 473 { 474 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 475 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 476 .pipenum = __cpu_to_le32(0), 477 }, 478 { 479 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 480 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 481 .pipenum = __cpu_to_le32(1), 482 }, 483 { /* not used */ 484 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 485 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 486 .pipenum = __cpu_to_le32(0), 487 }, 488 { /* not used */ 489 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 490 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 491 .pipenum = __cpu_to_le32(1), 492 }, 493 { 494 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 495 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 496 .pipenum = __cpu_to_le32(4), 497 }, 498 { 499 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 500 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 501 .pipenum = __cpu_to_le32(1), 502 }, 503 { 504 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 505 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 506 .pipenum = __cpu_to_le32(5), 507 }, 508 509 /* (Additions here) */ 510 511 { /* terminator entry */ } 512 }; 513 514 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq6018[] = { 515 { 516 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 517 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 518 .pipenum = __cpu_to_le32(3), 519 }, 520 { 521 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 522 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 523 .pipenum = __cpu_to_le32(2), 524 }, 525 { 526 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 527 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 528 .pipenum = __cpu_to_le32(3), 529 }, 530 { 531 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 532 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 533 .pipenum = __cpu_to_le32(2), 534 }, 535 { 536 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 537 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 538 .pipenum = __cpu_to_le32(3), 539 }, 540 { 541 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 542 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 543 .pipenum = __cpu_to_le32(2), 544 }, 545 { 546 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 547 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 548 .pipenum = __cpu_to_le32(3), 549 }, 550 { 551 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 552 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 553 .pipenum = __cpu_to_le32(2), 554 }, 555 { 556 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 557 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 558 .pipenum = __cpu_to_le32(3), 559 }, 560 { 561 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 562 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 563 .pipenum = __cpu_to_le32(2), 564 }, 565 { 566 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 567 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 568 .pipenum = __cpu_to_le32(7), 569 }, 570 { 571 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 572 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 573 .pipenum = __cpu_to_le32(2), 574 }, 575 { 576 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 577 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 578 .pipenum = __cpu_to_le32(0), 579 }, 580 { 581 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 582 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 583 .pipenum = __cpu_to_le32(1), 584 }, 585 { /* not used */ 586 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 587 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 588 .pipenum = __cpu_to_le32(0), 589 }, 590 { /* not used */ 591 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 592 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 593 .pipenum = __cpu_to_le32(1), 594 }, 595 { 596 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 597 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 598 .pipenum = __cpu_to_le32(4), 599 }, 600 { 601 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 602 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 603 .pipenum = __cpu_to_le32(1), 604 }, 605 { 606 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 607 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 608 .pipenum = __cpu_to_le32(5), 609 }, 610 611 /* (Additions here) */ 612 613 { /* terminator entry */ } 614 }; 615 616 /* Target firmware's Copy Engine configuration. */ 617 const struct ce_pipe_config ath11k_target_ce_config_wlan_qca6390[] = { 618 /* CE0: host->target HTC control and raw streams */ 619 { 620 .pipenum = __cpu_to_le32(0), 621 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 622 .nentries = __cpu_to_le32(32), 623 .nbytes_max = __cpu_to_le32(2048), 624 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 625 .reserved = __cpu_to_le32(0), 626 }, 627 628 /* CE1: target->host HTT + HTC control */ 629 { 630 .pipenum = __cpu_to_le32(1), 631 .pipedir = __cpu_to_le32(PIPEDIR_IN), 632 .nentries = __cpu_to_le32(32), 633 .nbytes_max = __cpu_to_le32(2048), 634 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 635 .reserved = __cpu_to_le32(0), 636 }, 637 638 /* CE2: target->host WMI */ 639 { 640 .pipenum = __cpu_to_le32(2), 641 .pipedir = __cpu_to_le32(PIPEDIR_IN), 642 .nentries = __cpu_to_le32(32), 643 .nbytes_max = __cpu_to_le32(2048), 644 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 645 .reserved = __cpu_to_le32(0), 646 }, 647 648 /* CE3: host->target WMI */ 649 { 650 .pipenum = __cpu_to_le32(3), 651 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 652 .nentries = __cpu_to_le32(32), 653 .nbytes_max = __cpu_to_le32(2048), 654 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 655 .reserved = __cpu_to_le32(0), 656 }, 657 658 /* CE4: host->target HTT */ 659 { 660 .pipenum = __cpu_to_le32(4), 661 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 662 .nentries = __cpu_to_le32(256), 663 .nbytes_max = __cpu_to_le32(256), 664 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 665 .reserved = __cpu_to_le32(0), 666 }, 667 668 /* CE5: target->host Pktlog */ 669 { 670 .pipenum = __cpu_to_le32(5), 671 .pipedir = __cpu_to_le32(PIPEDIR_IN), 672 .nentries = __cpu_to_le32(32), 673 .nbytes_max = __cpu_to_le32(2048), 674 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 675 .reserved = __cpu_to_le32(0), 676 }, 677 678 /* CE6: Reserved for target autonomous hif_memcpy */ 679 { 680 .pipenum = __cpu_to_le32(6), 681 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 682 .nentries = __cpu_to_le32(32), 683 .nbytes_max = __cpu_to_le32(16384), 684 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 685 .reserved = __cpu_to_le32(0), 686 }, 687 688 /* CE7 used only by Host */ 689 { 690 .pipenum = __cpu_to_le32(7), 691 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 692 .nentries = __cpu_to_le32(0), 693 .nbytes_max = __cpu_to_le32(0), 694 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 695 .reserved = __cpu_to_le32(0), 696 }, 697 698 /* CE8 target->host used only by IPA */ 699 { 700 .pipenum = __cpu_to_le32(8), 701 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 702 .nentries = __cpu_to_le32(32), 703 .nbytes_max = __cpu_to_le32(16384), 704 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 705 .reserved = __cpu_to_le32(0), 706 }, 707 /* CE 9, 10, 11 are used by MHI driver */ 708 }; 709 710 /* Map from service/endpoint to Copy Engine. 711 * This table is derived from the CE_PCI TABLE, above. 712 * It is passed to the Target at startup for use by firmware. 713 */ 714 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qca6390[] = { 715 { 716 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 717 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 718 __cpu_to_le32(3), 719 }, 720 { 721 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 722 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 723 __cpu_to_le32(2), 724 }, 725 { 726 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 727 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 728 __cpu_to_le32(3), 729 }, 730 { 731 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 732 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 733 __cpu_to_le32(2), 734 }, 735 { 736 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 737 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 738 __cpu_to_le32(3), 739 }, 740 { 741 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 742 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 743 __cpu_to_le32(2), 744 }, 745 { 746 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 747 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 748 __cpu_to_le32(3), 749 }, 750 { 751 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 752 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 753 __cpu_to_le32(2), 754 }, 755 { 756 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 757 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 758 __cpu_to_le32(3), 759 }, 760 { 761 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 762 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 763 __cpu_to_le32(2), 764 }, 765 { 766 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 767 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 768 __cpu_to_le32(0), 769 }, 770 { 771 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 772 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 773 __cpu_to_le32(2), 774 }, 775 { 776 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 777 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 778 __cpu_to_le32(4), 779 }, 780 { 781 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 782 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 783 __cpu_to_le32(1), 784 }, 785 786 /* (Additions here) */ 787 788 { /* must be last */ 789 __cpu_to_le32(0), 790 __cpu_to_le32(0), 791 __cpu_to_le32(0), 792 }, 793 }; 794 795 const struct ath11k_hw_regs ipq8074_regs = { 796 /* SW2TCL(x) R0 ring configuration address */ 797 .hal_tcl1_ring_base_lsb = 0x00000510, 798 .hal_tcl1_ring_base_msb = 0x00000514, 799 .hal_tcl1_ring_id = 0x00000518, 800 .hal_tcl1_ring_misc = 0x00000520, 801 .hal_tcl1_ring_tp_addr_lsb = 0x0000052c, 802 .hal_tcl1_ring_tp_addr_msb = 0x00000530, 803 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000540, 804 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000544, 805 .hal_tcl1_ring_msi1_base_lsb = 0x00000558, 806 .hal_tcl1_ring_msi1_base_msb = 0x0000055c, 807 .hal_tcl1_ring_msi1_data = 0x00000560, 808 .hal_tcl2_ring_base_lsb = 0x00000568, 809 .hal_tcl_ring_base_lsb = 0x00000618, 810 811 /* TCL STATUS ring address */ 812 .hal_tcl_status_ring_base_lsb = 0x00000720, 813 814 /* REO2SW(x) R0 ring configuration address */ 815 .hal_reo1_ring_base_lsb = 0x0000029c, 816 .hal_reo1_ring_base_msb = 0x000002a0, 817 .hal_reo1_ring_id = 0x000002a4, 818 .hal_reo1_ring_misc = 0x000002ac, 819 .hal_reo1_ring_hp_addr_lsb = 0x000002b0, 820 .hal_reo1_ring_hp_addr_msb = 0x000002b4, 821 .hal_reo1_ring_producer_int_setup = 0x000002c0, 822 .hal_reo1_ring_msi1_base_lsb = 0x000002e4, 823 .hal_reo1_ring_msi1_base_msb = 0x000002e8, 824 .hal_reo1_ring_msi1_data = 0x000002ec, 825 .hal_reo2_ring_base_lsb = 0x000002f4, 826 .hal_reo1_aging_thresh_ix_0 = 0x00000564, 827 .hal_reo1_aging_thresh_ix_1 = 0x00000568, 828 .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 829 .hal_reo1_aging_thresh_ix_3 = 0x00000570, 830 831 /* REO2SW(x) R2 ring pointers (head/tail) address */ 832 .hal_reo1_ring_hp = 0x00003038, 833 .hal_reo1_ring_tp = 0x0000303c, 834 .hal_reo2_ring_hp = 0x00003040, 835 836 /* REO2TCL R0 ring configuration address */ 837 .hal_reo_tcl_ring_base_lsb = 0x000003fc, 838 .hal_reo_tcl_ring_hp = 0x00003058, 839 840 /* REO status address */ 841 .hal_reo_status_ring_base_lsb = 0x00000504, 842 .hal_reo_status_hp = 0x00003070, 843 844 }; 845 846 const struct ath11k_hw_regs qca6390_regs = { 847 /* SW2TCL(x) R0 ring configuration address */ 848 .hal_tcl1_ring_base_lsb = 0x00000684, 849 .hal_tcl1_ring_base_msb = 0x00000688, 850 .hal_tcl1_ring_id = 0x0000068c, 851 .hal_tcl1_ring_misc = 0x00000694, 852 .hal_tcl1_ring_tp_addr_lsb = 0x000006a0, 853 .hal_tcl1_ring_tp_addr_msb = 0x000006a4, 854 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006b4, 855 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006b8, 856 .hal_tcl1_ring_msi1_base_lsb = 0x000006cc, 857 .hal_tcl1_ring_msi1_base_msb = 0x000006d0, 858 .hal_tcl1_ring_msi1_data = 0x000006d4, 859 .hal_tcl2_ring_base_lsb = 0x000006dc, 860 .hal_tcl_ring_base_lsb = 0x0000078c, 861 862 /* TCL STATUS ring address */ 863 .hal_tcl_status_ring_base_lsb = 0x00000894, 864 865 /* REO2SW(x) R0 ring configuration address */ 866 .hal_reo1_ring_base_lsb = 0x00000244, 867 .hal_reo1_ring_base_msb = 0x00000248, 868 .hal_reo1_ring_id = 0x0000024c, 869 .hal_reo1_ring_misc = 0x00000254, 870 .hal_reo1_ring_hp_addr_lsb = 0x00000258, 871 .hal_reo1_ring_hp_addr_msb = 0x0000025c, 872 .hal_reo1_ring_producer_int_setup = 0x00000268, 873 .hal_reo1_ring_msi1_base_lsb = 0x0000028c, 874 .hal_reo1_ring_msi1_base_msb = 0x00000290, 875 .hal_reo1_ring_msi1_data = 0x00000294, 876 .hal_reo2_ring_base_lsb = 0x0000029c, 877 .hal_reo1_aging_thresh_ix_0 = 0x0000050c, 878 .hal_reo1_aging_thresh_ix_1 = 0x00000510, 879 .hal_reo1_aging_thresh_ix_2 = 0x00000514, 880 .hal_reo1_aging_thresh_ix_3 = 0x00000518, 881 882 /* REO2SW(x) R2 ring pointers (head/tail) address */ 883 .hal_reo1_ring_hp = 0x00003030, 884 .hal_reo1_ring_tp = 0x00003034, 885 .hal_reo2_ring_hp = 0x00003038, 886 887 /* REO2TCL R0 ring configuration address */ 888 .hal_reo_tcl_ring_base_lsb = 0x000003a4, 889 .hal_reo_tcl_ring_hp = 0x00003050, 890 891 /* REO status address */ 892 .hal_reo_status_ring_base_lsb = 0x000004ac, 893 .hal_reo_status_hp = 0x00003068, 894 }; 895