1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7 #include <linux/types.h> 8 #include <linux/bitops.h> 9 #include <linux/bitfield.h> 10 11 #include "core.h" 12 #include "ce.h" 13 #include "hif.h" 14 #include "hal.h" 15 #include "hw.h" 16 17 /* Map from pdev index to hw mac index */ 18 static u8 ath11k_hw_ipq8074_mac_from_pdev_id(int pdev_idx) 19 { 20 switch (pdev_idx) { 21 case 0: 22 return 0; 23 case 1: 24 return 2; 25 case 2: 26 return 1; 27 default: 28 return ATH11K_INVALID_HW_MAC_ID; 29 } 30 } 31 32 static u8 ath11k_hw_ipq6018_mac_from_pdev_id(int pdev_idx) 33 { 34 return pdev_idx; 35 } 36 37 static void ath11k_hw_ipq8074_tx_mesh_enable(struct ath11k_base *ab, 38 struct hal_tcl_data_cmd *tcl_cmd) 39 { 40 tcl_cmd->info2 |= FIELD_PREP(HAL_IPQ8074_TCL_DATA_CMD_INFO2_MESH_ENABLE, 41 true); 42 } 43 44 static void ath11k_hw_qcn9074_tx_mesh_enable(struct ath11k_base *ab, 45 struct hal_tcl_data_cmd *tcl_cmd) 46 { 47 tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE, 48 true); 49 } 50 51 static void ath11k_hw_wcn6855_tx_mesh_enable(struct ath11k_base *ab, 52 struct hal_tcl_data_cmd *tcl_cmd) 53 { 54 tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE, 55 true); 56 } 57 58 static void ath11k_init_wmi_config_qca6390(struct ath11k_base *ab, 59 struct target_resource_config *config) 60 { 61 config->num_vdevs = 4; 62 config->num_peers = 16; 63 config->num_tids = 32; 64 65 config->num_offload_peers = 3; 66 config->num_offload_reorder_buffs = 3; 67 config->num_peer_keys = TARGET_NUM_PEER_KEYS; 68 config->ast_skid_limit = TARGET_AST_SKID_LIMIT; 69 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 70 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 71 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; 72 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI; 73 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; 74 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; 75 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; 76 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS; 77 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV; 78 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV; 79 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES; 80 config->num_mcast_groups = 0; 81 config->num_mcast_table_elems = 0; 82 config->mcast2ucast_mode = 0; 83 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE; 84 config->num_wds_entries = 0; 85 config->dma_burst_size = 0; 86 config->rx_skip_defrag_timeout_dup_detection_check = 0; 87 config->vow_config = TARGET_VOW_CONFIG; 88 config->gtk_offload_max_vdev = 2; 89 config->num_msdu_desc = 0x400; 90 config->beacon_tx_offload_max_vdev = 2; 91 config->rx_batchmode = TARGET_RX_BATCHMODE; 92 93 config->peer_map_unmap_v2_support = 0; 94 config->use_pdev_id = 1; 95 config->max_frag_entries = 0xa; 96 config->num_tdls_vdevs = 0x1; 97 config->num_tdls_conn_table_entries = 8; 98 config->beacon_tx_offload_max_vdev = 0x2; 99 config->num_multicast_filter_entries = 0x20; 100 config->num_wow_filters = 0x16; 101 config->num_keep_alive_pattern = 0; 102 config->flag1 |= WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64; 103 } 104 105 static void ath11k_hw_ipq8074_reo_setup(struct ath11k_base *ab) 106 { 107 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; 108 u32 val; 109 /* Each hash entry uses three bits to map to a particular ring. */ 110 u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 | 111 HAL_HASH_ROUTING_RING_SW2 << 3 | 112 HAL_HASH_ROUTING_RING_SW3 << 6 | 113 HAL_HASH_ROUTING_RING_SW4 << 9 | 114 HAL_HASH_ROUTING_RING_SW1 << 12 | 115 HAL_HASH_ROUTING_RING_SW2 << 15 | 116 HAL_HASH_ROUTING_RING_SW3 << 18 | 117 HAL_HASH_ROUTING_RING_SW4 << 21; 118 119 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); 120 121 val &= ~HAL_REO1_GEN_ENABLE_FRAG_DST_RING; 122 val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_FRAG_DST_RING, 123 HAL_SRNG_RING_ID_REO2SW1) | 124 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) | 125 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1); 126 ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); 127 128 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab), 129 HAL_DEFAULT_REO_TIMEOUT_USEC); 130 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab), 131 HAL_DEFAULT_REO_TIMEOUT_USEC); 132 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab), 133 HAL_DEFAULT_REO_TIMEOUT_USEC); 134 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab), 135 HAL_DEFAULT_REO_TIMEOUT_USEC); 136 137 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0, 138 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 139 ring_hash_map)); 140 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1, 141 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 142 ring_hash_map)); 143 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, 144 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 145 ring_hash_map)); 146 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, 147 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 148 ring_hash_map)); 149 } 150 151 static void ath11k_init_wmi_config_ipq8074(struct ath11k_base *ab, 152 struct target_resource_config *config) 153 { 154 config->num_vdevs = ab->num_radios * TARGET_NUM_VDEVS(ab); 155 156 if (ab->num_radios == 2) { 157 config->num_peers = TARGET_NUM_PEERS(ab, DBS); 158 config->num_tids = TARGET_NUM_TIDS(ab, DBS); 159 } else if (ab->num_radios == 3) { 160 config->num_peers = TARGET_NUM_PEERS(ab, DBS_SBS); 161 config->num_tids = TARGET_NUM_TIDS(ab, DBS_SBS); 162 } else { 163 /* Control should not reach here */ 164 config->num_peers = TARGET_NUM_PEERS(ab, SINGLE); 165 config->num_tids = TARGET_NUM_TIDS(ab, SINGLE); 166 } 167 config->num_offload_peers = TARGET_NUM_OFFLD_PEERS; 168 config->num_offload_reorder_buffs = TARGET_NUM_OFFLD_REORDER_BUFFS; 169 config->num_peer_keys = TARGET_NUM_PEER_KEYS; 170 config->ast_skid_limit = TARGET_AST_SKID_LIMIT; 171 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 172 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 173 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; 174 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI; 175 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; 176 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; 177 178 if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) 179 config->rx_decap_mode = TARGET_DECAP_MODE_RAW; 180 else 181 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; 182 183 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS; 184 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV; 185 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV; 186 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES; 187 config->num_mcast_groups = TARGET_NUM_MCAST_GROUPS; 188 config->num_mcast_table_elems = TARGET_NUM_MCAST_TABLE_ELEMS; 189 config->mcast2ucast_mode = TARGET_MCAST2UCAST_MODE; 190 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE; 191 config->num_wds_entries = TARGET_NUM_WDS_ENTRIES; 192 config->dma_burst_size = TARGET_DMA_BURST_SIZE; 193 config->rx_skip_defrag_timeout_dup_detection_check = 194 TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK; 195 config->vow_config = TARGET_VOW_CONFIG; 196 config->gtk_offload_max_vdev = TARGET_GTK_OFFLOAD_MAX_VDEV; 197 config->num_msdu_desc = TARGET_NUM_MSDU_DESC; 198 config->beacon_tx_offload_max_vdev = ab->num_radios * TARGET_MAX_BCN_OFFLD; 199 config->rx_batchmode = TARGET_RX_BATCHMODE; 200 config->peer_map_unmap_v2_support = 1; 201 config->twt_ap_pdev_count = ab->num_radios; 202 config->twt_ap_sta_count = 1000; 203 config->flag1 |= WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64; 204 config->flag1 |= WMI_RSRC_CFG_FLAG1_ACK_RSSI; 205 } 206 207 static int ath11k_hw_mac_id_to_pdev_id_ipq8074(struct ath11k_hw_params *hw, 208 int mac_id) 209 { 210 return mac_id; 211 } 212 213 static int ath11k_hw_mac_id_to_srng_id_ipq8074(struct ath11k_hw_params *hw, 214 int mac_id) 215 { 216 return 0; 217 } 218 219 static int ath11k_hw_mac_id_to_pdev_id_qca6390(struct ath11k_hw_params *hw, 220 int mac_id) 221 { 222 return 0; 223 } 224 225 static int ath11k_hw_mac_id_to_srng_id_qca6390(struct ath11k_hw_params *hw, 226 int mac_id) 227 { 228 return mac_id; 229 } 230 231 static bool ath11k_hw_ipq8074_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 232 { 233 return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU, 234 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 235 } 236 237 static bool ath11k_hw_ipq8074_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 238 { 239 return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU, 240 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 241 } 242 243 static u8 ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 244 { 245 return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING, 246 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 247 } 248 249 static u8 *ath11k_hw_ipq8074_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 250 { 251 return desc->u.ipq8074.hdr_status; 252 } 253 254 static bool ath11k_hw_ipq8074_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 255 { 256 return __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1) & 257 RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID; 258 } 259 260 static u32 ath11k_hw_ipq8074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 261 { 262 return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE, 263 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2)); 264 } 265 266 static u8 ath11k_hw_ipq8074_rx_desc_get_decap_type(struct hal_rx_desc *desc) 267 { 268 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 269 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2)); 270 } 271 272 static u8 ath11k_hw_ipq8074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 273 { 274 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 275 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2)); 276 } 277 278 static bool ath11k_hw_ipq8074_rx_desc_get_ldpc_support(struct hal_rx_desc *desc) 279 { 280 return FIELD_GET(RX_MSDU_START_INFO2_LDPC, 281 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2)); 282 } 283 284 static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 285 { 286 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID, 287 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 288 } 289 290 static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 291 { 292 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID, 293 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 294 } 295 296 static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 297 { 298 return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM, 299 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 300 } 301 302 static u16 ath11k_hw_ipq8074_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 303 { 304 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 305 __le32_to_cpu(desc->u.ipq8074.msdu_start.info1)); 306 } 307 308 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 309 { 310 return FIELD_GET(RX_MSDU_START_INFO3_SGI, 311 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 312 } 313 314 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 315 { 316 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 317 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 318 } 319 320 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 321 { 322 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 323 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 324 } 325 326 static u32 ath11k_hw_ipq8074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 327 { 328 return __le32_to_cpu(desc->u.ipq8074.msdu_start.phy_meta_data); 329 } 330 331 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 332 { 333 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 334 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 335 } 336 337 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 338 { 339 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 340 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 341 } 342 343 static u8 ath11k_hw_ipq8074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 344 { 345 return FIELD_GET(RX_MPDU_START_INFO2_TID, 346 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2)); 347 } 348 349 static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 350 { 351 return __le16_to_cpu(desc->u.ipq8074.mpdu_start.sw_peer_id); 352 } 353 354 static void ath11k_hw_ipq8074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 355 struct hal_rx_desc *ldesc) 356 { 357 memcpy((u8 *)&fdesc->u.ipq8074.msdu_end, (u8 *)&ldesc->u.ipq8074.msdu_end, 358 sizeof(struct rx_msdu_end_ipq8074)); 359 memcpy((u8 *)&fdesc->u.ipq8074.attention, (u8 *)&ldesc->u.ipq8074.attention, 360 sizeof(struct rx_attention)); 361 memcpy((u8 *)&fdesc->u.ipq8074.mpdu_end, (u8 *)&ldesc->u.ipq8074.mpdu_end, 362 sizeof(struct rx_mpdu_end)); 363 } 364 365 static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 366 { 367 return FIELD_GET(HAL_TLV_HDR_TAG, 368 __le32_to_cpu(desc->u.ipq8074.mpdu_start_tag)); 369 } 370 371 static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 372 { 373 return __le16_to_cpu(desc->u.ipq8074.mpdu_start.phy_ppdu_id); 374 } 375 376 static void ath11k_hw_ipq8074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 377 { 378 u32 info = __le32_to_cpu(desc->u.ipq8074.msdu_start.info1); 379 380 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 381 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 382 383 desc->u.ipq8074.msdu_start.info1 = __cpu_to_le32(info); 384 } 385 386 static bool ath11k_hw_ipq8074_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc) 387 { 388 return __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1) & 389 RX_MPDU_START_INFO1_MAC_ADDR2_VALID; 390 } 391 392 static u8 *ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc) 393 { 394 return desc->u.ipq8074.mpdu_start.addr2; 395 } 396 397 static 398 struct rx_attention *ath11k_hw_ipq8074_rx_desc_get_attention(struct hal_rx_desc *desc) 399 { 400 return &desc->u.ipq8074.attention; 401 } 402 403 static u8 *ath11k_hw_ipq8074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 404 { 405 return &desc->u.ipq8074.msdu_payload[0]; 406 } 407 408 static bool ath11k_hw_qcn9074_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 409 { 410 return !!FIELD_GET(RX_MSDU_END_INFO4_FIRST_MSDU, 411 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 412 } 413 414 static bool ath11k_hw_qcn9074_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 415 { 416 return !!FIELD_GET(RX_MSDU_END_INFO4_LAST_MSDU, 417 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 418 } 419 420 static u8 ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 421 { 422 return FIELD_GET(RX_MSDU_END_INFO4_L3_HDR_PADDING, 423 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 424 } 425 426 static u8 *ath11k_hw_qcn9074_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 427 { 428 return desc->u.qcn9074.hdr_status; 429 } 430 431 static bool ath11k_hw_qcn9074_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 432 { 433 return __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11) & 434 RX_MPDU_START_INFO11_ENCRYPT_INFO_VALID; 435 } 436 437 static u32 ath11k_hw_qcn9074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 438 { 439 return FIELD_GET(RX_MPDU_START_INFO9_ENC_TYPE, 440 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9)); 441 } 442 443 static u8 ath11k_hw_qcn9074_rx_desc_get_decap_type(struct hal_rx_desc *desc) 444 { 445 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 446 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2)); 447 } 448 449 static u8 ath11k_hw_qcn9074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 450 { 451 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 452 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2)); 453 } 454 455 static bool ath11k_hw_qcn9074_rx_desc_get_ldpc_support(struct hal_rx_desc *desc) 456 { 457 return FIELD_GET(RX_MSDU_START_INFO2_LDPC, 458 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2)); 459 } 460 461 static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 462 { 463 return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_CTRL_VALID, 464 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 465 } 466 467 static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 468 { 469 return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_FCTRL_VALID, 470 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 471 } 472 473 static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 474 { 475 return FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_NUM, 476 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 477 } 478 479 static u16 ath11k_hw_qcn9074_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 480 { 481 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 482 __le32_to_cpu(desc->u.qcn9074.msdu_start.info1)); 483 } 484 485 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 486 { 487 return FIELD_GET(RX_MSDU_START_INFO3_SGI, 488 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 489 } 490 491 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 492 { 493 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 494 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 495 } 496 497 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 498 { 499 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 500 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 501 } 502 503 static u32 ath11k_hw_qcn9074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 504 { 505 return __le32_to_cpu(desc->u.qcn9074.msdu_start.phy_meta_data); 506 } 507 508 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 509 { 510 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 511 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 512 } 513 514 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 515 { 516 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 517 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 518 } 519 520 static u8 ath11k_hw_qcn9074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 521 { 522 return FIELD_GET(RX_MPDU_START_INFO9_TID, 523 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9)); 524 } 525 526 static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 527 { 528 return __le16_to_cpu(desc->u.qcn9074.mpdu_start.sw_peer_id); 529 } 530 531 static void ath11k_hw_qcn9074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 532 struct hal_rx_desc *ldesc) 533 { 534 memcpy((u8 *)&fdesc->u.qcn9074.msdu_end, (u8 *)&ldesc->u.qcn9074.msdu_end, 535 sizeof(struct rx_msdu_end_qcn9074)); 536 memcpy((u8 *)&fdesc->u.qcn9074.attention, (u8 *)&ldesc->u.qcn9074.attention, 537 sizeof(struct rx_attention)); 538 memcpy((u8 *)&fdesc->u.qcn9074.mpdu_end, (u8 *)&ldesc->u.qcn9074.mpdu_end, 539 sizeof(struct rx_mpdu_end)); 540 } 541 542 static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 543 { 544 return FIELD_GET(HAL_TLV_HDR_TAG, 545 __le32_to_cpu(desc->u.qcn9074.mpdu_start_tag)); 546 } 547 548 static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 549 { 550 return __le16_to_cpu(desc->u.qcn9074.mpdu_start.phy_ppdu_id); 551 } 552 553 static void ath11k_hw_qcn9074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 554 { 555 u32 info = __le32_to_cpu(desc->u.qcn9074.msdu_start.info1); 556 557 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 558 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 559 560 desc->u.qcn9074.msdu_start.info1 = __cpu_to_le32(info); 561 } 562 563 static 564 struct rx_attention *ath11k_hw_qcn9074_rx_desc_get_attention(struct hal_rx_desc *desc) 565 { 566 return &desc->u.qcn9074.attention; 567 } 568 569 static u8 *ath11k_hw_qcn9074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 570 { 571 return &desc->u.qcn9074.msdu_payload[0]; 572 } 573 574 static bool ath11k_hw_ipq9074_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc) 575 { 576 return __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11) & 577 RX_MPDU_START_INFO11_MAC_ADDR2_VALID; 578 } 579 580 static u8 *ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc) 581 { 582 return desc->u.qcn9074.mpdu_start.addr2; 583 } 584 585 static bool ath11k_hw_wcn6855_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 586 { 587 return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU_WCN6855, 588 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2)); 589 } 590 591 static bool ath11k_hw_wcn6855_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 592 { 593 return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU_WCN6855, 594 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2)); 595 } 596 597 static u8 ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 598 { 599 return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING, 600 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2)); 601 } 602 603 static u8 *ath11k_hw_wcn6855_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 604 { 605 return desc->u.wcn6855.hdr_status; 606 } 607 608 static bool ath11k_hw_wcn6855_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 609 { 610 return __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1) & 611 RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID; 612 } 613 614 static u32 ath11k_hw_wcn6855_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 615 { 616 return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE, 617 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info2)); 618 } 619 620 static u8 ath11k_hw_wcn6855_rx_desc_get_decap_type(struct hal_rx_desc *desc) 621 { 622 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 623 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2)); 624 } 625 626 static u8 ath11k_hw_wcn6855_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 627 { 628 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 629 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2)); 630 } 631 632 static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 633 { 634 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID, 635 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1)); 636 } 637 638 static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 639 { 640 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID, 641 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1)); 642 } 643 644 static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 645 { 646 return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM, 647 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1)); 648 } 649 650 static u16 ath11k_hw_wcn6855_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 651 { 652 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 653 __le32_to_cpu(desc->u.wcn6855.msdu_start.info1)); 654 } 655 656 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 657 { 658 return FIELD_GET(RX_MSDU_START_INFO3_SGI, 659 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 660 } 661 662 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 663 { 664 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 665 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 666 } 667 668 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 669 { 670 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 671 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 672 } 673 674 static u32 ath11k_hw_wcn6855_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 675 { 676 return __le32_to_cpu(desc->u.wcn6855.msdu_start.phy_meta_data); 677 } 678 679 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 680 { 681 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 682 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 683 } 684 685 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 686 { 687 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 688 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 689 } 690 691 static u8 ath11k_hw_wcn6855_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 692 { 693 return FIELD_GET(RX_MPDU_START_INFO2_TID_WCN6855, 694 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info2)); 695 } 696 697 static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 698 { 699 return __le16_to_cpu(desc->u.wcn6855.mpdu_start.sw_peer_id); 700 } 701 702 static void ath11k_hw_wcn6855_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 703 struct hal_rx_desc *ldesc) 704 { 705 memcpy((u8 *)&fdesc->u.wcn6855.msdu_end, (u8 *)&ldesc->u.wcn6855.msdu_end, 706 sizeof(struct rx_msdu_end_wcn6855)); 707 memcpy((u8 *)&fdesc->u.wcn6855.attention, (u8 *)&ldesc->u.wcn6855.attention, 708 sizeof(struct rx_attention)); 709 memcpy((u8 *)&fdesc->u.wcn6855.mpdu_end, (u8 *)&ldesc->u.wcn6855.mpdu_end, 710 sizeof(struct rx_mpdu_end)); 711 } 712 713 static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 714 { 715 return FIELD_GET(HAL_TLV_HDR_TAG, 716 __le32_to_cpu(desc->u.wcn6855.mpdu_start_tag)); 717 } 718 719 static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 720 { 721 return __le16_to_cpu(desc->u.wcn6855.mpdu_start.phy_ppdu_id); 722 } 723 724 static void ath11k_hw_wcn6855_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 725 { 726 u32 info = __le32_to_cpu(desc->u.wcn6855.msdu_start.info1); 727 728 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 729 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 730 731 desc->u.wcn6855.msdu_start.info1 = __cpu_to_le32(info); 732 } 733 734 static 735 struct rx_attention *ath11k_hw_wcn6855_rx_desc_get_attention(struct hal_rx_desc *desc) 736 { 737 return &desc->u.wcn6855.attention; 738 } 739 740 static u8 *ath11k_hw_wcn6855_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 741 { 742 return &desc->u.wcn6855.msdu_payload[0]; 743 } 744 745 static bool ath11k_hw_wcn6855_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc) 746 { 747 return __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1) & 748 RX_MPDU_START_INFO1_MAC_ADDR2_VALID; 749 } 750 751 static u8 *ath11k_hw_wcn6855_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc) 752 { 753 return desc->u.wcn6855.mpdu_start.addr2; 754 } 755 756 static void ath11k_hw_wcn6855_reo_setup(struct ath11k_base *ab) 757 { 758 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; 759 u32 val; 760 /* Each hash entry uses four bits to map to a particular ring. */ 761 u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 | 762 HAL_HASH_ROUTING_RING_SW2 << 4 | 763 HAL_HASH_ROUTING_RING_SW3 << 8 | 764 HAL_HASH_ROUTING_RING_SW4 << 12 | 765 HAL_HASH_ROUTING_RING_SW1 << 16 | 766 HAL_HASH_ROUTING_RING_SW2 << 20 | 767 HAL_HASH_ROUTING_RING_SW3 << 24 | 768 HAL_HASH_ROUTING_RING_SW4 << 28; 769 770 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); 771 val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) | 772 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1); 773 ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); 774 775 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_MISC_CTL(ab)); 776 val &= ~HAL_REO1_MISC_CTL_FRAGMENT_DST_RING; 777 val |= FIELD_PREP(HAL_REO1_MISC_CTL_FRAGMENT_DST_RING, HAL_SRNG_RING_ID_REO2SW1); 778 ath11k_hif_write32(ab, reo_base + HAL_REO1_MISC_CTL(ab), val); 779 780 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab), 781 HAL_DEFAULT_REO_TIMEOUT_USEC); 782 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab), 783 HAL_DEFAULT_REO_TIMEOUT_USEC); 784 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab), 785 HAL_DEFAULT_REO_TIMEOUT_USEC); 786 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab), 787 HAL_DEFAULT_REO_TIMEOUT_USEC); 788 789 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, 790 ring_hash_map); 791 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, 792 ring_hash_map); 793 } 794 795 static void ath11k_hw_ipq5018_reo_setup(struct ath11k_base *ab) 796 { 797 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; 798 u32 val; 799 800 /* Each hash entry uses three bits to map to a particular ring. */ 801 u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 | 802 HAL_HASH_ROUTING_RING_SW2 << 4 | 803 HAL_HASH_ROUTING_RING_SW3 << 8 | 804 HAL_HASH_ROUTING_RING_SW4 << 12 | 805 HAL_HASH_ROUTING_RING_SW1 << 16 | 806 HAL_HASH_ROUTING_RING_SW2 << 20 | 807 HAL_HASH_ROUTING_RING_SW3 << 24 | 808 HAL_HASH_ROUTING_RING_SW4 << 28; 809 810 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); 811 812 val &= ~HAL_REO1_GEN_ENABLE_FRAG_DST_RING; 813 val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_FRAG_DST_RING, 814 HAL_SRNG_RING_ID_REO2SW1) | 815 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) | 816 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1); 817 ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); 818 819 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab), 820 HAL_DEFAULT_REO_TIMEOUT_USEC); 821 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab), 822 HAL_DEFAULT_REO_TIMEOUT_USEC); 823 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab), 824 HAL_DEFAULT_REO_TIMEOUT_USEC); 825 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab), 826 HAL_DEFAULT_REO_TIMEOUT_USEC); 827 828 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0, 829 ring_hash_map); 830 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1, 831 ring_hash_map); 832 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, 833 ring_hash_map); 834 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, 835 ring_hash_map); 836 } 837 838 static u16 ath11k_hw_ipq8074_mpdu_info_get_peerid(u8 *tlv_data) 839 { 840 u16 peer_id = 0; 841 struct hal_rx_mpdu_info *mpdu_info = 842 (struct hal_rx_mpdu_info *)tlv_data; 843 844 peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID, 845 __le32_to_cpu(mpdu_info->info0)); 846 847 return peer_id; 848 } 849 850 static u16 ath11k_hw_wcn6855_mpdu_info_get_peerid(u8 *tlv_data) 851 { 852 u16 peer_id = 0; 853 struct hal_rx_mpdu_info_wcn6855 *mpdu_info = 854 (struct hal_rx_mpdu_info_wcn6855 *)tlv_data; 855 856 peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID_WCN6855, 857 __le32_to_cpu(mpdu_info->info0)); 858 return peer_id; 859 } 860 861 static bool ath11k_hw_wcn6855_rx_desc_get_ldpc_support(struct hal_rx_desc *desc) 862 { 863 return FIELD_GET(RX_MSDU_START_INFO2_LDPC, 864 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2)); 865 } 866 867 static u32 ath11k_hw_ipq8074_get_tcl_ring_selector(struct sk_buff *skb) 868 { 869 /* Let the default ring selection be based on current processor 870 * number, where one of the 3 tcl rings are selected based on 871 * the smp_processor_id(). In case that ring 872 * is full/busy, we resort to other available rings. 873 * If all rings are full, we drop the packet. 874 * 875 * TODO: Add throttling logic when all rings are full 876 */ 877 return smp_processor_id(); 878 } 879 880 static u32 ath11k_hw_wcn6750_get_tcl_ring_selector(struct sk_buff *skb) 881 { 882 /* Select the TCL ring based on the flow hash of the SKB instead 883 * of CPU ID. Since applications pumping the traffic can be scheduled 884 * on multiple CPUs, there is a chance that packets of the same flow 885 * could end on different TCL rings, this could sometimes results in 886 * an out of order arrival of the packets at the receiver. 887 */ 888 return skb_get_hash(skb); 889 } 890 891 const struct ath11k_hw_ops ipq8074_ops = { 892 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 893 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 894 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 895 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 896 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 897 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 898 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 899 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 900 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 901 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 902 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 903 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 904 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 905 .rx_desc_get_ldpc_support = ath11k_hw_ipq8074_rx_desc_get_ldpc_support, 906 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 907 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 908 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 909 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 910 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 911 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 912 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 913 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 914 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 915 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 916 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 917 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 918 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 919 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 920 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 921 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 922 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 923 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 924 .reo_setup = ath11k_hw_ipq8074_reo_setup, 925 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 926 .rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid, 927 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2, 928 .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector, 929 }; 930 931 const struct ath11k_hw_ops ipq6018_ops = { 932 .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 933 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 934 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 935 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 936 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 937 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 938 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 939 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 940 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 941 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 942 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 943 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 944 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 945 .rx_desc_get_ldpc_support = ath11k_hw_ipq8074_rx_desc_get_ldpc_support, 946 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 947 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 948 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 949 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 950 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 951 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 952 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 953 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 954 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 955 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 956 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 957 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 958 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 959 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 960 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 961 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 962 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 963 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 964 .reo_setup = ath11k_hw_ipq8074_reo_setup, 965 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 966 .rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid, 967 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2, 968 .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector, 969 }; 970 971 const struct ath11k_hw_ops qca6390_ops = { 972 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 973 .wmi_init_config = ath11k_init_wmi_config_qca6390, 974 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390, 975 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390, 976 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 977 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 978 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 979 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 980 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 981 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 982 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 983 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 984 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 985 .rx_desc_get_ldpc_support = ath11k_hw_ipq8074_rx_desc_get_ldpc_support, 986 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 987 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 988 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 989 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 990 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 991 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 992 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 993 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 994 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 995 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 996 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 997 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 998 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 999 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 1000 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 1001 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 1002 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 1003 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 1004 .reo_setup = ath11k_hw_ipq8074_reo_setup, 1005 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 1006 .rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid, 1007 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2, 1008 .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector, 1009 }; 1010 1011 const struct ath11k_hw_ops qcn9074_ops = { 1012 .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 1013 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 1014 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 1015 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 1016 .tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable, 1017 .rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu, 1018 .rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu, 1019 .rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes, 1020 .rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status, 1021 .rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid, 1022 .rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type, 1023 .rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type, 1024 .rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl, 1025 .rx_desc_get_ldpc_support = ath11k_hw_qcn9074_rx_desc_get_ldpc_support, 1026 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld, 1027 .rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid, 1028 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no, 1029 .rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len, 1030 .rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi, 1031 .rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs, 1032 .rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw, 1033 .rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq, 1034 .rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type, 1035 .rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss, 1036 .rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid, 1037 .rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id, 1038 .rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end, 1039 .rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag, 1040 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id, 1041 .rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len, 1042 .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention, 1043 .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload, 1044 .reo_setup = ath11k_hw_ipq8074_reo_setup, 1045 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 1046 .rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid, 1047 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2, 1048 .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector, 1049 }; 1050 1051 const struct ath11k_hw_ops wcn6855_ops = { 1052 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 1053 .wmi_init_config = ath11k_init_wmi_config_qca6390, 1054 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390, 1055 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390, 1056 .tx_mesh_enable = ath11k_hw_wcn6855_tx_mesh_enable, 1057 .rx_desc_get_first_msdu = ath11k_hw_wcn6855_rx_desc_get_first_msdu, 1058 .rx_desc_get_last_msdu = ath11k_hw_wcn6855_rx_desc_get_last_msdu, 1059 .rx_desc_get_l3_pad_bytes = ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes, 1060 .rx_desc_get_hdr_status = ath11k_hw_wcn6855_rx_desc_get_hdr_status, 1061 .rx_desc_encrypt_valid = ath11k_hw_wcn6855_rx_desc_encrypt_valid, 1062 .rx_desc_get_encrypt_type = ath11k_hw_wcn6855_rx_desc_get_encrypt_type, 1063 .rx_desc_get_decap_type = ath11k_hw_wcn6855_rx_desc_get_decap_type, 1064 .rx_desc_get_mesh_ctl = ath11k_hw_wcn6855_rx_desc_get_mesh_ctl, 1065 .rx_desc_get_ldpc_support = ath11k_hw_wcn6855_rx_desc_get_ldpc_support, 1066 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld, 1067 .rx_desc_get_mpdu_fc_valid = ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid, 1068 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no, 1069 .rx_desc_get_msdu_len = ath11k_hw_wcn6855_rx_desc_get_msdu_len, 1070 .rx_desc_get_msdu_sgi = ath11k_hw_wcn6855_rx_desc_get_msdu_sgi, 1071 .rx_desc_get_msdu_rate_mcs = ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs, 1072 .rx_desc_get_msdu_rx_bw = ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw, 1073 .rx_desc_get_msdu_freq = ath11k_hw_wcn6855_rx_desc_get_msdu_freq, 1074 .rx_desc_get_msdu_pkt_type = ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type, 1075 .rx_desc_get_msdu_nss = ath11k_hw_wcn6855_rx_desc_get_msdu_nss, 1076 .rx_desc_get_mpdu_tid = ath11k_hw_wcn6855_rx_desc_get_mpdu_tid, 1077 .rx_desc_get_mpdu_peer_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id, 1078 .rx_desc_copy_attn_end_tlv = ath11k_hw_wcn6855_rx_desc_copy_attn_end, 1079 .rx_desc_get_mpdu_start_tag = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag, 1080 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id, 1081 .rx_desc_set_msdu_len = ath11k_hw_wcn6855_rx_desc_set_msdu_len, 1082 .rx_desc_get_attention = ath11k_hw_wcn6855_rx_desc_get_attention, 1083 .rx_desc_get_msdu_payload = ath11k_hw_wcn6855_rx_desc_get_msdu_payload, 1084 .reo_setup = ath11k_hw_wcn6855_reo_setup, 1085 .mpdu_info_get_peerid = ath11k_hw_wcn6855_mpdu_info_get_peerid, 1086 .rx_desc_mac_addr2_valid = ath11k_hw_wcn6855_rx_desc_mac_addr2_valid, 1087 .rx_desc_mpdu_start_addr2 = ath11k_hw_wcn6855_rx_desc_mpdu_start_addr2, 1088 .get_ring_selector = ath11k_hw_ipq8074_get_tcl_ring_selector, 1089 }; 1090 1091 const struct ath11k_hw_ops wcn6750_ops = { 1092 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 1093 .wmi_init_config = ath11k_init_wmi_config_qca6390, 1094 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390, 1095 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390, 1096 .tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable, 1097 .rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu, 1098 .rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu, 1099 .rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes, 1100 .rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status, 1101 .rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid, 1102 .rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type, 1103 .rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type, 1104 .rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl, 1105 .rx_desc_get_ldpc_support = ath11k_hw_qcn9074_rx_desc_get_ldpc_support, 1106 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld, 1107 .rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid, 1108 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no, 1109 .rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len, 1110 .rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi, 1111 .rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs, 1112 .rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw, 1113 .rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq, 1114 .rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type, 1115 .rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss, 1116 .rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid, 1117 .rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id, 1118 .rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end, 1119 .rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag, 1120 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id, 1121 .rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len, 1122 .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention, 1123 .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload, 1124 .reo_setup = ath11k_hw_wcn6855_reo_setup, 1125 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 1126 .rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid, 1127 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2, 1128 .get_ring_selector = ath11k_hw_wcn6750_get_tcl_ring_selector, 1129 }; 1130 1131 /* IPQ5018 hw ops is similar to QCN9074 except for the dest ring remap */ 1132 const struct ath11k_hw_ops ipq5018_ops = { 1133 .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 1134 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 1135 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 1136 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 1137 .tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable, 1138 .rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu, 1139 .rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu, 1140 .rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes, 1141 .rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status, 1142 .rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid, 1143 .rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type, 1144 .rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type, 1145 .rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl, 1146 .rx_desc_get_ldpc_support = ath11k_hw_qcn9074_rx_desc_get_ldpc_support, 1147 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld, 1148 .rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid, 1149 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no, 1150 .rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len, 1151 .rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi, 1152 .rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs, 1153 .rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw, 1154 .rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq, 1155 .rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type, 1156 .rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss, 1157 .rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid, 1158 .rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id, 1159 .rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end, 1160 .rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag, 1161 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id, 1162 .rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len, 1163 .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention, 1164 .reo_setup = ath11k_hw_ipq5018_reo_setup, 1165 .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload, 1166 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 1167 .rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid, 1168 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2, 1169 1170 }; 1171 1172 #define ATH11K_TX_RING_MASK_0 BIT(0) 1173 #define ATH11K_TX_RING_MASK_1 BIT(1) 1174 #define ATH11K_TX_RING_MASK_2 BIT(2) 1175 #define ATH11K_TX_RING_MASK_3 BIT(3) 1176 #define ATH11K_TX_RING_MASK_4 BIT(4) 1177 1178 #define ATH11K_RX_RING_MASK_0 0x1 1179 #define ATH11K_RX_RING_MASK_1 0x2 1180 #define ATH11K_RX_RING_MASK_2 0x4 1181 #define ATH11K_RX_RING_MASK_3 0x8 1182 1183 #define ATH11K_RX_ERR_RING_MASK_0 0x1 1184 1185 #define ATH11K_RX_WBM_REL_RING_MASK_0 0x1 1186 1187 #define ATH11K_REO_STATUS_RING_MASK_0 0x1 1188 1189 #define ATH11K_RXDMA2HOST_RING_MASK_0 0x1 1190 #define ATH11K_RXDMA2HOST_RING_MASK_1 0x2 1191 #define ATH11K_RXDMA2HOST_RING_MASK_2 0x4 1192 1193 #define ATH11K_HOST2RXDMA_RING_MASK_0 0x1 1194 #define ATH11K_HOST2RXDMA_RING_MASK_1 0x2 1195 #define ATH11K_HOST2RXDMA_RING_MASK_2 0x4 1196 1197 #define ATH11K_RX_MON_STATUS_RING_MASK_0 0x1 1198 #define ATH11K_RX_MON_STATUS_RING_MASK_1 0x2 1199 #define ATH11K_RX_MON_STATUS_RING_MASK_2 0x4 1200 1201 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074 = { 1202 .tx = { 1203 ATH11K_TX_RING_MASK_0, 1204 ATH11K_TX_RING_MASK_1, 1205 ATH11K_TX_RING_MASK_2, 1206 }, 1207 .rx_mon_status = { 1208 0, 0, 0, 0, 1209 ATH11K_RX_MON_STATUS_RING_MASK_0, 1210 ATH11K_RX_MON_STATUS_RING_MASK_1, 1211 ATH11K_RX_MON_STATUS_RING_MASK_2, 1212 }, 1213 .rx = { 1214 0, 0, 0, 0, 0, 0, 0, 1215 ATH11K_RX_RING_MASK_0, 1216 ATH11K_RX_RING_MASK_1, 1217 ATH11K_RX_RING_MASK_2, 1218 ATH11K_RX_RING_MASK_3, 1219 }, 1220 .rx_err = { 1221 ATH11K_RX_ERR_RING_MASK_0, 1222 }, 1223 .rx_wbm_rel = { 1224 ATH11K_RX_WBM_REL_RING_MASK_0, 1225 }, 1226 .reo_status = { 1227 ATH11K_REO_STATUS_RING_MASK_0, 1228 }, 1229 .rxdma2host = { 1230 ATH11K_RXDMA2HOST_RING_MASK_0, 1231 ATH11K_RXDMA2HOST_RING_MASK_1, 1232 ATH11K_RXDMA2HOST_RING_MASK_2, 1233 }, 1234 .host2rxdma = { 1235 ATH11K_HOST2RXDMA_RING_MASK_0, 1236 ATH11K_HOST2RXDMA_RING_MASK_1, 1237 ATH11K_HOST2RXDMA_RING_MASK_2, 1238 }, 1239 }; 1240 1241 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390 = { 1242 .tx = { 1243 ATH11K_TX_RING_MASK_0, 1244 }, 1245 .rx_mon_status = { 1246 0, 0, 0, 0, 1247 ATH11K_RX_MON_STATUS_RING_MASK_0, 1248 ATH11K_RX_MON_STATUS_RING_MASK_1, 1249 ATH11K_RX_MON_STATUS_RING_MASK_2, 1250 }, 1251 .rx = { 1252 0, 0, 0, 0, 0, 0, 0, 1253 ATH11K_RX_RING_MASK_0, 1254 ATH11K_RX_RING_MASK_1, 1255 ATH11K_RX_RING_MASK_2, 1256 ATH11K_RX_RING_MASK_3, 1257 }, 1258 .rx_err = { 1259 ATH11K_RX_ERR_RING_MASK_0, 1260 }, 1261 .rx_wbm_rel = { 1262 ATH11K_RX_WBM_REL_RING_MASK_0, 1263 }, 1264 .reo_status = { 1265 ATH11K_REO_STATUS_RING_MASK_0, 1266 }, 1267 .rxdma2host = { 1268 ATH11K_RXDMA2HOST_RING_MASK_0, 1269 ATH11K_RXDMA2HOST_RING_MASK_1, 1270 ATH11K_RXDMA2HOST_RING_MASK_2, 1271 }, 1272 .host2rxdma = { 1273 }, 1274 }; 1275 1276 /* Target firmware's Copy Engine configuration. */ 1277 const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq8074[] = { 1278 /* CE0: host->target HTC control and raw streams */ 1279 { 1280 .pipenum = __cpu_to_le32(0), 1281 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1282 .nentries = __cpu_to_le32(32), 1283 .nbytes_max = __cpu_to_le32(2048), 1284 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1285 .reserved = __cpu_to_le32(0), 1286 }, 1287 1288 /* CE1: target->host HTT + HTC control */ 1289 { 1290 .pipenum = __cpu_to_le32(1), 1291 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1292 .nentries = __cpu_to_le32(32), 1293 .nbytes_max = __cpu_to_le32(2048), 1294 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1295 .reserved = __cpu_to_le32(0), 1296 }, 1297 1298 /* CE2: target->host WMI */ 1299 { 1300 .pipenum = __cpu_to_le32(2), 1301 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1302 .nentries = __cpu_to_le32(32), 1303 .nbytes_max = __cpu_to_le32(2048), 1304 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1305 .reserved = __cpu_to_le32(0), 1306 }, 1307 1308 /* CE3: host->target WMI */ 1309 { 1310 .pipenum = __cpu_to_le32(3), 1311 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1312 .nentries = __cpu_to_le32(32), 1313 .nbytes_max = __cpu_to_le32(2048), 1314 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1315 .reserved = __cpu_to_le32(0), 1316 }, 1317 1318 /* CE4: host->target HTT */ 1319 { 1320 .pipenum = __cpu_to_le32(4), 1321 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1322 .nentries = __cpu_to_le32(256), 1323 .nbytes_max = __cpu_to_le32(256), 1324 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1325 .reserved = __cpu_to_le32(0), 1326 }, 1327 1328 /* CE5: target->host Pktlog */ 1329 { 1330 .pipenum = __cpu_to_le32(5), 1331 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1332 .nentries = __cpu_to_le32(32), 1333 .nbytes_max = __cpu_to_le32(2048), 1334 .flags = __cpu_to_le32(0), 1335 .reserved = __cpu_to_le32(0), 1336 }, 1337 1338 /* CE6: Reserved for target autonomous hif_memcpy */ 1339 { 1340 .pipenum = __cpu_to_le32(6), 1341 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1342 .nentries = __cpu_to_le32(32), 1343 .nbytes_max = __cpu_to_le32(65535), 1344 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1345 .reserved = __cpu_to_le32(0), 1346 }, 1347 1348 /* CE7 used only by Host */ 1349 { 1350 .pipenum = __cpu_to_le32(7), 1351 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1352 .nentries = __cpu_to_le32(32), 1353 .nbytes_max = __cpu_to_le32(2048), 1354 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1355 .reserved = __cpu_to_le32(0), 1356 }, 1357 1358 /* CE8 target->host used only by IPA */ 1359 { 1360 .pipenum = __cpu_to_le32(8), 1361 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1362 .nentries = __cpu_to_le32(32), 1363 .nbytes_max = __cpu_to_le32(65535), 1364 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1365 .reserved = __cpu_to_le32(0), 1366 }, 1367 1368 /* CE9 host->target HTT */ 1369 { 1370 .pipenum = __cpu_to_le32(9), 1371 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1372 .nentries = __cpu_to_le32(32), 1373 .nbytes_max = __cpu_to_le32(2048), 1374 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1375 .reserved = __cpu_to_le32(0), 1376 }, 1377 1378 /* CE10 target->host HTT */ 1379 { 1380 .pipenum = __cpu_to_le32(10), 1381 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 1382 .nentries = __cpu_to_le32(0), 1383 .nbytes_max = __cpu_to_le32(0), 1384 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1385 .reserved = __cpu_to_le32(0), 1386 }, 1387 1388 /* CE11 Not used */ 1389 }; 1390 1391 /* Map from service/endpoint to Copy Engine. 1392 * This table is derived from the CE_PCI TABLE, above. 1393 * It is passed to the Target at startup for use by firmware. 1394 */ 1395 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq8074[] = { 1396 { 1397 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1398 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1399 .pipenum = __cpu_to_le32(3), 1400 }, 1401 { 1402 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1403 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1404 .pipenum = __cpu_to_le32(2), 1405 }, 1406 { 1407 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1408 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1409 .pipenum = __cpu_to_le32(3), 1410 }, 1411 { 1412 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1413 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1414 .pipenum = __cpu_to_le32(2), 1415 }, 1416 { 1417 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1418 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1419 .pipenum = __cpu_to_le32(3), 1420 }, 1421 { 1422 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1423 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1424 .pipenum = __cpu_to_le32(2), 1425 }, 1426 { 1427 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1428 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1429 .pipenum = __cpu_to_le32(3), 1430 }, 1431 { 1432 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1433 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1434 .pipenum = __cpu_to_le32(2), 1435 }, 1436 { 1437 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1438 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1439 .pipenum = __cpu_to_le32(3), 1440 }, 1441 { 1442 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1443 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1444 .pipenum = __cpu_to_le32(2), 1445 }, 1446 { 1447 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1448 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1449 .pipenum = __cpu_to_le32(7), 1450 }, 1451 { 1452 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1453 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1454 .pipenum = __cpu_to_le32(2), 1455 }, 1456 { 1457 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2), 1458 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1459 .pipenum = __cpu_to_le32(9), 1460 }, 1461 { 1462 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2), 1463 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1464 .pipenum = __cpu_to_le32(2), 1465 }, 1466 { 1467 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1468 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1469 .pipenum = __cpu_to_le32(0), 1470 }, 1471 { 1472 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1473 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1474 .pipenum = __cpu_to_le32(1), 1475 }, 1476 { /* not used */ 1477 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1478 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1479 .pipenum = __cpu_to_le32(0), 1480 }, 1481 { /* not used */ 1482 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1483 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1484 .pipenum = __cpu_to_le32(1), 1485 }, 1486 { 1487 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1488 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1489 .pipenum = __cpu_to_le32(4), 1490 }, 1491 { 1492 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1493 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1494 .pipenum = __cpu_to_le32(1), 1495 }, 1496 { 1497 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 1498 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1499 .pipenum = __cpu_to_le32(5), 1500 }, 1501 1502 /* (Additions here) */ 1503 1504 { /* terminator entry */ } 1505 }; 1506 1507 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq6018[] = { 1508 { 1509 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1510 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1511 .pipenum = __cpu_to_le32(3), 1512 }, 1513 { 1514 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1515 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1516 .pipenum = __cpu_to_le32(2), 1517 }, 1518 { 1519 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1520 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1521 .pipenum = __cpu_to_le32(3), 1522 }, 1523 { 1524 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1525 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1526 .pipenum = __cpu_to_le32(2), 1527 }, 1528 { 1529 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1530 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1531 .pipenum = __cpu_to_le32(3), 1532 }, 1533 { 1534 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1535 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1536 .pipenum = __cpu_to_le32(2), 1537 }, 1538 { 1539 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1540 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1541 .pipenum = __cpu_to_le32(3), 1542 }, 1543 { 1544 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1545 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1546 .pipenum = __cpu_to_le32(2), 1547 }, 1548 { 1549 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1550 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1551 .pipenum = __cpu_to_le32(3), 1552 }, 1553 { 1554 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1555 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1556 .pipenum = __cpu_to_le32(2), 1557 }, 1558 { 1559 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1560 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1561 .pipenum = __cpu_to_le32(7), 1562 }, 1563 { 1564 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1565 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1566 .pipenum = __cpu_to_le32(2), 1567 }, 1568 { 1569 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1570 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1571 .pipenum = __cpu_to_le32(0), 1572 }, 1573 { 1574 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1575 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1576 .pipenum = __cpu_to_le32(1), 1577 }, 1578 { /* not used */ 1579 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1580 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1581 .pipenum = __cpu_to_le32(0), 1582 }, 1583 { /* not used */ 1584 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1585 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1586 .pipenum = __cpu_to_le32(1), 1587 }, 1588 { 1589 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1590 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1591 .pipenum = __cpu_to_le32(4), 1592 }, 1593 { 1594 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1595 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1596 .pipenum = __cpu_to_le32(1), 1597 }, 1598 { 1599 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 1600 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1601 .pipenum = __cpu_to_le32(5), 1602 }, 1603 1604 /* (Additions here) */ 1605 1606 { /* terminator entry */ } 1607 }; 1608 1609 /* Target firmware's Copy Engine configuration. */ 1610 const struct ce_pipe_config ath11k_target_ce_config_wlan_qca6390[] = { 1611 /* CE0: host->target HTC control and raw streams */ 1612 { 1613 .pipenum = __cpu_to_le32(0), 1614 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1615 .nentries = __cpu_to_le32(32), 1616 .nbytes_max = __cpu_to_le32(2048), 1617 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1618 .reserved = __cpu_to_le32(0), 1619 }, 1620 1621 /* CE1: target->host HTT + HTC control */ 1622 { 1623 .pipenum = __cpu_to_le32(1), 1624 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1625 .nentries = __cpu_to_le32(32), 1626 .nbytes_max = __cpu_to_le32(2048), 1627 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1628 .reserved = __cpu_to_le32(0), 1629 }, 1630 1631 /* CE2: target->host WMI */ 1632 { 1633 .pipenum = __cpu_to_le32(2), 1634 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1635 .nentries = __cpu_to_le32(32), 1636 .nbytes_max = __cpu_to_le32(2048), 1637 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1638 .reserved = __cpu_to_le32(0), 1639 }, 1640 1641 /* CE3: host->target WMI */ 1642 { 1643 .pipenum = __cpu_to_le32(3), 1644 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1645 .nentries = __cpu_to_le32(32), 1646 .nbytes_max = __cpu_to_le32(2048), 1647 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1648 .reserved = __cpu_to_le32(0), 1649 }, 1650 1651 /* CE4: host->target HTT */ 1652 { 1653 .pipenum = __cpu_to_le32(4), 1654 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1655 .nentries = __cpu_to_le32(256), 1656 .nbytes_max = __cpu_to_le32(256), 1657 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1658 .reserved = __cpu_to_le32(0), 1659 }, 1660 1661 /* CE5: target->host Pktlog */ 1662 { 1663 .pipenum = __cpu_to_le32(5), 1664 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1665 .nentries = __cpu_to_le32(32), 1666 .nbytes_max = __cpu_to_le32(2048), 1667 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1668 .reserved = __cpu_to_le32(0), 1669 }, 1670 1671 /* CE6: Reserved for target autonomous hif_memcpy */ 1672 { 1673 .pipenum = __cpu_to_le32(6), 1674 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1675 .nentries = __cpu_to_le32(32), 1676 .nbytes_max = __cpu_to_le32(16384), 1677 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1678 .reserved = __cpu_to_le32(0), 1679 }, 1680 1681 /* CE7 used only by Host */ 1682 { 1683 .pipenum = __cpu_to_le32(7), 1684 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 1685 .nentries = __cpu_to_le32(0), 1686 .nbytes_max = __cpu_to_le32(0), 1687 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1688 .reserved = __cpu_to_le32(0), 1689 }, 1690 1691 /* CE8 target->host used only by IPA */ 1692 { 1693 .pipenum = __cpu_to_le32(8), 1694 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1695 .nentries = __cpu_to_le32(32), 1696 .nbytes_max = __cpu_to_le32(16384), 1697 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1698 .reserved = __cpu_to_le32(0), 1699 }, 1700 /* CE 9, 10, 11 are used by MHI driver */ 1701 }; 1702 1703 /* Map from service/endpoint to Copy Engine. 1704 * This table is derived from the CE_PCI TABLE, above. 1705 * It is passed to the Target at startup for use by firmware. 1706 */ 1707 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qca6390[] = { 1708 { 1709 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1710 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1711 __cpu_to_le32(3), 1712 }, 1713 { 1714 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1715 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1716 __cpu_to_le32(2), 1717 }, 1718 { 1719 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1720 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1721 __cpu_to_le32(3), 1722 }, 1723 { 1724 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1725 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1726 __cpu_to_le32(2), 1727 }, 1728 { 1729 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1730 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1731 __cpu_to_le32(3), 1732 }, 1733 { 1734 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1735 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1736 __cpu_to_le32(2), 1737 }, 1738 { 1739 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1740 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1741 __cpu_to_le32(3), 1742 }, 1743 { 1744 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1745 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1746 __cpu_to_le32(2), 1747 }, 1748 { 1749 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1750 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1751 __cpu_to_le32(3), 1752 }, 1753 { 1754 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1755 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1756 __cpu_to_le32(2), 1757 }, 1758 { 1759 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1760 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1761 __cpu_to_le32(0), 1762 }, 1763 { 1764 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1765 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1766 __cpu_to_le32(2), 1767 }, 1768 { 1769 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1770 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1771 __cpu_to_le32(4), 1772 }, 1773 { 1774 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1775 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1776 __cpu_to_le32(1), 1777 }, 1778 1779 /* (Additions here) */ 1780 1781 { /* must be last */ 1782 __cpu_to_le32(0), 1783 __cpu_to_le32(0), 1784 __cpu_to_le32(0), 1785 }, 1786 }; 1787 1788 /* Target firmware's Copy Engine configuration. */ 1789 const struct ce_pipe_config ath11k_target_ce_config_wlan_qcn9074[] = { 1790 /* CE0: host->target HTC control and raw streams */ 1791 { 1792 .pipenum = __cpu_to_le32(0), 1793 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1794 .nentries = __cpu_to_le32(32), 1795 .nbytes_max = __cpu_to_le32(2048), 1796 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1797 .reserved = __cpu_to_le32(0), 1798 }, 1799 1800 /* CE1: target->host HTT + HTC control */ 1801 { 1802 .pipenum = __cpu_to_le32(1), 1803 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1804 .nentries = __cpu_to_le32(32), 1805 .nbytes_max = __cpu_to_le32(2048), 1806 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1807 .reserved = __cpu_to_le32(0), 1808 }, 1809 1810 /* CE2: target->host WMI */ 1811 { 1812 .pipenum = __cpu_to_le32(2), 1813 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1814 .nentries = __cpu_to_le32(32), 1815 .nbytes_max = __cpu_to_le32(2048), 1816 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1817 .reserved = __cpu_to_le32(0), 1818 }, 1819 1820 /* CE3: host->target WMI */ 1821 { 1822 .pipenum = __cpu_to_le32(3), 1823 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1824 .nentries = __cpu_to_le32(32), 1825 .nbytes_max = __cpu_to_le32(2048), 1826 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1827 .reserved = __cpu_to_le32(0), 1828 }, 1829 1830 /* CE4: host->target HTT */ 1831 { 1832 .pipenum = __cpu_to_le32(4), 1833 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1834 .nentries = __cpu_to_le32(256), 1835 .nbytes_max = __cpu_to_le32(256), 1836 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1837 .reserved = __cpu_to_le32(0), 1838 }, 1839 1840 /* CE5: target->host Pktlog */ 1841 { 1842 .pipenum = __cpu_to_le32(5), 1843 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1844 .nentries = __cpu_to_le32(32), 1845 .nbytes_max = __cpu_to_le32(2048), 1846 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1847 .reserved = __cpu_to_le32(0), 1848 }, 1849 1850 /* CE6: Reserved for target autonomous hif_memcpy */ 1851 { 1852 .pipenum = __cpu_to_le32(6), 1853 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1854 .nentries = __cpu_to_le32(32), 1855 .nbytes_max = __cpu_to_le32(16384), 1856 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1857 .reserved = __cpu_to_le32(0), 1858 }, 1859 1860 /* CE7 used only by Host */ 1861 { 1862 .pipenum = __cpu_to_le32(7), 1863 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 1864 .nentries = __cpu_to_le32(0), 1865 .nbytes_max = __cpu_to_le32(0), 1866 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1867 .reserved = __cpu_to_le32(0), 1868 }, 1869 1870 /* CE8 target->host used only by IPA */ 1871 { 1872 .pipenum = __cpu_to_le32(8), 1873 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1874 .nentries = __cpu_to_le32(32), 1875 .nbytes_max = __cpu_to_le32(16384), 1876 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1877 .reserved = __cpu_to_le32(0), 1878 }, 1879 /* CE 9, 10, 11 are used by MHI driver */ 1880 }; 1881 1882 /* Map from service/endpoint to Copy Engine. 1883 * This table is derived from the CE_PCI TABLE, above. 1884 * It is passed to the Target at startup for use by firmware. 1885 */ 1886 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qcn9074[] = { 1887 { 1888 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1889 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1890 __cpu_to_le32(3), 1891 }, 1892 { 1893 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1894 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1895 __cpu_to_le32(2), 1896 }, 1897 { 1898 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1899 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1900 __cpu_to_le32(3), 1901 }, 1902 { 1903 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1904 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1905 __cpu_to_le32(2), 1906 }, 1907 { 1908 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1909 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1910 __cpu_to_le32(3), 1911 }, 1912 { 1913 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1914 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1915 __cpu_to_le32(2), 1916 }, 1917 { 1918 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1919 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1920 __cpu_to_le32(3), 1921 }, 1922 { 1923 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1924 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1925 __cpu_to_le32(2), 1926 }, 1927 { 1928 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1929 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1930 __cpu_to_le32(3), 1931 }, 1932 { 1933 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1934 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1935 __cpu_to_le32(2), 1936 }, 1937 { 1938 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1939 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1940 __cpu_to_le32(0), 1941 }, 1942 { 1943 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1944 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1945 __cpu_to_le32(1), 1946 }, 1947 { 1948 __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1949 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1950 __cpu_to_le32(0), 1951 }, 1952 { 1953 __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1954 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1955 __cpu_to_le32(1), 1956 }, 1957 { 1958 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1959 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1960 __cpu_to_le32(4), 1961 }, 1962 { 1963 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1964 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1965 __cpu_to_le32(1), 1966 }, 1967 { 1968 __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 1969 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1970 __cpu_to_le32(5), 1971 }, 1972 1973 /* (Additions here) */ 1974 1975 { /* must be last */ 1976 __cpu_to_le32(0), 1977 __cpu_to_le32(0), 1978 __cpu_to_le32(0), 1979 }, 1980 }; 1981 1982 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qcn9074 = { 1983 .tx = { 1984 ATH11K_TX_RING_MASK_0, 1985 ATH11K_TX_RING_MASK_1, 1986 ATH11K_TX_RING_MASK_2, 1987 }, 1988 .rx_mon_status = { 1989 0, 0, 0, 1990 ATH11K_RX_MON_STATUS_RING_MASK_0, 1991 ATH11K_RX_MON_STATUS_RING_MASK_1, 1992 ATH11K_RX_MON_STATUS_RING_MASK_2, 1993 }, 1994 .rx = { 1995 0, 0, 0, 0, 1996 ATH11K_RX_RING_MASK_0, 1997 ATH11K_RX_RING_MASK_1, 1998 ATH11K_RX_RING_MASK_2, 1999 ATH11K_RX_RING_MASK_3, 2000 }, 2001 .rx_err = { 2002 0, 0, 0, 2003 ATH11K_RX_ERR_RING_MASK_0, 2004 }, 2005 .rx_wbm_rel = { 2006 0, 0, 0, 2007 ATH11K_RX_WBM_REL_RING_MASK_0, 2008 }, 2009 .reo_status = { 2010 0, 0, 0, 2011 ATH11K_REO_STATUS_RING_MASK_0, 2012 }, 2013 .rxdma2host = { 2014 0, 0, 0, 2015 ATH11K_RXDMA2HOST_RING_MASK_0, 2016 }, 2017 .host2rxdma = { 2018 0, 0, 0, 2019 ATH11K_HOST2RXDMA_RING_MASK_0, 2020 }, 2021 }; 2022 2023 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_wcn6750 = { 2024 .tx = { 2025 ATH11K_TX_RING_MASK_0, 2026 0, 2027 ATH11K_TX_RING_MASK_2, 2028 0, 2029 ATH11K_TX_RING_MASK_4, 2030 }, 2031 .rx_mon_status = { 2032 0, 0, 0, 0, 0, 0, 2033 ATH11K_RX_MON_STATUS_RING_MASK_0, 2034 }, 2035 .rx = { 2036 0, 0, 0, 0, 0, 0, 0, 2037 ATH11K_RX_RING_MASK_0, 2038 ATH11K_RX_RING_MASK_1, 2039 ATH11K_RX_RING_MASK_2, 2040 ATH11K_RX_RING_MASK_3, 2041 }, 2042 .rx_err = { 2043 0, ATH11K_RX_ERR_RING_MASK_0, 2044 }, 2045 .rx_wbm_rel = { 2046 0, ATH11K_RX_WBM_REL_RING_MASK_0, 2047 }, 2048 .reo_status = { 2049 0, ATH11K_REO_STATUS_RING_MASK_0, 2050 }, 2051 .rxdma2host = { 2052 ATH11K_RXDMA2HOST_RING_MASK_0, 2053 ATH11K_RXDMA2HOST_RING_MASK_1, 2054 ATH11K_RXDMA2HOST_RING_MASK_2, 2055 }, 2056 .host2rxdma = { 2057 }, 2058 }; 2059 2060 /* Target firmware's Copy Engine configuration for IPQ5018 */ 2061 const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq5018[] = { 2062 /* CE0: host->target HTC control and raw streams */ 2063 { 2064 .pipenum = __cpu_to_le32(0), 2065 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 2066 .nentries = __cpu_to_le32(32), 2067 .nbytes_max = __cpu_to_le32(2048), 2068 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 2069 .reserved = __cpu_to_le32(0), 2070 }, 2071 2072 /* CE1: target->host HTT + HTC control */ 2073 { 2074 .pipenum = __cpu_to_le32(1), 2075 .pipedir = __cpu_to_le32(PIPEDIR_IN), 2076 .nentries = __cpu_to_le32(32), 2077 .nbytes_max = __cpu_to_le32(2048), 2078 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 2079 .reserved = __cpu_to_le32(0), 2080 }, 2081 2082 /* CE2: target->host WMI */ 2083 { 2084 .pipenum = __cpu_to_le32(2), 2085 .pipedir = __cpu_to_le32(PIPEDIR_IN), 2086 .nentries = __cpu_to_le32(32), 2087 .nbytes_max = __cpu_to_le32(2048), 2088 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 2089 .reserved = __cpu_to_le32(0), 2090 }, 2091 2092 /* CE3: host->target WMI */ 2093 { 2094 .pipenum = __cpu_to_le32(3), 2095 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 2096 .nentries = __cpu_to_le32(32), 2097 .nbytes_max = __cpu_to_le32(2048), 2098 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 2099 .reserved = __cpu_to_le32(0), 2100 }, 2101 2102 /* CE4: host->target HTT */ 2103 { 2104 .pipenum = __cpu_to_le32(4), 2105 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 2106 .nentries = __cpu_to_le32(256), 2107 .nbytes_max = __cpu_to_le32(256), 2108 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 2109 .reserved = __cpu_to_le32(0), 2110 }, 2111 2112 /* CE5: target->host Pktlog */ 2113 { 2114 .pipenum = __cpu_to_le32(5), 2115 .pipedir = __cpu_to_le32(PIPEDIR_IN), 2116 .nentries = __cpu_to_le32(32), 2117 .nbytes_max = __cpu_to_le32(2048), 2118 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 2119 .reserved = __cpu_to_le32(0), 2120 }, 2121 2122 /* CE6: Reserved for target autonomous hif_memcpy */ 2123 { 2124 .pipenum = __cpu_to_le32(6), 2125 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 2126 .nentries = __cpu_to_le32(32), 2127 .nbytes_max = __cpu_to_le32(16384), 2128 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 2129 .reserved = __cpu_to_le32(0), 2130 }, 2131 2132 /* CE7 used only by Host */ 2133 { 2134 .pipenum = __cpu_to_le32(7), 2135 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 2136 .nentries = __cpu_to_le32(32), 2137 .nbytes_max = __cpu_to_le32(2048), 2138 .flags = __cpu_to_le32(0x2000), 2139 .reserved = __cpu_to_le32(0), 2140 }, 2141 2142 /* CE8 target->host used only by IPA */ 2143 { 2144 .pipenum = __cpu_to_le32(8), 2145 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 2146 .nentries = __cpu_to_le32(32), 2147 .nbytes_max = __cpu_to_le32(16384), 2148 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 2149 .reserved = __cpu_to_le32(0), 2150 }, 2151 }; 2152 2153 /* Map from service/endpoint to Copy Engine for IPQ5018. 2154 * This table is derived from the CE TABLE, above. 2155 * It is passed to the Target at startup for use by firmware. 2156 */ 2157 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq5018[] = { 2158 { 2159 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 2160 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 2161 .pipenum = __cpu_to_le32(3), 2162 }, 2163 { 2164 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 2165 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 2166 .pipenum = __cpu_to_le32(2), 2167 }, 2168 { 2169 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 2170 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 2171 .pipenum = __cpu_to_le32(3), 2172 }, 2173 { 2174 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 2175 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 2176 .pipenum = __cpu_to_le32(2), 2177 }, 2178 { 2179 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 2180 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 2181 .pipenum = __cpu_to_le32(3), 2182 }, 2183 { 2184 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 2185 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 2186 .pipenum = __cpu_to_le32(2), 2187 }, 2188 { 2189 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 2190 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 2191 .pipenum = __cpu_to_le32(3), 2192 }, 2193 { 2194 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 2195 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 2196 .pipenum = __cpu_to_le32(2), 2197 }, 2198 { 2199 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 2200 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 2201 .pipenum = __cpu_to_le32(3), 2202 }, 2203 { 2204 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 2205 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 2206 .pipenum = __cpu_to_le32(2), 2207 }, 2208 2209 { 2210 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 2211 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 2212 .pipenum = __cpu_to_le32(0), 2213 }, 2214 { 2215 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 2216 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 2217 .pipenum = __cpu_to_le32(1), 2218 }, 2219 2220 { 2221 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 2222 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 2223 .pipenum = __cpu_to_le32(0), 2224 }, 2225 { 2226 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 2227 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 2228 .pipenum = __cpu_to_le32(1), 2229 }, 2230 { 2231 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 2232 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 2233 .pipenum = __cpu_to_le32(4), 2234 }, 2235 { 2236 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 2237 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 2238 .pipenum = __cpu_to_le32(1), 2239 }, 2240 { 2241 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 2242 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 2243 .pipenum = __cpu_to_le32(5), 2244 }, 2245 2246 /* (Additions here) */ 2247 2248 { /* terminator entry */ } 2249 }; 2250 2251 const struct ce_ie_addr ath11k_ce_ie_addr_ipq8074 = { 2252 .ie1_reg_addr = CE_HOST_IE_ADDRESS, 2253 .ie2_reg_addr = CE_HOST_IE_2_ADDRESS, 2254 .ie3_reg_addr = CE_HOST_IE_3_ADDRESS, 2255 }; 2256 2257 const struct ce_ie_addr ath11k_ce_ie_addr_ipq5018 = { 2258 .ie1_reg_addr = CE_HOST_IPQ5018_IE_ADDRESS - HAL_IPQ5018_CE_WFSS_REG_BASE, 2259 .ie2_reg_addr = CE_HOST_IPQ5018_IE_2_ADDRESS - HAL_IPQ5018_CE_WFSS_REG_BASE, 2260 .ie3_reg_addr = CE_HOST_IPQ5018_IE_3_ADDRESS - HAL_IPQ5018_CE_WFSS_REG_BASE, 2261 }; 2262 2263 const struct ce_remap ath11k_ce_remap_ipq5018 = { 2264 .base = HAL_IPQ5018_CE_WFSS_REG_BASE, 2265 .size = HAL_IPQ5018_CE_SIZE, 2266 }; 2267 2268 const struct ath11k_hw_regs ipq8074_regs = { 2269 /* SW2TCL(x) R0 ring configuration address */ 2270 .hal_tcl1_ring_base_lsb = 0x00000510, 2271 .hal_tcl1_ring_base_msb = 0x00000514, 2272 .hal_tcl1_ring_id = 0x00000518, 2273 .hal_tcl1_ring_misc = 0x00000520, 2274 .hal_tcl1_ring_tp_addr_lsb = 0x0000052c, 2275 .hal_tcl1_ring_tp_addr_msb = 0x00000530, 2276 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000540, 2277 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000544, 2278 .hal_tcl1_ring_msi1_base_lsb = 0x00000558, 2279 .hal_tcl1_ring_msi1_base_msb = 0x0000055c, 2280 .hal_tcl1_ring_msi1_data = 0x00000560, 2281 .hal_tcl2_ring_base_lsb = 0x00000568, 2282 .hal_tcl_ring_base_lsb = 0x00000618, 2283 2284 /* TCL STATUS ring address */ 2285 .hal_tcl_status_ring_base_lsb = 0x00000720, 2286 2287 /* REO2SW(x) R0 ring configuration address */ 2288 .hal_reo1_ring_base_lsb = 0x0000029c, 2289 .hal_reo1_ring_base_msb = 0x000002a0, 2290 .hal_reo1_ring_id = 0x000002a4, 2291 .hal_reo1_ring_misc = 0x000002ac, 2292 .hal_reo1_ring_hp_addr_lsb = 0x000002b0, 2293 .hal_reo1_ring_hp_addr_msb = 0x000002b4, 2294 .hal_reo1_ring_producer_int_setup = 0x000002c0, 2295 .hal_reo1_ring_msi1_base_lsb = 0x000002e4, 2296 .hal_reo1_ring_msi1_base_msb = 0x000002e8, 2297 .hal_reo1_ring_msi1_data = 0x000002ec, 2298 .hal_reo2_ring_base_lsb = 0x000002f4, 2299 .hal_reo1_aging_thresh_ix_0 = 0x00000564, 2300 .hal_reo1_aging_thresh_ix_1 = 0x00000568, 2301 .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 2302 .hal_reo1_aging_thresh_ix_3 = 0x00000570, 2303 2304 /* REO2SW(x) R2 ring pointers (head/tail) address */ 2305 .hal_reo1_ring_hp = 0x00003038, 2306 .hal_reo1_ring_tp = 0x0000303c, 2307 .hal_reo2_ring_hp = 0x00003040, 2308 2309 /* REO2TCL R0 ring configuration address */ 2310 .hal_reo_tcl_ring_base_lsb = 0x000003fc, 2311 .hal_reo_tcl_ring_hp = 0x00003058, 2312 2313 /* REO CMD ring address */ 2314 .hal_reo_cmd_ring_base_lsb = 0x00000194, 2315 .hal_reo_cmd_ring_hp = 0x00003020, 2316 2317 /* REO status address */ 2318 .hal_reo_status_ring_base_lsb = 0x00000504, 2319 .hal_reo_status_hp = 0x00003070, 2320 2321 /* SW2REO ring address */ 2322 .hal_sw2reo_ring_base_lsb = 0x000001ec, 2323 .hal_sw2reo_ring_hp = 0x00003028, 2324 2325 /* WCSS relative address */ 2326 .hal_seq_wcss_umac_ce0_src_reg = 0x00a00000, 2327 .hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000, 2328 .hal_seq_wcss_umac_ce1_src_reg = 0x00a02000, 2329 .hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000, 2330 2331 /* WBM Idle address */ 2332 .hal_wbm_idle_link_ring_base_lsb = 0x00000860, 2333 .hal_wbm_idle_link_ring_misc = 0x00000870, 2334 2335 /* SW2WBM release address */ 2336 .hal_wbm_release_ring_base_lsb = 0x000001d8, 2337 2338 /* WBM2SW release address */ 2339 .hal_wbm0_release_ring_base_lsb = 0x00000910, 2340 .hal_wbm1_release_ring_base_lsb = 0x00000968, 2341 2342 /* PCIe base address */ 2343 .pcie_qserdes_sysclk_en_sel = 0x0, 2344 .pcie_pcs_osc_dtct_config_base = 0x0, 2345 2346 /* Shadow register area */ 2347 .hal_shadow_base_addr = 0x0, 2348 2349 /* REO misc control register, not used in IPQ8074 */ 2350 .hal_reo1_misc_ctl = 0x0, 2351 }; 2352 2353 const struct ath11k_hw_regs qca6390_regs = { 2354 /* SW2TCL(x) R0 ring configuration address */ 2355 .hal_tcl1_ring_base_lsb = 0x00000684, 2356 .hal_tcl1_ring_base_msb = 0x00000688, 2357 .hal_tcl1_ring_id = 0x0000068c, 2358 .hal_tcl1_ring_misc = 0x00000694, 2359 .hal_tcl1_ring_tp_addr_lsb = 0x000006a0, 2360 .hal_tcl1_ring_tp_addr_msb = 0x000006a4, 2361 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006b4, 2362 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006b8, 2363 .hal_tcl1_ring_msi1_base_lsb = 0x000006cc, 2364 .hal_tcl1_ring_msi1_base_msb = 0x000006d0, 2365 .hal_tcl1_ring_msi1_data = 0x000006d4, 2366 .hal_tcl2_ring_base_lsb = 0x000006dc, 2367 .hal_tcl_ring_base_lsb = 0x0000078c, 2368 2369 /* TCL STATUS ring address */ 2370 .hal_tcl_status_ring_base_lsb = 0x00000894, 2371 2372 /* REO2SW(x) R0 ring configuration address */ 2373 .hal_reo1_ring_base_lsb = 0x00000244, 2374 .hal_reo1_ring_base_msb = 0x00000248, 2375 .hal_reo1_ring_id = 0x0000024c, 2376 .hal_reo1_ring_misc = 0x00000254, 2377 .hal_reo1_ring_hp_addr_lsb = 0x00000258, 2378 .hal_reo1_ring_hp_addr_msb = 0x0000025c, 2379 .hal_reo1_ring_producer_int_setup = 0x00000268, 2380 .hal_reo1_ring_msi1_base_lsb = 0x0000028c, 2381 .hal_reo1_ring_msi1_base_msb = 0x00000290, 2382 .hal_reo1_ring_msi1_data = 0x00000294, 2383 .hal_reo2_ring_base_lsb = 0x0000029c, 2384 .hal_reo1_aging_thresh_ix_0 = 0x0000050c, 2385 .hal_reo1_aging_thresh_ix_1 = 0x00000510, 2386 .hal_reo1_aging_thresh_ix_2 = 0x00000514, 2387 .hal_reo1_aging_thresh_ix_3 = 0x00000518, 2388 2389 /* REO2SW(x) R2 ring pointers (head/tail) address */ 2390 .hal_reo1_ring_hp = 0x00003030, 2391 .hal_reo1_ring_tp = 0x00003034, 2392 .hal_reo2_ring_hp = 0x00003038, 2393 2394 /* REO2TCL R0 ring configuration address */ 2395 .hal_reo_tcl_ring_base_lsb = 0x000003a4, 2396 .hal_reo_tcl_ring_hp = 0x00003050, 2397 2398 /* REO CMD ring address */ 2399 .hal_reo_cmd_ring_base_lsb = 0x00000194, 2400 .hal_reo_cmd_ring_hp = 0x00003020, 2401 2402 /* REO status address */ 2403 .hal_reo_status_ring_base_lsb = 0x000004ac, 2404 .hal_reo_status_hp = 0x00003068, 2405 2406 /* SW2REO ring address */ 2407 .hal_sw2reo_ring_base_lsb = 0x000001ec, 2408 .hal_sw2reo_ring_hp = 0x00003028, 2409 2410 /* WCSS relative address */ 2411 .hal_seq_wcss_umac_ce0_src_reg = 0x00a00000, 2412 .hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000, 2413 .hal_seq_wcss_umac_ce1_src_reg = 0x00a02000, 2414 .hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000, 2415 2416 /* WBM Idle address */ 2417 .hal_wbm_idle_link_ring_base_lsb = 0x00000860, 2418 .hal_wbm_idle_link_ring_misc = 0x00000870, 2419 2420 /* SW2WBM release address */ 2421 .hal_wbm_release_ring_base_lsb = 0x000001d8, 2422 2423 /* WBM2SW release address */ 2424 .hal_wbm0_release_ring_base_lsb = 0x00000910, 2425 .hal_wbm1_release_ring_base_lsb = 0x00000968, 2426 2427 /* PCIe base address */ 2428 .pcie_qserdes_sysclk_en_sel = 0x01e0c0ac, 2429 .pcie_pcs_osc_dtct_config_base = 0x01e0c628, 2430 2431 /* Shadow register area */ 2432 .hal_shadow_base_addr = 0x000008fc, 2433 2434 /* REO misc control register, not used in QCA6390 */ 2435 .hal_reo1_misc_ctl = 0x0, 2436 }; 2437 2438 const struct ath11k_hw_regs qcn9074_regs = { 2439 /* SW2TCL(x) R0 ring configuration address */ 2440 .hal_tcl1_ring_base_lsb = 0x000004f0, 2441 .hal_tcl1_ring_base_msb = 0x000004f4, 2442 .hal_tcl1_ring_id = 0x000004f8, 2443 .hal_tcl1_ring_misc = 0x00000500, 2444 .hal_tcl1_ring_tp_addr_lsb = 0x0000050c, 2445 .hal_tcl1_ring_tp_addr_msb = 0x00000510, 2446 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000520, 2447 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000524, 2448 .hal_tcl1_ring_msi1_base_lsb = 0x00000538, 2449 .hal_tcl1_ring_msi1_base_msb = 0x0000053c, 2450 .hal_tcl1_ring_msi1_data = 0x00000540, 2451 .hal_tcl2_ring_base_lsb = 0x00000548, 2452 .hal_tcl_ring_base_lsb = 0x000005f8, 2453 2454 /* TCL STATUS ring address */ 2455 .hal_tcl_status_ring_base_lsb = 0x00000700, 2456 2457 /* REO2SW(x) R0 ring configuration address */ 2458 .hal_reo1_ring_base_lsb = 0x0000029c, 2459 .hal_reo1_ring_base_msb = 0x000002a0, 2460 .hal_reo1_ring_id = 0x000002a4, 2461 .hal_reo1_ring_misc = 0x000002ac, 2462 .hal_reo1_ring_hp_addr_lsb = 0x000002b0, 2463 .hal_reo1_ring_hp_addr_msb = 0x000002b4, 2464 .hal_reo1_ring_producer_int_setup = 0x000002c0, 2465 .hal_reo1_ring_msi1_base_lsb = 0x000002e4, 2466 .hal_reo1_ring_msi1_base_msb = 0x000002e8, 2467 .hal_reo1_ring_msi1_data = 0x000002ec, 2468 .hal_reo2_ring_base_lsb = 0x000002f4, 2469 .hal_reo1_aging_thresh_ix_0 = 0x00000564, 2470 .hal_reo1_aging_thresh_ix_1 = 0x00000568, 2471 .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 2472 .hal_reo1_aging_thresh_ix_3 = 0x00000570, 2473 2474 /* REO2SW(x) R2 ring pointers (head/tail) address */ 2475 .hal_reo1_ring_hp = 0x00003038, 2476 .hal_reo1_ring_tp = 0x0000303c, 2477 .hal_reo2_ring_hp = 0x00003040, 2478 2479 /* REO2TCL R0 ring configuration address */ 2480 .hal_reo_tcl_ring_base_lsb = 0x000003fc, 2481 .hal_reo_tcl_ring_hp = 0x00003058, 2482 2483 /* REO CMD ring address */ 2484 .hal_reo_cmd_ring_base_lsb = 0x00000194, 2485 .hal_reo_cmd_ring_hp = 0x00003020, 2486 2487 /* REO status address */ 2488 .hal_reo_status_ring_base_lsb = 0x00000504, 2489 .hal_reo_status_hp = 0x00003070, 2490 2491 /* SW2REO ring address */ 2492 .hal_sw2reo_ring_base_lsb = 0x000001ec, 2493 .hal_sw2reo_ring_hp = 0x00003028, 2494 2495 /* WCSS relative address */ 2496 .hal_seq_wcss_umac_ce0_src_reg = 0x01b80000, 2497 .hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000, 2498 .hal_seq_wcss_umac_ce1_src_reg = 0x01b82000, 2499 .hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000, 2500 2501 /* WBM Idle address */ 2502 .hal_wbm_idle_link_ring_base_lsb = 0x00000874, 2503 .hal_wbm_idle_link_ring_misc = 0x00000884, 2504 2505 /* SW2WBM release address */ 2506 .hal_wbm_release_ring_base_lsb = 0x000001ec, 2507 2508 /* WBM2SW release address */ 2509 .hal_wbm0_release_ring_base_lsb = 0x00000924, 2510 .hal_wbm1_release_ring_base_lsb = 0x0000097c, 2511 2512 /* PCIe base address */ 2513 .pcie_qserdes_sysclk_en_sel = 0x01e0e0a8, 2514 .pcie_pcs_osc_dtct_config_base = 0x01e0f45c, 2515 2516 /* Shadow register area */ 2517 .hal_shadow_base_addr = 0x0, 2518 2519 /* REO misc control register, not used in QCN9074 */ 2520 .hal_reo1_misc_ctl = 0x0, 2521 }; 2522 2523 const struct ath11k_hw_regs wcn6855_regs = { 2524 /* SW2TCL(x) R0 ring configuration address */ 2525 .hal_tcl1_ring_base_lsb = 0x00000690, 2526 .hal_tcl1_ring_base_msb = 0x00000694, 2527 .hal_tcl1_ring_id = 0x00000698, 2528 .hal_tcl1_ring_misc = 0x000006a0, 2529 .hal_tcl1_ring_tp_addr_lsb = 0x000006ac, 2530 .hal_tcl1_ring_tp_addr_msb = 0x000006b0, 2531 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c0, 2532 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c4, 2533 .hal_tcl1_ring_msi1_base_lsb = 0x000006d8, 2534 .hal_tcl1_ring_msi1_base_msb = 0x000006dc, 2535 .hal_tcl1_ring_msi1_data = 0x000006e0, 2536 .hal_tcl2_ring_base_lsb = 0x000006e8, 2537 .hal_tcl_ring_base_lsb = 0x00000798, 2538 2539 /* TCL STATUS ring address */ 2540 .hal_tcl_status_ring_base_lsb = 0x000008a0, 2541 2542 /* REO2SW(x) R0 ring configuration address */ 2543 .hal_reo1_ring_base_lsb = 0x00000244, 2544 .hal_reo1_ring_base_msb = 0x00000248, 2545 .hal_reo1_ring_id = 0x0000024c, 2546 .hal_reo1_ring_misc = 0x00000254, 2547 .hal_reo1_ring_hp_addr_lsb = 0x00000258, 2548 .hal_reo1_ring_hp_addr_msb = 0x0000025c, 2549 .hal_reo1_ring_producer_int_setup = 0x00000268, 2550 .hal_reo1_ring_msi1_base_lsb = 0x0000028c, 2551 .hal_reo1_ring_msi1_base_msb = 0x00000290, 2552 .hal_reo1_ring_msi1_data = 0x00000294, 2553 .hal_reo2_ring_base_lsb = 0x0000029c, 2554 .hal_reo1_aging_thresh_ix_0 = 0x000005bc, 2555 .hal_reo1_aging_thresh_ix_1 = 0x000005c0, 2556 .hal_reo1_aging_thresh_ix_2 = 0x000005c4, 2557 .hal_reo1_aging_thresh_ix_3 = 0x000005c8, 2558 2559 /* REO2SW(x) R2 ring pointers (head/tail) address */ 2560 .hal_reo1_ring_hp = 0x00003030, 2561 .hal_reo1_ring_tp = 0x00003034, 2562 .hal_reo2_ring_hp = 0x00003038, 2563 2564 /* REO2TCL R0 ring configuration address */ 2565 .hal_reo_tcl_ring_base_lsb = 0x00000454, 2566 .hal_reo_tcl_ring_hp = 0x00003060, 2567 2568 /* REO CMD ring address */ 2569 .hal_reo_cmd_ring_base_lsb = 0x00000194, 2570 .hal_reo_cmd_ring_hp = 0x00003020, 2571 2572 /* REO status address */ 2573 .hal_reo_status_ring_base_lsb = 0x0000055c, 2574 .hal_reo_status_hp = 0x00003078, 2575 2576 /* SW2REO ring address */ 2577 .hal_sw2reo_ring_base_lsb = 0x000001ec, 2578 .hal_sw2reo_ring_hp = 0x00003028, 2579 2580 /* WCSS relative address */ 2581 .hal_seq_wcss_umac_ce0_src_reg = 0x1b80000, 2582 .hal_seq_wcss_umac_ce0_dst_reg = 0x1b81000, 2583 .hal_seq_wcss_umac_ce1_src_reg = 0x1b82000, 2584 .hal_seq_wcss_umac_ce1_dst_reg = 0x1b83000, 2585 2586 /* WBM Idle address */ 2587 .hal_wbm_idle_link_ring_base_lsb = 0x00000870, 2588 .hal_wbm_idle_link_ring_misc = 0x00000880, 2589 2590 /* SW2WBM release address */ 2591 .hal_wbm_release_ring_base_lsb = 0x000001e8, 2592 2593 /* WBM2SW release address */ 2594 .hal_wbm0_release_ring_base_lsb = 0x00000920, 2595 .hal_wbm1_release_ring_base_lsb = 0x00000978, 2596 2597 /* PCIe base address */ 2598 .pcie_qserdes_sysclk_en_sel = 0x01e0c0ac, 2599 .pcie_pcs_osc_dtct_config_base = 0x01e0c628, 2600 2601 /* Shadow register area */ 2602 .hal_shadow_base_addr = 0x000008fc, 2603 2604 /* REO misc control register, used for fragment 2605 * destination ring config in WCN6855. 2606 */ 2607 .hal_reo1_misc_ctl = 0x00000630, 2608 }; 2609 2610 const struct ath11k_hw_regs wcn6750_regs = { 2611 /* SW2TCL(x) R0 ring configuration address */ 2612 .hal_tcl1_ring_base_lsb = 0x00000694, 2613 .hal_tcl1_ring_base_msb = 0x00000698, 2614 .hal_tcl1_ring_id = 0x0000069c, 2615 .hal_tcl1_ring_misc = 0x000006a4, 2616 .hal_tcl1_ring_tp_addr_lsb = 0x000006b0, 2617 .hal_tcl1_ring_tp_addr_msb = 0x000006b4, 2618 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c4, 2619 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c8, 2620 .hal_tcl1_ring_msi1_base_lsb = 0x000006dc, 2621 .hal_tcl1_ring_msi1_base_msb = 0x000006e0, 2622 .hal_tcl1_ring_msi1_data = 0x000006e4, 2623 .hal_tcl2_ring_base_lsb = 0x000006ec, 2624 .hal_tcl_ring_base_lsb = 0x0000079c, 2625 2626 /* TCL STATUS ring address */ 2627 .hal_tcl_status_ring_base_lsb = 0x000008a4, 2628 2629 /* REO2SW(x) R0 ring configuration address */ 2630 .hal_reo1_ring_base_lsb = 0x000001ec, 2631 .hal_reo1_ring_base_msb = 0x000001f0, 2632 .hal_reo1_ring_id = 0x000001f4, 2633 .hal_reo1_ring_misc = 0x000001fc, 2634 .hal_reo1_ring_hp_addr_lsb = 0x00000200, 2635 .hal_reo1_ring_hp_addr_msb = 0x00000204, 2636 .hal_reo1_ring_producer_int_setup = 0x00000210, 2637 .hal_reo1_ring_msi1_base_lsb = 0x00000234, 2638 .hal_reo1_ring_msi1_base_msb = 0x00000238, 2639 .hal_reo1_ring_msi1_data = 0x0000023c, 2640 .hal_reo2_ring_base_lsb = 0x00000244, 2641 .hal_reo1_aging_thresh_ix_0 = 0x00000564, 2642 .hal_reo1_aging_thresh_ix_1 = 0x00000568, 2643 .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 2644 .hal_reo1_aging_thresh_ix_3 = 0x00000570, 2645 2646 /* REO2SW(x) R2 ring pointers (head/tail) address */ 2647 .hal_reo1_ring_hp = 0x00003028, 2648 .hal_reo1_ring_tp = 0x0000302c, 2649 .hal_reo2_ring_hp = 0x00003030, 2650 2651 /* REO2TCL R0 ring configuration address */ 2652 .hal_reo_tcl_ring_base_lsb = 0x000003fc, 2653 .hal_reo_tcl_ring_hp = 0x00003058, 2654 2655 /* REO CMD ring address */ 2656 .hal_reo_cmd_ring_base_lsb = 0x000000e4, 2657 .hal_reo_cmd_ring_hp = 0x00003010, 2658 2659 /* REO status address */ 2660 .hal_reo_status_ring_base_lsb = 0x00000504, 2661 .hal_reo_status_hp = 0x00003070, 2662 2663 /* SW2REO ring address */ 2664 .hal_sw2reo_ring_base_lsb = 0x0000013c, 2665 .hal_sw2reo_ring_hp = 0x00003018, 2666 2667 /* WCSS relative address */ 2668 .hal_seq_wcss_umac_ce0_src_reg = 0x01b80000, 2669 .hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000, 2670 .hal_seq_wcss_umac_ce1_src_reg = 0x01b82000, 2671 .hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000, 2672 2673 /* WBM Idle address */ 2674 .hal_wbm_idle_link_ring_base_lsb = 0x00000874, 2675 .hal_wbm_idle_link_ring_misc = 0x00000884, 2676 2677 /* SW2WBM release address */ 2678 .hal_wbm_release_ring_base_lsb = 0x000001ec, 2679 2680 /* WBM2SW release address */ 2681 .hal_wbm0_release_ring_base_lsb = 0x00000924, 2682 .hal_wbm1_release_ring_base_lsb = 0x0000097c, 2683 2684 /* PCIe base address */ 2685 .pcie_qserdes_sysclk_en_sel = 0x0, 2686 .pcie_pcs_osc_dtct_config_base = 0x0, 2687 2688 /* Shadow register area */ 2689 .hal_shadow_base_addr = 0x00000504, 2690 2691 /* REO misc control register, used for fragment 2692 * destination ring config in WCN6750. 2693 */ 2694 .hal_reo1_misc_ctl = 0x000005d8, 2695 }; 2696 2697 static const struct ath11k_hw_tcl2wbm_rbm_map ath11k_hw_tcl2wbm_rbm_map_ipq8074[] = { 2698 { 2699 .tcl_ring_num = 0, 2700 .wbm_ring_num = 0, 2701 .rbm_id = HAL_RX_BUF_RBM_SW0_BM, 2702 }, 2703 { 2704 .tcl_ring_num = 1, 2705 .wbm_ring_num = 1, 2706 .rbm_id = HAL_RX_BUF_RBM_SW1_BM, 2707 }, 2708 { 2709 .tcl_ring_num = 2, 2710 .wbm_ring_num = 2, 2711 .rbm_id = HAL_RX_BUF_RBM_SW2_BM, 2712 }, 2713 }; 2714 2715 static const struct ath11k_hw_tcl2wbm_rbm_map ath11k_hw_tcl2wbm_rbm_map_wcn6750[] = { 2716 { 2717 .tcl_ring_num = 0, 2718 .wbm_ring_num = 0, 2719 .rbm_id = HAL_RX_BUF_RBM_SW0_BM, 2720 }, 2721 { 2722 .tcl_ring_num = 1, 2723 .wbm_ring_num = 4, 2724 .rbm_id = HAL_RX_BUF_RBM_SW4_BM, 2725 }, 2726 { 2727 .tcl_ring_num = 2, 2728 .wbm_ring_num = 2, 2729 .rbm_id = HAL_RX_BUF_RBM_SW2_BM, 2730 }, 2731 }; 2732 2733 const struct ath11k_hw_regs ipq5018_regs = { 2734 /* SW2TCL(x) R0 ring configuration address */ 2735 .hal_tcl1_ring_base_lsb = 0x00000694, 2736 .hal_tcl1_ring_base_msb = 0x00000698, 2737 .hal_tcl1_ring_id = 0x0000069c, 2738 .hal_tcl1_ring_misc = 0x000006a4, 2739 .hal_tcl1_ring_tp_addr_lsb = 0x000006b0, 2740 .hal_tcl1_ring_tp_addr_msb = 0x000006b4, 2741 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c4, 2742 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c8, 2743 .hal_tcl1_ring_msi1_base_lsb = 0x000006dc, 2744 .hal_tcl1_ring_msi1_base_msb = 0x000006e0, 2745 .hal_tcl1_ring_msi1_data = 0x000006e4, 2746 .hal_tcl2_ring_base_lsb = 0x000006ec, 2747 .hal_tcl_ring_base_lsb = 0x0000079c, 2748 2749 /* TCL STATUS ring address */ 2750 .hal_tcl_status_ring_base_lsb = 0x000008a4, 2751 2752 /* REO2SW(x) R0 ring configuration address */ 2753 .hal_reo1_ring_base_lsb = 0x000001ec, 2754 .hal_reo1_ring_base_msb = 0x000001f0, 2755 .hal_reo1_ring_id = 0x000001f4, 2756 .hal_reo1_ring_misc = 0x000001fc, 2757 .hal_reo1_ring_hp_addr_lsb = 0x00000200, 2758 .hal_reo1_ring_hp_addr_msb = 0x00000204, 2759 .hal_reo1_ring_producer_int_setup = 0x00000210, 2760 .hal_reo1_ring_msi1_base_lsb = 0x00000234, 2761 .hal_reo1_ring_msi1_base_msb = 0x00000238, 2762 .hal_reo1_ring_msi1_data = 0x0000023c, 2763 .hal_reo2_ring_base_lsb = 0x00000244, 2764 .hal_reo1_aging_thresh_ix_0 = 0x00000564, 2765 .hal_reo1_aging_thresh_ix_1 = 0x00000568, 2766 .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 2767 .hal_reo1_aging_thresh_ix_3 = 0x00000570, 2768 2769 /* REO2SW(x) R2 ring pointers (head/tail) address */ 2770 .hal_reo1_ring_hp = 0x00003028, 2771 .hal_reo1_ring_tp = 0x0000302c, 2772 .hal_reo2_ring_hp = 0x00003030, 2773 2774 /* REO2TCL R0 ring configuration address */ 2775 .hal_reo_tcl_ring_base_lsb = 0x000003fc, 2776 .hal_reo_tcl_ring_hp = 0x00003058, 2777 2778 /* SW2REO ring address */ 2779 .hal_sw2reo_ring_base_lsb = 0x0000013c, 2780 .hal_sw2reo_ring_hp = 0x00003018, 2781 2782 /* REO CMD ring address */ 2783 .hal_reo_cmd_ring_base_lsb = 0x000000e4, 2784 .hal_reo_cmd_ring_hp = 0x00003010, 2785 2786 /* REO status address */ 2787 .hal_reo_status_ring_base_lsb = 0x00000504, 2788 .hal_reo_status_hp = 0x00003070, 2789 2790 /* WCSS relative address */ 2791 .hal_seq_wcss_umac_ce0_src_reg = 0x08400000 2792 - HAL_IPQ5018_CE_WFSS_REG_BASE, 2793 .hal_seq_wcss_umac_ce0_dst_reg = 0x08401000 2794 - HAL_IPQ5018_CE_WFSS_REG_BASE, 2795 .hal_seq_wcss_umac_ce1_src_reg = 0x08402000 2796 - HAL_IPQ5018_CE_WFSS_REG_BASE, 2797 .hal_seq_wcss_umac_ce1_dst_reg = 0x08403000 2798 - HAL_IPQ5018_CE_WFSS_REG_BASE, 2799 2800 /* WBM Idle address */ 2801 .hal_wbm_idle_link_ring_base_lsb = 0x00000874, 2802 .hal_wbm_idle_link_ring_misc = 0x00000884, 2803 2804 /* SW2WBM release address */ 2805 .hal_wbm_release_ring_base_lsb = 0x000001ec, 2806 2807 /* WBM2SW release address */ 2808 .hal_wbm0_release_ring_base_lsb = 0x00000924, 2809 .hal_wbm1_release_ring_base_lsb = 0x0000097c, 2810 }; 2811 2812 const struct ath11k_hw_hal_params ath11k_hw_hal_params_ipq8074 = { 2813 .rx_buf_rbm = HAL_RX_BUF_RBM_SW3_BM, 2814 .tcl2wbm_rbm_map = ath11k_hw_tcl2wbm_rbm_map_ipq8074, 2815 }; 2816 2817 const struct ath11k_hw_hal_params ath11k_hw_hal_params_qca6390 = { 2818 .rx_buf_rbm = HAL_RX_BUF_RBM_SW1_BM, 2819 .tcl2wbm_rbm_map = ath11k_hw_tcl2wbm_rbm_map_ipq8074, 2820 }; 2821 2822 const struct ath11k_hw_hal_params ath11k_hw_hal_params_wcn6750 = { 2823 .rx_buf_rbm = HAL_RX_BUF_RBM_SW1_BM, 2824 .tcl2wbm_rbm_map = ath11k_hw_tcl2wbm_rbm_map_wcn6750, 2825 }; 2826 2827 static const struct cfg80211_sar_freq_ranges ath11k_hw_sar_freq_ranges_wcn6855[] = { 2828 {.start_freq = 2402, .end_freq = 2482 }, /* 2G ch1~ch13 */ 2829 {.start_freq = 5150, .end_freq = 5250 }, /* 5G UNII-1 ch32~ch48 */ 2830 {.start_freq = 5250, .end_freq = 5725 }, /* 5G UNII-2 ch50~ch144 */ 2831 {.start_freq = 5725, .end_freq = 5810 }, /* 5G UNII-3 ch149~ch161 */ 2832 {.start_freq = 5815, .end_freq = 5895 }, /* 5G UNII-4 ch163~ch177 */ 2833 {.start_freq = 5925, .end_freq = 6165 }, /* 6G UNII-5 Ch1, Ch2 ~ Ch41 */ 2834 {.start_freq = 6165, .end_freq = 6425 }, /* 6G UNII-5 ch45~ch93 */ 2835 {.start_freq = 6425, .end_freq = 6525 }, /* 6G UNII-6 ch97~ch113 */ 2836 {.start_freq = 6525, .end_freq = 6705 }, /* 6G UNII-7 ch117~ch149 */ 2837 {.start_freq = 6705, .end_freq = 6875 }, /* 6G UNII-7 ch153~ch185 */ 2838 {.start_freq = 6875, .end_freq = 7125 }, /* 6G UNII-8 ch189~ch233 */ 2839 }; 2840 2841 const struct cfg80211_sar_capa ath11k_hw_sar_capa_wcn6855 = { 2842 .type = NL80211_SAR_TYPE_POWER, 2843 .num_freq_ranges = (ARRAY_SIZE(ath11k_hw_sar_freq_ranges_wcn6855)), 2844 .freq_ranges = ath11k_hw_sar_freq_ranges_wcn6855, 2845 }; 2846