1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/types.h> 7 #include <linux/bitops.h> 8 #include <linux/bitfield.h> 9 10 #include "hw.h" 11 #include "core.h" 12 #include "ce.h" 13 14 /* Map from pdev index to hw mac index */ 15 static u8 ath11k_hw_ipq8074_mac_from_pdev_id(int pdev_idx) 16 { 17 switch (pdev_idx) { 18 case 0: 19 return 0; 20 case 1: 21 return 2; 22 case 2: 23 return 1; 24 default: 25 return ATH11K_INVALID_HW_MAC_ID; 26 } 27 } 28 29 static u8 ath11k_hw_ipq6018_mac_from_pdev_id(int pdev_idx) 30 { 31 return pdev_idx; 32 } 33 34 static void ath11k_hw_ipq8074_tx_mesh_enable(struct ath11k_base *ab, 35 struct hal_tcl_data_cmd *tcl_cmd) 36 { 37 tcl_cmd->info2 |= FIELD_PREP(HAL_IPQ8074_TCL_DATA_CMD_INFO2_MESH_ENABLE, 38 true); 39 } 40 41 static void ath11k_hw_qcn9074_tx_mesh_enable(struct ath11k_base *ab, 42 struct hal_tcl_data_cmd *tcl_cmd) 43 { 44 tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE, 45 true); 46 } 47 48 static void ath11k_init_wmi_config_qca6390(struct ath11k_base *ab, 49 struct target_resource_config *config) 50 { 51 config->num_vdevs = 4; 52 config->num_peers = 16; 53 config->num_tids = 32; 54 55 config->num_offload_peers = 3; 56 config->num_offload_reorder_buffs = 3; 57 config->num_peer_keys = TARGET_NUM_PEER_KEYS; 58 config->ast_skid_limit = TARGET_AST_SKID_LIMIT; 59 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 60 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 61 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; 62 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI; 63 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; 64 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; 65 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; 66 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS; 67 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV; 68 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV; 69 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES; 70 config->num_mcast_groups = 0; 71 config->num_mcast_table_elems = 0; 72 config->mcast2ucast_mode = 0; 73 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE; 74 config->num_wds_entries = 0; 75 config->dma_burst_size = 0; 76 config->rx_skip_defrag_timeout_dup_detection_check = 0; 77 config->vow_config = TARGET_VOW_CONFIG; 78 config->gtk_offload_max_vdev = 2; 79 config->num_msdu_desc = 0x400; 80 config->beacon_tx_offload_max_vdev = 2; 81 config->rx_batchmode = TARGET_RX_BATCHMODE; 82 83 config->peer_map_unmap_v2_support = 0; 84 config->use_pdev_id = 1; 85 config->max_frag_entries = 0xa; 86 config->num_tdls_vdevs = 0x1; 87 config->num_tdls_conn_table_entries = 8; 88 config->beacon_tx_offload_max_vdev = 0x2; 89 config->num_multicast_filter_entries = 0x20; 90 config->num_wow_filters = 0x16; 91 config->num_keep_alive_pattern = 0; 92 } 93 94 static void ath11k_init_wmi_config_ipq8074(struct ath11k_base *ab, 95 struct target_resource_config *config) 96 { 97 config->num_vdevs = ab->num_radios * TARGET_NUM_VDEVS; 98 99 if (ab->num_radios == 2) { 100 config->num_peers = TARGET_NUM_PEERS(DBS); 101 config->num_tids = TARGET_NUM_TIDS(DBS); 102 } else if (ab->num_radios == 3) { 103 config->num_peers = TARGET_NUM_PEERS(DBS_SBS); 104 config->num_tids = TARGET_NUM_TIDS(DBS_SBS); 105 } else { 106 /* Control should not reach here */ 107 config->num_peers = TARGET_NUM_PEERS(SINGLE); 108 config->num_tids = TARGET_NUM_TIDS(SINGLE); 109 } 110 config->num_offload_peers = TARGET_NUM_OFFLD_PEERS; 111 config->num_offload_reorder_buffs = TARGET_NUM_OFFLD_REORDER_BUFFS; 112 config->num_peer_keys = TARGET_NUM_PEER_KEYS; 113 config->ast_skid_limit = TARGET_AST_SKID_LIMIT; 114 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 115 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 116 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; 117 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI; 118 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; 119 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; 120 121 if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) 122 config->rx_decap_mode = TARGET_DECAP_MODE_RAW; 123 else 124 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; 125 126 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS; 127 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV; 128 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV; 129 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES; 130 config->num_mcast_groups = TARGET_NUM_MCAST_GROUPS; 131 config->num_mcast_table_elems = TARGET_NUM_MCAST_TABLE_ELEMS; 132 config->mcast2ucast_mode = TARGET_MCAST2UCAST_MODE; 133 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE; 134 config->num_wds_entries = TARGET_NUM_WDS_ENTRIES; 135 config->dma_burst_size = TARGET_DMA_BURST_SIZE; 136 config->rx_skip_defrag_timeout_dup_detection_check = 137 TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK; 138 config->vow_config = TARGET_VOW_CONFIG; 139 config->gtk_offload_max_vdev = TARGET_GTK_OFFLOAD_MAX_VDEV; 140 config->num_msdu_desc = TARGET_NUM_MSDU_DESC; 141 config->beacon_tx_offload_max_vdev = ab->num_radios * TARGET_MAX_BCN_OFFLD; 142 config->rx_batchmode = TARGET_RX_BATCHMODE; 143 config->peer_map_unmap_v2_support = 1; 144 config->twt_ap_pdev_count = ab->num_radios; 145 config->twt_ap_sta_count = 1000; 146 } 147 148 static int ath11k_hw_mac_id_to_pdev_id_ipq8074(struct ath11k_hw_params *hw, 149 int mac_id) 150 { 151 return mac_id; 152 } 153 154 static int ath11k_hw_mac_id_to_srng_id_ipq8074(struct ath11k_hw_params *hw, 155 int mac_id) 156 { 157 return 0; 158 } 159 160 static int ath11k_hw_mac_id_to_pdev_id_qca6390(struct ath11k_hw_params *hw, 161 int mac_id) 162 { 163 return 0; 164 } 165 166 static int ath11k_hw_mac_id_to_srng_id_qca6390(struct ath11k_hw_params *hw, 167 int mac_id) 168 { 169 return mac_id; 170 } 171 172 static bool ath11k_hw_ipq8074_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 173 { 174 return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU, 175 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 176 } 177 178 static bool ath11k_hw_ipq8074_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 179 { 180 return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU, 181 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 182 } 183 184 static u8 ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 185 { 186 return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING, 187 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 188 } 189 190 static u8 *ath11k_hw_ipq8074_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 191 { 192 return desc->u.ipq8074.hdr_status; 193 } 194 195 static bool ath11k_hw_ipq8074_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 196 { 197 return __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1) & 198 RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID; 199 } 200 201 static u32 ath11k_hw_ipq8074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 202 { 203 return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE, 204 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2)); 205 } 206 207 static u8 ath11k_hw_ipq8074_rx_desc_get_decap_type(struct hal_rx_desc *desc) 208 { 209 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 210 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2)); 211 } 212 213 static u8 ath11k_hw_ipq8074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 214 { 215 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 216 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2)); 217 } 218 219 static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 220 { 221 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID, 222 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 223 } 224 225 static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 226 { 227 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID, 228 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 229 } 230 231 static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 232 { 233 return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM, 234 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 235 } 236 237 static u16 ath11k_hw_ipq8074_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 238 { 239 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 240 __le32_to_cpu(desc->u.ipq8074.msdu_start.info1)); 241 } 242 243 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 244 { 245 return FIELD_GET(RX_MSDU_START_INFO3_SGI, 246 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 247 } 248 249 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 250 { 251 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 252 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 253 } 254 255 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 256 { 257 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 258 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 259 } 260 261 static u32 ath11k_hw_ipq8074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 262 { 263 return __le32_to_cpu(desc->u.ipq8074.msdu_start.phy_meta_data); 264 } 265 266 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 267 { 268 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 269 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 270 } 271 272 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 273 { 274 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 275 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 276 } 277 278 static u8 ath11k_hw_ipq8074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 279 { 280 return FIELD_GET(RX_MPDU_START_INFO2_TID, 281 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2)); 282 } 283 284 static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 285 { 286 return __le16_to_cpu(desc->u.ipq8074.mpdu_start.sw_peer_id); 287 } 288 289 static void ath11k_hw_ipq8074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 290 struct hal_rx_desc *ldesc) 291 { 292 memcpy((u8 *)&fdesc->u.ipq8074.msdu_end, (u8 *)&ldesc->u.ipq8074.msdu_end, 293 sizeof(struct rx_msdu_end_ipq8074)); 294 memcpy((u8 *)&fdesc->u.ipq8074.attention, (u8 *)&ldesc->u.ipq8074.attention, 295 sizeof(struct rx_attention)); 296 memcpy((u8 *)&fdesc->u.ipq8074.mpdu_end, (u8 *)&ldesc->u.ipq8074.mpdu_end, 297 sizeof(struct rx_mpdu_end)); 298 } 299 300 static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 301 { 302 return FIELD_GET(HAL_TLV_HDR_TAG, 303 __le32_to_cpu(desc->u.ipq8074.mpdu_start_tag)); 304 } 305 306 static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 307 { 308 return __le16_to_cpu(desc->u.ipq8074.mpdu_start.phy_ppdu_id); 309 } 310 311 static void ath11k_hw_ipq8074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 312 { 313 u32 info = __le32_to_cpu(desc->u.ipq8074.msdu_start.info1); 314 315 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 316 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 317 318 desc->u.ipq8074.msdu_start.info1 = __cpu_to_le32(info); 319 } 320 321 static 322 struct rx_attention *ath11k_hw_ipq8074_rx_desc_get_attention(struct hal_rx_desc *desc) 323 { 324 return &desc->u.ipq8074.attention; 325 } 326 327 static u8 *ath11k_hw_ipq8074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 328 { 329 return &desc->u.ipq8074.msdu_payload[0]; 330 } 331 332 static bool ath11k_hw_qcn9074_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 333 { 334 return !!FIELD_GET(RX_MSDU_END_INFO4_FIRST_MSDU, 335 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 336 } 337 338 static bool ath11k_hw_qcn9074_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 339 { 340 return !!FIELD_GET(RX_MSDU_END_INFO4_LAST_MSDU, 341 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 342 } 343 344 static u8 ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 345 { 346 return FIELD_GET(RX_MSDU_END_INFO4_L3_HDR_PADDING, 347 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 348 } 349 350 static u8 *ath11k_hw_qcn9074_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 351 { 352 return desc->u.qcn9074.hdr_status; 353 } 354 355 static bool ath11k_hw_qcn9074_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 356 { 357 return __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11) & 358 RX_MPDU_START_INFO11_ENCRYPT_INFO_VALID; 359 } 360 361 static u32 ath11k_hw_qcn9074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 362 { 363 return FIELD_GET(RX_MPDU_START_INFO9_ENC_TYPE, 364 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9)); 365 } 366 367 static u8 ath11k_hw_qcn9074_rx_desc_get_decap_type(struct hal_rx_desc *desc) 368 { 369 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 370 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2)); 371 } 372 373 static u8 ath11k_hw_qcn9074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 374 { 375 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 376 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2)); 377 } 378 379 static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 380 { 381 return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_CTRL_VALID, 382 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 383 } 384 385 static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 386 { 387 return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_FCTRL_VALID, 388 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 389 } 390 391 static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 392 { 393 return FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_NUM, 394 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 395 } 396 397 static u16 ath11k_hw_qcn9074_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 398 { 399 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 400 __le32_to_cpu(desc->u.qcn9074.msdu_start.info1)); 401 } 402 403 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 404 { 405 return FIELD_GET(RX_MSDU_START_INFO3_SGI, 406 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 407 } 408 409 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 410 { 411 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 412 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 413 } 414 415 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 416 { 417 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 418 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 419 } 420 421 static u32 ath11k_hw_qcn9074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 422 { 423 return __le32_to_cpu(desc->u.qcn9074.msdu_start.phy_meta_data); 424 } 425 426 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 427 { 428 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 429 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 430 } 431 432 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 433 { 434 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 435 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 436 } 437 438 static u8 ath11k_hw_qcn9074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 439 { 440 return FIELD_GET(RX_MPDU_START_INFO9_TID, 441 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9)); 442 } 443 444 static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 445 { 446 return __le16_to_cpu(desc->u.qcn9074.mpdu_start.sw_peer_id); 447 } 448 449 static void ath11k_hw_qcn9074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 450 struct hal_rx_desc *ldesc) 451 { 452 memcpy((u8 *)&fdesc->u.qcn9074.msdu_end, (u8 *)&ldesc->u.qcn9074.msdu_end, 453 sizeof(struct rx_msdu_end_qcn9074)); 454 memcpy((u8 *)&fdesc->u.qcn9074.attention, (u8 *)&ldesc->u.qcn9074.attention, 455 sizeof(struct rx_attention)); 456 memcpy((u8 *)&fdesc->u.qcn9074.mpdu_end, (u8 *)&ldesc->u.qcn9074.mpdu_end, 457 sizeof(struct rx_mpdu_end)); 458 } 459 460 static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 461 { 462 return FIELD_GET(HAL_TLV_HDR_TAG, 463 __le32_to_cpu(desc->u.qcn9074.mpdu_start_tag)); 464 } 465 466 static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 467 { 468 return __le16_to_cpu(desc->u.qcn9074.mpdu_start.phy_ppdu_id); 469 } 470 471 static void ath11k_hw_qcn9074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 472 { 473 u32 info = __le32_to_cpu(desc->u.qcn9074.msdu_start.info1); 474 475 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 476 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 477 478 desc->u.qcn9074.msdu_start.info1 = __cpu_to_le32(info); 479 } 480 481 static 482 struct rx_attention *ath11k_hw_qcn9074_rx_desc_get_attention(struct hal_rx_desc *desc) 483 { 484 return &desc->u.qcn9074.attention; 485 } 486 487 static u8 *ath11k_hw_qcn9074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 488 { 489 return &desc->u.qcn9074.msdu_payload[0]; 490 } 491 492 const struct ath11k_hw_ops ipq8074_ops = { 493 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 494 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 495 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 496 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 497 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 498 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 499 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 500 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 501 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 502 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 503 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 504 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 505 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 506 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 507 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 508 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 509 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 510 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 511 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 512 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 513 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 514 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 515 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 516 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 517 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 518 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 519 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 520 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 521 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 522 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 523 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 524 }; 525 526 const struct ath11k_hw_ops ipq6018_ops = { 527 .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 528 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 529 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 530 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 531 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 532 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 533 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 534 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 535 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 536 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 537 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 538 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 539 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 540 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 541 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 542 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 543 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 544 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 545 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 546 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 547 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 548 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 549 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 550 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 551 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 552 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 553 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 554 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 555 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 556 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 557 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 558 }; 559 560 const struct ath11k_hw_ops qca6390_ops = { 561 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 562 .wmi_init_config = ath11k_init_wmi_config_qca6390, 563 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390, 564 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390, 565 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 566 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 567 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 568 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 569 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 570 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 571 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 572 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 573 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 574 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 575 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 576 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 577 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 578 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 579 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 580 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 581 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 582 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 583 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 584 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 585 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 586 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 587 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 588 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 589 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 590 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 591 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 592 }; 593 594 const struct ath11k_hw_ops qcn9074_ops = { 595 .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 596 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 597 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 598 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 599 .tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable, 600 .rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu, 601 .rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu, 602 .rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes, 603 .rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status, 604 .rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid, 605 .rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type, 606 .rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type, 607 .rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl, 608 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld, 609 .rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid, 610 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no, 611 .rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len, 612 .rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi, 613 .rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs, 614 .rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw, 615 .rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq, 616 .rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type, 617 .rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss, 618 .rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid, 619 .rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id, 620 .rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end, 621 .rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag, 622 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id, 623 .rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len, 624 .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention, 625 .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload, 626 }; 627 628 #define ATH11K_TX_RING_MASK_0 0x1 629 #define ATH11K_TX_RING_MASK_1 0x2 630 #define ATH11K_TX_RING_MASK_2 0x4 631 632 #define ATH11K_RX_RING_MASK_0 0x1 633 #define ATH11K_RX_RING_MASK_1 0x2 634 #define ATH11K_RX_RING_MASK_2 0x4 635 #define ATH11K_RX_RING_MASK_3 0x8 636 637 #define ATH11K_RX_ERR_RING_MASK_0 0x1 638 639 #define ATH11K_RX_WBM_REL_RING_MASK_0 0x1 640 641 #define ATH11K_REO_STATUS_RING_MASK_0 0x1 642 643 #define ATH11K_RXDMA2HOST_RING_MASK_0 0x1 644 #define ATH11K_RXDMA2HOST_RING_MASK_1 0x2 645 #define ATH11K_RXDMA2HOST_RING_MASK_2 0x4 646 647 #define ATH11K_HOST2RXDMA_RING_MASK_0 0x1 648 #define ATH11K_HOST2RXDMA_RING_MASK_1 0x2 649 #define ATH11K_HOST2RXDMA_RING_MASK_2 0x4 650 651 #define ATH11K_RX_MON_STATUS_RING_MASK_0 0x1 652 #define ATH11K_RX_MON_STATUS_RING_MASK_1 0x2 653 #define ATH11K_RX_MON_STATUS_RING_MASK_2 0x4 654 655 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074 = { 656 .tx = { 657 ATH11K_TX_RING_MASK_0, 658 ATH11K_TX_RING_MASK_1, 659 ATH11K_TX_RING_MASK_2, 660 }, 661 .rx_mon_status = { 662 0, 0, 0, 0, 663 ATH11K_RX_MON_STATUS_RING_MASK_0, 664 ATH11K_RX_MON_STATUS_RING_MASK_1, 665 ATH11K_RX_MON_STATUS_RING_MASK_2, 666 }, 667 .rx = { 668 0, 0, 0, 0, 0, 0, 0, 669 ATH11K_RX_RING_MASK_0, 670 ATH11K_RX_RING_MASK_1, 671 ATH11K_RX_RING_MASK_2, 672 ATH11K_RX_RING_MASK_3, 673 }, 674 .rx_err = { 675 ATH11K_RX_ERR_RING_MASK_0, 676 }, 677 .rx_wbm_rel = { 678 ATH11K_RX_WBM_REL_RING_MASK_0, 679 }, 680 .reo_status = { 681 ATH11K_REO_STATUS_RING_MASK_0, 682 }, 683 .rxdma2host = { 684 ATH11K_RXDMA2HOST_RING_MASK_0, 685 ATH11K_RXDMA2HOST_RING_MASK_1, 686 ATH11K_RXDMA2HOST_RING_MASK_2, 687 }, 688 .host2rxdma = { 689 ATH11K_HOST2RXDMA_RING_MASK_0, 690 ATH11K_HOST2RXDMA_RING_MASK_1, 691 ATH11K_HOST2RXDMA_RING_MASK_2, 692 }, 693 }; 694 695 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390 = { 696 .tx = { 697 ATH11K_TX_RING_MASK_0, 698 ATH11K_TX_RING_MASK_1, 699 ATH11K_TX_RING_MASK_2, 700 }, 701 .rx_mon_status = { 702 0, 0, 0, 0, 703 ATH11K_RX_MON_STATUS_RING_MASK_0, 704 ATH11K_RX_MON_STATUS_RING_MASK_1, 705 ATH11K_RX_MON_STATUS_RING_MASK_2, 706 }, 707 .rx = { 708 0, 0, 0, 0, 0, 0, 0, 709 ATH11K_RX_RING_MASK_0, 710 ATH11K_RX_RING_MASK_1, 711 ATH11K_RX_RING_MASK_2, 712 ATH11K_RX_RING_MASK_3, 713 }, 714 .rx_err = { 715 ATH11K_RX_ERR_RING_MASK_0, 716 }, 717 .rx_wbm_rel = { 718 ATH11K_RX_WBM_REL_RING_MASK_0, 719 }, 720 .reo_status = { 721 ATH11K_REO_STATUS_RING_MASK_0, 722 }, 723 .rxdma2host = { 724 ATH11K_RXDMA2HOST_RING_MASK_0, 725 ATH11K_RXDMA2HOST_RING_MASK_1, 726 ATH11K_RXDMA2HOST_RING_MASK_2, 727 }, 728 .host2rxdma = { 729 }, 730 }; 731 732 /* Target firmware's Copy Engine configuration. */ 733 const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq8074[] = { 734 /* CE0: host->target HTC control and raw streams */ 735 { 736 .pipenum = __cpu_to_le32(0), 737 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 738 .nentries = __cpu_to_le32(32), 739 .nbytes_max = __cpu_to_le32(2048), 740 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 741 .reserved = __cpu_to_le32(0), 742 }, 743 744 /* CE1: target->host HTT + HTC control */ 745 { 746 .pipenum = __cpu_to_le32(1), 747 .pipedir = __cpu_to_le32(PIPEDIR_IN), 748 .nentries = __cpu_to_le32(32), 749 .nbytes_max = __cpu_to_le32(2048), 750 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 751 .reserved = __cpu_to_le32(0), 752 }, 753 754 /* CE2: target->host WMI */ 755 { 756 .pipenum = __cpu_to_le32(2), 757 .pipedir = __cpu_to_le32(PIPEDIR_IN), 758 .nentries = __cpu_to_le32(32), 759 .nbytes_max = __cpu_to_le32(2048), 760 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 761 .reserved = __cpu_to_le32(0), 762 }, 763 764 /* CE3: host->target WMI */ 765 { 766 .pipenum = __cpu_to_le32(3), 767 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 768 .nentries = __cpu_to_le32(32), 769 .nbytes_max = __cpu_to_le32(2048), 770 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 771 .reserved = __cpu_to_le32(0), 772 }, 773 774 /* CE4: host->target HTT */ 775 { 776 .pipenum = __cpu_to_le32(4), 777 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 778 .nentries = __cpu_to_le32(256), 779 .nbytes_max = __cpu_to_le32(256), 780 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 781 .reserved = __cpu_to_le32(0), 782 }, 783 784 /* CE5: target->host Pktlog */ 785 { 786 .pipenum = __cpu_to_le32(5), 787 .pipedir = __cpu_to_le32(PIPEDIR_IN), 788 .nentries = __cpu_to_le32(32), 789 .nbytes_max = __cpu_to_le32(2048), 790 .flags = __cpu_to_le32(0), 791 .reserved = __cpu_to_le32(0), 792 }, 793 794 /* CE6: Reserved for target autonomous hif_memcpy */ 795 { 796 .pipenum = __cpu_to_le32(6), 797 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 798 .nentries = __cpu_to_le32(32), 799 .nbytes_max = __cpu_to_le32(65535), 800 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 801 .reserved = __cpu_to_le32(0), 802 }, 803 804 /* CE7 used only by Host */ 805 { 806 .pipenum = __cpu_to_le32(7), 807 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 808 .nentries = __cpu_to_le32(32), 809 .nbytes_max = __cpu_to_le32(2048), 810 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 811 .reserved = __cpu_to_le32(0), 812 }, 813 814 /* CE8 target->host used only by IPA */ 815 { 816 .pipenum = __cpu_to_le32(8), 817 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 818 .nentries = __cpu_to_le32(32), 819 .nbytes_max = __cpu_to_le32(65535), 820 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 821 .reserved = __cpu_to_le32(0), 822 }, 823 824 /* CE9 host->target HTT */ 825 { 826 .pipenum = __cpu_to_le32(9), 827 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 828 .nentries = __cpu_to_le32(32), 829 .nbytes_max = __cpu_to_le32(2048), 830 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 831 .reserved = __cpu_to_le32(0), 832 }, 833 834 /* CE10 target->host HTT */ 835 { 836 .pipenum = __cpu_to_le32(10), 837 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 838 .nentries = __cpu_to_le32(0), 839 .nbytes_max = __cpu_to_le32(0), 840 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 841 .reserved = __cpu_to_le32(0), 842 }, 843 844 /* CE11 Not used */ 845 }; 846 847 /* Map from service/endpoint to Copy Engine. 848 * This table is derived from the CE_PCI TABLE, above. 849 * It is passed to the Target at startup for use by firmware. 850 */ 851 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq8074[] = { 852 { 853 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 854 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 855 .pipenum = __cpu_to_le32(3), 856 }, 857 { 858 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 859 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 860 .pipenum = __cpu_to_le32(2), 861 }, 862 { 863 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 864 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 865 .pipenum = __cpu_to_le32(3), 866 }, 867 { 868 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 869 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 870 .pipenum = __cpu_to_le32(2), 871 }, 872 { 873 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 874 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 875 .pipenum = __cpu_to_le32(3), 876 }, 877 { 878 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 879 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 880 .pipenum = __cpu_to_le32(2), 881 }, 882 { 883 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 884 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 885 .pipenum = __cpu_to_le32(3), 886 }, 887 { 888 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 889 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 890 .pipenum = __cpu_to_le32(2), 891 }, 892 { 893 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 894 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 895 .pipenum = __cpu_to_le32(3), 896 }, 897 { 898 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 899 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 900 .pipenum = __cpu_to_le32(2), 901 }, 902 { 903 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 904 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 905 .pipenum = __cpu_to_le32(7), 906 }, 907 { 908 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 909 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 910 .pipenum = __cpu_to_le32(2), 911 }, 912 { 913 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2), 914 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 915 .pipenum = __cpu_to_le32(9), 916 }, 917 { 918 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2), 919 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 920 .pipenum = __cpu_to_le32(2), 921 }, 922 { 923 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 924 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 925 .pipenum = __cpu_to_le32(0), 926 }, 927 { 928 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 929 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 930 .pipenum = __cpu_to_le32(1), 931 }, 932 { /* not used */ 933 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 934 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 935 .pipenum = __cpu_to_le32(0), 936 }, 937 { /* not used */ 938 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 939 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 940 .pipenum = __cpu_to_le32(1), 941 }, 942 { 943 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 944 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 945 .pipenum = __cpu_to_le32(4), 946 }, 947 { 948 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 949 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 950 .pipenum = __cpu_to_le32(1), 951 }, 952 { 953 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 954 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 955 .pipenum = __cpu_to_le32(5), 956 }, 957 958 /* (Additions here) */ 959 960 { /* terminator entry */ } 961 }; 962 963 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq6018[] = { 964 { 965 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 966 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 967 .pipenum = __cpu_to_le32(3), 968 }, 969 { 970 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 971 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 972 .pipenum = __cpu_to_le32(2), 973 }, 974 { 975 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 976 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 977 .pipenum = __cpu_to_le32(3), 978 }, 979 { 980 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 981 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 982 .pipenum = __cpu_to_le32(2), 983 }, 984 { 985 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 986 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 987 .pipenum = __cpu_to_le32(3), 988 }, 989 { 990 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 991 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 992 .pipenum = __cpu_to_le32(2), 993 }, 994 { 995 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 996 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 997 .pipenum = __cpu_to_le32(3), 998 }, 999 { 1000 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1001 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1002 .pipenum = __cpu_to_le32(2), 1003 }, 1004 { 1005 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1006 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1007 .pipenum = __cpu_to_le32(3), 1008 }, 1009 { 1010 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1011 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1012 .pipenum = __cpu_to_le32(2), 1013 }, 1014 { 1015 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1016 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1017 .pipenum = __cpu_to_le32(7), 1018 }, 1019 { 1020 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1021 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1022 .pipenum = __cpu_to_le32(2), 1023 }, 1024 { 1025 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1026 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1027 .pipenum = __cpu_to_le32(0), 1028 }, 1029 { 1030 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1031 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1032 .pipenum = __cpu_to_le32(1), 1033 }, 1034 { /* not used */ 1035 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1036 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1037 .pipenum = __cpu_to_le32(0), 1038 }, 1039 { /* not used */ 1040 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1041 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1042 .pipenum = __cpu_to_le32(1), 1043 }, 1044 { 1045 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1046 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1047 .pipenum = __cpu_to_le32(4), 1048 }, 1049 { 1050 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1051 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1052 .pipenum = __cpu_to_le32(1), 1053 }, 1054 { 1055 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 1056 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1057 .pipenum = __cpu_to_le32(5), 1058 }, 1059 1060 /* (Additions here) */ 1061 1062 { /* terminator entry */ } 1063 }; 1064 1065 /* Target firmware's Copy Engine configuration. */ 1066 const struct ce_pipe_config ath11k_target_ce_config_wlan_qca6390[] = { 1067 /* CE0: host->target HTC control and raw streams */ 1068 { 1069 .pipenum = __cpu_to_le32(0), 1070 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1071 .nentries = __cpu_to_le32(32), 1072 .nbytes_max = __cpu_to_le32(2048), 1073 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1074 .reserved = __cpu_to_le32(0), 1075 }, 1076 1077 /* CE1: target->host HTT + HTC control */ 1078 { 1079 .pipenum = __cpu_to_le32(1), 1080 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1081 .nentries = __cpu_to_le32(32), 1082 .nbytes_max = __cpu_to_le32(2048), 1083 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1084 .reserved = __cpu_to_le32(0), 1085 }, 1086 1087 /* CE2: target->host WMI */ 1088 { 1089 .pipenum = __cpu_to_le32(2), 1090 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1091 .nentries = __cpu_to_le32(32), 1092 .nbytes_max = __cpu_to_le32(2048), 1093 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1094 .reserved = __cpu_to_le32(0), 1095 }, 1096 1097 /* CE3: host->target WMI */ 1098 { 1099 .pipenum = __cpu_to_le32(3), 1100 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1101 .nentries = __cpu_to_le32(32), 1102 .nbytes_max = __cpu_to_le32(2048), 1103 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1104 .reserved = __cpu_to_le32(0), 1105 }, 1106 1107 /* CE4: host->target HTT */ 1108 { 1109 .pipenum = __cpu_to_le32(4), 1110 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1111 .nentries = __cpu_to_le32(256), 1112 .nbytes_max = __cpu_to_le32(256), 1113 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1114 .reserved = __cpu_to_le32(0), 1115 }, 1116 1117 /* CE5: target->host Pktlog */ 1118 { 1119 .pipenum = __cpu_to_le32(5), 1120 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1121 .nentries = __cpu_to_le32(32), 1122 .nbytes_max = __cpu_to_le32(2048), 1123 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1124 .reserved = __cpu_to_le32(0), 1125 }, 1126 1127 /* CE6: Reserved for target autonomous hif_memcpy */ 1128 { 1129 .pipenum = __cpu_to_le32(6), 1130 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1131 .nentries = __cpu_to_le32(32), 1132 .nbytes_max = __cpu_to_le32(16384), 1133 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1134 .reserved = __cpu_to_le32(0), 1135 }, 1136 1137 /* CE7 used only by Host */ 1138 { 1139 .pipenum = __cpu_to_le32(7), 1140 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 1141 .nentries = __cpu_to_le32(0), 1142 .nbytes_max = __cpu_to_le32(0), 1143 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1144 .reserved = __cpu_to_le32(0), 1145 }, 1146 1147 /* CE8 target->host used only by IPA */ 1148 { 1149 .pipenum = __cpu_to_le32(8), 1150 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1151 .nentries = __cpu_to_le32(32), 1152 .nbytes_max = __cpu_to_le32(16384), 1153 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1154 .reserved = __cpu_to_le32(0), 1155 }, 1156 /* CE 9, 10, 11 are used by MHI driver */ 1157 }; 1158 1159 /* Map from service/endpoint to Copy Engine. 1160 * This table is derived from the CE_PCI TABLE, above. 1161 * It is passed to the Target at startup for use by firmware. 1162 */ 1163 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qca6390[] = { 1164 { 1165 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1166 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1167 __cpu_to_le32(3), 1168 }, 1169 { 1170 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1171 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1172 __cpu_to_le32(2), 1173 }, 1174 { 1175 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1176 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1177 __cpu_to_le32(3), 1178 }, 1179 { 1180 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1181 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1182 __cpu_to_le32(2), 1183 }, 1184 { 1185 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1186 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1187 __cpu_to_le32(3), 1188 }, 1189 { 1190 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1191 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1192 __cpu_to_le32(2), 1193 }, 1194 { 1195 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1196 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1197 __cpu_to_le32(3), 1198 }, 1199 { 1200 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1201 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1202 __cpu_to_le32(2), 1203 }, 1204 { 1205 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1206 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1207 __cpu_to_le32(3), 1208 }, 1209 { 1210 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1211 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1212 __cpu_to_le32(2), 1213 }, 1214 { 1215 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1216 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1217 __cpu_to_le32(0), 1218 }, 1219 { 1220 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1221 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1222 __cpu_to_le32(2), 1223 }, 1224 { 1225 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1226 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1227 __cpu_to_le32(4), 1228 }, 1229 { 1230 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1231 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1232 __cpu_to_le32(1), 1233 }, 1234 1235 /* (Additions here) */ 1236 1237 { /* must be last */ 1238 __cpu_to_le32(0), 1239 __cpu_to_le32(0), 1240 __cpu_to_le32(0), 1241 }, 1242 }; 1243 1244 /* Target firmware's Copy Engine configuration. */ 1245 const struct ce_pipe_config ath11k_target_ce_config_wlan_qcn9074[] = { 1246 /* CE0: host->target HTC control and raw streams */ 1247 { 1248 .pipenum = __cpu_to_le32(0), 1249 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1250 .nentries = __cpu_to_le32(32), 1251 .nbytes_max = __cpu_to_le32(2048), 1252 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1253 .reserved = __cpu_to_le32(0), 1254 }, 1255 1256 /* CE1: target->host HTT + HTC control */ 1257 { 1258 .pipenum = __cpu_to_le32(1), 1259 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1260 .nentries = __cpu_to_le32(32), 1261 .nbytes_max = __cpu_to_le32(2048), 1262 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1263 .reserved = __cpu_to_le32(0), 1264 }, 1265 1266 /* CE2: target->host WMI */ 1267 { 1268 .pipenum = __cpu_to_le32(2), 1269 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1270 .nentries = __cpu_to_le32(32), 1271 .nbytes_max = __cpu_to_le32(2048), 1272 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1273 .reserved = __cpu_to_le32(0), 1274 }, 1275 1276 /* CE3: host->target WMI */ 1277 { 1278 .pipenum = __cpu_to_le32(3), 1279 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1280 .nentries = __cpu_to_le32(32), 1281 .nbytes_max = __cpu_to_le32(2048), 1282 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1283 .reserved = __cpu_to_le32(0), 1284 }, 1285 1286 /* CE4: host->target HTT */ 1287 { 1288 .pipenum = __cpu_to_le32(4), 1289 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1290 .nentries = __cpu_to_le32(256), 1291 .nbytes_max = __cpu_to_le32(256), 1292 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1293 .reserved = __cpu_to_le32(0), 1294 }, 1295 1296 /* CE5: target->host Pktlog */ 1297 { 1298 .pipenum = __cpu_to_le32(5), 1299 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1300 .nentries = __cpu_to_le32(32), 1301 .nbytes_max = __cpu_to_le32(2048), 1302 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1303 .reserved = __cpu_to_le32(0), 1304 }, 1305 1306 /* CE6: Reserved for target autonomous hif_memcpy */ 1307 { 1308 .pipenum = __cpu_to_le32(6), 1309 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1310 .nentries = __cpu_to_le32(32), 1311 .nbytes_max = __cpu_to_le32(16384), 1312 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1313 .reserved = __cpu_to_le32(0), 1314 }, 1315 1316 /* CE7 used only by Host */ 1317 { 1318 .pipenum = __cpu_to_le32(7), 1319 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 1320 .nentries = __cpu_to_le32(0), 1321 .nbytes_max = __cpu_to_le32(0), 1322 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1323 .reserved = __cpu_to_le32(0), 1324 }, 1325 1326 /* CE8 target->host used only by IPA */ 1327 { 1328 .pipenum = __cpu_to_le32(8), 1329 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1330 .nentries = __cpu_to_le32(32), 1331 .nbytes_max = __cpu_to_le32(16384), 1332 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1333 .reserved = __cpu_to_le32(0), 1334 }, 1335 /* CE 9, 10, 11 are used by MHI driver */ 1336 }; 1337 1338 /* Map from service/endpoint to Copy Engine. 1339 * This table is derived from the CE_PCI TABLE, above. 1340 * It is passed to the Target at startup for use by firmware. 1341 */ 1342 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qcn9074[] = { 1343 { 1344 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1345 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1346 __cpu_to_le32(3), 1347 }, 1348 { 1349 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1350 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1351 __cpu_to_le32(2), 1352 }, 1353 { 1354 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1355 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1356 __cpu_to_le32(3), 1357 }, 1358 { 1359 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1360 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1361 __cpu_to_le32(2), 1362 }, 1363 { 1364 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1365 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1366 __cpu_to_le32(3), 1367 }, 1368 { 1369 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1370 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1371 __cpu_to_le32(2), 1372 }, 1373 { 1374 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1375 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1376 __cpu_to_le32(3), 1377 }, 1378 { 1379 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1380 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1381 __cpu_to_le32(2), 1382 }, 1383 { 1384 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1385 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1386 __cpu_to_le32(3), 1387 }, 1388 { 1389 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1390 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1391 __cpu_to_le32(2), 1392 }, 1393 { 1394 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1395 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1396 __cpu_to_le32(0), 1397 }, 1398 { 1399 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1400 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1401 __cpu_to_le32(1), 1402 }, 1403 { 1404 __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1405 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1406 __cpu_to_le32(0), 1407 }, 1408 { 1409 __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1410 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1411 __cpu_to_le32(1), 1412 }, 1413 { 1414 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1415 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1416 __cpu_to_le32(4), 1417 }, 1418 { 1419 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1420 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1421 __cpu_to_le32(1), 1422 }, 1423 { 1424 __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 1425 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1426 __cpu_to_le32(5), 1427 }, 1428 1429 /* (Additions here) */ 1430 1431 { /* must be last */ 1432 __cpu_to_le32(0), 1433 __cpu_to_le32(0), 1434 __cpu_to_le32(0), 1435 }, 1436 }; 1437 1438 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qcn9074 = { 1439 .tx = { 1440 ATH11K_TX_RING_MASK_0, 1441 ATH11K_TX_RING_MASK_1, 1442 ATH11K_TX_RING_MASK_2, 1443 }, 1444 .rx_mon_status = { 1445 0, 0, 0, 1446 ATH11K_RX_MON_STATUS_RING_MASK_0, 1447 ATH11K_RX_MON_STATUS_RING_MASK_1, 1448 ATH11K_RX_MON_STATUS_RING_MASK_2, 1449 }, 1450 .rx = { 1451 0, 0, 0, 0, 1452 ATH11K_RX_RING_MASK_0, 1453 ATH11K_RX_RING_MASK_1, 1454 ATH11K_RX_RING_MASK_2, 1455 ATH11K_RX_RING_MASK_3, 1456 }, 1457 .rx_err = { 1458 0, 0, 0, 1459 ATH11K_RX_ERR_RING_MASK_0, 1460 }, 1461 .rx_wbm_rel = { 1462 0, 0, 0, 1463 ATH11K_RX_WBM_REL_RING_MASK_0, 1464 }, 1465 .reo_status = { 1466 0, 0, 0, 1467 ATH11K_REO_STATUS_RING_MASK_0, 1468 }, 1469 .rxdma2host = { 1470 0, 0, 0, 1471 ATH11K_RXDMA2HOST_RING_MASK_0, 1472 }, 1473 .host2rxdma = { 1474 0, 0, 0, 1475 ATH11K_HOST2RXDMA_RING_MASK_0, 1476 }, 1477 }; 1478 1479 const struct ath11k_hw_regs ipq8074_regs = { 1480 /* SW2TCL(x) R0 ring configuration address */ 1481 .hal_tcl1_ring_base_lsb = 0x00000510, 1482 .hal_tcl1_ring_base_msb = 0x00000514, 1483 .hal_tcl1_ring_id = 0x00000518, 1484 .hal_tcl1_ring_misc = 0x00000520, 1485 .hal_tcl1_ring_tp_addr_lsb = 0x0000052c, 1486 .hal_tcl1_ring_tp_addr_msb = 0x00000530, 1487 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000540, 1488 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000544, 1489 .hal_tcl1_ring_msi1_base_lsb = 0x00000558, 1490 .hal_tcl1_ring_msi1_base_msb = 0x0000055c, 1491 .hal_tcl1_ring_msi1_data = 0x00000560, 1492 .hal_tcl2_ring_base_lsb = 0x00000568, 1493 .hal_tcl_ring_base_lsb = 0x00000618, 1494 1495 /* TCL STATUS ring address */ 1496 .hal_tcl_status_ring_base_lsb = 0x00000720, 1497 1498 /* REO2SW(x) R0 ring configuration address */ 1499 .hal_reo1_ring_base_lsb = 0x0000029c, 1500 .hal_reo1_ring_base_msb = 0x000002a0, 1501 .hal_reo1_ring_id = 0x000002a4, 1502 .hal_reo1_ring_misc = 0x000002ac, 1503 .hal_reo1_ring_hp_addr_lsb = 0x000002b0, 1504 .hal_reo1_ring_hp_addr_msb = 0x000002b4, 1505 .hal_reo1_ring_producer_int_setup = 0x000002c0, 1506 .hal_reo1_ring_msi1_base_lsb = 0x000002e4, 1507 .hal_reo1_ring_msi1_base_msb = 0x000002e8, 1508 .hal_reo1_ring_msi1_data = 0x000002ec, 1509 .hal_reo2_ring_base_lsb = 0x000002f4, 1510 .hal_reo1_aging_thresh_ix_0 = 0x00000564, 1511 .hal_reo1_aging_thresh_ix_1 = 0x00000568, 1512 .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 1513 .hal_reo1_aging_thresh_ix_3 = 0x00000570, 1514 1515 /* REO2SW(x) R2 ring pointers (head/tail) address */ 1516 .hal_reo1_ring_hp = 0x00003038, 1517 .hal_reo1_ring_tp = 0x0000303c, 1518 .hal_reo2_ring_hp = 0x00003040, 1519 1520 /* REO2TCL R0 ring configuration address */ 1521 .hal_reo_tcl_ring_base_lsb = 0x000003fc, 1522 .hal_reo_tcl_ring_hp = 0x00003058, 1523 1524 /* REO status address */ 1525 .hal_reo_status_ring_base_lsb = 0x00000504, 1526 .hal_reo_status_hp = 0x00003070, 1527 1528 /* WCSS relative address */ 1529 .hal_seq_wcss_umac_ce0_src_reg = 0x00a00000, 1530 .hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000, 1531 .hal_seq_wcss_umac_ce1_src_reg = 0x00a02000, 1532 .hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000, 1533 1534 /* WBM Idle address */ 1535 .hal_wbm_idle_link_ring_base_lsb = 0x00000860, 1536 .hal_wbm_idle_link_ring_misc = 0x00000870, 1537 1538 /* SW2WBM release address */ 1539 .hal_wbm_release_ring_base_lsb = 0x000001d8, 1540 1541 /* WBM2SW release address */ 1542 .hal_wbm0_release_ring_base_lsb = 0x00000910, 1543 .hal_wbm1_release_ring_base_lsb = 0x00000968, 1544 1545 /* PCIe base address */ 1546 .pcie_qserdes_sysclk_en_sel = 0x0, 1547 .pcie_pcs_osc_dtct_config_base = 0x0, 1548 }; 1549 1550 const struct ath11k_hw_regs qca6390_regs = { 1551 /* SW2TCL(x) R0 ring configuration address */ 1552 .hal_tcl1_ring_base_lsb = 0x00000684, 1553 .hal_tcl1_ring_base_msb = 0x00000688, 1554 .hal_tcl1_ring_id = 0x0000068c, 1555 .hal_tcl1_ring_misc = 0x00000694, 1556 .hal_tcl1_ring_tp_addr_lsb = 0x000006a0, 1557 .hal_tcl1_ring_tp_addr_msb = 0x000006a4, 1558 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006b4, 1559 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006b8, 1560 .hal_tcl1_ring_msi1_base_lsb = 0x000006cc, 1561 .hal_tcl1_ring_msi1_base_msb = 0x000006d0, 1562 .hal_tcl1_ring_msi1_data = 0x000006d4, 1563 .hal_tcl2_ring_base_lsb = 0x000006dc, 1564 .hal_tcl_ring_base_lsb = 0x0000078c, 1565 1566 /* TCL STATUS ring address */ 1567 .hal_tcl_status_ring_base_lsb = 0x00000894, 1568 1569 /* REO2SW(x) R0 ring configuration address */ 1570 .hal_reo1_ring_base_lsb = 0x00000244, 1571 .hal_reo1_ring_base_msb = 0x00000248, 1572 .hal_reo1_ring_id = 0x0000024c, 1573 .hal_reo1_ring_misc = 0x00000254, 1574 .hal_reo1_ring_hp_addr_lsb = 0x00000258, 1575 .hal_reo1_ring_hp_addr_msb = 0x0000025c, 1576 .hal_reo1_ring_producer_int_setup = 0x00000268, 1577 .hal_reo1_ring_msi1_base_lsb = 0x0000028c, 1578 .hal_reo1_ring_msi1_base_msb = 0x00000290, 1579 .hal_reo1_ring_msi1_data = 0x00000294, 1580 .hal_reo2_ring_base_lsb = 0x0000029c, 1581 .hal_reo1_aging_thresh_ix_0 = 0x0000050c, 1582 .hal_reo1_aging_thresh_ix_1 = 0x00000510, 1583 .hal_reo1_aging_thresh_ix_2 = 0x00000514, 1584 .hal_reo1_aging_thresh_ix_3 = 0x00000518, 1585 1586 /* REO2SW(x) R2 ring pointers (head/tail) address */ 1587 .hal_reo1_ring_hp = 0x00003030, 1588 .hal_reo1_ring_tp = 0x00003034, 1589 .hal_reo2_ring_hp = 0x00003038, 1590 1591 /* REO2TCL R0 ring configuration address */ 1592 .hal_reo_tcl_ring_base_lsb = 0x000003a4, 1593 .hal_reo_tcl_ring_hp = 0x00003050, 1594 1595 /* REO status address */ 1596 .hal_reo_status_ring_base_lsb = 0x000004ac, 1597 .hal_reo_status_hp = 0x00003068, 1598 1599 /* WCSS relative address */ 1600 .hal_seq_wcss_umac_ce0_src_reg = 0x00a00000, 1601 .hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000, 1602 .hal_seq_wcss_umac_ce1_src_reg = 0x00a02000, 1603 .hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000, 1604 1605 /* WBM Idle address */ 1606 .hal_wbm_idle_link_ring_base_lsb = 0x00000860, 1607 .hal_wbm_idle_link_ring_misc = 0x00000870, 1608 1609 /* SW2WBM release address */ 1610 .hal_wbm_release_ring_base_lsb = 0x000001d8, 1611 1612 /* WBM2SW release address */ 1613 .hal_wbm0_release_ring_base_lsb = 0x00000910, 1614 .hal_wbm1_release_ring_base_lsb = 0x00000968, 1615 1616 /* PCIe base address */ 1617 .pcie_qserdes_sysclk_en_sel = 0x01e0c0ac, 1618 .pcie_pcs_osc_dtct_config_base = 0x01e0c628, 1619 }; 1620 1621 const struct ath11k_hw_regs qcn9074_regs = { 1622 /* SW2TCL(x) R0 ring configuration address */ 1623 .hal_tcl1_ring_base_lsb = 0x000004f0, 1624 .hal_tcl1_ring_base_msb = 0x000004f4, 1625 .hal_tcl1_ring_id = 0x000004f8, 1626 .hal_tcl1_ring_misc = 0x00000500, 1627 .hal_tcl1_ring_tp_addr_lsb = 0x0000050c, 1628 .hal_tcl1_ring_tp_addr_msb = 0x00000510, 1629 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000520, 1630 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000524, 1631 .hal_tcl1_ring_msi1_base_lsb = 0x00000538, 1632 .hal_tcl1_ring_msi1_base_msb = 0x0000053c, 1633 .hal_tcl1_ring_msi1_data = 0x00000540, 1634 .hal_tcl2_ring_base_lsb = 0x00000548, 1635 .hal_tcl_ring_base_lsb = 0x000005f8, 1636 1637 /* TCL STATUS ring address */ 1638 .hal_tcl_status_ring_base_lsb = 0x00000700, 1639 1640 /* REO2SW(x) R0 ring configuration address */ 1641 .hal_reo1_ring_base_lsb = 0x0000029c, 1642 .hal_reo1_ring_base_msb = 0x000002a0, 1643 .hal_reo1_ring_id = 0x000002a4, 1644 .hal_reo1_ring_misc = 0x000002ac, 1645 .hal_reo1_ring_hp_addr_lsb = 0x000002b0, 1646 .hal_reo1_ring_hp_addr_msb = 0x000002b4, 1647 .hal_reo1_ring_producer_int_setup = 0x000002c0, 1648 .hal_reo1_ring_msi1_base_lsb = 0x000002e4, 1649 .hal_reo1_ring_msi1_base_msb = 0x000002e8, 1650 .hal_reo1_ring_msi1_data = 0x000002ec, 1651 .hal_reo2_ring_base_lsb = 0x000002f4, 1652 .hal_reo1_aging_thresh_ix_0 = 0x00000564, 1653 .hal_reo1_aging_thresh_ix_1 = 0x00000568, 1654 .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 1655 .hal_reo1_aging_thresh_ix_3 = 0x00000570, 1656 1657 /* REO2SW(x) R2 ring pointers (head/tail) address */ 1658 .hal_reo1_ring_hp = 0x00003038, 1659 .hal_reo1_ring_tp = 0x0000303c, 1660 .hal_reo2_ring_hp = 0x00003040, 1661 1662 /* REO2TCL R0 ring configuration address */ 1663 .hal_reo_tcl_ring_base_lsb = 0x000003fc, 1664 .hal_reo_tcl_ring_hp = 0x00003058, 1665 1666 /* REO status address */ 1667 .hal_reo_status_ring_base_lsb = 0x00000504, 1668 .hal_reo_status_hp = 0x00003070, 1669 1670 /* WCSS relative address */ 1671 .hal_seq_wcss_umac_ce0_src_reg = 0x01b80000, 1672 .hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000, 1673 .hal_seq_wcss_umac_ce1_src_reg = 0x01b82000, 1674 .hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000, 1675 1676 /* WBM Idle address */ 1677 .hal_wbm_idle_link_ring_base_lsb = 0x00000874, 1678 .hal_wbm_idle_link_ring_misc = 0x00000884, 1679 1680 /* SW2WBM release address */ 1681 .hal_wbm_release_ring_base_lsb = 0x000001ec, 1682 1683 /* WBM2SW release address */ 1684 .hal_wbm0_release_ring_base_lsb = 0x00000924, 1685 .hal_wbm1_release_ring_base_lsb = 0x0000097c, 1686 1687 /* PCIe base address */ 1688 .pcie_qserdes_sysclk_en_sel = 0x01e0e0a8, 1689 .pcie_pcs_osc_dtct_config_base = 0x01e0f45c, 1690 }; 1691