1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/types.h> 7 #include <linux/bitops.h> 8 #include <linux/bitfield.h> 9 10 #include "core.h" 11 #include "ce.h" 12 #include "hif.h" 13 #include "hal.h" 14 #include "hw.h" 15 16 /* Map from pdev index to hw mac index */ 17 static u8 ath11k_hw_ipq8074_mac_from_pdev_id(int pdev_idx) 18 { 19 switch (pdev_idx) { 20 case 0: 21 return 0; 22 case 1: 23 return 2; 24 case 2: 25 return 1; 26 default: 27 return ATH11K_INVALID_HW_MAC_ID; 28 } 29 } 30 31 static u8 ath11k_hw_ipq6018_mac_from_pdev_id(int pdev_idx) 32 { 33 return pdev_idx; 34 } 35 36 static void ath11k_hw_ipq8074_tx_mesh_enable(struct ath11k_base *ab, 37 struct hal_tcl_data_cmd *tcl_cmd) 38 { 39 tcl_cmd->info2 |= FIELD_PREP(HAL_IPQ8074_TCL_DATA_CMD_INFO2_MESH_ENABLE, 40 true); 41 } 42 43 static void ath11k_hw_qcn9074_tx_mesh_enable(struct ath11k_base *ab, 44 struct hal_tcl_data_cmd *tcl_cmd) 45 { 46 tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE, 47 true); 48 } 49 50 static void ath11k_hw_wcn6855_tx_mesh_enable(struct ath11k_base *ab, 51 struct hal_tcl_data_cmd *tcl_cmd) 52 { 53 tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE, 54 true); 55 } 56 57 static void ath11k_init_wmi_config_qca6390(struct ath11k_base *ab, 58 struct target_resource_config *config) 59 { 60 config->num_vdevs = 4; 61 config->num_peers = 16; 62 config->num_tids = 32; 63 64 config->num_offload_peers = 3; 65 config->num_offload_reorder_buffs = 3; 66 config->num_peer_keys = TARGET_NUM_PEER_KEYS; 67 config->ast_skid_limit = TARGET_AST_SKID_LIMIT; 68 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 69 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 70 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; 71 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI; 72 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; 73 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; 74 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; 75 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS; 76 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV; 77 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV; 78 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES; 79 config->num_mcast_groups = 0; 80 config->num_mcast_table_elems = 0; 81 config->mcast2ucast_mode = 0; 82 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE; 83 config->num_wds_entries = 0; 84 config->dma_burst_size = 0; 85 config->rx_skip_defrag_timeout_dup_detection_check = 0; 86 config->vow_config = TARGET_VOW_CONFIG; 87 config->gtk_offload_max_vdev = 2; 88 config->num_msdu_desc = 0x400; 89 config->beacon_tx_offload_max_vdev = 2; 90 config->rx_batchmode = TARGET_RX_BATCHMODE; 91 92 config->peer_map_unmap_v2_support = 0; 93 config->use_pdev_id = 1; 94 config->max_frag_entries = 0xa; 95 config->num_tdls_vdevs = 0x1; 96 config->num_tdls_conn_table_entries = 8; 97 config->beacon_tx_offload_max_vdev = 0x2; 98 config->num_multicast_filter_entries = 0x20; 99 config->num_wow_filters = 0x16; 100 config->num_keep_alive_pattern = 0; 101 config->flag1 |= WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64; 102 } 103 104 static void ath11k_hw_ipq8074_reo_setup(struct ath11k_base *ab) 105 { 106 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; 107 u32 val; 108 /* Each hash entry uses three bits to map to a particular ring. */ 109 u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 | 110 HAL_HASH_ROUTING_RING_SW2 << 3 | 111 HAL_HASH_ROUTING_RING_SW3 << 6 | 112 HAL_HASH_ROUTING_RING_SW4 << 9 | 113 HAL_HASH_ROUTING_RING_SW1 << 12 | 114 HAL_HASH_ROUTING_RING_SW2 << 15 | 115 HAL_HASH_ROUTING_RING_SW3 << 18 | 116 HAL_HASH_ROUTING_RING_SW4 << 21; 117 118 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); 119 120 val &= ~HAL_REO1_GEN_ENABLE_FRAG_DST_RING; 121 val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_FRAG_DST_RING, 122 HAL_SRNG_RING_ID_REO2SW1) | 123 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) | 124 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1); 125 ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); 126 127 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab), 128 HAL_DEFAULT_REO_TIMEOUT_USEC); 129 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab), 130 HAL_DEFAULT_REO_TIMEOUT_USEC); 131 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab), 132 HAL_DEFAULT_REO_TIMEOUT_USEC); 133 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab), 134 HAL_DEFAULT_REO_TIMEOUT_USEC); 135 136 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_0, 137 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 138 ring_hash_map)); 139 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_1, 140 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 141 ring_hash_map)); 142 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, 143 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 144 ring_hash_map)); 145 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, 146 FIELD_PREP(HAL_REO_DEST_RING_CTRL_HASH_RING_MAP, 147 ring_hash_map)); 148 } 149 150 static void ath11k_init_wmi_config_ipq8074(struct ath11k_base *ab, 151 struct target_resource_config *config) 152 { 153 config->num_vdevs = ab->num_radios * TARGET_NUM_VDEVS(ab); 154 155 if (ab->num_radios == 2) { 156 config->num_peers = TARGET_NUM_PEERS(ab, DBS); 157 config->num_tids = TARGET_NUM_TIDS(ab, DBS); 158 } else if (ab->num_radios == 3) { 159 config->num_peers = TARGET_NUM_PEERS(ab, DBS_SBS); 160 config->num_tids = TARGET_NUM_TIDS(ab, DBS_SBS); 161 } else { 162 /* Control should not reach here */ 163 config->num_peers = TARGET_NUM_PEERS(ab, SINGLE); 164 config->num_tids = TARGET_NUM_TIDS(ab, SINGLE); 165 } 166 config->num_offload_peers = TARGET_NUM_OFFLD_PEERS; 167 config->num_offload_reorder_buffs = TARGET_NUM_OFFLD_REORDER_BUFFS; 168 config->num_peer_keys = TARGET_NUM_PEER_KEYS; 169 config->ast_skid_limit = TARGET_AST_SKID_LIMIT; 170 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 171 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 172 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; 173 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI; 174 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; 175 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; 176 177 if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) 178 config->rx_decap_mode = TARGET_DECAP_MODE_RAW; 179 else 180 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; 181 182 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS; 183 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV; 184 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV; 185 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES; 186 config->num_mcast_groups = TARGET_NUM_MCAST_GROUPS; 187 config->num_mcast_table_elems = TARGET_NUM_MCAST_TABLE_ELEMS; 188 config->mcast2ucast_mode = TARGET_MCAST2UCAST_MODE; 189 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE; 190 config->num_wds_entries = TARGET_NUM_WDS_ENTRIES; 191 config->dma_burst_size = TARGET_DMA_BURST_SIZE; 192 config->rx_skip_defrag_timeout_dup_detection_check = 193 TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK; 194 config->vow_config = TARGET_VOW_CONFIG; 195 config->gtk_offload_max_vdev = TARGET_GTK_OFFLOAD_MAX_VDEV; 196 config->num_msdu_desc = TARGET_NUM_MSDU_DESC; 197 config->beacon_tx_offload_max_vdev = ab->num_radios * TARGET_MAX_BCN_OFFLD; 198 config->rx_batchmode = TARGET_RX_BATCHMODE; 199 config->peer_map_unmap_v2_support = 1; 200 config->twt_ap_pdev_count = ab->num_radios; 201 config->twt_ap_sta_count = 1000; 202 config->flag1 |= WMI_RSRC_CFG_FLAG1_BSS_CHANNEL_INFO_64; 203 } 204 205 static int ath11k_hw_mac_id_to_pdev_id_ipq8074(struct ath11k_hw_params *hw, 206 int mac_id) 207 { 208 return mac_id; 209 } 210 211 static int ath11k_hw_mac_id_to_srng_id_ipq8074(struct ath11k_hw_params *hw, 212 int mac_id) 213 { 214 return 0; 215 } 216 217 static int ath11k_hw_mac_id_to_pdev_id_qca6390(struct ath11k_hw_params *hw, 218 int mac_id) 219 { 220 return 0; 221 } 222 223 static int ath11k_hw_mac_id_to_srng_id_qca6390(struct ath11k_hw_params *hw, 224 int mac_id) 225 { 226 return mac_id; 227 } 228 229 static bool ath11k_hw_ipq8074_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 230 { 231 return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU, 232 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 233 } 234 235 static bool ath11k_hw_ipq8074_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 236 { 237 return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU, 238 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 239 } 240 241 static u8 ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 242 { 243 return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING, 244 __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 245 } 246 247 static u8 *ath11k_hw_ipq8074_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 248 { 249 return desc->u.ipq8074.hdr_status; 250 } 251 252 static bool ath11k_hw_ipq8074_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 253 { 254 return __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1) & 255 RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID; 256 } 257 258 static u32 ath11k_hw_ipq8074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 259 { 260 return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE, 261 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2)); 262 } 263 264 static u8 ath11k_hw_ipq8074_rx_desc_get_decap_type(struct hal_rx_desc *desc) 265 { 266 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 267 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2)); 268 } 269 270 static u8 ath11k_hw_ipq8074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 271 { 272 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 273 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2)); 274 } 275 276 static bool ath11k_hw_ipq8074_rx_desc_get_ldpc_support(struct hal_rx_desc *desc) 277 { 278 return FIELD_GET(RX_MSDU_START_INFO2_LDPC, 279 __le32_to_cpu(desc->u.ipq8074.msdu_start.info2)); 280 } 281 282 static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 283 { 284 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID, 285 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 286 } 287 288 static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 289 { 290 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID, 291 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 292 } 293 294 static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 295 { 296 return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM, 297 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 298 } 299 300 static u16 ath11k_hw_ipq8074_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 301 { 302 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 303 __le32_to_cpu(desc->u.ipq8074.msdu_start.info1)); 304 } 305 306 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 307 { 308 return FIELD_GET(RX_MSDU_START_INFO3_SGI, 309 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 310 } 311 312 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 313 { 314 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 315 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 316 } 317 318 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 319 { 320 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 321 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 322 } 323 324 static u32 ath11k_hw_ipq8074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 325 { 326 return __le32_to_cpu(desc->u.ipq8074.msdu_start.phy_meta_data); 327 } 328 329 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 330 { 331 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 332 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 333 } 334 335 static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 336 { 337 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 338 __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 339 } 340 341 static u8 ath11k_hw_ipq8074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 342 { 343 return FIELD_GET(RX_MPDU_START_INFO2_TID, 344 __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2)); 345 } 346 347 static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 348 { 349 return __le16_to_cpu(desc->u.ipq8074.mpdu_start.sw_peer_id); 350 } 351 352 static void ath11k_hw_ipq8074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 353 struct hal_rx_desc *ldesc) 354 { 355 memcpy((u8 *)&fdesc->u.ipq8074.msdu_end, (u8 *)&ldesc->u.ipq8074.msdu_end, 356 sizeof(struct rx_msdu_end_ipq8074)); 357 memcpy((u8 *)&fdesc->u.ipq8074.attention, (u8 *)&ldesc->u.ipq8074.attention, 358 sizeof(struct rx_attention)); 359 memcpy((u8 *)&fdesc->u.ipq8074.mpdu_end, (u8 *)&ldesc->u.ipq8074.mpdu_end, 360 sizeof(struct rx_mpdu_end)); 361 } 362 363 static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 364 { 365 return FIELD_GET(HAL_TLV_HDR_TAG, 366 __le32_to_cpu(desc->u.ipq8074.mpdu_start_tag)); 367 } 368 369 static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 370 { 371 return __le16_to_cpu(desc->u.ipq8074.mpdu_start.phy_ppdu_id); 372 } 373 374 static void ath11k_hw_ipq8074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 375 { 376 u32 info = __le32_to_cpu(desc->u.ipq8074.msdu_start.info1); 377 378 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 379 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 380 381 desc->u.ipq8074.msdu_start.info1 = __cpu_to_le32(info); 382 } 383 384 static bool ath11k_hw_ipq8074_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc) 385 { 386 return __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1) & 387 RX_MPDU_START_INFO1_MAC_ADDR2_VALID; 388 } 389 390 static u8 *ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc) 391 { 392 return desc->u.ipq8074.mpdu_start.addr2; 393 } 394 395 static 396 struct rx_attention *ath11k_hw_ipq8074_rx_desc_get_attention(struct hal_rx_desc *desc) 397 { 398 return &desc->u.ipq8074.attention; 399 } 400 401 static u8 *ath11k_hw_ipq8074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 402 { 403 return &desc->u.ipq8074.msdu_payload[0]; 404 } 405 406 static bool ath11k_hw_qcn9074_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 407 { 408 return !!FIELD_GET(RX_MSDU_END_INFO4_FIRST_MSDU, 409 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 410 } 411 412 static bool ath11k_hw_qcn9074_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 413 { 414 return !!FIELD_GET(RX_MSDU_END_INFO4_LAST_MSDU, 415 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 416 } 417 418 static u8 ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 419 { 420 return FIELD_GET(RX_MSDU_END_INFO4_L3_HDR_PADDING, 421 __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 422 } 423 424 static u8 *ath11k_hw_qcn9074_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 425 { 426 return desc->u.qcn9074.hdr_status; 427 } 428 429 static bool ath11k_hw_qcn9074_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 430 { 431 return __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11) & 432 RX_MPDU_START_INFO11_ENCRYPT_INFO_VALID; 433 } 434 435 static u32 ath11k_hw_qcn9074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 436 { 437 return FIELD_GET(RX_MPDU_START_INFO9_ENC_TYPE, 438 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9)); 439 } 440 441 static u8 ath11k_hw_qcn9074_rx_desc_get_decap_type(struct hal_rx_desc *desc) 442 { 443 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 444 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2)); 445 } 446 447 static u8 ath11k_hw_qcn9074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 448 { 449 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 450 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2)); 451 } 452 453 static bool ath11k_hw_qcn9074_rx_desc_get_ldpc_support(struct hal_rx_desc *desc) 454 { 455 return FIELD_GET(RX_MSDU_START_INFO2_LDPC, 456 __le32_to_cpu(desc->u.qcn9074.msdu_start.info2)); 457 } 458 459 static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 460 { 461 return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_CTRL_VALID, 462 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 463 } 464 465 static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 466 { 467 return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_FCTRL_VALID, 468 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 469 } 470 471 static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 472 { 473 return FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_NUM, 474 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 475 } 476 477 static u16 ath11k_hw_qcn9074_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 478 { 479 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 480 __le32_to_cpu(desc->u.qcn9074.msdu_start.info1)); 481 } 482 483 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 484 { 485 return FIELD_GET(RX_MSDU_START_INFO3_SGI, 486 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 487 } 488 489 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 490 { 491 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 492 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 493 } 494 495 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 496 { 497 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 498 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 499 } 500 501 static u32 ath11k_hw_qcn9074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 502 { 503 return __le32_to_cpu(desc->u.qcn9074.msdu_start.phy_meta_data); 504 } 505 506 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 507 { 508 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 509 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 510 } 511 512 static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 513 { 514 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 515 __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 516 } 517 518 static u8 ath11k_hw_qcn9074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 519 { 520 return FIELD_GET(RX_MPDU_START_INFO9_TID, 521 __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9)); 522 } 523 524 static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 525 { 526 return __le16_to_cpu(desc->u.qcn9074.mpdu_start.sw_peer_id); 527 } 528 529 static void ath11k_hw_qcn9074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 530 struct hal_rx_desc *ldesc) 531 { 532 memcpy((u8 *)&fdesc->u.qcn9074.msdu_end, (u8 *)&ldesc->u.qcn9074.msdu_end, 533 sizeof(struct rx_msdu_end_qcn9074)); 534 memcpy((u8 *)&fdesc->u.qcn9074.attention, (u8 *)&ldesc->u.qcn9074.attention, 535 sizeof(struct rx_attention)); 536 memcpy((u8 *)&fdesc->u.qcn9074.mpdu_end, (u8 *)&ldesc->u.qcn9074.mpdu_end, 537 sizeof(struct rx_mpdu_end)); 538 } 539 540 static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 541 { 542 return FIELD_GET(HAL_TLV_HDR_TAG, 543 __le32_to_cpu(desc->u.qcn9074.mpdu_start_tag)); 544 } 545 546 static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 547 { 548 return __le16_to_cpu(desc->u.qcn9074.mpdu_start.phy_ppdu_id); 549 } 550 551 static void ath11k_hw_qcn9074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 552 { 553 u32 info = __le32_to_cpu(desc->u.qcn9074.msdu_start.info1); 554 555 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 556 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 557 558 desc->u.qcn9074.msdu_start.info1 = __cpu_to_le32(info); 559 } 560 561 static 562 struct rx_attention *ath11k_hw_qcn9074_rx_desc_get_attention(struct hal_rx_desc *desc) 563 { 564 return &desc->u.qcn9074.attention; 565 } 566 567 static u8 *ath11k_hw_qcn9074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 568 { 569 return &desc->u.qcn9074.msdu_payload[0]; 570 } 571 572 static bool ath11k_hw_ipq9074_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc) 573 { 574 return __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11) & 575 RX_MPDU_START_INFO11_MAC_ADDR2_VALID; 576 } 577 578 static u8 *ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc) 579 { 580 return desc->u.qcn9074.mpdu_start.addr2; 581 } 582 583 static bool ath11k_hw_wcn6855_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 584 { 585 return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU_WCN6855, 586 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2)); 587 } 588 589 static bool ath11k_hw_wcn6855_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 590 { 591 return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU_WCN6855, 592 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2)); 593 } 594 595 static u8 ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 596 { 597 return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING, 598 __le32_to_cpu(desc->u.wcn6855.msdu_end.info2)); 599 } 600 601 static u8 *ath11k_hw_wcn6855_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 602 { 603 return desc->u.wcn6855.hdr_status; 604 } 605 606 static bool ath11k_hw_wcn6855_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 607 { 608 return __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1) & 609 RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID; 610 } 611 612 static u32 ath11k_hw_wcn6855_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 613 { 614 return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE, 615 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info2)); 616 } 617 618 static u8 ath11k_hw_wcn6855_rx_desc_get_decap_type(struct hal_rx_desc *desc) 619 { 620 return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 621 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2)); 622 } 623 624 static u8 ath11k_hw_wcn6855_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 625 { 626 return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 627 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2)); 628 } 629 630 static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 631 { 632 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID, 633 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1)); 634 } 635 636 static bool ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 637 { 638 return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID, 639 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1)); 640 } 641 642 static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 643 { 644 return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM, 645 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1)); 646 } 647 648 static u16 ath11k_hw_wcn6855_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 649 { 650 return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 651 __le32_to_cpu(desc->u.wcn6855.msdu_start.info1)); 652 } 653 654 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 655 { 656 return FIELD_GET(RX_MSDU_START_INFO3_SGI, 657 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 658 } 659 660 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 661 { 662 return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 663 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 664 } 665 666 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 667 { 668 return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 669 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 670 } 671 672 static u32 ath11k_hw_wcn6855_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 673 { 674 return __le32_to_cpu(desc->u.wcn6855.msdu_start.phy_meta_data); 675 } 676 677 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 678 { 679 return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 680 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 681 } 682 683 static u8 ath11k_hw_wcn6855_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 684 { 685 return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 686 __le32_to_cpu(desc->u.wcn6855.msdu_start.info3)); 687 } 688 689 static u8 ath11k_hw_wcn6855_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 690 { 691 return FIELD_GET(RX_MPDU_START_INFO2_TID_WCN6855, 692 __le32_to_cpu(desc->u.wcn6855.mpdu_start.info2)); 693 } 694 695 static u16 ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 696 { 697 return __le16_to_cpu(desc->u.wcn6855.mpdu_start.sw_peer_id); 698 } 699 700 static void ath11k_hw_wcn6855_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 701 struct hal_rx_desc *ldesc) 702 { 703 memcpy((u8 *)&fdesc->u.wcn6855.msdu_end, (u8 *)&ldesc->u.wcn6855.msdu_end, 704 sizeof(struct rx_msdu_end_wcn6855)); 705 memcpy((u8 *)&fdesc->u.wcn6855.attention, (u8 *)&ldesc->u.wcn6855.attention, 706 sizeof(struct rx_attention)); 707 memcpy((u8 *)&fdesc->u.wcn6855.mpdu_end, (u8 *)&ldesc->u.wcn6855.mpdu_end, 708 sizeof(struct rx_mpdu_end)); 709 } 710 711 static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 712 { 713 return FIELD_GET(HAL_TLV_HDR_TAG, 714 __le32_to_cpu(desc->u.wcn6855.mpdu_start_tag)); 715 } 716 717 static u32 ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 718 { 719 return __le16_to_cpu(desc->u.wcn6855.mpdu_start.phy_ppdu_id); 720 } 721 722 static void ath11k_hw_wcn6855_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 723 { 724 u32 info = __le32_to_cpu(desc->u.wcn6855.msdu_start.info1); 725 726 info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 727 info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 728 729 desc->u.wcn6855.msdu_start.info1 = __cpu_to_le32(info); 730 } 731 732 static 733 struct rx_attention *ath11k_hw_wcn6855_rx_desc_get_attention(struct hal_rx_desc *desc) 734 { 735 return &desc->u.wcn6855.attention; 736 } 737 738 static u8 *ath11k_hw_wcn6855_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 739 { 740 return &desc->u.wcn6855.msdu_payload[0]; 741 } 742 743 static bool ath11k_hw_wcn6855_rx_desc_mac_addr2_valid(struct hal_rx_desc *desc) 744 { 745 return __le32_to_cpu(desc->u.wcn6855.mpdu_start.info1) & 746 RX_MPDU_START_INFO1_MAC_ADDR2_VALID; 747 } 748 749 static u8 *ath11k_hw_wcn6855_rx_desc_mpdu_start_addr2(struct hal_rx_desc *desc) 750 { 751 return desc->u.wcn6855.mpdu_start.addr2; 752 } 753 754 static void ath11k_hw_wcn6855_reo_setup(struct ath11k_base *ab) 755 { 756 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; 757 u32 val; 758 /* Each hash entry uses four bits to map to a particular ring. */ 759 u32 ring_hash_map = HAL_HASH_ROUTING_RING_SW1 << 0 | 760 HAL_HASH_ROUTING_RING_SW2 << 4 | 761 HAL_HASH_ROUTING_RING_SW3 << 8 | 762 HAL_HASH_ROUTING_RING_SW4 << 12 | 763 HAL_HASH_ROUTING_RING_SW1 << 16 | 764 HAL_HASH_ROUTING_RING_SW2 << 20 | 765 HAL_HASH_ROUTING_RING_SW3 << 24 | 766 HAL_HASH_ROUTING_RING_SW4 << 28; 767 768 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); 769 val |= FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE, 1) | 770 FIELD_PREP(HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE, 1); 771 ath11k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); 772 773 val = ath11k_hif_read32(ab, reo_base + HAL_REO1_MISC_CTL); 774 val &= ~HAL_REO1_MISC_CTL_FRAGMENT_DST_RING; 775 val |= FIELD_PREP(HAL_REO1_MISC_CTL_FRAGMENT_DST_RING, HAL_SRNG_RING_ID_REO2SW1); 776 ath11k_hif_write32(ab, reo_base + HAL_REO1_MISC_CTL, val); 777 778 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab), 779 HAL_DEFAULT_REO_TIMEOUT_USEC); 780 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab), 781 HAL_DEFAULT_REO_TIMEOUT_USEC); 782 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab), 783 HAL_DEFAULT_REO_TIMEOUT_USEC); 784 ath11k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab), 785 HAL_DEFAULT_REO_TIMEOUT_USEC); 786 787 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, 788 ring_hash_map); 789 ath11k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, 790 ring_hash_map); 791 } 792 793 static u16 ath11k_hw_ipq8074_mpdu_info_get_peerid(u8 *tlv_data) 794 { 795 u16 peer_id = 0; 796 struct hal_rx_mpdu_info *mpdu_info = 797 (struct hal_rx_mpdu_info *)tlv_data; 798 799 peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID, 800 __le32_to_cpu(mpdu_info->info0)); 801 802 return peer_id; 803 } 804 805 static u16 ath11k_hw_wcn6855_mpdu_info_get_peerid(u8 *tlv_data) 806 { 807 u16 peer_id = 0; 808 struct hal_rx_mpdu_info_wcn6855 *mpdu_info = 809 (struct hal_rx_mpdu_info_wcn6855 *)tlv_data; 810 811 peer_id = FIELD_GET(HAL_RX_MPDU_INFO_INFO0_PEERID_WCN6855, 812 __le32_to_cpu(mpdu_info->info0)); 813 return peer_id; 814 } 815 816 static bool ath11k_hw_wcn6855_rx_desc_get_ldpc_support(struct hal_rx_desc *desc) 817 { 818 return FIELD_GET(RX_MSDU_START_INFO2_LDPC, 819 __le32_to_cpu(desc->u.wcn6855.msdu_start.info2)); 820 } 821 822 const struct ath11k_hw_ops ipq8074_ops = { 823 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 824 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 825 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 826 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 827 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 828 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 829 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 830 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 831 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 832 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 833 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 834 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 835 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 836 .rx_desc_get_ldpc_support = ath11k_hw_ipq8074_rx_desc_get_ldpc_support, 837 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 838 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 839 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 840 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 841 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 842 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 843 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 844 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 845 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 846 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 847 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 848 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 849 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 850 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 851 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 852 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 853 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 854 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 855 .reo_setup = ath11k_hw_ipq8074_reo_setup, 856 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 857 .rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid, 858 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2, 859 }; 860 861 const struct ath11k_hw_ops ipq6018_ops = { 862 .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 863 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 864 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 865 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 866 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 867 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 868 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 869 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 870 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 871 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 872 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 873 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 874 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 875 .rx_desc_get_ldpc_support = ath11k_hw_ipq8074_rx_desc_get_ldpc_support, 876 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 877 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 878 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 879 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 880 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 881 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 882 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 883 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 884 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 885 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 886 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 887 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 888 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 889 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 890 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 891 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 892 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 893 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 894 .reo_setup = ath11k_hw_ipq8074_reo_setup, 895 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 896 .rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid, 897 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2, 898 }; 899 900 const struct ath11k_hw_ops qca6390_ops = { 901 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 902 .wmi_init_config = ath11k_init_wmi_config_qca6390, 903 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390, 904 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390, 905 .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 906 .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 907 .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 908 .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 909 .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 910 .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 911 .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 912 .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 913 .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 914 .rx_desc_get_ldpc_support = ath11k_hw_ipq8074_rx_desc_get_ldpc_support, 915 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 916 .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 917 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 918 .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 919 .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 920 .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 921 .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 922 .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 923 .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 924 .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 925 .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 926 .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 927 .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 928 .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 929 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 930 .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 931 .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 932 .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 933 .reo_setup = ath11k_hw_ipq8074_reo_setup, 934 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 935 .rx_desc_mac_addr2_valid = ath11k_hw_ipq8074_rx_desc_mac_addr2_valid, 936 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq8074_rx_desc_mpdu_start_addr2, 937 }; 938 939 const struct ath11k_hw_ops qcn9074_ops = { 940 .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 941 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 942 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 943 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 944 .tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable, 945 .rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu, 946 .rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu, 947 .rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes, 948 .rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status, 949 .rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid, 950 .rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type, 951 .rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type, 952 .rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl, 953 .rx_desc_get_ldpc_support = ath11k_hw_qcn9074_rx_desc_get_ldpc_support, 954 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld, 955 .rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid, 956 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no, 957 .rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len, 958 .rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi, 959 .rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs, 960 .rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw, 961 .rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq, 962 .rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type, 963 .rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss, 964 .rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid, 965 .rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id, 966 .rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end, 967 .rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag, 968 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id, 969 .rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len, 970 .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention, 971 .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload, 972 .reo_setup = ath11k_hw_ipq8074_reo_setup, 973 .mpdu_info_get_peerid = ath11k_hw_ipq8074_mpdu_info_get_peerid, 974 .rx_desc_mac_addr2_valid = ath11k_hw_ipq9074_rx_desc_mac_addr2_valid, 975 .rx_desc_mpdu_start_addr2 = ath11k_hw_ipq9074_rx_desc_mpdu_start_addr2, 976 }; 977 978 const struct ath11k_hw_ops wcn6855_ops = { 979 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 980 .wmi_init_config = ath11k_init_wmi_config_qca6390, 981 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390, 982 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390, 983 .tx_mesh_enable = ath11k_hw_wcn6855_tx_mesh_enable, 984 .rx_desc_get_first_msdu = ath11k_hw_wcn6855_rx_desc_get_first_msdu, 985 .rx_desc_get_last_msdu = ath11k_hw_wcn6855_rx_desc_get_last_msdu, 986 .rx_desc_get_l3_pad_bytes = ath11k_hw_wcn6855_rx_desc_get_l3_pad_bytes, 987 .rx_desc_get_hdr_status = ath11k_hw_wcn6855_rx_desc_get_hdr_status, 988 .rx_desc_encrypt_valid = ath11k_hw_wcn6855_rx_desc_encrypt_valid, 989 .rx_desc_get_encrypt_type = ath11k_hw_wcn6855_rx_desc_get_encrypt_type, 990 .rx_desc_get_decap_type = ath11k_hw_wcn6855_rx_desc_get_decap_type, 991 .rx_desc_get_mesh_ctl = ath11k_hw_wcn6855_rx_desc_get_mesh_ctl, 992 .rx_desc_get_ldpc_support = ath11k_hw_wcn6855_rx_desc_get_ldpc_support, 993 .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_wcn6855_rx_desc_get_mpdu_seq_ctl_vld, 994 .rx_desc_get_mpdu_fc_valid = ath11k_hw_wcn6855_rx_desc_get_mpdu_fc_valid, 995 .rx_desc_get_mpdu_start_seq_no = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_seq_no, 996 .rx_desc_get_msdu_len = ath11k_hw_wcn6855_rx_desc_get_msdu_len, 997 .rx_desc_get_msdu_sgi = ath11k_hw_wcn6855_rx_desc_get_msdu_sgi, 998 .rx_desc_get_msdu_rate_mcs = ath11k_hw_wcn6855_rx_desc_get_msdu_rate_mcs, 999 .rx_desc_get_msdu_rx_bw = ath11k_hw_wcn6855_rx_desc_get_msdu_rx_bw, 1000 .rx_desc_get_msdu_freq = ath11k_hw_wcn6855_rx_desc_get_msdu_freq, 1001 .rx_desc_get_msdu_pkt_type = ath11k_hw_wcn6855_rx_desc_get_msdu_pkt_type, 1002 .rx_desc_get_msdu_nss = ath11k_hw_wcn6855_rx_desc_get_msdu_nss, 1003 .rx_desc_get_mpdu_tid = ath11k_hw_wcn6855_rx_desc_get_mpdu_tid, 1004 .rx_desc_get_mpdu_peer_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_peer_id, 1005 .rx_desc_copy_attn_end_tlv = ath11k_hw_wcn6855_rx_desc_copy_attn_end, 1006 .rx_desc_get_mpdu_start_tag = ath11k_hw_wcn6855_rx_desc_get_mpdu_start_tag, 1007 .rx_desc_get_mpdu_ppdu_id = ath11k_hw_wcn6855_rx_desc_get_mpdu_ppdu_id, 1008 .rx_desc_set_msdu_len = ath11k_hw_wcn6855_rx_desc_set_msdu_len, 1009 .rx_desc_get_attention = ath11k_hw_wcn6855_rx_desc_get_attention, 1010 .rx_desc_get_msdu_payload = ath11k_hw_wcn6855_rx_desc_get_msdu_payload, 1011 .reo_setup = ath11k_hw_wcn6855_reo_setup, 1012 .mpdu_info_get_peerid = ath11k_hw_wcn6855_mpdu_info_get_peerid, 1013 .rx_desc_mac_addr2_valid = ath11k_hw_wcn6855_rx_desc_mac_addr2_valid, 1014 .rx_desc_mpdu_start_addr2 = ath11k_hw_wcn6855_rx_desc_mpdu_start_addr2, 1015 }; 1016 1017 #define ATH11K_TX_RING_MASK_0 0x1 1018 #define ATH11K_TX_RING_MASK_1 0x2 1019 #define ATH11K_TX_RING_MASK_2 0x4 1020 1021 #define ATH11K_RX_RING_MASK_0 0x1 1022 #define ATH11K_RX_RING_MASK_1 0x2 1023 #define ATH11K_RX_RING_MASK_2 0x4 1024 #define ATH11K_RX_RING_MASK_3 0x8 1025 1026 #define ATH11K_RX_ERR_RING_MASK_0 0x1 1027 1028 #define ATH11K_RX_WBM_REL_RING_MASK_0 0x1 1029 1030 #define ATH11K_REO_STATUS_RING_MASK_0 0x1 1031 1032 #define ATH11K_RXDMA2HOST_RING_MASK_0 0x1 1033 #define ATH11K_RXDMA2HOST_RING_MASK_1 0x2 1034 #define ATH11K_RXDMA2HOST_RING_MASK_2 0x4 1035 1036 #define ATH11K_HOST2RXDMA_RING_MASK_0 0x1 1037 #define ATH11K_HOST2RXDMA_RING_MASK_1 0x2 1038 #define ATH11K_HOST2RXDMA_RING_MASK_2 0x4 1039 1040 #define ATH11K_RX_MON_STATUS_RING_MASK_0 0x1 1041 #define ATH11K_RX_MON_STATUS_RING_MASK_1 0x2 1042 #define ATH11K_RX_MON_STATUS_RING_MASK_2 0x4 1043 1044 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074 = { 1045 .tx = { 1046 ATH11K_TX_RING_MASK_0, 1047 ATH11K_TX_RING_MASK_1, 1048 ATH11K_TX_RING_MASK_2, 1049 }, 1050 .rx_mon_status = { 1051 0, 0, 0, 0, 1052 ATH11K_RX_MON_STATUS_RING_MASK_0, 1053 ATH11K_RX_MON_STATUS_RING_MASK_1, 1054 ATH11K_RX_MON_STATUS_RING_MASK_2, 1055 }, 1056 .rx = { 1057 0, 0, 0, 0, 0, 0, 0, 1058 ATH11K_RX_RING_MASK_0, 1059 ATH11K_RX_RING_MASK_1, 1060 ATH11K_RX_RING_MASK_2, 1061 ATH11K_RX_RING_MASK_3, 1062 }, 1063 .rx_err = { 1064 ATH11K_RX_ERR_RING_MASK_0, 1065 }, 1066 .rx_wbm_rel = { 1067 ATH11K_RX_WBM_REL_RING_MASK_0, 1068 }, 1069 .reo_status = { 1070 ATH11K_REO_STATUS_RING_MASK_0, 1071 }, 1072 .rxdma2host = { 1073 ATH11K_RXDMA2HOST_RING_MASK_0, 1074 ATH11K_RXDMA2HOST_RING_MASK_1, 1075 ATH11K_RXDMA2HOST_RING_MASK_2, 1076 }, 1077 .host2rxdma = { 1078 ATH11K_HOST2RXDMA_RING_MASK_0, 1079 ATH11K_HOST2RXDMA_RING_MASK_1, 1080 ATH11K_HOST2RXDMA_RING_MASK_2, 1081 }, 1082 }; 1083 1084 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390 = { 1085 .tx = { 1086 ATH11K_TX_RING_MASK_0, 1087 }, 1088 .rx_mon_status = { 1089 0, 0, 0, 0, 1090 ATH11K_RX_MON_STATUS_RING_MASK_0, 1091 ATH11K_RX_MON_STATUS_RING_MASK_1, 1092 ATH11K_RX_MON_STATUS_RING_MASK_2, 1093 }, 1094 .rx = { 1095 0, 0, 0, 0, 0, 0, 0, 1096 ATH11K_RX_RING_MASK_0, 1097 ATH11K_RX_RING_MASK_1, 1098 ATH11K_RX_RING_MASK_2, 1099 ATH11K_RX_RING_MASK_3, 1100 }, 1101 .rx_err = { 1102 ATH11K_RX_ERR_RING_MASK_0, 1103 }, 1104 .rx_wbm_rel = { 1105 ATH11K_RX_WBM_REL_RING_MASK_0, 1106 }, 1107 .reo_status = { 1108 ATH11K_REO_STATUS_RING_MASK_0, 1109 }, 1110 .rxdma2host = { 1111 ATH11K_RXDMA2HOST_RING_MASK_0, 1112 ATH11K_RXDMA2HOST_RING_MASK_1, 1113 ATH11K_RXDMA2HOST_RING_MASK_2, 1114 }, 1115 .host2rxdma = { 1116 }, 1117 }; 1118 1119 /* Target firmware's Copy Engine configuration. */ 1120 const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq8074[] = { 1121 /* CE0: host->target HTC control and raw streams */ 1122 { 1123 .pipenum = __cpu_to_le32(0), 1124 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1125 .nentries = __cpu_to_le32(32), 1126 .nbytes_max = __cpu_to_le32(2048), 1127 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1128 .reserved = __cpu_to_le32(0), 1129 }, 1130 1131 /* CE1: target->host HTT + HTC control */ 1132 { 1133 .pipenum = __cpu_to_le32(1), 1134 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1135 .nentries = __cpu_to_le32(32), 1136 .nbytes_max = __cpu_to_le32(2048), 1137 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1138 .reserved = __cpu_to_le32(0), 1139 }, 1140 1141 /* CE2: target->host WMI */ 1142 { 1143 .pipenum = __cpu_to_le32(2), 1144 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1145 .nentries = __cpu_to_le32(32), 1146 .nbytes_max = __cpu_to_le32(2048), 1147 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1148 .reserved = __cpu_to_le32(0), 1149 }, 1150 1151 /* CE3: host->target WMI */ 1152 { 1153 .pipenum = __cpu_to_le32(3), 1154 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1155 .nentries = __cpu_to_le32(32), 1156 .nbytes_max = __cpu_to_le32(2048), 1157 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1158 .reserved = __cpu_to_le32(0), 1159 }, 1160 1161 /* CE4: host->target HTT */ 1162 { 1163 .pipenum = __cpu_to_le32(4), 1164 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1165 .nentries = __cpu_to_le32(256), 1166 .nbytes_max = __cpu_to_le32(256), 1167 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1168 .reserved = __cpu_to_le32(0), 1169 }, 1170 1171 /* CE5: target->host Pktlog */ 1172 { 1173 .pipenum = __cpu_to_le32(5), 1174 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1175 .nentries = __cpu_to_le32(32), 1176 .nbytes_max = __cpu_to_le32(2048), 1177 .flags = __cpu_to_le32(0), 1178 .reserved = __cpu_to_le32(0), 1179 }, 1180 1181 /* CE6: Reserved for target autonomous hif_memcpy */ 1182 { 1183 .pipenum = __cpu_to_le32(6), 1184 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1185 .nentries = __cpu_to_le32(32), 1186 .nbytes_max = __cpu_to_le32(65535), 1187 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1188 .reserved = __cpu_to_le32(0), 1189 }, 1190 1191 /* CE7 used only by Host */ 1192 { 1193 .pipenum = __cpu_to_le32(7), 1194 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1195 .nentries = __cpu_to_le32(32), 1196 .nbytes_max = __cpu_to_le32(2048), 1197 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1198 .reserved = __cpu_to_le32(0), 1199 }, 1200 1201 /* CE8 target->host used only by IPA */ 1202 { 1203 .pipenum = __cpu_to_le32(8), 1204 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1205 .nentries = __cpu_to_le32(32), 1206 .nbytes_max = __cpu_to_le32(65535), 1207 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1208 .reserved = __cpu_to_le32(0), 1209 }, 1210 1211 /* CE9 host->target HTT */ 1212 { 1213 .pipenum = __cpu_to_le32(9), 1214 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1215 .nentries = __cpu_to_le32(32), 1216 .nbytes_max = __cpu_to_le32(2048), 1217 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1218 .reserved = __cpu_to_le32(0), 1219 }, 1220 1221 /* CE10 target->host HTT */ 1222 { 1223 .pipenum = __cpu_to_le32(10), 1224 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 1225 .nentries = __cpu_to_le32(0), 1226 .nbytes_max = __cpu_to_le32(0), 1227 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1228 .reserved = __cpu_to_le32(0), 1229 }, 1230 1231 /* CE11 Not used */ 1232 }; 1233 1234 /* Map from service/endpoint to Copy Engine. 1235 * This table is derived from the CE_PCI TABLE, above. 1236 * It is passed to the Target at startup for use by firmware. 1237 */ 1238 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq8074[] = { 1239 { 1240 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1241 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1242 .pipenum = __cpu_to_le32(3), 1243 }, 1244 { 1245 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1246 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1247 .pipenum = __cpu_to_le32(2), 1248 }, 1249 { 1250 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1251 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1252 .pipenum = __cpu_to_le32(3), 1253 }, 1254 { 1255 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1256 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1257 .pipenum = __cpu_to_le32(2), 1258 }, 1259 { 1260 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1261 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1262 .pipenum = __cpu_to_le32(3), 1263 }, 1264 { 1265 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1266 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1267 .pipenum = __cpu_to_le32(2), 1268 }, 1269 { 1270 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1271 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1272 .pipenum = __cpu_to_le32(3), 1273 }, 1274 { 1275 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1276 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1277 .pipenum = __cpu_to_le32(2), 1278 }, 1279 { 1280 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1281 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1282 .pipenum = __cpu_to_le32(3), 1283 }, 1284 { 1285 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1286 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1287 .pipenum = __cpu_to_le32(2), 1288 }, 1289 { 1290 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1291 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1292 .pipenum = __cpu_to_le32(7), 1293 }, 1294 { 1295 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1296 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1297 .pipenum = __cpu_to_le32(2), 1298 }, 1299 { 1300 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2), 1301 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1302 .pipenum = __cpu_to_le32(9), 1303 }, 1304 { 1305 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2), 1306 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1307 .pipenum = __cpu_to_le32(2), 1308 }, 1309 { 1310 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1311 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1312 .pipenum = __cpu_to_le32(0), 1313 }, 1314 { 1315 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1316 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1317 .pipenum = __cpu_to_le32(1), 1318 }, 1319 { /* not used */ 1320 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1321 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1322 .pipenum = __cpu_to_le32(0), 1323 }, 1324 { /* not used */ 1325 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1326 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1327 .pipenum = __cpu_to_le32(1), 1328 }, 1329 { 1330 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1331 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1332 .pipenum = __cpu_to_le32(4), 1333 }, 1334 { 1335 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1336 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1337 .pipenum = __cpu_to_le32(1), 1338 }, 1339 { 1340 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 1341 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1342 .pipenum = __cpu_to_le32(5), 1343 }, 1344 1345 /* (Additions here) */ 1346 1347 { /* terminator entry */ } 1348 }; 1349 1350 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq6018[] = { 1351 { 1352 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1353 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1354 .pipenum = __cpu_to_le32(3), 1355 }, 1356 { 1357 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1358 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1359 .pipenum = __cpu_to_le32(2), 1360 }, 1361 { 1362 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1363 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1364 .pipenum = __cpu_to_le32(3), 1365 }, 1366 { 1367 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1368 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1369 .pipenum = __cpu_to_le32(2), 1370 }, 1371 { 1372 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1373 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1374 .pipenum = __cpu_to_le32(3), 1375 }, 1376 { 1377 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1378 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1379 .pipenum = __cpu_to_le32(2), 1380 }, 1381 { 1382 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1383 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1384 .pipenum = __cpu_to_le32(3), 1385 }, 1386 { 1387 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1388 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1389 .pipenum = __cpu_to_le32(2), 1390 }, 1391 { 1392 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1393 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1394 .pipenum = __cpu_to_le32(3), 1395 }, 1396 { 1397 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1398 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1399 .pipenum = __cpu_to_le32(2), 1400 }, 1401 { 1402 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1403 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1404 .pipenum = __cpu_to_le32(7), 1405 }, 1406 { 1407 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1408 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1409 .pipenum = __cpu_to_le32(2), 1410 }, 1411 { 1412 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1413 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1414 .pipenum = __cpu_to_le32(0), 1415 }, 1416 { 1417 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1418 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1419 .pipenum = __cpu_to_le32(1), 1420 }, 1421 { /* not used */ 1422 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1423 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1424 .pipenum = __cpu_to_le32(0), 1425 }, 1426 { /* not used */ 1427 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1428 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1429 .pipenum = __cpu_to_le32(1), 1430 }, 1431 { 1432 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1433 .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1434 .pipenum = __cpu_to_le32(4), 1435 }, 1436 { 1437 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1438 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1439 .pipenum = __cpu_to_le32(1), 1440 }, 1441 { 1442 .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 1443 .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1444 .pipenum = __cpu_to_le32(5), 1445 }, 1446 1447 /* (Additions here) */ 1448 1449 { /* terminator entry */ } 1450 }; 1451 1452 /* Target firmware's Copy Engine configuration. */ 1453 const struct ce_pipe_config ath11k_target_ce_config_wlan_qca6390[] = { 1454 /* CE0: host->target HTC control and raw streams */ 1455 { 1456 .pipenum = __cpu_to_le32(0), 1457 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1458 .nentries = __cpu_to_le32(32), 1459 .nbytes_max = __cpu_to_le32(2048), 1460 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1461 .reserved = __cpu_to_le32(0), 1462 }, 1463 1464 /* CE1: target->host HTT + HTC control */ 1465 { 1466 .pipenum = __cpu_to_le32(1), 1467 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1468 .nentries = __cpu_to_le32(32), 1469 .nbytes_max = __cpu_to_le32(2048), 1470 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1471 .reserved = __cpu_to_le32(0), 1472 }, 1473 1474 /* CE2: target->host WMI */ 1475 { 1476 .pipenum = __cpu_to_le32(2), 1477 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1478 .nentries = __cpu_to_le32(32), 1479 .nbytes_max = __cpu_to_le32(2048), 1480 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1481 .reserved = __cpu_to_le32(0), 1482 }, 1483 1484 /* CE3: host->target WMI */ 1485 { 1486 .pipenum = __cpu_to_le32(3), 1487 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1488 .nentries = __cpu_to_le32(32), 1489 .nbytes_max = __cpu_to_le32(2048), 1490 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1491 .reserved = __cpu_to_le32(0), 1492 }, 1493 1494 /* CE4: host->target HTT */ 1495 { 1496 .pipenum = __cpu_to_le32(4), 1497 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1498 .nentries = __cpu_to_le32(256), 1499 .nbytes_max = __cpu_to_le32(256), 1500 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1501 .reserved = __cpu_to_le32(0), 1502 }, 1503 1504 /* CE5: target->host Pktlog */ 1505 { 1506 .pipenum = __cpu_to_le32(5), 1507 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1508 .nentries = __cpu_to_le32(32), 1509 .nbytes_max = __cpu_to_le32(2048), 1510 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1511 .reserved = __cpu_to_le32(0), 1512 }, 1513 1514 /* CE6: Reserved for target autonomous hif_memcpy */ 1515 { 1516 .pipenum = __cpu_to_le32(6), 1517 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1518 .nentries = __cpu_to_le32(32), 1519 .nbytes_max = __cpu_to_le32(16384), 1520 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1521 .reserved = __cpu_to_le32(0), 1522 }, 1523 1524 /* CE7 used only by Host */ 1525 { 1526 .pipenum = __cpu_to_le32(7), 1527 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 1528 .nentries = __cpu_to_le32(0), 1529 .nbytes_max = __cpu_to_le32(0), 1530 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1531 .reserved = __cpu_to_le32(0), 1532 }, 1533 1534 /* CE8 target->host used only by IPA */ 1535 { 1536 .pipenum = __cpu_to_le32(8), 1537 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1538 .nentries = __cpu_to_le32(32), 1539 .nbytes_max = __cpu_to_le32(16384), 1540 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1541 .reserved = __cpu_to_le32(0), 1542 }, 1543 /* CE 9, 10, 11 are used by MHI driver */ 1544 }; 1545 1546 /* Map from service/endpoint to Copy Engine. 1547 * This table is derived from the CE_PCI TABLE, above. 1548 * It is passed to the Target at startup for use by firmware. 1549 */ 1550 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qca6390[] = { 1551 { 1552 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1553 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1554 __cpu_to_le32(3), 1555 }, 1556 { 1557 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1558 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1559 __cpu_to_le32(2), 1560 }, 1561 { 1562 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1563 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1564 __cpu_to_le32(3), 1565 }, 1566 { 1567 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1568 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1569 __cpu_to_le32(2), 1570 }, 1571 { 1572 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1573 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1574 __cpu_to_le32(3), 1575 }, 1576 { 1577 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1578 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1579 __cpu_to_le32(2), 1580 }, 1581 { 1582 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1583 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1584 __cpu_to_le32(3), 1585 }, 1586 { 1587 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1588 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1589 __cpu_to_le32(2), 1590 }, 1591 { 1592 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1593 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1594 __cpu_to_le32(3), 1595 }, 1596 { 1597 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1598 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1599 __cpu_to_le32(2), 1600 }, 1601 { 1602 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1603 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1604 __cpu_to_le32(0), 1605 }, 1606 { 1607 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1608 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1609 __cpu_to_le32(2), 1610 }, 1611 { 1612 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1613 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1614 __cpu_to_le32(4), 1615 }, 1616 { 1617 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1618 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1619 __cpu_to_le32(1), 1620 }, 1621 1622 /* (Additions here) */ 1623 1624 { /* must be last */ 1625 __cpu_to_le32(0), 1626 __cpu_to_le32(0), 1627 __cpu_to_le32(0), 1628 }, 1629 }; 1630 1631 /* Target firmware's Copy Engine configuration. */ 1632 const struct ce_pipe_config ath11k_target_ce_config_wlan_qcn9074[] = { 1633 /* CE0: host->target HTC control and raw streams */ 1634 { 1635 .pipenum = __cpu_to_le32(0), 1636 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1637 .nentries = __cpu_to_le32(32), 1638 .nbytes_max = __cpu_to_le32(2048), 1639 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1640 .reserved = __cpu_to_le32(0), 1641 }, 1642 1643 /* CE1: target->host HTT + HTC control */ 1644 { 1645 .pipenum = __cpu_to_le32(1), 1646 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1647 .nentries = __cpu_to_le32(32), 1648 .nbytes_max = __cpu_to_le32(2048), 1649 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1650 .reserved = __cpu_to_le32(0), 1651 }, 1652 1653 /* CE2: target->host WMI */ 1654 { 1655 .pipenum = __cpu_to_le32(2), 1656 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1657 .nentries = __cpu_to_le32(32), 1658 .nbytes_max = __cpu_to_le32(2048), 1659 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1660 .reserved = __cpu_to_le32(0), 1661 }, 1662 1663 /* CE3: host->target WMI */ 1664 { 1665 .pipenum = __cpu_to_le32(3), 1666 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1667 .nentries = __cpu_to_le32(32), 1668 .nbytes_max = __cpu_to_le32(2048), 1669 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1670 .reserved = __cpu_to_le32(0), 1671 }, 1672 1673 /* CE4: host->target HTT */ 1674 { 1675 .pipenum = __cpu_to_le32(4), 1676 .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1677 .nentries = __cpu_to_le32(256), 1678 .nbytes_max = __cpu_to_le32(256), 1679 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1680 .reserved = __cpu_to_le32(0), 1681 }, 1682 1683 /* CE5: target->host Pktlog */ 1684 { 1685 .pipenum = __cpu_to_le32(5), 1686 .pipedir = __cpu_to_le32(PIPEDIR_IN), 1687 .nentries = __cpu_to_le32(32), 1688 .nbytes_max = __cpu_to_le32(2048), 1689 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1690 .reserved = __cpu_to_le32(0), 1691 }, 1692 1693 /* CE6: Reserved for target autonomous hif_memcpy */ 1694 { 1695 .pipenum = __cpu_to_le32(6), 1696 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1697 .nentries = __cpu_to_le32(32), 1698 .nbytes_max = __cpu_to_le32(16384), 1699 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1700 .reserved = __cpu_to_le32(0), 1701 }, 1702 1703 /* CE7 used only by Host */ 1704 { 1705 .pipenum = __cpu_to_le32(7), 1706 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 1707 .nentries = __cpu_to_le32(0), 1708 .nbytes_max = __cpu_to_le32(0), 1709 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1710 .reserved = __cpu_to_le32(0), 1711 }, 1712 1713 /* CE8 target->host used only by IPA */ 1714 { 1715 .pipenum = __cpu_to_le32(8), 1716 .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1717 .nentries = __cpu_to_le32(32), 1718 .nbytes_max = __cpu_to_le32(16384), 1719 .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1720 .reserved = __cpu_to_le32(0), 1721 }, 1722 /* CE 9, 10, 11 are used by MHI driver */ 1723 }; 1724 1725 /* Map from service/endpoint to Copy Engine. 1726 * This table is derived from the CE_PCI TABLE, above. 1727 * It is passed to the Target at startup for use by firmware. 1728 */ 1729 const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qcn9074[] = { 1730 { 1731 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1732 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1733 __cpu_to_le32(3), 1734 }, 1735 { 1736 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1737 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1738 __cpu_to_le32(2), 1739 }, 1740 { 1741 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1742 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1743 __cpu_to_le32(3), 1744 }, 1745 { 1746 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1747 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1748 __cpu_to_le32(2), 1749 }, 1750 { 1751 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1752 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1753 __cpu_to_le32(3), 1754 }, 1755 { 1756 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1757 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1758 __cpu_to_le32(2), 1759 }, 1760 { 1761 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1762 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1763 __cpu_to_le32(3), 1764 }, 1765 { 1766 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1767 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1768 __cpu_to_le32(2), 1769 }, 1770 { 1771 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1772 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1773 __cpu_to_le32(3), 1774 }, 1775 { 1776 __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1777 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1778 __cpu_to_le32(2), 1779 }, 1780 { 1781 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1782 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1783 __cpu_to_le32(0), 1784 }, 1785 { 1786 __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1787 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1788 __cpu_to_le32(1), 1789 }, 1790 { 1791 __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1792 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1793 __cpu_to_le32(0), 1794 }, 1795 { 1796 __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1797 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1798 __cpu_to_le32(1), 1799 }, 1800 { 1801 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1802 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1803 __cpu_to_le32(4), 1804 }, 1805 { 1806 __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1807 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1808 __cpu_to_le32(1), 1809 }, 1810 { 1811 __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 1812 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1813 __cpu_to_le32(5), 1814 }, 1815 1816 /* (Additions here) */ 1817 1818 { /* must be last */ 1819 __cpu_to_le32(0), 1820 __cpu_to_le32(0), 1821 __cpu_to_le32(0), 1822 }, 1823 }; 1824 1825 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qcn9074 = { 1826 .tx = { 1827 ATH11K_TX_RING_MASK_0, 1828 ATH11K_TX_RING_MASK_1, 1829 ATH11K_TX_RING_MASK_2, 1830 }, 1831 .rx_mon_status = { 1832 0, 0, 0, 1833 ATH11K_RX_MON_STATUS_RING_MASK_0, 1834 ATH11K_RX_MON_STATUS_RING_MASK_1, 1835 ATH11K_RX_MON_STATUS_RING_MASK_2, 1836 }, 1837 .rx = { 1838 0, 0, 0, 0, 1839 ATH11K_RX_RING_MASK_0, 1840 ATH11K_RX_RING_MASK_1, 1841 ATH11K_RX_RING_MASK_2, 1842 ATH11K_RX_RING_MASK_3, 1843 }, 1844 .rx_err = { 1845 0, 0, 0, 1846 ATH11K_RX_ERR_RING_MASK_0, 1847 }, 1848 .rx_wbm_rel = { 1849 0, 0, 0, 1850 ATH11K_RX_WBM_REL_RING_MASK_0, 1851 }, 1852 .reo_status = { 1853 0, 0, 0, 1854 ATH11K_REO_STATUS_RING_MASK_0, 1855 }, 1856 .rxdma2host = { 1857 0, 0, 0, 1858 ATH11K_RXDMA2HOST_RING_MASK_0, 1859 }, 1860 .host2rxdma = { 1861 0, 0, 0, 1862 ATH11K_HOST2RXDMA_RING_MASK_0, 1863 }, 1864 }; 1865 1866 const struct ath11k_hw_regs ipq8074_regs = { 1867 /* SW2TCL(x) R0 ring configuration address */ 1868 .hal_tcl1_ring_base_lsb = 0x00000510, 1869 .hal_tcl1_ring_base_msb = 0x00000514, 1870 .hal_tcl1_ring_id = 0x00000518, 1871 .hal_tcl1_ring_misc = 0x00000520, 1872 .hal_tcl1_ring_tp_addr_lsb = 0x0000052c, 1873 .hal_tcl1_ring_tp_addr_msb = 0x00000530, 1874 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000540, 1875 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000544, 1876 .hal_tcl1_ring_msi1_base_lsb = 0x00000558, 1877 .hal_tcl1_ring_msi1_base_msb = 0x0000055c, 1878 .hal_tcl1_ring_msi1_data = 0x00000560, 1879 .hal_tcl2_ring_base_lsb = 0x00000568, 1880 .hal_tcl_ring_base_lsb = 0x00000618, 1881 1882 /* TCL STATUS ring address */ 1883 .hal_tcl_status_ring_base_lsb = 0x00000720, 1884 1885 /* REO2SW(x) R0 ring configuration address */ 1886 .hal_reo1_ring_base_lsb = 0x0000029c, 1887 .hal_reo1_ring_base_msb = 0x000002a0, 1888 .hal_reo1_ring_id = 0x000002a4, 1889 .hal_reo1_ring_misc = 0x000002ac, 1890 .hal_reo1_ring_hp_addr_lsb = 0x000002b0, 1891 .hal_reo1_ring_hp_addr_msb = 0x000002b4, 1892 .hal_reo1_ring_producer_int_setup = 0x000002c0, 1893 .hal_reo1_ring_msi1_base_lsb = 0x000002e4, 1894 .hal_reo1_ring_msi1_base_msb = 0x000002e8, 1895 .hal_reo1_ring_msi1_data = 0x000002ec, 1896 .hal_reo2_ring_base_lsb = 0x000002f4, 1897 .hal_reo1_aging_thresh_ix_0 = 0x00000564, 1898 .hal_reo1_aging_thresh_ix_1 = 0x00000568, 1899 .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 1900 .hal_reo1_aging_thresh_ix_3 = 0x00000570, 1901 1902 /* REO2SW(x) R2 ring pointers (head/tail) address */ 1903 .hal_reo1_ring_hp = 0x00003038, 1904 .hal_reo1_ring_tp = 0x0000303c, 1905 .hal_reo2_ring_hp = 0x00003040, 1906 1907 /* REO2TCL R0 ring configuration address */ 1908 .hal_reo_tcl_ring_base_lsb = 0x000003fc, 1909 .hal_reo_tcl_ring_hp = 0x00003058, 1910 1911 /* REO status address */ 1912 .hal_reo_status_ring_base_lsb = 0x00000504, 1913 .hal_reo_status_hp = 0x00003070, 1914 1915 /* WCSS relative address */ 1916 .hal_seq_wcss_umac_ce0_src_reg = 0x00a00000, 1917 .hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000, 1918 .hal_seq_wcss_umac_ce1_src_reg = 0x00a02000, 1919 .hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000, 1920 1921 /* WBM Idle address */ 1922 .hal_wbm_idle_link_ring_base_lsb = 0x00000860, 1923 .hal_wbm_idle_link_ring_misc = 0x00000870, 1924 1925 /* SW2WBM release address */ 1926 .hal_wbm_release_ring_base_lsb = 0x000001d8, 1927 1928 /* WBM2SW release address */ 1929 .hal_wbm0_release_ring_base_lsb = 0x00000910, 1930 .hal_wbm1_release_ring_base_lsb = 0x00000968, 1931 1932 /* PCIe base address */ 1933 .pcie_qserdes_sysclk_en_sel = 0x0, 1934 .pcie_pcs_osc_dtct_config_base = 0x0, 1935 }; 1936 1937 const struct ath11k_hw_regs qca6390_regs = { 1938 /* SW2TCL(x) R0 ring configuration address */ 1939 .hal_tcl1_ring_base_lsb = 0x00000684, 1940 .hal_tcl1_ring_base_msb = 0x00000688, 1941 .hal_tcl1_ring_id = 0x0000068c, 1942 .hal_tcl1_ring_misc = 0x00000694, 1943 .hal_tcl1_ring_tp_addr_lsb = 0x000006a0, 1944 .hal_tcl1_ring_tp_addr_msb = 0x000006a4, 1945 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006b4, 1946 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006b8, 1947 .hal_tcl1_ring_msi1_base_lsb = 0x000006cc, 1948 .hal_tcl1_ring_msi1_base_msb = 0x000006d0, 1949 .hal_tcl1_ring_msi1_data = 0x000006d4, 1950 .hal_tcl2_ring_base_lsb = 0x000006dc, 1951 .hal_tcl_ring_base_lsb = 0x0000078c, 1952 1953 /* TCL STATUS ring address */ 1954 .hal_tcl_status_ring_base_lsb = 0x00000894, 1955 1956 /* REO2SW(x) R0 ring configuration address */ 1957 .hal_reo1_ring_base_lsb = 0x00000244, 1958 .hal_reo1_ring_base_msb = 0x00000248, 1959 .hal_reo1_ring_id = 0x0000024c, 1960 .hal_reo1_ring_misc = 0x00000254, 1961 .hal_reo1_ring_hp_addr_lsb = 0x00000258, 1962 .hal_reo1_ring_hp_addr_msb = 0x0000025c, 1963 .hal_reo1_ring_producer_int_setup = 0x00000268, 1964 .hal_reo1_ring_msi1_base_lsb = 0x0000028c, 1965 .hal_reo1_ring_msi1_base_msb = 0x00000290, 1966 .hal_reo1_ring_msi1_data = 0x00000294, 1967 .hal_reo2_ring_base_lsb = 0x0000029c, 1968 .hal_reo1_aging_thresh_ix_0 = 0x0000050c, 1969 .hal_reo1_aging_thresh_ix_1 = 0x00000510, 1970 .hal_reo1_aging_thresh_ix_2 = 0x00000514, 1971 .hal_reo1_aging_thresh_ix_3 = 0x00000518, 1972 1973 /* REO2SW(x) R2 ring pointers (head/tail) address */ 1974 .hal_reo1_ring_hp = 0x00003030, 1975 .hal_reo1_ring_tp = 0x00003034, 1976 .hal_reo2_ring_hp = 0x00003038, 1977 1978 /* REO2TCL R0 ring configuration address */ 1979 .hal_reo_tcl_ring_base_lsb = 0x000003a4, 1980 .hal_reo_tcl_ring_hp = 0x00003050, 1981 1982 /* REO status address */ 1983 .hal_reo_status_ring_base_lsb = 0x000004ac, 1984 .hal_reo_status_hp = 0x00003068, 1985 1986 /* WCSS relative address */ 1987 .hal_seq_wcss_umac_ce0_src_reg = 0x00a00000, 1988 .hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000, 1989 .hal_seq_wcss_umac_ce1_src_reg = 0x00a02000, 1990 .hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000, 1991 1992 /* WBM Idle address */ 1993 .hal_wbm_idle_link_ring_base_lsb = 0x00000860, 1994 .hal_wbm_idle_link_ring_misc = 0x00000870, 1995 1996 /* SW2WBM release address */ 1997 .hal_wbm_release_ring_base_lsb = 0x000001d8, 1998 1999 /* WBM2SW release address */ 2000 .hal_wbm0_release_ring_base_lsb = 0x00000910, 2001 .hal_wbm1_release_ring_base_lsb = 0x00000968, 2002 2003 /* PCIe base address */ 2004 .pcie_qserdes_sysclk_en_sel = 0x01e0c0ac, 2005 .pcie_pcs_osc_dtct_config_base = 0x01e0c628, 2006 }; 2007 2008 const struct ath11k_hw_regs qcn9074_regs = { 2009 /* SW2TCL(x) R0 ring configuration address */ 2010 .hal_tcl1_ring_base_lsb = 0x000004f0, 2011 .hal_tcl1_ring_base_msb = 0x000004f4, 2012 .hal_tcl1_ring_id = 0x000004f8, 2013 .hal_tcl1_ring_misc = 0x00000500, 2014 .hal_tcl1_ring_tp_addr_lsb = 0x0000050c, 2015 .hal_tcl1_ring_tp_addr_msb = 0x00000510, 2016 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000520, 2017 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000524, 2018 .hal_tcl1_ring_msi1_base_lsb = 0x00000538, 2019 .hal_tcl1_ring_msi1_base_msb = 0x0000053c, 2020 .hal_tcl1_ring_msi1_data = 0x00000540, 2021 .hal_tcl2_ring_base_lsb = 0x00000548, 2022 .hal_tcl_ring_base_lsb = 0x000005f8, 2023 2024 /* TCL STATUS ring address */ 2025 .hal_tcl_status_ring_base_lsb = 0x00000700, 2026 2027 /* REO2SW(x) R0 ring configuration address */ 2028 .hal_reo1_ring_base_lsb = 0x0000029c, 2029 .hal_reo1_ring_base_msb = 0x000002a0, 2030 .hal_reo1_ring_id = 0x000002a4, 2031 .hal_reo1_ring_misc = 0x000002ac, 2032 .hal_reo1_ring_hp_addr_lsb = 0x000002b0, 2033 .hal_reo1_ring_hp_addr_msb = 0x000002b4, 2034 .hal_reo1_ring_producer_int_setup = 0x000002c0, 2035 .hal_reo1_ring_msi1_base_lsb = 0x000002e4, 2036 .hal_reo1_ring_msi1_base_msb = 0x000002e8, 2037 .hal_reo1_ring_msi1_data = 0x000002ec, 2038 .hal_reo2_ring_base_lsb = 0x000002f4, 2039 .hal_reo1_aging_thresh_ix_0 = 0x00000564, 2040 .hal_reo1_aging_thresh_ix_1 = 0x00000568, 2041 .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 2042 .hal_reo1_aging_thresh_ix_3 = 0x00000570, 2043 2044 /* REO2SW(x) R2 ring pointers (head/tail) address */ 2045 .hal_reo1_ring_hp = 0x00003038, 2046 .hal_reo1_ring_tp = 0x0000303c, 2047 .hal_reo2_ring_hp = 0x00003040, 2048 2049 /* REO2TCL R0 ring configuration address */ 2050 .hal_reo_tcl_ring_base_lsb = 0x000003fc, 2051 .hal_reo_tcl_ring_hp = 0x00003058, 2052 2053 /* REO status address */ 2054 .hal_reo_status_ring_base_lsb = 0x00000504, 2055 .hal_reo_status_hp = 0x00003070, 2056 2057 /* WCSS relative address */ 2058 .hal_seq_wcss_umac_ce0_src_reg = 0x01b80000, 2059 .hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000, 2060 .hal_seq_wcss_umac_ce1_src_reg = 0x01b82000, 2061 .hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000, 2062 2063 /* WBM Idle address */ 2064 .hal_wbm_idle_link_ring_base_lsb = 0x00000874, 2065 .hal_wbm_idle_link_ring_misc = 0x00000884, 2066 2067 /* SW2WBM release address */ 2068 .hal_wbm_release_ring_base_lsb = 0x000001ec, 2069 2070 /* WBM2SW release address */ 2071 .hal_wbm0_release_ring_base_lsb = 0x00000924, 2072 .hal_wbm1_release_ring_base_lsb = 0x0000097c, 2073 2074 /* PCIe base address */ 2075 .pcie_qserdes_sysclk_en_sel = 0x01e0e0a8, 2076 .pcie_pcs_osc_dtct_config_base = 0x01e0f45c, 2077 }; 2078 2079 const struct ath11k_hw_regs wcn6855_regs = { 2080 /* SW2TCL(x) R0 ring configuration address */ 2081 .hal_tcl1_ring_base_lsb = 0x00000690, 2082 .hal_tcl1_ring_base_msb = 0x00000694, 2083 .hal_tcl1_ring_id = 0x00000698, 2084 .hal_tcl1_ring_misc = 0x000006a0, 2085 .hal_tcl1_ring_tp_addr_lsb = 0x000006ac, 2086 .hal_tcl1_ring_tp_addr_msb = 0x000006b0, 2087 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006c0, 2088 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006c4, 2089 .hal_tcl1_ring_msi1_base_lsb = 0x000006d8, 2090 .hal_tcl1_ring_msi1_base_msb = 0x000006dc, 2091 .hal_tcl1_ring_msi1_data = 0x000006e0, 2092 .hal_tcl2_ring_base_lsb = 0x000006e8, 2093 .hal_tcl_ring_base_lsb = 0x00000798, 2094 2095 /* TCL STATUS ring address */ 2096 .hal_tcl_status_ring_base_lsb = 0x000008a0, 2097 2098 /* REO2SW(x) R0 ring configuration address */ 2099 .hal_reo1_ring_base_lsb = 0x00000244, 2100 .hal_reo1_ring_base_msb = 0x00000248, 2101 .hal_reo1_ring_id = 0x0000024c, 2102 .hal_reo1_ring_misc = 0x00000254, 2103 .hal_reo1_ring_hp_addr_lsb = 0x00000258, 2104 .hal_reo1_ring_hp_addr_msb = 0x0000025c, 2105 .hal_reo1_ring_producer_int_setup = 0x00000268, 2106 .hal_reo1_ring_msi1_base_lsb = 0x0000028c, 2107 .hal_reo1_ring_msi1_base_msb = 0x00000290, 2108 .hal_reo1_ring_msi1_data = 0x00000294, 2109 .hal_reo2_ring_base_lsb = 0x0000029c, 2110 .hal_reo1_aging_thresh_ix_0 = 0x000005bc, 2111 .hal_reo1_aging_thresh_ix_1 = 0x000005c0, 2112 .hal_reo1_aging_thresh_ix_2 = 0x000005c4, 2113 .hal_reo1_aging_thresh_ix_3 = 0x000005c8, 2114 2115 /* REO2SW(x) R2 ring pointers (head/tail) address */ 2116 .hal_reo1_ring_hp = 0x00003030, 2117 .hal_reo1_ring_tp = 0x00003034, 2118 .hal_reo2_ring_hp = 0x00003038, 2119 2120 /* REO2TCL R0 ring configuration address */ 2121 .hal_reo_tcl_ring_base_lsb = 0x00000454, 2122 .hal_reo_tcl_ring_hp = 0x00003060, 2123 2124 /* REO status address */ 2125 .hal_reo_status_ring_base_lsb = 0x0000055c, 2126 .hal_reo_status_hp = 0x00003078, 2127 2128 /* WCSS relative address */ 2129 .hal_seq_wcss_umac_ce0_src_reg = 0x1b80000, 2130 .hal_seq_wcss_umac_ce0_dst_reg = 0x1b81000, 2131 .hal_seq_wcss_umac_ce1_src_reg = 0x1b82000, 2132 .hal_seq_wcss_umac_ce1_dst_reg = 0x1b83000, 2133 2134 /* WBM Idle address */ 2135 .hal_wbm_idle_link_ring_base_lsb = 0x00000870, 2136 .hal_wbm_idle_link_ring_misc = 0x00000880, 2137 2138 /* SW2WBM release address */ 2139 .hal_wbm_release_ring_base_lsb = 0x000001e8, 2140 2141 /* WBM2SW release address */ 2142 .hal_wbm0_release_ring_base_lsb = 0x00000920, 2143 .hal_wbm1_release_ring_base_lsb = 0x00000978, 2144 2145 /* PCIe base address */ 2146 .pcie_qserdes_sysclk_en_sel = 0x01e0c0ac, 2147 .pcie_pcs_osc_dtct_config_base = 0x01e0c628, 2148 }; 2149 2150 const struct ath11k_hw_hal_params ath11k_hw_hal_params_ipq8074 = { 2151 .rx_buf_rbm = HAL_RX_BUF_RBM_SW3_BM, 2152 }; 2153 2154 const struct ath11k_hw_hal_params ath11k_hw_hal_params_qca6390 = { 2155 .rx_buf_rbm = HAL_RX_BUF_RBM_SW1_BM, 2156 }; 2157