1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/types.h> 7 #include <linux/bitops.h> 8 #include <linux/bitfield.h> 9 10 #include "hw.h" 11 #include "core.h" 12 #include "ce.h" 13 14 /* Map from pdev index to hw mac index */ 15 static u8 ath11k_hw_ipq8074_mac_from_pdev_id(int pdev_idx) 16 { 17 switch (pdev_idx) { 18 case 0: 19 return 0; 20 case 1: 21 return 2; 22 case 2: 23 return 1; 24 default: 25 return ATH11K_INVALID_HW_MAC_ID; 26 } 27 } 28 29 static u8 ath11k_hw_ipq6018_mac_from_pdev_id(int pdev_idx) 30 { 31 return pdev_idx; 32 } 33 34 static void ath11k_init_wmi_config_qca6390(struct ath11k_base *ab, 35 struct target_resource_config *config) 36 { 37 config->num_vdevs = 4; 38 config->num_peers = 16; 39 config->num_tids = 32; 40 41 config->num_offload_peers = 3; 42 config->num_offload_reorder_buffs = 3; 43 config->num_peer_keys = TARGET_NUM_PEER_KEYS; 44 config->ast_skid_limit = TARGET_AST_SKID_LIMIT; 45 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 46 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 47 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; 48 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI; 49 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; 50 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; 51 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; 52 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS; 53 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV; 54 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV; 55 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES; 56 config->num_mcast_groups = 0; 57 config->num_mcast_table_elems = 0; 58 config->mcast2ucast_mode = 0; 59 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE; 60 config->num_wds_entries = 0; 61 config->dma_burst_size = 0; 62 config->rx_skip_defrag_timeout_dup_detection_check = 0; 63 config->vow_config = TARGET_VOW_CONFIG; 64 config->gtk_offload_max_vdev = 2; 65 config->num_msdu_desc = 0x400; 66 config->beacon_tx_offload_max_vdev = 2; 67 config->rx_batchmode = TARGET_RX_BATCHMODE; 68 69 config->peer_map_unmap_v2_support = 0; 70 config->use_pdev_id = 1; 71 config->max_frag_entries = 0xa; 72 config->num_tdls_vdevs = 0x1; 73 config->num_tdls_conn_table_entries = 8; 74 config->beacon_tx_offload_max_vdev = 0x2; 75 config->num_multicast_filter_entries = 0x20; 76 config->num_wow_filters = 0x16; 77 config->num_keep_alive_pattern = 0x1; 78 config->num_keep_alive_pattern = 0; 79 } 80 81 static void ath11k_init_wmi_config_ipq8074(struct ath11k_base *ab, 82 struct target_resource_config *config) 83 { 84 config->num_vdevs = ab->num_radios * TARGET_NUM_VDEVS; 85 86 if (ab->num_radios == 2) { 87 config->num_peers = TARGET_NUM_PEERS(DBS); 88 config->num_tids = TARGET_NUM_TIDS(DBS); 89 } else if (ab->num_radios == 3) { 90 config->num_peers = TARGET_NUM_PEERS(DBS_SBS); 91 config->num_tids = TARGET_NUM_TIDS(DBS_SBS); 92 } else { 93 /* Control should not reach here */ 94 config->num_peers = TARGET_NUM_PEERS(SINGLE); 95 config->num_tids = TARGET_NUM_TIDS(SINGLE); 96 } 97 config->num_offload_peers = TARGET_NUM_OFFLD_PEERS; 98 config->num_offload_reorder_buffs = TARGET_NUM_OFFLD_REORDER_BUFFS; 99 config->num_peer_keys = TARGET_NUM_PEER_KEYS; 100 config->ast_skid_limit = TARGET_AST_SKID_LIMIT; 101 config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 102 config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 103 config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; 104 config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI; 105 config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; 106 config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; 107 config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; 108 config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS; 109 config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV; 110 config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV; 111 config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES; 112 config->num_mcast_groups = TARGET_NUM_MCAST_GROUPS; 113 config->num_mcast_table_elems = TARGET_NUM_MCAST_TABLE_ELEMS; 114 config->mcast2ucast_mode = TARGET_MCAST2UCAST_MODE; 115 config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE; 116 config->num_wds_entries = TARGET_NUM_WDS_ENTRIES; 117 config->dma_burst_size = TARGET_DMA_BURST_SIZE; 118 config->rx_skip_defrag_timeout_dup_detection_check = 119 TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK; 120 config->vow_config = TARGET_VOW_CONFIG; 121 config->gtk_offload_max_vdev = TARGET_GTK_OFFLOAD_MAX_VDEV; 122 config->num_msdu_desc = TARGET_NUM_MSDU_DESC; 123 config->beacon_tx_offload_max_vdev = ab->num_radios * TARGET_MAX_BCN_OFFLD; 124 config->rx_batchmode = TARGET_RX_BATCHMODE; 125 config->peer_map_unmap_v2_support = 1; 126 config->twt_ap_pdev_count = 2; 127 config->twt_ap_sta_count = 1000; 128 } 129 130 static int ath11k_hw_mac_id_to_pdev_id_ipq8074(struct ath11k_hw_params *hw, 131 int mac_id) 132 { 133 return mac_id; 134 } 135 136 static int ath11k_hw_mac_id_to_srng_id_ipq8074(struct ath11k_hw_params *hw, 137 int mac_id) 138 { 139 return 0; 140 } 141 142 static int ath11k_hw_mac_id_to_pdev_id_qca6390(struct ath11k_hw_params *hw, 143 int mac_id) 144 { 145 return 0; 146 } 147 148 static int ath11k_hw_mac_id_to_srng_id_qca6390(struct ath11k_hw_params *hw, 149 int mac_id) 150 { 151 return mac_id; 152 } 153 154 const struct ath11k_hw_ops ipq8074_ops = { 155 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 156 .wmi_init_config = ath11k_init_wmi_config_qca6390, 157 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 158 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 159 }; 160 161 const struct ath11k_hw_ops ipq6018_ops = { 162 .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 163 .wmi_init_config = ath11k_init_wmi_config_ipq8074, 164 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 165 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 166 }; 167 168 const struct ath11k_hw_ops qca6390_ops = { 169 .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 170 .wmi_init_config = ath11k_init_wmi_config_qca6390, 171 .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390, 172 .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390, 173 }; 174 175 #define ATH11K_TX_RING_MASK_0 0x1 176 #define ATH11K_TX_RING_MASK_1 0x2 177 #define ATH11K_TX_RING_MASK_2 0x4 178 179 #define ATH11K_RX_RING_MASK_0 0x1 180 #define ATH11K_RX_RING_MASK_1 0x2 181 #define ATH11K_RX_RING_MASK_2 0x4 182 #define ATH11K_RX_RING_MASK_3 0x8 183 184 #define ATH11K_RX_ERR_RING_MASK_0 0x1 185 186 #define ATH11K_RX_WBM_REL_RING_MASK_0 0x1 187 188 #define ATH11K_REO_STATUS_RING_MASK_0 0x1 189 190 #define ATH11K_RXDMA2HOST_RING_MASK_0 0x1 191 #define ATH11K_RXDMA2HOST_RING_MASK_1 0x2 192 #define ATH11K_RXDMA2HOST_RING_MASK_2 0x4 193 194 #define ATH11K_HOST2RXDMA_RING_MASK_0 0x1 195 #define ATH11K_HOST2RXDMA_RING_MASK_1 0x2 196 #define ATH11K_HOST2RXDMA_RING_MASK_2 0x4 197 198 #define ATH11K_RX_MON_STATUS_RING_MASK_0 0x1 199 #define ATH11K_RX_MON_STATUS_RING_MASK_1 0x2 200 #define ATH11K_RX_MON_STATUS_RING_MASK_2 0x4 201 202 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074 = { 203 .tx = { 204 ATH11K_TX_RING_MASK_0, 205 ATH11K_TX_RING_MASK_1, 206 ATH11K_TX_RING_MASK_2, 207 }, 208 .rx_mon_status = { 209 0, 0, 0, 0, 210 ATH11K_RX_MON_STATUS_RING_MASK_0, 211 ATH11K_RX_MON_STATUS_RING_MASK_1, 212 ATH11K_RX_MON_STATUS_RING_MASK_2, 213 }, 214 .rx = { 215 0, 0, 0, 0, 0, 0, 0, 216 ATH11K_RX_RING_MASK_0, 217 ATH11K_RX_RING_MASK_1, 218 ATH11K_RX_RING_MASK_2, 219 ATH11K_RX_RING_MASK_3, 220 }, 221 .rx_err = { 222 ATH11K_RX_ERR_RING_MASK_0, 223 }, 224 .rx_wbm_rel = { 225 ATH11K_RX_WBM_REL_RING_MASK_0, 226 }, 227 .reo_status = { 228 ATH11K_REO_STATUS_RING_MASK_0, 229 }, 230 .rxdma2host = { 231 ATH11K_RXDMA2HOST_RING_MASK_0, 232 ATH11K_RXDMA2HOST_RING_MASK_1, 233 ATH11K_RXDMA2HOST_RING_MASK_2, 234 }, 235 .host2rxdma = { 236 ATH11K_HOST2RXDMA_RING_MASK_0, 237 ATH11K_HOST2RXDMA_RING_MASK_1, 238 ATH11K_HOST2RXDMA_RING_MASK_2, 239 }, 240 }; 241 242 const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390 = { 243 .tx = { 244 ATH11K_TX_RING_MASK_0, 245 ATH11K_TX_RING_MASK_1, 246 ATH11K_TX_RING_MASK_2, 247 }, 248 .rx_mon_status = { 249 0, 0, 0, 0, 250 ATH11K_RX_MON_STATUS_RING_MASK_0, 251 ATH11K_RX_MON_STATUS_RING_MASK_1, 252 ATH11K_RX_MON_STATUS_RING_MASK_2, 253 }, 254 .rx = { 255 0, 0, 0, 0, 0, 0, 0, 256 ATH11K_RX_RING_MASK_0, 257 ATH11K_RX_RING_MASK_1, 258 ATH11K_RX_RING_MASK_2, 259 ATH11K_RX_RING_MASK_3, 260 }, 261 .rx_err = { 262 ATH11K_RX_ERR_RING_MASK_0, 263 }, 264 .rx_wbm_rel = { 265 ATH11K_RX_WBM_REL_RING_MASK_0, 266 }, 267 .reo_status = { 268 ATH11K_REO_STATUS_RING_MASK_0, 269 }, 270 .rxdma2host = { 271 ATH11K_RXDMA2HOST_RING_MASK_0, 272 ATH11K_RXDMA2HOST_RING_MASK_1, 273 ATH11K_RXDMA2HOST_RING_MASK_2, 274 }, 275 .host2rxdma = { 276 }, 277 }; 278 279 const struct ath11k_hw_regs ipq8074_regs = { 280 /* SW2TCL(x) R0 ring configuration address */ 281 .hal_tcl1_ring_base_lsb = 0x00000510, 282 .hal_tcl1_ring_base_msb = 0x00000514, 283 .hal_tcl1_ring_id = 0x00000518, 284 .hal_tcl1_ring_misc = 0x00000520, 285 .hal_tcl1_ring_tp_addr_lsb = 0x0000052c, 286 .hal_tcl1_ring_tp_addr_msb = 0x00000530, 287 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000540, 288 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000544, 289 .hal_tcl1_ring_msi1_base_lsb = 0x00000558, 290 .hal_tcl1_ring_msi1_base_msb = 0x0000055c, 291 .hal_tcl1_ring_msi1_data = 0x00000560, 292 .hal_tcl2_ring_base_lsb = 0x00000568, 293 .hal_tcl_ring_base_lsb = 0x00000618, 294 295 /* TCL STATUS ring address */ 296 .hal_tcl_status_ring_base_lsb = 0x00000720, 297 298 /* REO2SW(x) R0 ring configuration address */ 299 .hal_reo1_ring_base_lsb = 0x0000029c, 300 .hal_reo1_ring_base_msb = 0x000002a0, 301 .hal_reo1_ring_id = 0x000002a4, 302 .hal_reo1_ring_misc = 0x000002ac, 303 .hal_reo1_ring_hp_addr_lsb = 0x000002b0, 304 .hal_reo1_ring_hp_addr_msb = 0x000002b4, 305 .hal_reo1_ring_producer_int_setup = 0x000002c0, 306 .hal_reo1_ring_msi1_base_lsb = 0x000002e4, 307 .hal_reo1_ring_msi1_base_msb = 0x000002e8, 308 .hal_reo1_ring_msi1_data = 0x000002ec, 309 .hal_reo2_ring_base_lsb = 0x000002f4, 310 .hal_reo1_aging_thresh_ix_0 = 0x00000564, 311 .hal_reo1_aging_thresh_ix_1 = 0x00000568, 312 .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 313 .hal_reo1_aging_thresh_ix_3 = 0x00000570, 314 315 /* REO2SW(x) R2 ring pointers (head/tail) address */ 316 .hal_reo1_ring_hp = 0x00003038, 317 .hal_reo1_ring_tp = 0x0000303c, 318 .hal_reo2_ring_hp = 0x00003040, 319 320 /* REO2TCL R0 ring configuration address */ 321 .hal_reo_tcl_ring_base_lsb = 0x000003fc, 322 .hal_reo_tcl_ring_hp = 0x00003058, 323 324 /* REO status address */ 325 .hal_reo_status_ring_base_lsb = 0x00000504, 326 .hal_reo_status_hp = 0x00003070, 327 328 }; 329 330 const struct ath11k_hw_regs qca6390_regs = { 331 /* SW2TCL(x) R0 ring configuration address */ 332 .hal_tcl1_ring_base_lsb = 0x00000684, 333 .hal_tcl1_ring_base_msb = 0x00000688, 334 .hal_tcl1_ring_id = 0x0000068c, 335 .hal_tcl1_ring_misc = 0x00000694, 336 .hal_tcl1_ring_tp_addr_lsb = 0x000006a0, 337 .hal_tcl1_ring_tp_addr_msb = 0x000006a4, 338 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006b4, 339 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006b8, 340 .hal_tcl1_ring_msi1_base_lsb = 0x000006cc, 341 .hal_tcl1_ring_msi1_base_msb = 0x000006d0, 342 .hal_tcl1_ring_msi1_data = 0x000006d4, 343 .hal_tcl2_ring_base_lsb = 0x000006dc, 344 .hal_tcl_ring_base_lsb = 0x0000078c, 345 346 /* TCL STATUS ring address */ 347 .hal_tcl_status_ring_base_lsb = 0x00000894, 348 349 /* REO2SW(x) R0 ring configuration address */ 350 .hal_reo1_ring_base_lsb = 0x00000244, 351 .hal_reo1_ring_base_msb = 0x00000248, 352 .hal_reo1_ring_id = 0x0000024c, 353 .hal_reo1_ring_misc = 0x00000254, 354 .hal_reo1_ring_hp_addr_lsb = 0x00000258, 355 .hal_reo1_ring_hp_addr_msb = 0x0000025c, 356 .hal_reo1_ring_producer_int_setup = 0x00000268, 357 .hal_reo1_ring_msi1_base_lsb = 0x0000028c, 358 .hal_reo1_ring_msi1_base_msb = 0x00000290, 359 .hal_reo1_ring_msi1_data = 0x00000294, 360 .hal_reo2_ring_base_lsb = 0x0000029c, 361 .hal_reo1_aging_thresh_ix_0 = 0x0000050c, 362 .hal_reo1_aging_thresh_ix_1 = 0x00000510, 363 .hal_reo1_aging_thresh_ix_2 = 0x00000514, 364 .hal_reo1_aging_thresh_ix_3 = 0x00000518, 365 366 /* REO2SW(x) R2 ring pointers (head/tail) address */ 367 .hal_reo1_ring_hp = 0x00003030, 368 .hal_reo1_ring_tp = 0x00003034, 369 .hal_reo2_ring_hp = 0x00003038, 370 371 /* REO2TCL R0 ring configuration address */ 372 .hal_reo_tcl_ring_base_lsb = 0x000003a4, 373 .hal_reo_tcl_ring_hp = 0x00003050, 374 375 /* REO status address */ 376 .hal_reo_status_ring_base_lsb = 0x000004ac, 377 .hal_reo_status_hp = 0x00003068, 378 }; 379