1d547ca4cSAnilkumar Kolli // SPDX-License-Identifier: BSD-3-Clause-Clear 2d547ca4cSAnilkumar Kolli /* 3d547ca4cSAnilkumar Kolli * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. 4d547ca4cSAnilkumar Kolli */ 5d547ca4cSAnilkumar Kolli 66976433cSCarl Huang #include <linux/types.h> 76976433cSCarl Huang #include <linux/bitops.h> 86976433cSCarl Huang #include <linux/bitfield.h> 96976433cSCarl Huang 106976433cSCarl Huang #include "hw.h" 11d547ca4cSAnilkumar Kolli #include "core.h" 12e3396b8bSCarl Huang #include "ce.h" 13d547ca4cSAnilkumar Kolli 14d547ca4cSAnilkumar Kolli /* Map from pdev index to hw mac index */ 15d547ca4cSAnilkumar Kolli static u8 ath11k_hw_ipq8074_mac_from_pdev_id(int pdev_idx) 16d547ca4cSAnilkumar Kolli { 17d547ca4cSAnilkumar Kolli switch (pdev_idx) { 18d547ca4cSAnilkumar Kolli case 0: 19d547ca4cSAnilkumar Kolli return 0; 20d547ca4cSAnilkumar Kolli case 1: 21d547ca4cSAnilkumar Kolli return 2; 22d547ca4cSAnilkumar Kolli case 2: 23d547ca4cSAnilkumar Kolli return 1; 24d547ca4cSAnilkumar Kolli default: 25d547ca4cSAnilkumar Kolli return ATH11K_INVALID_HW_MAC_ID; 26d547ca4cSAnilkumar Kolli } 27d547ca4cSAnilkumar Kolli } 28d547ca4cSAnilkumar Kolli 29d547ca4cSAnilkumar Kolli static u8 ath11k_hw_ipq6018_mac_from_pdev_id(int pdev_idx) 30d547ca4cSAnilkumar Kolli { 31d547ca4cSAnilkumar Kolli return pdev_idx; 32d547ca4cSAnilkumar Kolli } 33d547ca4cSAnilkumar Kolli 346fe6f68fSKarthikeyan Periyasamy static void ath11k_hw_ipq8074_tx_mesh_enable(struct ath11k_base *ab, 356fe6f68fSKarthikeyan Periyasamy struct hal_tcl_data_cmd *tcl_cmd) 366fe6f68fSKarthikeyan Periyasamy { 376fe6f68fSKarthikeyan Periyasamy tcl_cmd->info2 |= FIELD_PREP(HAL_IPQ8074_TCL_DATA_CMD_INFO2_MESH_ENABLE, 386fe6f68fSKarthikeyan Periyasamy true); 396fe6f68fSKarthikeyan Periyasamy } 406fe6f68fSKarthikeyan Periyasamy 416fe6f68fSKarthikeyan Periyasamy static void ath11k_hw_qcn9074_tx_mesh_enable(struct ath11k_base *ab, 426fe6f68fSKarthikeyan Periyasamy struct hal_tcl_data_cmd *tcl_cmd) 436fe6f68fSKarthikeyan Periyasamy { 446fe6f68fSKarthikeyan Periyasamy tcl_cmd->info3 |= FIELD_PREP(HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE, 456fe6f68fSKarthikeyan Periyasamy true); 466fe6f68fSKarthikeyan Periyasamy } 476fe6f68fSKarthikeyan Periyasamy 482d4bcbedSCarl Huang static void ath11k_init_wmi_config_qca6390(struct ath11k_base *ab, 492d4bcbedSCarl Huang struct target_resource_config *config) 502d4bcbedSCarl Huang { 512d4bcbedSCarl Huang config->num_vdevs = 4; 522d4bcbedSCarl Huang config->num_peers = 16; 532d4bcbedSCarl Huang config->num_tids = 32; 542d4bcbedSCarl Huang 552d4bcbedSCarl Huang config->num_offload_peers = 3; 562d4bcbedSCarl Huang config->num_offload_reorder_buffs = 3; 572d4bcbedSCarl Huang config->num_peer_keys = TARGET_NUM_PEER_KEYS; 582d4bcbedSCarl Huang config->ast_skid_limit = TARGET_AST_SKID_LIMIT; 592d4bcbedSCarl Huang config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 602d4bcbedSCarl Huang config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 612d4bcbedSCarl Huang config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; 622d4bcbedSCarl Huang config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI; 632d4bcbedSCarl Huang config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; 642d4bcbedSCarl Huang config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; 652d4bcbedSCarl Huang config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; 662d4bcbedSCarl Huang config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS; 672d4bcbedSCarl Huang config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV; 682d4bcbedSCarl Huang config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV; 692d4bcbedSCarl Huang config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES; 702d4bcbedSCarl Huang config->num_mcast_groups = 0; 712d4bcbedSCarl Huang config->num_mcast_table_elems = 0; 722d4bcbedSCarl Huang config->mcast2ucast_mode = 0; 732d4bcbedSCarl Huang config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE; 742d4bcbedSCarl Huang config->num_wds_entries = 0; 752d4bcbedSCarl Huang config->dma_burst_size = 0; 762d4bcbedSCarl Huang config->rx_skip_defrag_timeout_dup_detection_check = 0; 772d4bcbedSCarl Huang config->vow_config = TARGET_VOW_CONFIG; 782d4bcbedSCarl Huang config->gtk_offload_max_vdev = 2; 792d4bcbedSCarl Huang config->num_msdu_desc = 0x400; 802d4bcbedSCarl Huang config->beacon_tx_offload_max_vdev = 2; 812d4bcbedSCarl Huang config->rx_batchmode = TARGET_RX_BATCHMODE; 822d4bcbedSCarl Huang 832d4bcbedSCarl Huang config->peer_map_unmap_v2_support = 0; 842d4bcbedSCarl Huang config->use_pdev_id = 1; 852d4bcbedSCarl Huang config->max_frag_entries = 0xa; 862d4bcbedSCarl Huang config->num_tdls_vdevs = 0x1; 872d4bcbedSCarl Huang config->num_tdls_conn_table_entries = 8; 882d4bcbedSCarl Huang config->beacon_tx_offload_max_vdev = 0x2; 892d4bcbedSCarl Huang config->num_multicast_filter_entries = 0x20; 902d4bcbedSCarl Huang config->num_wow_filters = 0x16; 912d4bcbedSCarl Huang config->num_keep_alive_pattern = 0; 922d4bcbedSCarl Huang } 932d4bcbedSCarl Huang 942d4bcbedSCarl Huang static void ath11k_init_wmi_config_ipq8074(struct ath11k_base *ab, 952d4bcbedSCarl Huang struct target_resource_config *config) 962d4bcbedSCarl Huang { 972d4bcbedSCarl Huang config->num_vdevs = ab->num_radios * TARGET_NUM_VDEVS; 982d4bcbedSCarl Huang 992d4bcbedSCarl Huang if (ab->num_radios == 2) { 1002d4bcbedSCarl Huang config->num_peers = TARGET_NUM_PEERS(DBS); 1012d4bcbedSCarl Huang config->num_tids = TARGET_NUM_TIDS(DBS); 1022d4bcbedSCarl Huang } else if (ab->num_radios == 3) { 1032d4bcbedSCarl Huang config->num_peers = TARGET_NUM_PEERS(DBS_SBS); 1042d4bcbedSCarl Huang config->num_tids = TARGET_NUM_TIDS(DBS_SBS); 1052d4bcbedSCarl Huang } else { 1062d4bcbedSCarl Huang /* Control should not reach here */ 1072d4bcbedSCarl Huang config->num_peers = TARGET_NUM_PEERS(SINGLE); 1082d4bcbedSCarl Huang config->num_tids = TARGET_NUM_TIDS(SINGLE); 1092d4bcbedSCarl Huang } 1102d4bcbedSCarl Huang config->num_offload_peers = TARGET_NUM_OFFLD_PEERS; 1112d4bcbedSCarl Huang config->num_offload_reorder_buffs = TARGET_NUM_OFFLD_REORDER_BUFFS; 1122d4bcbedSCarl Huang config->num_peer_keys = TARGET_NUM_PEER_KEYS; 1132d4bcbedSCarl Huang config->ast_skid_limit = TARGET_AST_SKID_LIMIT; 1142d4bcbedSCarl Huang config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 1152d4bcbedSCarl Huang config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 1162d4bcbedSCarl Huang config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; 1172d4bcbedSCarl Huang config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI; 1182d4bcbedSCarl Huang config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; 1192d4bcbedSCarl Huang config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; 120c695faf7SKalle Valo 121c695faf7SKalle Valo if (test_bit(ATH11K_FLAG_RAW_MODE, &ab->dev_flags)) 122c695faf7SKalle Valo config->rx_decap_mode = TARGET_DECAP_MODE_RAW; 123c695faf7SKalle Valo else 1242d4bcbedSCarl Huang config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; 125c695faf7SKalle Valo 1262d4bcbedSCarl Huang config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS; 1272d4bcbedSCarl Huang config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV; 1282d4bcbedSCarl Huang config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV; 1292d4bcbedSCarl Huang config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES; 1302d4bcbedSCarl Huang config->num_mcast_groups = TARGET_NUM_MCAST_GROUPS; 1312d4bcbedSCarl Huang config->num_mcast_table_elems = TARGET_NUM_MCAST_TABLE_ELEMS; 1322d4bcbedSCarl Huang config->mcast2ucast_mode = TARGET_MCAST2UCAST_MODE; 1332d4bcbedSCarl Huang config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE; 1342d4bcbedSCarl Huang config->num_wds_entries = TARGET_NUM_WDS_ENTRIES; 1352d4bcbedSCarl Huang config->dma_burst_size = TARGET_DMA_BURST_SIZE; 1362d4bcbedSCarl Huang config->rx_skip_defrag_timeout_dup_detection_check = 1372d4bcbedSCarl Huang TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK; 1382d4bcbedSCarl Huang config->vow_config = TARGET_VOW_CONFIG; 1392d4bcbedSCarl Huang config->gtk_offload_max_vdev = TARGET_GTK_OFFLOAD_MAX_VDEV; 1402d4bcbedSCarl Huang config->num_msdu_desc = TARGET_NUM_MSDU_DESC; 1412d4bcbedSCarl Huang config->beacon_tx_offload_max_vdev = ab->num_radios * TARGET_MAX_BCN_OFFLD; 1422d4bcbedSCarl Huang config->rx_batchmode = TARGET_RX_BATCHMODE; 1432d4bcbedSCarl Huang config->peer_map_unmap_v2_support = 1; 14436c7c640SKarthikeyan Periyasamy config->twt_ap_pdev_count = ab->num_radios; 1452d4bcbedSCarl Huang config->twt_ap_sta_count = 1000; 1462d4bcbedSCarl Huang } 1472d4bcbedSCarl Huang 1484152e420SCarl Huang static int ath11k_hw_mac_id_to_pdev_id_ipq8074(struct ath11k_hw_params *hw, 1494152e420SCarl Huang int mac_id) 1504152e420SCarl Huang { 1514152e420SCarl Huang return mac_id; 1524152e420SCarl Huang } 1534152e420SCarl Huang 1544152e420SCarl Huang static int ath11k_hw_mac_id_to_srng_id_ipq8074(struct ath11k_hw_params *hw, 1554152e420SCarl Huang int mac_id) 1564152e420SCarl Huang { 1574152e420SCarl Huang return 0; 1584152e420SCarl Huang } 1594152e420SCarl Huang 1604152e420SCarl Huang static int ath11k_hw_mac_id_to_pdev_id_qca6390(struct ath11k_hw_params *hw, 1614152e420SCarl Huang int mac_id) 1624152e420SCarl Huang { 1634152e420SCarl Huang return 0; 1644152e420SCarl Huang } 1654152e420SCarl Huang 1664152e420SCarl Huang static int ath11k_hw_mac_id_to_srng_id_qca6390(struct ath11k_hw_params *hw, 1674152e420SCarl Huang int mac_id) 1684152e420SCarl Huang { 1694152e420SCarl Huang return mac_id; 1704152e420SCarl Huang } 1714152e420SCarl Huang 172*e678fbd4SKarthikeyan Periyasamy static bool ath11k_hw_ipq8074_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 173*e678fbd4SKarthikeyan Periyasamy { 174*e678fbd4SKarthikeyan Periyasamy return !!FIELD_GET(RX_MSDU_END_INFO2_FIRST_MSDU, 175*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 176*e678fbd4SKarthikeyan Periyasamy } 177*e678fbd4SKarthikeyan Periyasamy 178*e678fbd4SKarthikeyan Periyasamy static bool ath11k_hw_ipq8074_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 179*e678fbd4SKarthikeyan Periyasamy { 180*e678fbd4SKarthikeyan Periyasamy return !!FIELD_GET(RX_MSDU_END_INFO2_LAST_MSDU, 181*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 182*e678fbd4SKarthikeyan Periyasamy } 183*e678fbd4SKarthikeyan Periyasamy 184*e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 185*e678fbd4SKarthikeyan Periyasamy { 186*e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_END_INFO2_L3_HDR_PADDING, 187*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.msdu_end.info2)); 188*e678fbd4SKarthikeyan Periyasamy } 189*e678fbd4SKarthikeyan Periyasamy 190*e678fbd4SKarthikeyan Periyasamy static u8 *ath11k_hw_ipq8074_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 191*e678fbd4SKarthikeyan Periyasamy { 192*e678fbd4SKarthikeyan Periyasamy return desc->u.ipq8074.hdr_status; 193*e678fbd4SKarthikeyan Periyasamy } 194*e678fbd4SKarthikeyan Periyasamy 195*e678fbd4SKarthikeyan Periyasamy static bool ath11k_hw_ipq8074_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 196*e678fbd4SKarthikeyan Periyasamy { 197*e678fbd4SKarthikeyan Periyasamy return __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1) & 198*e678fbd4SKarthikeyan Periyasamy RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID; 199*e678fbd4SKarthikeyan Periyasamy } 200*e678fbd4SKarthikeyan Periyasamy 201*e678fbd4SKarthikeyan Periyasamy static u32 ath11k_hw_ipq8074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 202*e678fbd4SKarthikeyan Periyasamy { 203*e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MPDU_START_INFO2_ENC_TYPE, 204*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2)); 205*e678fbd4SKarthikeyan Periyasamy } 206*e678fbd4SKarthikeyan Periyasamy 207*e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_ipq8074_rx_desc_get_decap_type(struct hal_rx_desc *desc) 208*e678fbd4SKarthikeyan Periyasamy { 209*e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 210*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.msdu_start.info2)); 211*e678fbd4SKarthikeyan Periyasamy } 212*e678fbd4SKarthikeyan Periyasamy 213*e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_ipq8074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 214*e678fbd4SKarthikeyan Periyasamy { 215*e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 216*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.msdu_start.info2)); 217*e678fbd4SKarthikeyan Periyasamy } 218*e678fbd4SKarthikeyan Periyasamy 219*e678fbd4SKarthikeyan Periyasamy static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 220*e678fbd4SKarthikeyan Periyasamy { 221*e678fbd4SKarthikeyan Periyasamy return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID, 222*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 223*e678fbd4SKarthikeyan Periyasamy } 224*e678fbd4SKarthikeyan Periyasamy 225*e678fbd4SKarthikeyan Periyasamy static bool ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 226*e678fbd4SKarthikeyan Periyasamy { 227*e678fbd4SKarthikeyan Periyasamy return !!FIELD_GET(RX_MPDU_START_INFO1_MPDU_FCTRL_VALID, 228*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 229*e678fbd4SKarthikeyan Periyasamy } 230*e678fbd4SKarthikeyan Periyasamy 231*e678fbd4SKarthikeyan Periyasamy static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 232*e678fbd4SKarthikeyan Periyasamy { 233*e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MPDU_START_INFO1_MPDU_SEQ_NUM, 234*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.mpdu_start.info1)); 235*e678fbd4SKarthikeyan Periyasamy } 236*e678fbd4SKarthikeyan Periyasamy 237*e678fbd4SKarthikeyan Periyasamy static u16 ath11k_hw_ipq8074_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 238*e678fbd4SKarthikeyan Periyasamy { 239*e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 240*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.msdu_start.info1)); 241*e678fbd4SKarthikeyan Periyasamy } 242*e678fbd4SKarthikeyan Periyasamy 243*e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 244*e678fbd4SKarthikeyan Periyasamy { 245*e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO3_SGI, 246*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 247*e678fbd4SKarthikeyan Periyasamy } 248*e678fbd4SKarthikeyan Periyasamy 249*e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 250*e678fbd4SKarthikeyan Periyasamy { 251*e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 252*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 253*e678fbd4SKarthikeyan Periyasamy } 254*e678fbd4SKarthikeyan Periyasamy 255*e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 256*e678fbd4SKarthikeyan Periyasamy { 257*e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 258*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 259*e678fbd4SKarthikeyan Periyasamy } 260*e678fbd4SKarthikeyan Periyasamy 261*e678fbd4SKarthikeyan Periyasamy static u32 ath11k_hw_ipq8074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 262*e678fbd4SKarthikeyan Periyasamy { 263*e678fbd4SKarthikeyan Periyasamy return __le32_to_cpu(desc->u.ipq8074.msdu_start.phy_meta_data); 264*e678fbd4SKarthikeyan Periyasamy } 265*e678fbd4SKarthikeyan Periyasamy 266*e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 267*e678fbd4SKarthikeyan Periyasamy { 268*e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 269*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 270*e678fbd4SKarthikeyan Periyasamy } 271*e678fbd4SKarthikeyan Periyasamy 272*e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_ipq8074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 273*e678fbd4SKarthikeyan Periyasamy { 274*e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 275*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.msdu_start.info3)); 276*e678fbd4SKarthikeyan Periyasamy } 277*e678fbd4SKarthikeyan Periyasamy 278*e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_ipq8074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 279*e678fbd4SKarthikeyan Periyasamy { 280*e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MPDU_START_INFO2_TID, 281*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.mpdu_start.info2)); 282*e678fbd4SKarthikeyan Periyasamy } 283*e678fbd4SKarthikeyan Periyasamy 284*e678fbd4SKarthikeyan Periyasamy static u16 ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 285*e678fbd4SKarthikeyan Periyasamy { 286*e678fbd4SKarthikeyan Periyasamy return __le16_to_cpu(desc->u.ipq8074.mpdu_start.sw_peer_id); 287*e678fbd4SKarthikeyan Periyasamy } 288*e678fbd4SKarthikeyan Periyasamy 289*e678fbd4SKarthikeyan Periyasamy static void ath11k_hw_ipq8074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 290*e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *ldesc) 291*e678fbd4SKarthikeyan Periyasamy { 292*e678fbd4SKarthikeyan Periyasamy memcpy((u8 *)&fdesc->u.ipq8074.msdu_end, (u8 *)&ldesc->u.ipq8074.msdu_end, 293*e678fbd4SKarthikeyan Periyasamy sizeof(struct rx_msdu_end_ipq8074)); 294*e678fbd4SKarthikeyan Periyasamy memcpy((u8 *)&fdesc->u.ipq8074.attention, (u8 *)&ldesc->u.ipq8074.attention, 295*e678fbd4SKarthikeyan Periyasamy sizeof(struct rx_attention)); 296*e678fbd4SKarthikeyan Periyasamy memcpy((u8 *)&fdesc->u.ipq8074.mpdu_end, (u8 *)&ldesc->u.ipq8074.mpdu_end, 297*e678fbd4SKarthikeyan Periyasamy sizeof(struct rx_mpdu_end)); 298*e678fbd4SKarthikeyan Periyasamy } 299*e678fbd4SKarthikeyan Periyasamy 300*e678fbd4SKarthikeyan Periyasamy static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 301*e678fbd4SKarthikeyan Periyasamy { 302*e678fbd4SKarthikeyan Periyasamy return FIELD_GET(HAL_TLV_HDR_TAG, 303*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.ipq8074.mpdu_start_tag)); 304*e678fbd4SKarthikeyan Periyasamy } 305*e678fbd4SKarthikeyan Periyasamy 306*e678fbd4SKarthikeyan Periyasamy static u32 ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 307*e678fbd4SKarthikeyan Periyasamy { 308*e678fbd4SKarthikeyan Periyasamy return __le16_to_cpu(desc->u.ipq8074.mpdu_start.phy_ppdu_id); 309*e678fbd4SKarthikeyan Periyasamy } 310*e678fbd4SKarthikeyan Periyasamy 311*e678fbd4SKarthikeyan Periyasamy static void ath11k_hw_ipq8074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 312*e678fbd4SKarthikeyan Periyasamy { 313*e678fbd4SKarthikeyan Periyasamy u32 info = __le32_to_cpu(desc->u.ipq8074.msdu_start.info1); 314*e678fbd4SKarthikeyan Periyasamy 315*e678fbd4SKarthikeyan Periyasamy info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 316*e678fbd4SKarthikeyan Periyasamy info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 317*e678fbd4SKarthikeyan Periyasamy 318*e678fbd4SKarthikeyan Periyasamy desc->u.ipq8074.msdu_start.info1 = __cpu_to_le32(info); 319*e678fbd4SKarthikeyan Periyasamy } 320*e678fbd4SKarthikeyan Periyasamy 321*e678fbd4SKarthikeyan Periyasamy static 322*e678fbd4SKarthikeyan Periyasamy struct rx_attention *ath11k_hw_ipq8074_rx_desc_get_attention(struct hal_rx_desc *desc) 323*e678fbd4SKarthikeyan Periyasamy { 324*e678fbd4SKarthikeyan Periyasamy return &desc->u.ipq8074.attention; 325*e678fbd4SKarthikeyan Periyasamy } 326*e678fbd4SKarthikeyan Periyasamy 327*e678fbd4SKarthikeyan Periyasamy static u8 *ath11k_hw_ipq8074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 328*e678fbd4SKarthikeyan Periyasamy { 329*e678fbd4SKarthikeyan Periyasamy return &desc->u.ipq8074.msdu_payload[0]; 330*e678fbd4SKarthikeyan Periyasamy } 331*e678fbd4SKarthikeyan Periyasamy 332*e678fbd4SKarthikeyan Periyasamy static bool ath11k_hw_qcn9074_rx_desc_get_first_msdu(struct hal_rx_desc *desc) 333*e678fbd4SKarthikeyan Periyasamy { 334*e678fbd4SKarthikeyan Periyasamy return !!FIELD_GET(RX_MSDU_END_INFO4_FIRST_MSDU, 335*e678fbd4SKarthikeyan Periyasamy __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 336*e678fbd4SKarthikeyan Periyasamy } 337*e678fbd4SKarthikeyan Periyasamy 338*e678fbd4SKarthikeyan Periyasamy static bool ath11k_hw_qcn9074_rx_desc_get_last_msdu(struct hal_rx_desc *desc) 339*e678fbd4SKarthikeyan Periyasamy { 340*e678fbd4SKarthikeyan Periyasamy return !!FIELD_GET(RX_MSDU_END_INFO4_LAST_MSDU, 341*e678fbd4SKarthikeyan Periyasamy __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 342*e678fbd4SKarthikeyan Periyasamy } 343*e678fbd4SKarthikeyan Periyasamy 344*e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes(struct hal_rx_desc *desc) 345*e678fbd4SKarthikeyan Periyasamy { 346*e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_END_INFO4_L3_HDR_PADDING, 347*e678fbd4SKarthikeyan Periyasamy __le16_to_cpu(desc->u.qcn9074.msdu_end.info4)); 348*e678fbd4SKarthikeyan Periyasamy } 349*e678fbd4SKarthikeyan Periyasamy 350*e678fbd4SKarthikeyan Periyasamy static u8 *ath11k_hw_qcn9074_rx_desc_get_hdr_status(struct hal_rx_desc *desc) 351*e678fbd4SKarthikeyan Periyasamy { 352*e678fbd4SKarthikeyan Periyasamy return desc->u.qcn9074.hdr_status; 353*e678fbd4SKarthikeyan Periyasamy } 354*e678fbd4SKarthikeyan Periyasamy 355*e678fbd4SKarthikeyan Periyasamy static bool ath11k_hw_qcn9074_rx_desc_encrypt_valid(struct hal_rx_desc *desc) 356*e678fbd4SKarthikeyan Periyasamy { 357*e678fbd4SKarthikeyan Periyasamy return __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11) & 358*e678fbd4SKarthikeyan Periyasamy RX_MPDU_START_INFO11_ENCRYPT_INFO_VALID; 359*e678fbd4SKarthikeyan Periyasamy } 360*e678fbd4SKarthikeyan Periyasamy 361*e678fbd4SKarthikeyan Periyasamy static u32 ath11k_hw_qcn9074_rx_desc_get_encrypt_type(struct hal_rx_desc *desc) 362*e678fbd4SKarthikeyan Periyasamy { 363*e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MPDU_START_INFO9_ENC_TYPE, 364*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9)); 365*e678fbd4SKarthikeyan Periyasamy } 366*e678fbd4SKarthikeyan Periyasamy 367*e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_qcn9074_rx_desc_get_decap_type(struct hal_rx_desc *desc) 368*e678fbd4SKarthikeyan Periyasamy { 369*e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO2_DECAP_FORMAT, 370*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.qcn9074.msdu_start.info2)); 371*e678fbd4SKarthikeyan Periyasamy } 372*e678fbd4SKarthikeyan Periyasamy 373*e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_qcn9074_rx_desc_get_mesh_ctl(struct hal_rx_desc *desc) 374*e678fbd4SKarthikeyan Periyasamy { 375*e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO2_MESH_CTRL_PRESENT, 376*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.qcn9074.msdu_start.info2)); 377*e678fbd4SKarthikeyan Periyasamy } 378*e678fbd4SKarthikeyan Periyasamy 379*e678fbd4SKarthikeyan Periyasamy static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld(struct hal_rx_desc *desc) 380*e678fbd4SKarthikeyan Periyasamy { 381*e678fbd4SKarthikeyan Periyasamy return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_CTRL_VALID, 382*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 383*e678fbd4SKarthikeyan Periyasamy } 384*e678fbd4SKarthikeyan Periyasamy 385*e678fbd4SKarthikeyan Periyasamy static bool ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid(struct hal_rx_desc *desc) 386*e678fbd4SKarthikeyan Periyasamy { 387*e678fbd4SKarthikeyan Periyasamy return !!FIELD_GET(RX_MPDU_START_INFO11_MPDU_FCTRL_VALID, 388*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 389*e678fbd4SKarthikeyan Periyasamy } 390*e678fbd4SKarthikeyan Periyasamy 391*e678fbd4SKarthikeyan Periyasamy static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no(struct hal_rx_desc *desc) 392*e678fbd4SKarthikeyan Periyasamy { 393*e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MPDU_START_INFO11_MPDU_SEQ_NUM, 394*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.qcn9074.mpdu_start.info11)); 395*e678fbd4SKarthikeyan Periyasamy } 396*e678fbd4SKarthikeyan Periyasamy 397*e678fbd4SKarthikeyan Periyasamy static u16 ath11k_hw_qcn9074_rx_desc_get_msdu_len(struct hal_rx_desc *desc) 398*e678fbd4SKarthikeyan Periyasamy { 399*e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO1_MSDU_LENGTH, 400*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.qcn9074.msdu_start.info1)); 401*e678fbd4SKarthikeyan Periyasamy } 402*e678fbd4SKarthikeyan Periyasamy 403*e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_sgi(struct hal_rx_desc *desc) 404*e678fbd4SKarthikeyan Periyasamy { 405*e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO3_SGI, 406*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 407*e678fbd4SKarthikeyan Periyasamy } 408*e678fbd4SKarthikeyan Periyasamy 409*e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs(struct hal_rx_desc *desc) 410*e678fbd4SKarthikeyan Periyasamy { 411*e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO3_RATE_MCS, 412*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 413*e678fbd4SKarthikeyan Periyasamy } 414*e678fbd4SKarthikeyan Periyasamy 415*e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw(struct hal_rx_desc *desc) 416*e678fbd4SKarthikeyan Periyasamy { 417*e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO3_RECV_BW, 418*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 419*e678fbd4SKarthikeyan Periyasamy } 420*e678fbd4SKarthikeyan Periyasamy 421*e678fbd4SKarthikeyan Periyasamy static u32 ath11k_hw_qcn9074_rx_desc_get_msdu_freq(struct hal_rx_desc *desc) 422*e678fbd4SKarthikeyan Periyasamy { 423*e678fbd4SKarthikeyan Periyasamy return __le32_to_cpu(desc->u.qcn9074.msdu_start.phy_meta_data); 424*e678fbd4SKarthikeyan Periyasamy } 425*e678fbd4SKarthikeyan Periyasamy 426*e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type(struct hal_rx_desc *desc) 427*e678fbd4SKarthikeyan Periyasamy { 428*e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO3_PKT_TYPE, 429*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 430*e678fbd4SKarthikeyan Periyasamy } 431*e678fbd4SKarthikeyan Periyasamy 432*e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_qcn9074_rx_desc_get_msdu_nss(struct hal_rx_desc *desc) 433*e678fbd4SKarthikeyan Periyasamy { 434*e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MSDU_START_INFO3_MIMO_SS_BITMAP, 435*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.qcn9074.msdu_start.info3)); 436*e678fbd4SKarthikeyan Periyasamy } 437*e678fbd4SKarthikeyan Periyasamy 438*e678fbd4SKarthikeyan Periyasamy static u8 ath11k_hw_qcn9074_rx_desc_get_mpdu_tid(struct hal_rx_desc *desc) 439*e678fbd4SKarthikeyan Periyasamy { 440*e678fbd4SKarthikeyan Periyasamy return FIELD_GET(RX_MPDU_START_INFO9_TID, 441*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.qcn9074.mpdu_start.info9)); 442*e678fbd4SKarthikeyan Periyasamy } 443*e678fbd4SKarthikeyan Periyasamy 444*e678fbd4SKarthikeyan Periyasamy static u16 ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id(struct hal_rx_desc *desc) 445*e678fbd4SKarthikeyan Periyasamy { 446*e678fbd4SKarthikeyan Periyasamy return __le16_to_cpu(desc->u.qcn9074.mpdu_start.sw_peer_id); 447*e678fbd4SKarthikeyan Periyasamy } 448*e678fbd4SKarthikeyan Periyasamy 449*e678fbd4SKarthikeyan Periyasamy static void ath11k_hw_qcn9074_rx_desc_copy_attn_end(struct hal_rx_desc *fdesc, 450*e678fbd4SKarthikeyan Periyasamy struct hal_rx_desc *ldesc) 451*e678fbd4SKarthikeyan Periyasamy { 452*e678fbd4SKarthikeyan Periyasamy memcpy((u8 *)&fdesc->u.qcn9074.msdu_end, (u8 *)&ldesc->u.qcn9074.msdu_end, 453*e678fbd4SKarthikeyan Periyasamy sizeof(struct rx_msdu_end_qcn9074)); 454*e678fbd4SKarthikeyan Periyasamy memcpy((u8 *)&fdesc->u.qcn9074.attention, (u8 *)&ldesc->u.qcn9074.attention, 455*e678fbd4SKarthikeyan Periyasamy sizeof(struct rx_attention)); 456*e678fbd4SKarthikeyan Periyasamy memcpy((u8 *)&fdesc->u.qcn9074.mpdu_end, (u8 *)&ldesc->u.qcn9074.mpdu_end, 457*e678fbd4SKarthikeyan Periyasamy sizeof(struct rx_mpdu_end)); 458*e678fbd4SKarthikeyan Periyasamy } 459*e678fbd4SKarthikeyan Periyasamy 460*e678fbd4SKarthikeyan Periyasamy static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag(struct hal_rx_desc *desc) 461*e678fbd4SKarthikeyan Periyasamy { 462*e678fbd4SKarthikeyan Periyasamy return FIELD_GET(HAL_TLV_HDR_TAG, 463*e678fbd4SKarthikeyan Periyasamy __le32_to_cpu(desc->u.qcn9074.mpdu_start_tag)); 464*e678fbd4SKarthikeyan Periyasamy } 465*e678fbd4SKarthikeyan Periyasamy 466*e678fbd4SKarthikeyan Periyasamy static u32 ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id(struct hal_rx_desc *desc) 467*e678fbd4SKarthikeyan Periyasamy { 468*e678fbd4SKarthikeyan Periyasamy return __le16_to_cpu(desc->u.qcn9074.mpdu_start.phy_ppdu_id); 469*e678fbd4SKarthikeyan Periyasamy } 470*e678fbd4SKarthikeyan Periyasamy 471*e678fbd4SKarthikeyan Periyasamy static void ath11k_hw_qcn9074_rx_desc_set_msdu_len(struct hal_rx_desc *desc, u16 len) 472*e678fbd4SKarthikeyan Periyasamy { 473*e678fbd4SKarthikeyan Periyasamy u32 info = __le32_to_cpu(desc->u.qcn9074.msdu_start.info1); 474*e678fbd4SKarthikeyan Periyasamy 475*e678fbd4SKarthikeyan Periyasamy info &= ~RX_MSDU_START_INFO1_MSDU_LENGTH; 476*e678fbd4SKarthikeyan Periyasamy info |= FIELD_PREP(RX_MSDU_START_INFO1_MSDU_LENGTH, len); 477*e678fbd4SKarthikeyan Periyasamy 478*e678fbd4SKarthikeyan Periyasamy desc->u.qcn9074.msdu_start.info1 = __cpu_to_le32(info); 479*e678fbd4SKarthikeyan Periyasamy } 480*e678fbd4SKarthikeyan Periyasamy 481*e678fbd4SKarthikeyan Periyasamy static 482*e678fbd4SKarthikeyan Periyasamy struct rx_attention *ath11k_hw_qcn9074_rx_desc_get_attention(struct hal_rx_desc *desc) 483*e678fbd4SKarthikeyan Periyasamy { 484*e678fbd4SKarthikeyan Periyasamy return &desc->u.qcn9074.attention; 485*e678fbd4SKarthikeyan Periyasamy } 486*e678fbd4SKarthikeyan Periyasamy 487*e678fbd4SKarthikeyan Periyasamy static u8 *ath11k_hw_qcn9074_rx_desc_get_msdu_payload(struct hal_rx_desc *desc) 488*e678fbd4SKarthikeyan Periyasamy { 489*e678fbd4SKarthikeyan Periyasamy return &desc->u.qcn9074.msdu_payload[0]; 490*e678fbd4SKarthikeyan Periyasamy } 491*e678fbd4SKarthikeyan Periyasamy 492d547ca4cSAnilkumar Kolli const struct ath11k_hw_ops ipq8074_ops = { 493d547ca4cSAnilkumar Kolli .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 49436c7c640SKarthikeyan Periyasamy .wmi_init_config = ath11k_init_wmi_config_ipq8074, 4954152e420SCarl Huang .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 4964152e420SCarl Huang .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 4976fe6f68fSKarthikeyan Periyasamy .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 498*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 499*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 500*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 501*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 502*e678fbd4SKarthikeyan Periyasamy .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 503*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 504*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 505*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 506*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 507*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 508*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 509*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 510*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 511*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 512*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 513*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 514*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 515*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 516*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 517*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 518*e678fbd4SKarthikeyan Periyasamy .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 519*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 520*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 521*e678fbd4SKarthikeyan Periyasamy .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 522*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 523*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 524d547ca4cSAnilkumar Kolli }; 525d547ca4cSAnilkumar Kolli 526d547ca4cSAnilkumar Kolli const struct ath11k_hw_ops ipq6018_ops = { 527d547ca4cSAnilkumar Kolli .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 5282d4bcbedSCarl Huang .wmi_init_config = ath11k_init_wmi_config_ipq8074, 5294152e420SCarl Huang .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 5304152e420SCarl Huang .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 5316fe6f68fSKarthikeyan Periyasamy .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 532*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 533*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 534*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 535*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 536*e678fbd4SKarthikeyan Periyasamy .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 537*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 538*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 539*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 540*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 541*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 542*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 543*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 544*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 545*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 546*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 547*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 548*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 549*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 550*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 551*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 552*e678fbd4SKarthikeyan Periyasamy .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 553*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 554*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 555*e678fbd4SKarthikeyan Periyasamy .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 556*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 557*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 558d547ca4cSAnilkumar Kolli }; 5599de2ad43SCarl Huang 5609de2ad43SCarl Huang const struct ath11k_hw_ops qca6390_ops = { 5619de2ad43SCarl Huang .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 5624152e420SCarl Huang .wmi_init_config = ath11k_init_wmi_config_qca6390, 5634152e420SCarl Huang .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390, 5644152e420SCarl Huang .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390, 5656fe6f68fSKarthikeyan Periyasamy .tx_mesh_enable = ath11k_hw_ipq8074_tx_mesh_enable, 566*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_first_msdu = ath11k_hw_ipq8074_rx_desc_get_first_msdu, 567*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_last_msdu = ath11k_hw_ipq8074_rx_desc_get_last_msdu, 568*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_l3_pad_bytes = ath11k_hw_ipq8074_rx_desc_get_l3_pad_bytes, 569*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_hdr_status = ath11k_hw_ipq8074_rx_desc_get_hdr_status, 570*e678fbd4SKarthikeyan Periyasamy .rx_desc_encrypt_valid = ath11k_hw_ipq8074_rx_desc_encrypt_valid, 571*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_encrypt_type = ath11k_hw_ipq8074_rx_desc_get_encrypt_type, 572*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_decap_type = ath11k_hw_ipq8074_rx_desc_get_decap_type, 573*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mesh_ctl = ath11k_hw_ipq8074_rx_desc_get_mesh_ctl, 574*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_ipq8074_rx_desc_get_mpdu_seq_ctl_vld, 575*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_fc_valid = ath11k_hw_ipq8074_rx_desc_get_mpdu_fc_valid, 576*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_start_seq_no = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_seq_no, 577*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_len = ath11k_hw_ipq8074_rx_desc_get_msdu_len, 578*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_sgi = ath11k_hw_ipq8074_rx_desc_get_msdu_sgi, 579*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_rate_mcs = ath11k_hw_ipq8074_rx_desc_get_msdu_rate_mcs, 580*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_rx_bw = ath11k_hw_ipq8074_rx_desc_get_msdu_rx_bw, 581*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_freq = ath11k_hw_ipq8074_rx_desc_get_msdu_freq, 582*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_pkt_type = ath11k_hw_ipq8074_rx_desc_get_msdu_pkt_type, 583*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_nss = ath11k_hw_ipq8074_rx_desc_get_msdu_nss, 584*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_tid = ath11k_hw_ipq8074_rx_desc_get_mpdu_tid, 585*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_peer_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_peer_id, 586*e678fbd4SKarthikeyan Periyasamy .rx_desc_copy_attn_end_tlv = ath11k_hw_ipq8074_rx_desc_copy_attn_end, 587*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_start_tag = ath11k_hw_ipq8074_rx_desc_get_mpdu_start_tag, 588*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_ppdu_id = ath11k_hw_ipq8074_rx_desc_get_mpdu_ppdu_id, 589*e678fbd4SKarthikeyan Periyasamy .rx_desc_set_msdu_len = ath11k_hw_ipq8074_rx_desc_set_msdu_len, 590*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_attention = ath11k_hw_ipq8074_rx_desc_get_attention, 591*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_payload = ath11k_hw_ipq8074_rx_desc_get_msdu_payload, 5926fe6f68fSKarthikeyan Periyasamy }; 5936fe6f68fSKarthikeyan Periyasamy 5946fe6f68fSKarthikeyan Periyasamy const struct ath11k_hw_ops qcn9074_ops = { 5956fe6f68fSKarthikeyan Periyasamy .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 5966fe6f68fSKarthikeyan Periyasamy .wmi_init_config = ath11k_init_wmi_config_ipq8074, 5976fe6f68fSKarthikeyan Periyasamy .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 5986fe6f68fSKarthikeyan Periyasamy .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 5996fe6f68fSKarthikeyan Periyasamy .tx_mesh_enable = ath11k_hw_qcn9074_tx_mesh_enable, 600*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_first_msdu = ath11k_hw_qcn9074_rx_desc_get_first_msdu, 601*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_last_msdu = ath11k_hw_qcn9074_rx_desc_get_last_msdu, 602*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_l3_pad_bytes = ath11k_hw_qcn9074_rx_desc_get_l3_pad_bytes, 603*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_hdr_status = ath11k_hw_qcn9074_rx_desc_get_hdr_status, 604*e678fbd4SKarthikeyan Periyasamy .rx_desc_encrypt_valid = ath11k_hw_qcn9074_rx_desc_encrypt_valid, 605*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_encrypt_type = ath11k_hw_qcn9074_rx_desc_get_encrypt_type, 606*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_decap_type = ath11k_hw_qcn9074_rx_desc_get_decap_type, 607*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mesh_ctl = ath11k_hw_qcn9074_rx_desc_get_mesh_ctl, 608*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_seq_ctl_vld = ath11k_hw_qcn9074_rx_desc_get_mpdu_seq_ctl_vld, 609*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_fc_valid = ath11k_hw_qcn9074_rx_desc_get_mpdu_fc_valid, 610*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_start_seq_no = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_seq_no, 611*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_len = ath11k_hw_qcn9074_rx_desc_get_msdu_len, 612*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_sgi = ath11k_hw_qcn9074_rx_desc_get_msdu_sgi, 613*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_rate_mcs = ath11k_hw_qcn9074_rx_desc_get_msdu_rate_mcs, 614*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_rx_bw = ath11k_hw_qcn9074_rx_desc_get_msdu_rx_bw, 615*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_freq = ath11k_hw_qcn9074_rx_desc_get_msdu_freq, 616*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_pkt_type = ath11k_hw_qcn9074_rx_desc_get_msdu_pkt_type, 617*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_nss = ath11k_hw_qcn9074_rx_desc_get_msdu_nss, 618*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_tid = ath11k_hw_qcn9074_rx_desc_get_mpdu_tid, 619*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_peer_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_peer_id, 620*e678fbd4SKarthikeyan Periyasamy .rx_desc_copy_attn_end_tlv = ath11k_hw_qcn9074_rx_desc_copy_attn_end, 621*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_start_tag = ath11k_hw_qcn9074_rx_desc_get_mpdu_start_tag, 622*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_mpdu_ppdu_id = ath11k_hw_qcn9074_rx_desc_get_mpdu_ppdu_id, 623*e678fbd4SKarthikeyan Periyasamy .rx_desc_set_msdu_len = ath11k_hw_qcn9074_rx_desc_set_msdu_len, 624*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_attention = ath11k_hw_qcn9074_rx_desc_get_attention, 625*e678fbd4SKarthikeyan Periyasamy .rx_desc_get_msdu_payload = ath11k_hw_qcn9074_rx_desc_get_msdu_payload, 6269de2ad43SCarl Huang }; 62734d5a3a8SKalle Valo 62834d5a3a8SKalle Valo #define ATH11K_TX_RING_MASK_0 0x1 62934d5a3a8SKalle Valo #define ATH11K_TX_RING_MASK_1 0x2 63034d5a3a8SKalle Valo #define ATH11K_TX_RING_MASK_2 0x4 63134d5a3a8SKalle Valo 63234d5a3a8SKalle Valo #define ATH11K_RX_RING_MASK_0 0x1 63334d5a3a8SKalle Valo #define ATH11K_RX_RING_MASK_1 0x2 63434d5a3a8SKalle Valo #define ATH11K_RX_RING_MASK_2 0x4 63534d5a3a8SKalle Valo #define ATH11K_RX_RING_MASK_3 0x8 63634d5a3a8SKalle Valo 63734d5a3a8SKalle Valo #define ATH11K_RX_ERR_RING_MASK_0 0x1 63834d5a3a8SKalle Valo 63934d5a3a8SKalle Valo #define ATH11K_RX_WBM_REL_RING_MASK_0 0x1 64034d5a3a8SKalle Valo 64134d5a3a8SKalle Valo #define ATH11K_REO_STATUS_RING_MASK_0 0x1 64234d5a3a8SKalle Valo 64334d5a3a8SKalle Valo #define ATH11K_RXDMA2HOST_RING_MASK_0 0x1 64434d5a3a8SKalle Valo #define ATH11K_RXDMA2HOST_RING_MASK_1 0x2 64534d5a3a8SKalle Valo #define ATH11K_RXDMA2HOST_RING_MASK_2 0x4 64634d5a3a8SKalle Valo 64734d5a3a8SKalle Valo #define ATH11K_HOST2RXDMA_RING_MASK_0 0x1 64834d5a3a8SKalle Valo #define ATH11K_HOST2RXDMA_RING_MASK_1 0x2 64934d5a3a8SKalle Valo #define ATH11K_HOST2RXDMA_RING_MASK_2 0x4 65034d5a3a8SKalle Valo 65134d5a3a8SKalle Valo #define ATH11K_RX_MON_STATUS_RING_MASK_0 0x1 65234d5a3a8SKalle Valo #define ATH11K_RX_MON_STATUS_RING_MASK_1 0x2 65334d5a3a8SKalle Valo #define ATH11K_RX_MON_STATUS_RING_MASK_2 0x4 65434d5a3a8SKalle Valo 65534d5a3a8SKalle Valo const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074 = { 65634d5a3a8SKalle Valo .tx = { 65734d5a3a8SKalle Valo ATH11K_TX_RING_MASK_0, 65834d5a3a8SKalle Valo ATH11K_TX_RING_MASK_1, 65934d5a3a8SKalle Valo ATH11K_TX_RING_MASK_2, 66034d5a3a8SKalle Valo }, 66134d5a3a8SKalle Valo .rx_mon_status = { 66234d5a3a8SKalle Valo 0, 0, 0, 0, 66334d5a3a8SKalle Valo ATH11K_RX_MON_STATUS_RING_MASK_0, 66434d5a3a8SKalle Valo ATH11K_RX_MON_STATUS_RING_MASK_1, 66534d5a3a8SKalle Valo ATH11K_RX_MON_STATUS_RING_MASK_2, 66634d5a3a8SKalle Valo }, 66734d5a3a8SKalle Valo .rx = { 66834d5a3a8SKalle Valo 0, 0, 0, 0, 0, 0, 0, 66934d5a3a8SKalle Valo ATH11K_RX_RING_MASK_0, 67034d5a3a8SKalle Valo ATH11K_RX_RING_MASK_1, 67134d5a3a8SKalle Valo ATH11K_RX_RING_MASK_2, 67234d5a3a8SKalle Valo ATH11K_RX_RING_MASK_3, 67334d5a3a8SKalle Valo }, 67434d5a3a8SKalle Valo .rx_err = { 67534d5a3a8SKalle Valo ATH11K_RX_ERR_RING_MASK_0, 67634d5a3a8SKalle Valo }, 67734d5a3a8SKalle Valo .rx_wbm_rel = { 67834d5a3a8SKalle Valo ATH11K_RX_WBM_REL_RING_MASK_0, 67934d5a3a8SKalle Valo }, 68034d5a3a8SKalle Valo .reo_status = { 68134d5a3a8SKalle Valo ATH11K_REO_STATUS_RING_MASK_0, 68234d5a3a8SKalle Valo }, 68334d5a3a8SKalle Valo .rxdma2host = { 68434d5a3a8SKalle Valo ATH11K_RXDMA2HOST_RING_MASK_0, 68534d5a3a8SKalle Valo ATH11K_RXDMA2HOST_RING_MASK_1, 68634d5a3a8SKalle Valo ATH11K_RXDMA2HOST_RING_MASK_2, 68734d5a3a8SKalle Valo }, 68834d5a3a8SKalle Valo .host2rxdma = { 68934d5a3a8SKalle Valo ATH11K_HOST2RXDMA_RING_MASK_0, 69034d5a3a8SKalle Valo ATH11K_HOST2RXDMA_RING_MASK_1, 69134d5a3a8SKalle Valo ATH11K_HOST2RXDMA_RING_MASK_2, 69234d5a3a8SKalle Valo }, 69334d5a3a8SKalle Valo }; 69434d5a3a8SKalle Valo 695d4ecb90bSCarl Huang const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390 = { 696d4ecb90bSCarl Huang .tx = { 697d4ecb90bSCarl Huang ATH11K_TX_RING_MASK_0, 698d4ecb90bSCarl Huang ATH11K_TX_RING_MASK_1, 699d4ecb90bSCarl Huang ATH11K_TX_RING_MASK_2, 700d4ecb90bSCarl Huang }, 701d4ecb90bSCarl Huang .rx_mon_status = { 702d4ecb90bSCarl Huang 0, 0, 0, 0, 703d4ecb90bSCarl Huang ATH11K_RX_MON_STATUS_RING_MASK_0, 704d4ecb90bSCarl Huang ATH11K_RX_MON_STATUS_RING_MASK_1, 705d4ecb90bSCarl Huang ATH11K_RX_MON_STATUS_RING_MASK_2, 706d4ecb90bSCarl Huang }, 707d4ecb90bSCarl Huang .rx = { 708d4ecb90bSCarl Huang 0, 0, 0, 0, 0, 0, 0, 709d4ecb90bSCarl Huang ATH11K_RX_RING_MASK_0, 710d4ecb90bSCarl Huang ATH11K_RX_RING_MASK_1, 711d4ecb90bSCarl Huang ATH11K_RX_RING_MASK_2, 712d4ecb90bSCarl Huang ATH11K_RX_RING_MASK_3, 713d4ecb90bSCarl Huang }, 714d4ecb90bSCarl Huang .rx_err = { 715d4ecb90bSCarl Huang ATH11K_RX_ERR_RING_MASK_0, 716d4ecb90bSCarl Huang }, 717d4ecb90bSCarl Huang .rx_wbm_rel = { 718d4ecb90bSCarl Huang ATH11K_RX_WBM_REL_RING_MASK_0, 719d4ecb90bSCarl Huang }, 720d4ecb90bSCarl Huang .reo_status = { 721d4ecb90bSCarl Huang ATH11K_REO_STATUS_RING_MASK_0, 722d4ecb90bSCarl Huang }, 723d4ecb90bSCarl Huang .rxdma2host = { 724d4ecb90bSCarl Huang ATH11K_RXDMA2HOST_RING_MASK_0, 725d4ecb90bSCarl Huang ATH11K_RXDMA2HOST_RING_MASK_1, 726d4ecb90bSCarl Huang ATH11K_RXDMA2HOST_RING_MASK_2, 727d4ecb90bSCarl Huang }, 728d4ecb90bSCarl Huang .host2rxdma = { 729d4ecb90bSCarl Huang }, 730d4ecb90bSCarl Huang }; 731d4ecb90bSCarl Huang 732967c1d11SAnilkumar Kolli /* Target firmware's Copy Engine configuration. */ 733967c1d11SAnilkumar Kolli const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq8074[] = { 734967c1d11SAnilkumar Kolli /* CE0: host->target HTC control and raw streams */ 735967c1d11SAnilkumar Kolli { 736967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(0), 737967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), 738967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 739967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 740967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 741967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 742967c1d11SAnilkumar Kolli }, 743967c1d11SAnilkumar Kolli 744967c1d11SAnilkumar Kolli /* CE1: target->host HTT + HTC control */ 745967c1d11SAnilkumar Kolli { 746967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(1), 747967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), 748967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 749967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 750967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 751967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 752967c1d11SAnilkumar Kolli }, 753967c1d11SAnilkumar Kolli 754967c1d11SAnilkumar Kolli /* CE2: target->host WMI */ 755967c1d11SAnilkumar Kolli { 756967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(2), 757967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), 758967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 759967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 760967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 761967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 762967c1d11SAnilkumar Kolli }, 763967c1d11SAnilkumar Kolli 764967c1d11SAnilkumar Kolli /* CE3: host->target WMI */ 765967c1d11SAnilkumar Kolli { 766967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(3), 767967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), 768967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 769967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 770967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 771967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 772967c1d11SAnilkumar Kolli }, 773967c1d11SAnilkumar Kolli 774967c1d11SAnilkumar Kolli /* CE4: host->target HTT */ 775967c1d11SAnilkumar Kolli { 776967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(4), 777967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), 778967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(256), 779967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(256), 780967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 781967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 782967c1d11SAnilkumar Kolli }, 783967c1d11SAnilkumar Kolli 784967c1d11SAnilkumar Kolli /* CE5: target->host Pktlog */ 785967c1d11SAnilkumar Kolli { 786967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(5), 787967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), 788967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 789967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 790967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(0), 791967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 792967c1d11SAnilkumar Kolli }, 793967c1d11SAnilkumar Kolli 794967c1d11SAnilkumar Kolli /* CE6: Reserved for target autonomous hif_memcpy */ 795967c1d11SAnilkumar Kolli { 796967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(6), 797967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 798967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 799967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(65535), 800967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 801967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 802967c1d11SAnilkumar Kolli }, 803967c1d11SAnilkumar Kolli 804967c1d11SAnilkumar Kolli /* CE7 used only by Host */ 805967c1d11SAnilkumar Kolli { 806967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(7), 807967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), 808967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 809967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 810967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 811967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 812967c1d11SAnilkumar Kolli }, 813967c1d11SAnilkumar Kolli 814967c1d11SAnilkumar Kolli /* CE8 target->host used only by IPA */ 815967c1d11SAnilkumar Kolli { 816967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(8), 817967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 818967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 819967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(65535), 820967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 821967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 822967c1d11SAnilkumar Kolli }, 823967c1d11SAnilkumar Kolli 824967c1d11SAnilkumar Kolli /* CE9 host->target HTT */ 825967c1d11SAnilkumar Kolli { 826967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(9), 827967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), 828967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 829967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 830967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 831967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 832967c1d11SAnilkumar Kolli }, 833967c1d11SAnilkumar Kolli 834967c1d11SAnilkumar Kolli /* CE10 target->host HTT */ 835967c1d11SAnilkumar Kolli { 836967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(10), 837967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 838967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(0), 839967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(0), 840967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 841967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 842967c1d11SAnilkumar Kolli }, 843967c1d11SAnilkumar Kolli 844967c1d11SAnilkumar Kolli /* CE11 Not used */ 845967c1d11SAnilkumar Kolli }; 846967c1d11SAnilkumar Kolli 847967c1d11SAnilkumar Kolli /* Map from service/endpoint to Copy Engine. 848967c1d11SAnilkumar Kolli * This table is derived from the CE_PCI TABLE, above. 849967c1d11SAnilkumar Kolli * It is passed to the Target at startup for use by firmware. 850967c1d11SAnilkumar Kolli */ 851967c1d11SAnilkumar Kolli const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq8074[] = { 852967c1d11SAnilkumar Kolli { 853967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 854967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 855967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(3), 856967c1d11SAnilkumar Kolli }, 857967c1d11SAnilkumar Kolli { 858967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 859967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 860967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(2), 861967c1d11SAnilkumar Kolli }, 862967c1d11SAnilkumar Kolli { 863967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 864967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 865967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(3), 866967c1d11SAnilkumar Kolli }, 867967c1d11SAnilkumar Kolli { 868967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 869967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 870967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(2), 871967c1d11SAnilkumar Kolli }, 872967c1d11SAnilkumar Kolli { 873967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 874967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 875967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(3), 876967c1d11SAnilkumar Kolli }, 877967c1d11SAnilkumar Kolli { 878967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 879967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 880967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(2), 881967c1d11SAnilkumar Kolli }, 882967c1d11SAnilkumar Kolli { 883967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 884967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 885967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(3), 886967c1d11SAnilkumar Kolli }, 887967c1d11SAnilkumar Kolli { 888967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 889967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 890967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(2), 891967c1d11SAnilkumar Kolli }, 892967c1d11SAnilkumar Kolli { 893967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 894967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 895967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(3), 896967c1d11SAnilkumar Kolli }, 897967c1d11SAnilkumar Kolli { 898967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 899967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 900967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(2), 901967c1d11SAnilkumar Kolli }, 902967c1d11SAnilkumar Kolli { 903967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 904967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 905967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(7), 906967c1d11SAnilkumar Kolli }, 907967c1d11SAnilkumar Kolli { 908967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 909967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 910967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(2), 911967c1d11SAnilkumar Kolli }, 912967c1d11SAnilkumar Kolli { 913967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2), 914967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 915967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(9), 916967c1d11SAnilkumar Kolli }, 917967c1d11SAnilkumar Kolli { 918967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2), 919967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 920967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(2), 921967c1d11SAnilkumar Kolli }, 922967c1d11SAnilkumar Kolli { 923967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 924967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 925967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(0), 926967c1d11SAnilkumar Kolli }, 927967c1d11SAnilkumar Kolli { 928967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 929967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 930967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(1), 931967c1d11SAnilkumar Kolli }, 932967c1d11SAnilkumar Kolli { /* not used */ 933967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 934967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 935967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(0), 936967c1d11SAnilkumar Kolli }, 937967c1d11SAnilkumar Kolli { /* not used */ 938967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 939967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 940967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(1), 941967c1d11SAnilkumar Kolli }, 942967c1d11SAnilkumar Kolli { 943967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 944967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 945967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(4), 946967c1d11SAnilkumar Kolli }, 947967c1d11SAnilkumar Kolli { 948967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 949967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 950967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(1), 951967c1d11SAnilkumar Kolli }, 952967c1d11SAnilkumar Kolli { 953967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 954967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 955967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(5), 956967c1d11SAnilkumar Kolli }, 957967c1d11SAnilkumar Kolli 958967c1d11SAnilkumar Kolli /* (Additions here) */ 959967c1d11SAnilkumar Kolli 960967c1d11SAnilkumar Kolli { /* terminator entry */ } 961967c1d11SAnilkumar Kolli }; 962967c1d11SAnilkumar Kolli 963b129699aSAnilkumar Kolli const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq6018[] = { 964b129699aSAnilkumar Kolli { 965b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 966b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 967b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(3), 968b129699aSAnilkumar Kolli }, 969b129699aSAnilkumar Kolli { 970b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 971b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 972b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(2), 973b129699aSAnilkumar Kolli }, 974b129699aSAnilkumar Kolli { 975b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 976b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 977b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(3), 978b129699aSAnilkumar Kolli }, 979b129699aSAnilkumar Kolli { 980b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 981b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 982b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(2), 983b129699aSAnilkumar Kolli }, 984b129699aSAnilkumar Kolli { 985b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 986b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 987b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(3), 988b129699aSAnilkumar Kolli }, 989b129699aSAnilkumar Kolli { 990b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 991b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 992b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(2), 993b129699aSAnilkumar Kolli }, 994b129699aSAnilkumar Kolli { 995b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 996b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 997b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(3), 998b129699aSAnilkumar Kolli }, 999b129699aSAnilkumar Kolli { 1000b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1001b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1002b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(2), 1003b129699aSAnilkumar Kolli }, 1004b129699aSAnilkumar Kolli { 1005b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1006b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1007b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(3), 1008b129699aSAnilkumar Kolli }, 1009b129699aSAnilkumar Kolli { 1010b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1011b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1012b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(2), 1013b129699aSAnilkumar Kolli }, 1014b129699aSAnilkumar Kolli { 1015b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1016b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1017b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(7), 1018b129699aSAnilkumar Kolli }, 1019b129699aSAnilkumar Kolli { 1020b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 1021b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1022b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(2), 1023b129699aSAnilkumar Kolli }, 1024b129699aSAnilkumar Kolli { 1025b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1026b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1027b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(0), 1028b129699aSAnilkumar Kolli }, 1029b129699aSAnilkumar Kolli { 1030b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1031b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1032b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(1), 1033b129699aSAnilkumar Kolli }, 1034b129699aSAnilkumar Kolli { /* not used */ 1035b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1036b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1037b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(0), 1038b129699aSAnilkumar Kolli }, 1039b129699aSAnilkumar Kolli { /* not used */ 1040b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 1041b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1042b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(1), 1043b129699aSAnilkumar Kolli }, 1044b129699aSAnilkumar Kolli { 1045b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1046b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1047b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(4), 1048b129699aSAnilkumar Kolli }, 1049b129699aSAnilkumar Kolli { 1050b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1051b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1052b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(1), 1053b129699aSAnilkumar Kolli }, 1054b129699aSAnilkumar Kolli { 1055b129699aSAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 1056b129699aSAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1057b129699aSAnilkumar Kolli .pipenum = __cpu_to_le32(5), 1058b129699aSAnilkumar Kolli }, 1059b129699aSAnilkumar Kolli 1060b129699aSAnilkumar Kolli /* (Additions here) */ 1061b129699aSAnilkumar Kolli 1062b129699aSAnilkumar Kolli { /* terminator entry */ } 1063b129699aSAnilkumar Kolli }; 1064b129699aSAnilkumar Kolli 1065967c1d11SAnilkumar Kolli /* Target firmware's Copy Engine configuration. */ 1066967c1d11SAnilkumar Kolli const struct ce_pipe_config ath11k_target_ce_config_wlan_qca6390[] = { 1067967c1d11SAnilkumar Kolli /* CE0: host->target HTC control and raw streams */ 1068967c1d11SAnilkumar Kolli { 1069967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(0), 1070967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1071967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 1072967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 1073967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1074967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 1075967c1d11SAnilkumar Kolli }, 1076967c1d11SAnilkumar Kolli 1077967c1d11SAnilkumar Kolli /* CE1: target->host HTT + HTC control */ 1078967c1d11SAnilkumar Kolli { 1079967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(1), 1080967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), 1081967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 1082967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 1083967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1084967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 1085967c1d11SAnilkumar Kolli }, 1086967c1d11SAnilkumar Kolli 1087967c1d11SAnilkumar Kolli /* CE2: target->host WMI */ 1088967c1d11SAnilkumar Kolli { 1089967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(2), 1090967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), 1091967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 1092967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 1093967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1094967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 1095967c1d11SAnilkumar Kolli }, 1096967c1d11SAnilkumar Kolli 1097967c1d11SAnilkumar Kolli /* CE3: host->target WMI */ 1098967c1d11SAnilkumar Kolli { 1099967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(3), 1100967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1101967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 1102967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 1103967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1104967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 1105967c1d11SAnilkumar Kolli }, 1106967c1d11SAnilkumar Kolli 1107967c1d11SAnilkumar Kolli /* CE4: host->target HTT */ 1108967c1d11SAnilkumar Kolli { 1109967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(4), 1110967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), 1111967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(256), 1112967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(256), 1113967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1114967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 1115967c1d11SAnilkumar Kolli }, 1116967c1d11SAnilkumar Kolli 1117967c1d11SAnilkumar Kolli /* CE5: target->host Pktlog */ 1118967c1d11SAnilkumar Kolli { 1119967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(5), 1120967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), 1121967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 1122967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 1123967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1124967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 1125967c1d11SAnilkumar Kolli }, 1126967c1d11SAnilkumar Kolli 1127967c1d11SAnilkumar Kolli /* CE6: Reserved for target autonomous hif_memcpy */ 1128967c1d11SAnilkumar Kolli { 1129967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(6), 1130967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1131967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 1132967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(16384), 1133967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1134967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 1135967c1d11SAnilkumar Kolli }, 1136967c1d11SAnilkumar Kolli 1137967c1d11SAnilkumar Kolli /* CE7 used only by Host */ 1138967c1d11SAnilkumar Kolli { 1139967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(7), 1140967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 1141967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(0), 1142967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(0), 1143967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 1144967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 1145967c1d11SAnilkumar Kolli }, 1146967c1d11SAnilkumar Kolli 1147967c1d11SAnilkumar Kolli /* CE8 target->host used only by IPA */ 1148967c1d11SAnilkumar Kolli { 1149967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(8), 1150967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 1151967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 1152967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(16384), 1153967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 1154967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 1155967c1d11SAnilkumar Kolli }, 1156967c1d11SAnilkumar Kolli /* CE 9, 10, 11 are used by MHI driver */ 1157967c1d11SAnilkumar Kolli }; 1158967c1d11SAnilkumar Kolli 1159967c1d11SAnilkumar Kolli /* Map from service/endpoint to Copy Engine. 1160967c1d11SAnilkumar Kolli * This table is derived from the CE_PCI TABLE, above. 1161967c1d11SAnilkumar Kolli * It is passed to the Target at startup for use by firmware. 1162967c1d11SAnilkumar Kolli */ 1163967c1d11SAnilkumar Kolli const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qca6390[] = { 1164967c1d11SAnilkumar Kolli { 1165967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1166967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1167967c1d11SAnilkumar Kolli __cpu_to_le32(3), 1168967c1d11SAnilkumar Kolli }, 1169967c1d11SAnilkumar Kolli { 1170967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 1171967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1172967c1d11SAnilkumar Kolli __cpu_to_le32(2), 1173967c1d11SAnilkumar Kolli }, 1174967c1d11SAnilkumar Kolli { 1175967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1176967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1177967c1d11SAnilkumar Kolli __cpu_to_le32(3), 1178967c1d11SAnilkumar Kolli }, 1179967c1d11SAnilkumar Kolli { 1180967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 1181967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1182967c1d11SAnilkumar Kolli __cpu_to_le32(2), 1183967c1d11SAnilkumar Kolli }, 1184967c1d11SAnilkumar Kolli { 1185967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1186967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1187967c1d11SAnilkumar Kolli __cpu_to_le32(3), 1188967c1d11SAnilkumar Kolli }, 1189967c1d11SAnilkumar Kolli { 1190967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 1191967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1192967c1d11SAnilkumar Kolli __cpu_to_le32(2), 1193967c1d11SAnilkumar Kolli }, 1194967c1d11SAnilkumar Kolli { 1195967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1196967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1197967c1d11SAnilkumar Kolli __cpu_to_le32(3), 1198967c1d11SAnilkumar Kolli }, 1199967c1d11SAnilkumar Kolli { 1200967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 1201967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1202967c1d11SAnilkumar Kolli __cpu_to_le32(2), 1203967c1d11SAnilkumar Kolli }, 1204967c1d11SAnilkumar Kolli { 1205967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1206967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1207967c1d11SAnilkumar Kolli __cpu_to_le32(3), 1208967c1d11SAnilkumar Kolli }, 1209967c1d11SAnilkumar Kolli { 1210967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 1211967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1212967c1d11SAnilkumar Kolli __cpu_to_le32(2), 1213967c1d11SAnilkumar Kolli }, 1214967c1d11SAnilkumar Kolli { 1215967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1216967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1217967c1d11SAnilkumar Kolli __cpu_to_le32(0), 1218967c1d11SAnilkumar Kolli }, 1219967c1d11SAnilkumar Kolli { 1220967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 1221967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1222967c1d11SAnilkumar Kolli __cpu_to_le32(2), 1223967c1d11SAnilkumar Kolli }, 1224967c1d11SAnilkumar Kolli { 1225967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1226967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 1227967c1d11SAnilkumar Kolli __cpu_to_le32(4), 1228967c1d11SAnilkumar Kolli }, 1229967c1d11SAnilkumar Kolli { 1230967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 1231967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 1232967c1d11SAnilkumar Kolli __cpu_to_le32(1), 1233967c1d11SAnilkumar Kolli }, 1234967c1d11SAnilkumar Kolli 1235967c1d11SAnilkumar Kolli /* (Additions here) */ 1236967c1d11SAnilkumar Kolli 1237967c1d11SAnilkumar Kolli { /* must be last */ 1238967c1d11SAnilkumar Kolli __cpu_to_le32(0), 1239967c1d11SAnilkumar Kolli __cpu_to_le32(0), 1240967c1d11SAnilkumar Kolli __cpu_to_le32(0), 1241967c1d11SAnilkumar Kolli }, 1242967c1d11SAnilkumar Kolli }; 1243967c1d11SAnilkumar Kolli 12446976433cSCarl Huang const struct ath11k_hw_regs ipq8074_regs = { 12456976433cSCarl Huang /* SW2TCL(x) R0 ring configuration address */ 12466976433cSCarl Huang .hal_tcl1_ring_base_lsb = 0x00000510, 12476976433cSCarl Huang .hal_tcl1_ring_base_msb = 0x00000514, 12486976433cSCarl Huang .hal_tcl1_ring_id = 0x00000518, 12496976433cSCarl Huang .hal_tcl1_ring_misc = 0x00000520, 12506976433cSCarl Huang .hal_tcl1_ring_tp_addr_lsb = 0x0000052c, 12516976433cSCarl Huang .hal_tcl1_ring_tp_addr_msb = 0x00000530, 12526976433cSCarl Huang .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000540, 12536976433cSCarl Huang .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000544, 12546976433cSCarl Huang .hal_tcl1_ring_msi1_base_lsb = 0x00000558, 12556976433cSCarl Huang .hal_tcl1_ring_msi1_base_msb = 0x0000055c, 12566976433cSCarl Huang .hal_tcl1_ring_msi1_data = 0x00000560, 12576976433cSCarl Huang .hal_tcl2_ring_base_lsb = 0x00000568, 12586976433cSCarl Huang .hal_tcl_ring_base_lsb = 0x00000618, 12596976433cSCarl Huang 12606976433cSCarl Huang /* TCL STATUS ring address */ 12616976433cSCarl Huang .hal_tcl_status_ring_base_lsb = 0x00000720, 12626976433cSCarl Huang 12636976433cSCarl Huang /* REO2SW(x) R0 ring configuration address */ 12646976433cSCarl Huang .hal_reo1_ring_base_lsb = 0x0000029c, 12656976433cSCarl Huang .hal_reo1_ring_base_msb = 0x000002a0, 12666976433cSCarl Huang .hal_reo1_ring_id = 0x000002a4, 12676976433cSCarl Huang .hal_reo1_ring_misc = 0x000002ac, 12686976433cSCarl Huang .hal_reo1_ring_hp_addr_lsb = 0x000002b0, 12696976433cSCarl Huang .hal_reo1_ring_hp_addr_msb = 0x000002b4, 12706976433cSCarl Huang .hal_reo1_ring_producer_int_setup = 0x000002c0, 12716976433cSCarl Huang .hal_reo1_ring_msi1_base_lsb = 0x000002e4, 12726976433cSCarl Huang .hal_reo1_ring_msi1_base_msb = 0x000002e8, 12736976433cSCarl Huang .hal_reo1_ring_msi1_data = 0x000002ec, 12746976433cSCarl Huang .hal_reo2_ring_base_lsb = 0x000002f4, 12756976433cSCarl Huang .hal_reo1_aging_thresh_ix_0 = 0x00000564, 12766976433cSCarl Huang .hal_reo1_aging_thresh_ix_1 = 0x00000568, 12776976433cSCarl Huang .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 12786976433cSCarl Huang .hal_reo1_aging_thresh_ix_3 = 0x00000570, 12796976433cSCarl Huang 12806976433cSCarl Huang /* REO2SW(x) R2 ring pointers (head/tail) address */ 12816976433cSCarl Huang .hal_reo1_ring_hp = 0x00003038, 12826976433cSCarl Huang .hal_reo1_ring_tp = 0x0000303c, 12836976433cSCarl Huang .hal_reo2_ring_hp = 0x00003040, 12846976433cSCarl Huang 12856976433cSCarl Huang /* REO2TCL R0 ring configuration address */ 12866976433cSCarl Huang .hal_reo_tcl_ring_base_lsb = 0x000003fc, 12876976433cSCarl Huang .hal_reo_tcl_ring_hp = 0x00003058, 12886976433cSCarl Huang 12896976433cSCarl Huang /* REO status address */ 12906976433cSCarl Huang .hal_reo_status_ring_base_lsb = 0x00000504, 12916976433cSCarl Huang .hal_reo_status_hp = 0x00003070, 12926976433cSCarl Huang 12936fe6f68fSKarthikeyan Periyasamy /* WCSS relative address */ 12946fe6f68fSKarthikeyan Periyasamy .hal_seq_wcss_umac_ce0_src_reg = 0x00a00000, 12956fe6f68fSKarthikeyan Periyasamy .hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000, 12966fe6f68fSKarthikeyan Periyasamy .hal_seq_wcss_umac_ce1_src_reg = 0x00a02000, 12976fe6f68fSKarthikeyan Periyasamy .hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000, 12986fe6f68fSKarthikeyan Periyasamy 12996fe6f68fSKarthikeyan Periyasamy /* WBM Idle address */ 13006fe6f68fSKarthikeyan Periyasamy .hal_wbm_idle_link_ring_base_lsb = 0x00000860, 13016fe6f68fSKarthikeyan Periyasamy .hal_wbm_idle_link_ring_misc = 0x00000870, 13026fe6f68fSKarthikeyan Periyasamy 13036fe6f68fSKarthikeyan Periyasamy /* SW2WBM release address */ 13046fe6f68fSKarthikeyan Periyasamy .hal_wbm_release_ring_base_lsb = 0x000001d8, 13056fe6f68fSKarthikeyan Periyasamy 13066fe6f68fSKarthikeyan Periyasamy /* WBM2SW release address */ 13076fe6f68fSKarthikeyan Periyasamy .hal_wbm0_release_ring_base_lsb = 0x00000910, 13086fe6f68fSKarthikeyan Periyasamy .hal_wbm1_release_ring_base_lsb = 0x00000968, 13096fe6f68fSKarthikeyan Periyasamy 13106fe6f68fSKarthikeyan Periyasamy /* PCIe base address */ 13116fe6f68fSKarthikeyan Periyasamy .pcie_qserdes_sysclk_en_sel = 0x0, 13126fe6f68fSKarthikeyan Periyasamy .pcie_pcs_osc_dtct_config_base = 0x0, 13136976433cSCarl Huang }; 13146976433cSCarl Huang 13156976433cSCarl Huang const struct ath11k_hw_regs qca6390_regs = { 13166976433cSCarl Huang /* SW2TCL(x) R0 ring configuration address */ 13176976433cSCarl Huang .hal_tcl1_ring_base_lsb = 0x00000684, 13186976433cSCarl Huang .hal_tcl1_ring_base_msb = 0x00000688, 13196976433cSCarl Huang .hal_tcl1_ring_id = 0x0000068c, 13206976433cSCarl Huang .hal_tcl1_ring_misc = 0x00000694, 13216976433cSCarl Huang .hal_tcl1_ring_tp_addr_lsb = 0x000006a0, 13226976433cSCarl Huang .hal_tcl1_ring_tp_addr_msb = 0x000006a4, 13236976433cSCarl Huang .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006b4, 13246976433cSCarl Huang .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006b8, 13256976433cSCarl Huang .hal_tcl1_ring_msi1_base_lsb = 0x000006cc, 13266976433cSCarl Huang .hal_tcl1_ring_msi1_base_msb = 0x000006d0, 13276976433cSCarl Huang .hal_tcl1_ring_msi1_data = 0x000006d4, 13286976433cSCarl Huang .hal_tcl2_ring_base_lsb = 0x000006dc, 13296976433cSCarl Huang .hal_tcl_ring_base_lsb = 0x0000078c, 13306976433cSCarl Huang 13316976433cSCarl Huang /* TCL STATUS ring address */ 13326976433cSCarl Huang .hal_tcl_status_ring_base_lsb = 0x00000894, 13336976433cSCarl Huang 13346976433cSCarl Huang /* REO2SW(x) R0 ring configuration address */ 13356976433cSCarl Huang .hal_reo1_ring_base_lsb = 0x00000244, 13366976433cSCarl Huang .hal_reo1_ring_base_msb = 0x00000248, 13376976433cSCarl Huang .hal_reo1_ring_id = 0x0000024c, 13386976433cSCarl Huang .hal_reo1_ring_misc = 0x00000254, 13396976433cSCarl Huang .hal_reo1_ring_hp_addr_lsb = 0x00000258, 13406976433cSCarl Huang .hal_reo1_ring_hp_addr_msb = 0x0000025c, 13416976433cSCarl Huang .hal_reo1_ring_producer_int_setup = 0x00000268, 13426976433cSCarl Huang .hal_reo1_ring_msi1_base_lsb = 0x0000028c, 13436976433cSCarl Huang .hal_reo1_ring_msi1_base_msb = 0x00000290, 13446976433cSCarl Huang .hal_reo1_ring_msi1_data = 0x00000294, 13456976433cSCarl Huang .hal_reo2_ring_base_lsb = 0x0000029c, 13466976433cSCarl Huang .hal_reo1_aging_thresh_ix_0 = 0x0000050c, 13476976433cSCarl Huang .hal_reo1_aging_thresh_ix_1 = 0x00000510, 13486976433cSCarl Huang .hal_reo1_aging_thresh_ix_2 = 0x00000514, 13496976433cSCarl Huang .hal_reo1_aging_thresh_ix_3 = 0x00000518, 13506976433cSCarl Huang 13516976433cSCarl Huang /* REO2SW(x) R2 ring pointers (head/tail) address */ 13526976433cSCarl Huang .hal_reo1_ring_hp = 0x00003030, 13536976433cSCarl Huang .hal_reo1_ring_tp = 0x00003034, 13546976433cSCarl Huang .hal_reo2_ring_hp = 0x00003038, 13556976433cSCarl Huang 13566976433cSCarl Huang /* REO2TCL R0 ring configuration address */ 13576976433cSCarl Huang .hal_reo_tcl_ring_base_lsb = 0x000003a4, 13586976433cSCarl Huang .hal_reo_tcl_ring_hp = 0x00003050, 13596976433cSCarl Huang 13606976433cSCarl Huang /* REO status address */ 13616976433cSCarl Huang .hal_reo_status_ring_base_lsb = 0x000004ac, 13626976433cSCarl Huang .hal_reo_status_hp = 0x00003068, 13636fe6f68fSKarthikeyan Periyasamy 13646fe6f68fSKarthikeyan Periyasamy /* WCSS relative address */ 13656fe6f68fSKarthikeyan Periyasamy .hal_seq_wcss_umac_ce0_src_reg = 0x00a00000, 13666fe6f68fSKarthikeyan Periyasamy .hal_seq_wcss_umac_ce0_dst_reg = 0x00a01000, 13676fe6f68fSKarthikeyan Periyasamy .hal_seq_wcss_umac_ce1_src_reg = 0x00a02000, 13686fe6f68fSKarthikeyan Periyasamy .hal_seq_wcss_umac_ce1_dst_reg = 0x00a03000, 13696fe6f68fSKarthikeyan Periyasamy 13706fe6f68fSKarthikeyan Periyasamy /* WBM Idle address */ 13716fe6f68fSKarthikeyan Periyasamy .hal_wbm_idle_link_ring_base_lsb = 0x00000860, 13726fe6f68fSKarthikeyan Periyasamy .hal_wbm_idle_link_ring_misc = 0x00000870, 13736fe6f68fSKarthikeyan Periyasamy 13746fe6f68fSKarthikeyan Periyasamy /* SW2WBM release address */ 13756fe6f68fSKarthikeyan Periyasamy .hal_wbm_release_ring_base_lsb = 0x000001d8, 13766fe6f68fSKarthikeyan Periyasamy 13776fe6f68fSKarthikeyan Periyasamy /* WBM2SW release address */ 13786fe6f68fSKarthikeyan Periyasamy .hal_wbm0_release_ring_base_lsb = 0x00000910, 13796fe6f68fSKarthikeyan Periyasamy .hal_wbm1_release_ring_base_lsb = 0x00000968, 13806fe6f68fSKarthikeyan Periyasamy 13816fe6f68fSKarthikeyan Periyasamy /* PCIe base address */ 13826fe6f68fSKarthikeyan Periyasamy .pcie_qserdes_sysclk_en_sel = 0x01e0c0ac, 13836fe6f68fSKarthikeyan Periyasamy .pcie_pcs_osc_dtct_config_base = 0x01e0c628, 13846fe6f68fSKarthikeyan Periyasamy }; 13856fe6f68fSKarthikeyan Periyasamy 13866fe6f68fSKarthikeyan Periyasamy const struct ath11k_hw_regs qcn9074_regs = { 13876fe6f68fSKarthikeyan Periyasamy /* SW2TCL(x) R0 ring configuration address */ 13886fe6f68fSKarthikeyan Periyasamy .hal_tcl1_ring_base_lsb = 0x000004f0, 13896fe6f68fSKarthikeyan Periyasamy .hal_tcl1_ring_base_msb = 0x000004f4, 13906fe6f68fSKarthikeyan Periyasamy .hal_tcl1_ring_id = 0x000004f8, 13916fe6f68fSKarthikeyan Periyasamy .hal_tcl1_ring_misc = 0x00000500, 13926fe6f68fSKarthikeyan Periyasamy .hal_tcl1_ring_tp_addr_lsb = 0x0000050c, 13936fe6f68fSKarthikeyan Periyasamy .hal_tcl1_ring_tp_addr_msb = 0x00000510, 13946fe6f68fSKarthikeyan Periyasamy .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000520, 13956fe6f68fSKarthikeyan Periyasamy .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000524, 13966fe6f68fSKarthikeyan Periyasamy .hal_tcl1_ring_msi1_base_lsb = 0x00000538, 13976fe6f68fSKarthikeyan Periyasamy .hal_tcl1_ring_msi1_base_msb = 0x0000053c, 13986fe6f68fSKarthikeyan Periyasamy .hal_tcl1_ring_msi1_data = 0x00000540, 13996fe6f68fSKarthikeyan Periyasamy .hal_tcl2_ring_base_lsb = 0x00000548, 14006fe6f68fSKarthikeyan Periyasamy .hal_tcl_ring_base_lsb = 0x000005f8, 14016fe6f68fSKarthikeyan Periyasamy 14026fe6f68fSKarthikeyan Periyasamy /* TCL STATUS ring address */ 14036fe6f68fSKarthikeyan Periyasamy .hal_tcl_status_ring_base_lsb = 0x00000700, 14046fe6f68fSKarthikeyan Periyasamy 14056fe6f68fSKarthikeyan Periyasamy /* REO2SW(x) R0 ring configuration address */ 14066fe6f68fSKarthikeyan Periyasamy .hal_reo1_ring_base_lsb = 0x0000029c, 14076fe6f68fSKarthikeyan Periyasamy .hal_reo1_ring_base_msb = 0x000002a0, 14086fe6f68fSKarthikeyan Periyasamy .hal_reo1_ring_id = 0x000002a4, 14096fe6f68fSKarthikeyan Periyasamy .hal_reo1_ring_misc = 0x000002ac, 14106fe6f68fSKarthikeyan Periyasamy .hal_reo1_ring_hp_addr_lsb = 0x000002b0, 14116fe6f68fSKarthikeyan Periyasamy .hal_reo1_ring_hp_addr_msb = 0x000002b4, 14126fe6f68fSKarthikeyan Periyasamy .hal_reo1_ring_producer_int_setup = 0x000002c0, 14136fe6f68fSKarthikeyan Periyasamy .hal_reo1_ring_msi1_base_lsb = 0x000002e4, 14146fe6f68fSKarthikeyan Periyasamy .hal_reo1_ring_msi1_base_msb = 0x000002e8, 14156fe6f68fSKarthikeyan Periyasamy .hal_reo1_ring_msi1_data = 0x000002ec, 14166fe6f68fSKarthikeyan Periyasamy .hal_reo2_ring_base_lsb = 0x000002f4, 14176fe6f68fSKarthikeyan Periyasamy .hal_reo1_aging_thresh_ix_0 = 0x00000564, 14186fe6f68fSKarthikeyan Periyasamy .hal_reo1_aging_thresh_ix_1 = 0x00000568, 14196fe6f68fSKarthikeyan Periyasamy .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 14206fe6f68fSKarthikeyan Periyasamy .hal_reo1_aging_thresh_ix_3 = 0x00000570, 14216fe6f68fSKarthikeyan Periyasamy 14226fe6f68fSKarthikeyan Periyasamy /* REO2SW(x) R2 ring pointers (head/tail) address */ 14236fe6f68fSKarthikeyan Periyasamy .hal_reo1_ring_hp = 0x00003038, 14246fe6f68fSKarthikeyan Periyasamy .hal_reo1_ring_tp = 0x0000303c, 14256fe6f68fSKarthikeyan Periyasamy .hal_reo2_ring_hp = 0x00003040, 14266fe6f68fSKarthikeyan Periyasamy 14276fe6f68fSKarthikeyan Periyasamy /* REO2TCL R0 ring configuration address */ 14286fe6f68fSKarthikeyan Periyasamy .hal_reo_tcl_ring_base_lsb = 0x000003fc, 14296fe6f68fSKarthikeyan Periyasamy .hal_reo_tcl_ring_hp = 0x00003058, 14306fe6f68fSKarthikeyan Periyasamy 14316fe6f68fSKarthikeyan Periyasamy /* REO status address */ 14326fe6f68fSKarthikeyan Periyasamy .hal_reo_status_ring_base_lsb = 0x00000504, 14336fe6f68fSKarthikeyan Periyasamy .hal_reo_status_hp = 0x00003070, 14346fe6f68fSKarthikeyan Periyasamy 14356fe6f68fSKarthikeyan Periyasamy /* WCSS relative address */ 14366fe6f68fSKarthikeyan Periyasamy .hal_seq_wcss_umac_ce0_src_reg = 0x01b80000, 14376fe6f68fSKarthikeyan Periyasamy .hal_seq_wcss_umac_ce0_dst_reg = 0x01b81000, 14386fe6f68fSKarthikeyan Periyasamy .hal_seq_wcss_umac_ce1_src_reg = 0x01b82000, 14396fe6f68fSKarthikeyan Periyasamy .hal_seq_wcss_umac_ce1_dst_reg = 0x01b83000, 14406fe6f68fSKarthikeyan Periyasamy 14416fe6f68fSKarthikeyan Periyasamy /* WBM Idle address */ 14426fe6f68fSKarthikeyan Periyasamy .hal_wbm_idle_link_ring_base_lsb = 0x00000874, 14436fe6f68fSKarthikeyan Periyasamy .hal_wbm_idle_link_ring_misc = 0x00000884, 14446fe6f68fSKarthikeyan Periyasamy 14456fe6f68fSKarthikeyan Periyasamy /* SW2WBM release address */ 14466fe6f68fSKarthikeyan Periyasamy .hal_wbm_release_ring_base_lsb = 0x000001ec, 14476fe6f68fSKarthikeyan Periyasamy 14486fe6f68fSKarthikeyan Periyasamy /* WBM2SW release address */ 14496fe6f68fSKarthikeyan Periyasamy .hal_wbm0_release_ring_base_lsb = 0x00000924, 14506fe6f68fSKarthikeyan Periyasamy .hal_wbm1_release_ring_base_lsb = 0x0000097c, 14516fe6f68fSKarthikeyan Periyasamy 14526fe6f68fSKarthikeyan Periyasamy /* PCIe base address */ 14536fe6f68fSKarthikeyan Periyasamy .pcie_qserdes_sysclk_en_sel = 0x01e0e0a8, 14546fe6f68fSKarthikeyan Periyasamy .pcie_pcs_osc_dtct_config_base = 0x01e0f45c, 14556976433cSCarl Huang }; 1456