1d547ca4cSAnilkumar Kolli // SPDX-License-Identifier: BSD-3-Clause-Clear 2d547ca4cSAnilkumar Kolli /* 3d547ca4cSAnilkumar Kolli * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. 4d547ca4cSAnilkumar Kolli */ 5d547ca4cSAnilkumar Kolli 66976433cSCarl Huang #include <linux/types.h> 76976433cSCarl Huang #include <linux/bitops.h> 86976433cSCarl Huang #include <linux/bitfield.h> 96976433cSCarl Huang 106976433cSCarl Huang #include "hw.h" 11d547ca4cSAnilkumar Kolli #include "core.h" 12e3396b8bSCarl Huang #include "ce.h" 13d547ca4cSAnilkumar Kolli 14d547ca4cSAnilkumar Kolli /* Map from pdev index to hw mac index */ 15d547ca4cSAnilkumar Kolli static u8 ath11k_hw_ipq8074_mac_from_pdev_id(int pdev_idx) 16d547ca4cSAnilkumar Kolli { 17d547ca4cSAnilkumar Kolli switch (pdev_idx) { 18d547ca4cSAnilkumar Kolli case 0: 19d547ca4cSAnilkumar Kolli return 0; 20d547ca4cSAnilkumar Kolli case 1: 21d547ca4cSAnilkumar Kolli return 2; 22d547ca4cSAnilkumar Kolli case 2: 23d547ca4cSAnilkumar Kolli return 1; 24d547ca4cSAnilkumar Kolli default: 25d547ca4cSAnilkumar Kolli return ATH11K_INVALID_HW_MAC_ID; 26d547ca4cSAnilkumar Kolli } 27d547ca4cSAnilkumar Kolli } 28d547ca4cSAnilkumar Kolli 29d547ca4cSAnilkumar Kolli static u8 ath11k_hw_ipq6018_mac_from_pdev_id(int pdev_idx) 30d547ca4cSAnilkumar Kolli { 31d547ca4cSAnilkumar Kolli return pdev_idx; 32d547ca4cSAnilkumar Kolli } 33d547ca4cSAnilkumar Kolli 342d4bcbedSCarl Huang static void ath11k_init_wmi_config_qca6390(struct ath11k_base *ab, 352d4bcbedSCarl Huang struct target_resource_config *config) 362d4bcbedSCarl Huang { 372d4bcbedSCarl Huang config->num_vdevs = 4; 382d4bcbedSCarl Huang config->num_peers = 16; 392d4bcbedSCarl Huang config->num_tids = 32; 402d4bcbedSCarl Huang 412d4bcbedSCarl Huang config->num_offload_peers = 3; 422d4bcbedSCarl Huang config->num_offload_reorder_buffs = 3; 432d4bcbedSCarl Huang config->num_peer_keys = TARGET_NUM_PEER_KEYS; 442d4bcbedSCarl Huang config->ast_skid_limit = TARGET_AST_SKID_LIMIT; 452d4bcbedSCarl Huang config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 462d4bcbedSCarl Huang config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 472d4bcbedSCarl Huang config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; 482d4bcbedSCarl Huang config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI; 492d4bcbedSCarl Huang config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; 502d4bcbedSCarl Huang config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; 512d4bcbedSCarl Huang config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; 522d4bcbedSCarl Huang config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS; 532d4bcbedSCarl Huang config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV; 542d4bcbedSCarl Huang config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV; 552d4bcbedSCarl Huang config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES; 562d4bcbedSCarl Huang config->num_mcast_groups = 0; 572d4bcbedSCarl Huang config->num_mcast_table_elems = 0; 582d4bcbedSCarl Huang config->mcast2ucast_mode = 0; 592d4bcbedSCarl Huang config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE; 602d4bcbedSCarl Huang config->num_wds_entries = 0; 612d4bcbedSCarl Huang config->dma_burst_size = 0; 622d4bcbedSCarl Huang config->rx_skip_defrag_timeout_dup_detection_check = 0; 632d4bcbedSCarl Huang config->vow_config = TARGET_VOW_CONFIG; 642d4bcbedSCarl Huang config->gtk_offload_max_vdev = 2; 652d4bcbedSCarl Huang config->num_msdu_desc = 0x400; 662d4bcbedSCarl Huang config->beacon_tx_offload_max_vdev = 2; 672d4bcbedSCarl Huang config->rx_batchmode = TARGET_RX_BATCHMODE; 682d4bcbedSCarl Huang 692d4bcbedSCarl Huang config->peer_map_unmap_v2_support = 0; 702d4bcbedSCarl Huang config->use_pdev_id = 1; 712d4bcbedSCarl Huang config->max_frag_entries = 0xa; 722d4bcbedSCarl Huang config->num_tdls_vdevs = 0x1; 732d4bcbedSCarl Huang config->num_tdls_conn_table_entries = 8; 742d4bcbedSCarl Huang config->beacon_tx_offload_max_vdev = 0x2; 752d4bcbedSCarl Huang config->num_multicast_filter_entries = 0x20; 762d4bcbedSCarl Huang config->num_wow_filters = 0x16; 772d4bcbedSCarl Huang config->num_keep_alive_pattern = 0x1; 782d4bcbedSCarl Huang config->num_keep_alive_pattern = 0; 792d4bcbedSCarl Huang } 802d4bcbedSCarl Huang 812d4bcbedSCarl Huang static void ath11k_init_wmi_config_ipq8074(struct ath11k_base *ab, 822d4bcbedSCarl Huang struct target_resource_config *config) 832d4bcbedSCarl Huang { 842d4bcbedSCarl Huang config->num_vdevs = ab->num_radios * TARGET_NUM_VDEVS; 852d4bcbedSCarl Huang 862d4bcbedSCarl Huang if (ab->num_radios == 2) { 872d4bcbedSCarl Huang config->num_peers = TARGET_NUM_PEERS(DBS); 882d4bcbedSCarl Huang config->num_tids = TARGET_NUM_TIDS(DBS); 892d4bcbedSCarl Huang } else if (ab->num_radios == 3) { 902d4bcbedSCarl Huang config->num_peers = TARGET_NUM_PEERS(DBS_SBS); 912d4bcbedSCarl Huang config->num_tids = TARGET_NUM_TIDS(DBS_SBS); 922d4bcbedSCarl Huang } else { 932d4bcbedSCarl Huang /* Control should not reach here */ 942d4bcbedSCarl Huang config->num_peers = TARGET_NUM_PEERS(SINGLE); 952d4bcbedSCarl Huang config->num_tids = TARGET_NUM_TIDS(SINGLE); 962d4bcbedSCarl Huang } 972d4bcbedSCarl Huang config->num_offload_peers = TARGET_NUM_OFFLD_PEERS; 982d4bcbedSCarl Huang config->num_offload_reorder_buffs = TARGET_NUM_OFFLD_REORDER_BUFFS; 992d4bcbedSCarl Huang config->num_peer_keys = TARGET_NUM_PEER_KEYS; 1002d4bcbedSCarl Huang config->ast_skid_limit = TARGET_AST_SKID_LIMIT; 1012d4bcbedSCarl Huang config->tx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 1022d4bcbedSCarl Huang config->rx_chain_mask = (1 << ab->target_caps.num_rf_chains) - 1; 1032d4bcbedSCarl Huang config->rx_timeout_pri[0] = TARGET_RX_TIMEOUT_LO_PRI; 1042d4bcbedSCarl Huang config->rx_timeout_pri[1] = TARGET_RX_TIMEOUT_LO_PRI; 1052d4bcbedSCarl Huang config->rx_timeout_pri[2] = TARGET_RX_TIMEOUT_LO_PRI; 1062d4bcbedSCarl Huang config->rx_timeout_pri[3] = TARGET_RX_TIMEOUT_HI_PRI; 1072d4bcbedSCarl Huang config->rx_decap_mode = TARGET_DECAP_MODE_NATIVE_WIFI; 1082d4bcbedSCarl Huang config->scan_max_pending_req = TARGET_SCAN_MAX_PENDING_REQS; 1092d4bcbedSCarl Huang config->bmiss_offload_max_vdev = TARGET_BMISS_OFFLOAD_MAX_VDEV; 1102d4bcbedSCarl Huang config->roam_offload_max_vdev = TARGET_ROAM_OFFLOAD_MAX_VDEV; 1112d4bcbedSCarl Huang config->roam_offload_max_ap_profiles = TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES; 1122d4bcbedSCarl Huang config->num_mcast_groups = TARGET_NUM_MCAST_GROUPS; 1132d4bcbedSCarl Huang config->num_mcast_table_elems = TARGET_NUM_MCAST_TABLE_ELEMS; 1142d4bcbedSCarl Huang config->mcast2ucast_mode = TARGET_MCAST2UCAST_MODE; 1152d4bcbedSCarl Huang config->tx_dbg_log_size = TARGET_TX_DBG_LOG_SIZE; 1162d4bcbedSCarl Huang config->num_wds_entries = TARGET_NUM_WDS_ENTRIES; 1172d4bcbedSCarl Huang config->dma_burst_size = TARGET_DMA_BURST_SIZE; 1182d4bcbedSCarl Huang config->rx_skip_defrag_timeout_dup_detection_check = 1192d4bcbedSCarl Huang TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK; 1202d4bcbedSCarl Huang config->vow_config = TARGET_VOW_CONFIG; 1212d4bcbedSCarl Huang config->gtk_offload_max_vdev = TARGET_GTK_OFFLOAD_MAX_VDEV; 1222d4bcbedSCarl Huang config->num_msdu_desc = TARGET_NUM_MSDU_DESC; 1232d4bcbedSCarl Huang config->beacon_tx_offload_max_vdev = ab->num_radios * TARGET_MAX_BCN_OFFLD; 1242d4bcbedSCarl Huang config->rx_batchmode = TARGET_RX_BATCHMODE; 1252d4bcbedSCarl Huang config->peer_map_unmap_v2_support = 1; 1262d4bcbedSCarl Huang config->twt_ap_pdev_count = 2; 1272d4bcbedSCarl Huang config->twt_ap_sta_count = 1000; 1282d4bcbedSCarl Huang } 1292d4bcbedSCarl Huang 1304152e420SCarl Huang static int ath11k_hw_mac_id_to_pdev_id_ipq8074(struct ath11k_hw_params *hw, 1314152e420SCarl Huang int mac_id) 1324152e420SCarl Huang { 1334152e420SCarl Huang return mac_id; 1344152e420SCarl Huang } 1354152e420SCarl Huang 1364152e420SCarl Huang static int ath11k_hw_mac_id_to_srng_id_ipq8074(struct ath11k_hw_params *hw, 1374152e420SCarl Huang int mac_id) 1384152e420SCarl Huang { 1394152e420SCarl Huang return 0; 1404152e420SCarl Huang } 1414152e420SCarl Huang 1424152e420SCarl Huang static int ath11k_hw_mac_id_to_pdev_id_qca6390(struct ath11k_hw_params *hw, 1434152e420SCarl Huang int mac_id) 1444152e420SCarl Huang { 1454152e420SCarl Huang return 0; 1464152e420SCarl Huang } 1474152e420SCarl Huang 1484152e420SCarl Huang static int ath11k_hw_mac_id_to_srng_id_qca6390(struct ath11k_hw_params *hw, 1494152e420SCarl Huang int mac_id) 1504152e420SCarl Huang { 1514152e420SCarl Huang return mac_id; 1524152e420SCarl Huang } 1534152e420SCarl Huang 154d547ca4cSAnilkumar Kolli const struct ath11k_hw_ops ipq8074_ops = { 155d547ca4cSAnilkumar Kolli .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 1562d4bcbedSCarl Huang .wmi_init_config = ath11k_init_wmi_config_qca6390, 1574152e420SCarl Huang .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 1584152e420SCarl Huang .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 159d547ca4cSAnilkumar Kolli }; 160d547ca4cSAnilkumar Kolli 161d547ca4cSAnilkumar Kolli const struct ath11k_hw_ops ipq6018_ops = { 162d547ca4cSAnilkumar Kolli .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 1632d4bcbedSCarl Huang .wmi_init_config = ath11k_init_wmi_config_ipq8074, 1644152e420SCarl Huang .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_ipq8074, 1654152e420SCarl Huang .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_ipq8074, 166d547ca4cSAnilkumar Kolli }; 1679de2ad43SCarl Huang 1689de2ad43SCarl Huang const struct ath11k_hw_ops qca6390_ops = { 1699de2ad43SCarl Huang .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 1704152e420SCarl Huang .wmi_init_config = ath11k_init_wmi_config_qca6390, 1714152e420SCarl Huang .mac_id_to_pdev_id = ath11k_hw_mac_id_to_pdev_id_qca6390, 1724152e420SCarl Huang .mac_id_to_srng_id = ath11k_hw_mac_id_to_srng_id_qca6390, 1739de2ad43SCarl Huang }; 17434d5a3a8SKalle Valo 17534d5a3a8SKalle Valo #define ATH11K_TX_RING_MASK_0 0x1 17634d5a3a8SKalle Valo #define ATH11K_TX_RING_MASK_1 0x2 17734d5a3a8SKalle Valo #define ATH11K_TX_RING_MASK_2 0x4 17834d5a3a8SKalle Valo 17934d5a3a8SKalle Valo #define ATH11K_RX_RING_MASK_0 0x1 18034d5a3a8SKalle Valo #define ATH11K_RX_RING_MASK_1 0x2 18134d5a3a8SKalle Valo #define ATH11K_RX_RING_MASK_2 0x4 18234d5a3a8SKalle Valo #define ATH11K_RX_RING_MASK_3 0x8 18334d5a3a8SKalle Valo 18434d5a3a8SKalle Valo #define ATH11K_RX_ERR_RING_MASK_0 0x1 18534d5a3a8SKalle Valo 18634d5a3a8SKalle Valo #define ATH11K_RX_WBM_REL_RING_MASK_0 0x1 18734d5a3a8SKalle Valo 18834d5a3a8SKalle Valo #define ATH11K_REO_STATUS_RING_MASK_0 0x1 18934d5a3a8SKalle Valo 19034d5a3a8SKalle Valo #define ATH11K_RXDMA2HOST_RING_MASK_0 0x1 19134d5a3a8SKalle Valo #define ATH11K_RXDMA2HOST_RING_MASK_1 0x2 19234d5a3a8SKalle Valo #define ATH11K_RXDMA2HOST_RING_MASK_2 0x4 19334d5a3a8SKalle Valo 19434d5a3a8SKalle Valo #define ATH11K_HOST2RXDMA_RING_MASK_0 0x1 19534d5a3a8SKalle Valo #define ATH11K_HOST2RXDMA_RING_MASK_1 0x2 19634d5a3a8SKalle Valo #define ATH11K_HOST2RXDMA_RING_MASK_2 0x4 19734d5a3a8SKalle Valo 19834d5a3a8SKalle Valo #define ATH11K_RX_MON_STATUS_RING_MASK_0 0x1 19934d5a3a8SKalle Valo #define ATH11K_RX_MON_STATUS_RING_MASK_1 0x2 20034d5a3a8SKalle Valo #define ATH11K_RX_MON_STATUS_RING_MASK_2 0x4 20134d5a3a8SKalle Valo 20234d5a3a8SKalle Valo const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074 = { 20334d5a3a8SKalle Valo .tx = { 20434d5a3a8SKalle Valo ATH11K_TX_RING_MASK_0, 20534d5a3a8SKalle Valo ATH11K_TX_RING_MASK_1, 20634d5a3a8SKalle Valo ATH11K_TX_RING_MASK_2, 20734d5a3a8SKalle Valo }, 20834d5a3a8SKalle Valo .rx_mon_status = { 20934d5a3a8SKalle Valo 0, 0, 0, 0, 21034d5a3a8SKalle Valo ATH11K_RX_MON_STATUS_RING_MASK_0, 21134d5a3a8SKalle Valo ATH11K_RX_MON_STATUS_RING_MASK_1, 21234d5a3a8SKalle Valo ATH11K_RX_MON_STATUS_RING_MASK_2, 21334d5a3a8SKalle Valo }, 21434d5a3a8SKalle Valo .rx = { 21534d5a3a8SKalle Valo 0, 0, 0, 0, 0, 0, 0, 21634d5a3a8SKalle Valo ATH11K_RX_RING_MASK_0, 21734d5a3a8SKalle Valo ATH11K_RX_RING_MASK_1, 21834d5a3a8SKalle Valo ATH11K_RX_RING_MASK_2, 21934d5a3a8SKalle Valo ATH11K_RX_RING_MASK_3, 22034d5a3a8SKalle Valo }, 22134d5a3a8SKalle Valo .rx_err = { 22234d5a3a8SKalle Valo ATH11K_RX_ERR_RING_MASK_0, 22334d5a3a8SKalle Valo }, 22434d5a3a8SKalle Valo .rx_wbm_rel = { 22534d5a3a8SKalle Valo ATH11K_RX_WBM_REL_RING_MASK_0, 22634d5a3a8SKalle Valo }, 22734d5a3a8SKalle Valo .reo_status = { 22834d5a3a8SKalle Valo ATH11K_REO_STATUS_RING_MASK_0, 22934d5a3a8SKalle Valo }, 23034d5a3a8SKalle Valo .rxdma2host = { 23134d5a3a8SKalle Valo ATH11K_RXDMA2HOST_RING_MASK_0, 23234d5a3a8SKalle Valo ATH11K_RXDMA2HOST_RING_MASK_1, 23334d5a3a8SKalle Valo ATH11K_RXDMA2HOST_RING_MASK_2, 23434d5a3a8SKalle Valo }, 23534d5a3a8SKalle Valo .host2rxdma = { 23634d5a3a8SKalle Valo ATH11K_HOST2RXDMA_RING_MASK_0, 23734d5a3a8SKalle Valo ATH11K_HOST2RXDMA_RING_MASK_1, 23834d5a3a8SKalle Valo ATH11K_HOST2RXDMA_RING_MASK_2, 23934d5a3a8SKalle Valo }, 24034d5a3a8SKalle Valo }; 24134d5a3a8SKalle Valo 242d4ecb90bSCarl Huang const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_qca6390 = { 243d4ecb90bSCarl Huang .tx = { 244d4ecb90bSCarl Huang ATH11K_TX_RING_MASK_0, 245d4ecb90bSCarl Huang ATH11K_TX_RING_MASK_1, 246d4ecb90bSCarl Huang ATH11K_TX_RING_MASK_2, 247d4ecb90bSCarl Huang }, 248d4ecb90bSCarl Huang .rx_mon_status = { 249d4ecb90bSCarl Huang 0, 0, 0, 0, 250d4ecb90bSCarl Huang ATH11K_RX_MON_STATUS_RING_MASK_0, 251d4ecb90bSCarl Huang ATH11K_RX_MON_STATUS_RING_MASK_1, 252d4ecb90bSCarl Huang ATH11K_RX_MON_STATUS_RING_MASK_2, 253d4ecb90bSCarl Huang }, 254d4ecb90bSCarl Huang .rx = { 255d4ecb90bSCarl Huang 0, 0, 0, 0, 0, 0, 0, 256d4ecb90bSCarl Huang ATH11K_RX_RING_MASK_0, 257d4ecb90bSCarl Huang ATH11K_RX_RING_MASK_1, 258d4ecb90bSCarl Huang ATH11K_RX_RING_MASK_2, 259d4ecb90bSCarl Huang ATH11K_RX_RING_MASK_3, 260d4ecb90bSCarl Huang }, 261d4ecb90bSCarl Huang .rx_err = { 262d4ecb90bSCarl Huang ATH11K_RX_ERR_RING_MASK_0, 263d4ecb90bSCarl Huang }, 264d4ecb90bSCarl Huang .rx_wbm_rel = { 265d4ecb90bSCarl Huang ATH11K_RX_WBM_REL_RING_MASK_0, 266d4ecb90bSCarl Huang }, 267d4ecb90bSCarl Huang .reo_status = { 268d4ecb90bSCarl Huang ATH11K_REO_STATUS_RING_MASK_0, 269d4ecb90bSCarl Huang }, 270d4ecb90bSCarl Huang .rxdma2host = { 271d4ecb90bSCarl Huang ATH11K_RXDMA2HOST_RING_MASK_0, 272d4ecb90bSCarl Huang ATH11K_RXDMA2HOST_RING_MASK_1, 273d4ecb90bSCarl Huang ATH11K_RXDMA2HOST_RING_MASK_2, 274d4ecb90bSCarl Huang }, 275d4ecb90bSCarl Huang .host2rxdma = { 276d4ecb90bSCarl Huang }, 277d4ecb90bSCarl Huang }; 278d4ecb90bSCarl Huang 279967c1d11SAnilkumar Kolli /* Target firmware's Copy Engine configuration. */ 280967c1d11SAnilkumar Kolli const struct ce_pipe_config ath11k_target_ce_config_wlan_ipq8074[] = { 281967c1d11SAnilkumar Kolli /* CE0: host->target HTC control and raw streams */ 282967c1d11SAnilkumar Kolli { 283967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(0), 284967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), 285967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 286967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 287967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 288967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 289967c1d11SAnilkumar Kolli }, 290967c1d11SAnilkumar Kolli 291967c1d11SAnilkumar Kolli /* CE1: target->host HTT + HTC control */ 292967c1d11SAnilkumar Kolli { 293967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(1), 294967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), 295967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 296967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 297967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 298967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 299967c1d11SAnilkumar Kolli }, 300967c1d11SAnilkumar Kolli 301967c1d11SAnilkumar Kolli /* CE2: target->host WMI */ 302967c1d11SAnilkumar Kolli { 303967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(2), 304967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), 305967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 306967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 307967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 308967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 309967c1d11SAnilkumar Kolli }, 310967c1d11SAnilkumar Kolli 311967c1d11SAnilkumar Kolli /* CE3: host->target WMI */ 312967c1d11SAnilkumar Kolli { 313967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(3), 314967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), 315967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 316967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 317967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 318967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 319967c1d11SAnilkumar Kolli }, 320967c1d11SAnilkumar Kolli 321967c1d11SAnilkumar Kolli /* CE4: host->target HTT */ 322967c1d11SAnilkumar Kolli { 323967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(4), 324967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), 325967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(256), 326967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(256), 327967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 328967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 329967c1d11SAnilkumar Kolli }, 330967c1d11SAnilkumar Kolli 331967c1d11SAnilkumar Kolli /* CE5: target->host Pktlog */ 332967c1d11SAnilkumar Kolli { 333967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(5), 334967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), 335967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 336967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 337967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(0), 338967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 339967c1d11SAnilkumar Kolli }, 340967c1d11SAnilkumar Kolli 341967c1d11SAnilkumar Kolli /* CE6: Reserved for target autonomous hif_memcpy */ 342967c1d11SAnilkumar Kolli { 343967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(6), 344967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 345967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 346967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(65535), 347967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 348967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 349967c1d11SAnilkumar Kolli }, 350967c1d11SAnilkumar Kolli 351967c1d11SAnilkumar Kolli /* CE7 used only by Host */ 352967c1d11SAnilkumar Kolli { 353967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(7), 354967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), 355967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 356967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 357967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 358967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 359967c1d11SAnilkumar Kolli }, 360967c1d11SAnilkumar Kolli 361967c1d11SAnilkumar Kolli /* CE8 target->host used only by IPA */ 362967c1d11SAnilkumar Kolli { 363967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(8), 364967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 365967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 366967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(65535), 367967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 368967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 369967c1d11SAnilkumar Kolli }, 370967c1d11SAnilkumar Kolli 371967c1d11SAnilkumar Kolli /* CE9 host->target HTT */ 372967c1d11SAnilkumar Kolli { 373967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(9), 374967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), 375967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 376967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 377967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 378967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 379967c1d11SAnilkumar Kolli }, 380967c1d11SAnilkumar Kolli 381967c1d11SAnilkumar Kolli /* CE10 target->host HTT */ 382967c1d11SAnilkumar Kolli { 383967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(10), 384967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 385967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(0), 386967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(0), 387967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 388967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 389967c1d11SAnilkumar Kolli }, 390967c1d11SAnilkumar Kolli 391967c1d11SAnilkumar Kolli /* CE11 Not used */ 392967c1d11SAnilkumar Kolli }; 393967c1d11SAnilkumar Kolli 394967c1d11SAnilkumar Kolli /* Map from service/endpoint to Copy Engine. 395967c1d11SAnilkumar Kolli * This table is derived from the CE_PCI TABLE, above. 396967c1d11SAnilkumar Kolli * It is passed to the Target at startup for use by firmware. 397967c1d11SAnilkumar Kolli */ 398967c1d11SAnilkumar Kolli const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_ipq8074[] = { 399967c1d11SAnilkumar Kolli { 400967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 401967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 402967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(3), 403967c1d11SAnilkumar Kolli }, 404967c1d11SAnilkumar Kolli { 405967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 406967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 407967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(2), 408967c1d11SAnilkumar Kolli }, 409967c1d11SAnilkumar Kolli { 410967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 411967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 412967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(3), 413967c1d11SAnilkumar Kolli }, 414967c1d11SAnilkumar Kolli { 415967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 416967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 417967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(2), 418967c1d11SAnilkumar Kolli }, 419967c1d11SAnilkumar Kolli { 420967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 421967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 422967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(3), 423967c1d11SAnilkumar Kolli }, 424967c1d11SAnilkumar Kolli { 425967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 426967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 427967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(2), 428967c1d11SAnilkumar Kolli }, 429967c1d11SAnilkumar Kolli { 430967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 431967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 432967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(3), 433967c1d11SAnilkumar Kolli }, 434967c1d11SAnilkumar Kolli { 435967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 436967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 437967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(2), 438967c1d11SAnilkumar Kolli }, 439967c1d11SAnilkumar Kolli { 440967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 441967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 442967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(3), 443967c1d11SAnilkumar Kolli }, 444967c1d11SAnilkumar Kolli { 445967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 446967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 447967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(2), 448967c1d11SAnilkumar Kolli }, 449967c1d11SAnilkumar Kolli { 450967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 451967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 452967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(7), 453967c1d11SAnilkumar Kolli }, 454967c1d11SAnilkumar Kolli { 455967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC1), 456967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 457967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(2), 458967c1d11SAnilkumar Kolli }, 459967c1d11SAnilkumar Kolli { 460967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2), 461967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 462967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(9), 463967c1d11SAnilkumar Kolli }, 464967c1d11SAnilkumar Kolli { 465967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL_MAC2), 466967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 467967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(2), 468967c1d11SAnilkumar Kolli }, 469967c1d11SAnilkumar Kolli { 470967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 471967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 472967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(0), 473967c1d11SAnilkumar Kolli }, 474967c1d11SAnilkumar Kolli { 475967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 476967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 477967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(1), 478967c1d11SAnilkumar Kolli }, 479967c1d11SAnilkumar Kolli { /* not used */ 480967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 481967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 482967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(0), 483967c1d11SAnilkumar Kolli }, 484967c1d11SAnilkumar Kolli { /* not used */ 485967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_TEST_RAW_STREAMS), 486967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 487967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(1), 488967c1d11SAnilkumar Kolli }, 489967c1d11SAnilkumar Kolli { 490967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 491967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 492967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(4), 493967c1d11SAnilkumar Kolli }, 494967c1d11SAnilkumar Kolli { 495967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 496967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 497967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(1), 498967c1d11SAnilkumar Kolli }, 499967c1d11SAnilkumar Kolli { 500967c1d11SAnilkumar Kolli .service_id = __cpu_to_le32(ATH11K_HTC_SVC_ID_PKT_LOG), 501967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 502967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(5), 503967c1d11SAnilkumar Kolli }, 504967c1d11SAnilkumar Kolli 505967c1d11SAnilkumar Kolli /* (Additions here) */ 506967c1d11SAnilkumar Kolli 507967c1d11SAnilkumar Kolli { /* terminator entry */ } 508967c1d11SAnilkumar Kolli }; 509967c1d11SAnilkumar Kolli 510967c1d11SAnilkumar Kolli /* Target firmware's Copy Engine configuration. */ 511967c1d11SAnilkumar Kolli const struct ce_pipe_config ath11k_target_ce_config_wlan_qca6390[] = { 512967c1d11SAnilkumar Kolli /* CE0: host->target HTC control and raw streams */ 513967c1d11SAnilkumar Kolli { 514967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(0), 515967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), 516967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 517967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 518967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 519967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 520967c1d11SAnilkumar Kolli }, 521967c1d11SAnilkumar Kolli 522967c1d11SAnilkumar Kolli /* CE1: target->host HTT + HTC control */ 523967c1d11SAnilkumar Kolli { 524967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(1), 525967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), 526967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 527967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 528967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 529967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 530967c1d11SAnilkumar Kolli }, 531967c1d11SAnilkumar Kolli 532967c1d11SAnilkumar Kolli /* CE2: target->host WMI */ 533967c1d11SAnilkumar Kolli { 534967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(2), 535967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), 536967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 537967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 538967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 539967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 540967c1d11SAnilkumar Kolli }, 541967c1d11SAnilkumar Kolli 542967c1d11SAnilkumar Kolli /* CE3: host->target WMI */ 543967c1d11SAnilkumar Kolli { 544967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(3), 545967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), 546967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 547967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 548967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 549967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 550967c1d11SAnilkumar Kolli }, 551967c1d11SAnilkumar Kolli 552967c1d11SAnilkumar Kolli /* CE4: host->target HTT */ 553967c1d11SAnilkumar Kolli { 554967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(4), 555967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_OUT), 556967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(256), 557967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(256), 558967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 559967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 560967c1d11SAnilkumar Kolli }, 561967c1d11SAnilkumar Kolli 562967c1d11SAnilkumar Kolli /* CE5: target->host Pktlog */ 563967c1d11SAnilkumar Kolli { 564967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(5), 565967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_IN), 566967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 567967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(2048), 568967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 569967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 570967c1d11SAnilkumar Kolli }, 571967c1d11SAnilkumar Kolli 572967c1d11SAnilkumar Kolli /* CE6: Reserved for target autonomous hif_memcpy */ 573967c1d11SAnilkumar Kolli { 574967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(6), 575967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 576967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 577967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(16384), 578967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 579967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 580967c1d11SAnilkumar Kolli }, 581967c1d11SAnilkumar Kolli 582967c1d11SAnilkumar Kolli /* CE7 used only by Host */ 583967c1d11SAnilkumar Kolli { 584967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(7), 585967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H), 586967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(0), 587967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(0), 588967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR), 589967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 590967c1d11SAnilkumar Kolli }, 591967c1d11SAnilkumar Kolli 592967c1d11SAnilkumar Kolli /* CE8 target->host used only by IPA */ 593967c1d11SAnilkumar Kolli { 594967c1d11SAnilkumar Kolli .pipenum = __cpu_to_le32(8), 595967c1d11SAnilkumar Kolli .pipedir = __cpu_to_le32(PIPEDIR_INOUT), 596967c1d11SAnilkumar Kolli .nentries = __cpu_to_le32(32), 597967c1d11SAnilkumar Kolli .nbytes_max = __cpu_to_le32(16384), 598967c1d11SAnilkumar Kolli .flags = __cpu_to_le32(CE_ATTR_FLAGS), 599967c1d11SAnilkumar Kolli .reserved = __cpu_to_le32(0), 600967c1d11SAnilkumar Kolli }, 601967c1d11SAnilkumar Kolli /* CE 9, 10, 11 are used by MHI driver */ 602967c1d11SAnilkumar Kolli }; 603967c1d11SAnilkumar Kolli 604967c1d11SAnilkumar Kolli /* Map from service/endpoint to Copy Engine. 605967c1d11SAnilkumar Kolli * This table is derived from the CE_PCI TABLE, above. 606967c1d11SAnilkumar Kolli * It is passed to the Target at startup for use by firmware. 607967c1d11SAnilkumar Kolli */ 608967c1d11SAnilkumar Kolli const struct service_to_pipe ath11k_target_service_to_ce_map_wlan_qca6390[] = { 609967c1d11SAnilkumar Kolli { 610967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 611967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 612967c1d11SAnilkumar Kolli __cpu_to_le32(3), 613967c1d11SAnilkumar Kolli }, 614967c1d11SAnilkumar Kolli { 615967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VO), 616967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 617967c1d11SAnilkumar Kolli __cpu_to_le32(2), 618967c1d11SAnilkumar Kolli }, 619967c1d11SAnilkumar Kolli { 620967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 621967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 622967c1d11SAnilkumar Kolli __cpu_to_le32(3), 623967c1d11SAnilkumar Kolli }, 624967c1d11SAnilkumar Kolli { 625967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BK), 626967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 627967c1d11SAnilkumar Kolli __cpu_to_le32(2), 628967c1d11SAnilkumar Kolli }, 629967c1d11SAnilkumar Kolli { 630967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 631967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 632967c1d11SAnilkumar Kolli __cpu_to_le32(3), 633967c1d11SAnilkumar Kolli }, 634967c1d11SAnilkumar Kolli { 635967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_BE), 636967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 637967c1d11SAnilkumar Kolli __cpu_to_le32(2), 638967c1d11SAnilkumar Kolli }, 639967c1d11SAnilkumar Kolli { 640967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 641967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 642967c1d11SAnilkumar Kolli __cpu_to_le32(3), 643967c1d11SAnilkumar Kolli }, 644967c1d11SAnilkumar Kolli { 645967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_DATA_VI), 646967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 647967c1d11SAnilkumar Kolli __cpu_to_le32(2), 648967c1d11SAnilkumar Kolli }, 649967c1d11SAnilkumar Kolli { 650967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 651967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 652967c1d11SAnilkumar Kolli __cpu_to_le32(3), 653967c1d11SAnilkumar Kolli }, 654967c1d11SAnilkumar Kolli { 655967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_WMI_CONTROL), 656967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 657967c1d11SAnilkumar Kolli __cpu_to_le32(2), 658967c1d11SAnilkumar Kolli }, 659967c1d11SAnilkumar Kolli { 660967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 661967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 662967c1d11SAnilkumar Kolli __cpu_to_le32(0), 663967c1d11SAnilkumar Kolli }, 664967c1d11SAnilkumar Kolli { 665967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_RSVD_CTRL), 666967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 667967c1d11SAnilkumar Kolli __cpu_to_le32(2), 668967c1d11SAnilkumar Kolli }, 669967c1d11SAnilkumar Kolli { 670967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 671967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */ 672967c1d11SAnilkumar Kolli __cpu_to_le32(4), 673967c1d11SAnilkumar Kolli }, 674967c1d11SAnilkumar Kolli { 675967c1d11SAnilkumar Kolli __cpu_to_le32(ATH11K_HTC_SVC_ID_HTT_DATA_MSG), 676967c1d11SAnilkumar Kolli __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */ 677967c1d11SAnilkumar Kolli __cpu_to_le32(1), 678967c1d11SAnilkumar Kolli }, 679967c1d11SAnilkumar Kolli 680967c1d11SAnilkumar Kolli /* (Additions here) */ 681967c1d11SAnilkumar Kolli 682967c1d11SAnilkumar Kolli { /* must be last */ 683967c1d11SAnilkumar Kolli __cpu_to_le32(0), 684967c1d11SAnilkumar Kolli __cpu_to_le32(0), 685967c1d11SAnilkumar Kolli __cpu_to_le32(0), 686967c1d11SAnilkumar Kolli }, 687967c1d11SAnilkumar Kolli }; 688967c1d11SAnilkumar Kolli 6896976433cSCarl Huang const struct ath11k_hw_regs ipq8074_regs = { 6906976433cSCarl Huang /* SW2TCL(x) R0 ring configuration address */ 6916976433cSCarl Huang .hal_tcl1_ring_base_lsb = 0x00000510, 6926976433cSCarl Huang .hal_tcl1_ring_base_msb = 0x00000514, 6936976433cSCarl Huang .hal_tcl1_ring_id = 0x00000518, 6946976433cSCarl Huang .hal_tcl1_ring_misc = 0x00000520, 6956976433cSCarl Huang .hal_tcl1_ring_tp_addr_lsb = 0x0000052c, 6966976433cSCarl Huang .hal_tcl1_ring_tp_addr_msb = 0x00000530, 6976976433cSCarl Huang .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000540, 6986976433cSCarl Huang .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000544, 6996976433cSCarl Huang .hal_tcl1_ring_msi1_base_lsb = 0x00000558, 7006976433cSCarl Huang .hal_tcl1_ring_msi1_base_msb = 0x0000055c, 7016976433cSCarl Huang .hal_tcl1_ring_msi1_data = 0x00000560, 7026976433cSCarl Huang .hal_tcl2_ring_base_lsb = 0x00000568, 7036976433cSCarl Huang .hal_tcl_ring_base_lsb = 0x00000618, 7046976433cSCarl Huang 7056976433cSCarl Huang /* TCL STATUS ring address */ 7066976433cSCarl Huang .hal_tcl_status_ring_base_lsb = 0x00000720, 7076976433cSCarl Huang 7086976433cSCarl Huang /* REO2SW(x) R0 ring configuration address */ 7096976433cSCarl Huang .hal_reo1_ring_base_lsb = 0x0000029c, 7106976433cSCarl Huang .hal_reo1_ring_base_msb = 0x000002a0, 7116976433cSCarl Huang .hal_reo1_ring_id = 0x000002a4, 7126976433cSCarl Huang .hal_reo1_ring_misc = 0x000002ac, 7136976433cSCarl Huang .hal_reo1_ring_hp_addr_lsb = 0x000002b0, 7146976433cSCarl Huang .hal_reo1_ring_hp_addr_msb = 0x000002b4, 7156976433cSCarl Huang .hal_reo1_ring_producer_int_setup = 0x000002c0, 7166976433cSCarl Huang .hal_reo1_ring_msi1_base_lsb = 0x000002e4, 7176976433cSCarl Huang .hal_reo1_ring_msi1_base_msb = 0x000002e8, 7186976433cSCarl Huang .hal_reo1_ring_msi1_data = 0x000002ec, 7196976433cSCarl Huang .hal_reo2_ring_base_lsb = 0x000002f4, 7206976433cSCarl Huang .hal_reo1_aging_thresh_ix_0 = 0x00000564, 7216976433cSCarl Huang .hal_reo1_aging_thresh_ix_1 = 0x00000568, 7226976433cSCarl Huang .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 7236976433cSCarl Huang .hal_reo1_aging_thresh_ix_3 = 0x00000570, 7246976433cSCarl Huang 7256976433cSCarl Huang /* REO2SW(x) R2 ring pointers (head/tail) address */ 7266976433cSCarl Huang .hal_reo1_ring_hp = 0x00003038, 7276976433cSCarl Huang .hal_reo1_ring_tp = 0x0000303c, 7286976433cSCarl Huang .hal_reo2_ring_hp = 0x00003040, 7296976433cSCarl Huang 7306976433cSCarl Huang /* REO2TCL R0 ring configuration address */ 7316976433cSCarl Huang .hal_reo_tcl_ring_base_lsb = 0x000003fc, 7326976433cSCarl Huang .hal_reo_tcl_ring_hp = 0x00003058, 7336976433cSCarl Huang 7346976433cSCarl Huang /* REO status address */ 7356976433cSCarl Huang .hal_reo_status_ring_base_lsb = 0x00000504, 7366976433cSCarl Huang .hal_reo_status_hp = 0x00003070, 7376976433cSCarl Huang 7386976433cSCarl Huang }; 7396976433cSCarl Huang 7406976433cSCarl Huang const struct ath11k_hw_regs qca6390_regs = { 7416976433cSCarl Huang /* SW2TCL(x) R0 ring configuration address */ 7426976433cSCarl Huang .hal_tcl1_ring_base_lsb = 0x00000684, 7436976433cSCarl Huang .hal_tcl1_ring_base_msb = 0x00000688, 7446976433cSCarl Huang .hal_tcl1_ring_id = 0x0000068c, 7456976433cSCarl Huang .hal_tcl1_ring_misc = 0x00000694, 7466976433cSCarl Huang .hal_tcl1_ring_tp_addr_lsb = 0x000006a0, 7476976433cSCarl Huang .hal_tcl1_ring_tp_addr_msb = 0x000006a4, 7486976433cSCarl Huang .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006b4, 7496976433cSCarl Huang .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006b8, 7506976433cSCarl Huang .hal_tcl1_ring_msi1_base_lsb = 0x000006cc, 7516976433cSCarl Huang .hal_tcl1_ring_msi1_base_msb = 0x000006d0, 7526976433cSCarl Huang .hal_tcl1_ring_msi1_data = 0x000006d4, 7536976433cSCarl Huang .hal_tcl2_ring_base_lsb = 0x000006dc, 7546976433cSCarl Huang .hal_tcl_ring_base_lsb = 0x0000078c, 7556976433cSCarl Huang 7566976433cSCarl Huang /* TCL STATUS ring address */ 7576976433cSCarl Huang .hal_tcl_status_ring_base_lsb = 0x00000894, 7586976433cSCarl Huang 7596976433cSCarl Huang /* REO2SW(x) R0 ring configuration address */ 7606976433cSCarl Huang .hal_reo1_ring_base_lsb = 0x00000244, 7616976433cSCarl Huang .hal_reo1_ring_base_msb = 0x00000248, 7626976433cSCarl Huang .hal_reo1_ring_id = 0x0000024c, 7636976433cSCarl Huang .hal_reo1_ring_misc = 0x00000254, 7646976433cSCarl Huang .hal_reo1_ring_hp_addr_lsb = 0x00000258, 7656976433cSCarl Huang .hal_reo1_ring_hp_addr_msb = 0x0000025c, 7666976433cSCarl Huang .hal_reo1_ring_producer_int_setup = 0x00000268, 7676976433cSCarl Huang .hal_reo1_ring_msi1_base_lsb = 0x0000028c, 7686976433cSCarl Huang .hal_reo1_ring_msi1_base_msb = 0x00000290, 7696976433cSCarl Huang .hal_reo1_ring_msi1_data = 0x00000294, 7706976433cSCarl Huang .hal_reo2_ring_base_lsb = 0x0000029c, 7716976433cSCarl Huang .hal_reo1_aging_thresh_ix_0 = 0x0000050c, 7726976433cSCarl Huang .hal_reo1_aging_thresh_ix_1 = 0x00000510, 7736976433cSCarl Huang .hal_reo1_aging_thresh_ix_2 = 0x00000514, 7746976433cSCarl Huang .hal_reo1_aging_thresh_ix_3 = 0x00000518, 7756976433cSCarl Huang 7766976433cSCarl Huang /* REO2SW(x) R2 ring pointers (head/tail) address */ 7776976433cSCarl Huang .hal_reo1_ring_hp = 0x00003030, 7786976433cSCarl Huang .hal_reo1_ring_tp = 0x00003034, 7796976433cSCarl Huang .hal_reo2_ring_hp = 0x00003038, 7806976433cSCarl Huang 7816976433cSCarl Huang /* REO2TCL R0 ring configuration address */ 7826976433cSCarl Huang .hal_reo_tcl_ring_base_lsb = 0x000003a4, 7836976433cSCarl Huang .hal_reo_tcl_ring_hp = 0x00003050, 7846976433cSCarl Huang 7856976433cSCarl Huang /* REO status address */ 7866976433cSCarl Huang .hal_reo_status_ring_base_lsb = 0x000004ac, 7876976433cSCarl Huang .hal_reo_status_hp = 0x00003068, 7886976433cSCarl Huang }; 789