1d547ca4cSAnilkumar Kolli // SPDX-License-Identifier: BSD-3-Clause-Clear 2d547ca4cSAnilkumar Kolli /* 3d547ca4cSAnilkumar Kolli * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved. 4d547ca4cSAnilkumar Kolli */ 5d547ca4cSAnilkumar Kolli 66976433cSCarl Huang #include <linux/types.h> 76976433cSCarl Huang #include <linux/bitops.h> 86976433cSCarl Huang #include <linux/bitfield.h> 96976433cSCarl Huang 106976433cSCarl Huang #include "hw.h" 11d547ca4cSAnilkumar Kolli #include "core.h" 12d547ca4cSAnilkumar Kolli 13d547ca4cSAnilkumar Kolli /* Map from pdev index to hw mac index */ 14d547ca4cSAnilkumar Kolli static u8 ath11k_hw_ipq8074_mac_from_pdev_id(int pdev_idx) 15d547ca4cSAnilkumar Kolli { 16d547ca4cSAnilkumar Kolli switch (pdev_idx) { 17d547ca4cSAnilkumar Kolli case 0: 18d547ca4cSAnilkumar Kolli return 0; 19d547ca4cSAnilkumar Kolli case 1: 20d547ca4cSAnilkumar Kolli return 2; 21d547ca4cSAnilkumar Kolli case 2: 22d547ca4cSAnilkumar Kolli return 1; 23d547ca4cSAnilkumar Kolli default: 24d547ca4cSAnilkumar Kolli return ATH11K_INVALID_HW_MAC_ID; 25d547ca4cSAnilkumar Kolli } 26d547ca4cSAnilkumar Kolli } 27d547ca4cSAnilkumar Kolli 28d547ca4cSAnilkumar Kolli static u8 ath11k_hw_ipq6018_mac_from_pdev_id(int pdev_idx) 29d547ca4cSAnilkumar Kolli { 30d547ca4cSAnilkumar Kolli return pdev_idx; 31d547ca4cSAnilkumar Kolli } 32d547ca4cSAnilkumar Kolli 33d547ca4cSAnilkumar Kolli const struct ath11k_hw_ops ipq8074_ops = { 34d547ca4cSAnilkumar Kolli .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 35d547ca4cSAnilkumar Kolli }; 36d547ca4cSAnilkumar Kolli 37d547ca4cSAnilkumar Kolli const struct ath11k_hw_ops ipq6018_ops = { 38d547ca4cSAnilkumar Kolli .get_hw_mac_from_pdev_id = ath11k_hw_ipq6018_mac_from_pdev_id, 39d547ca4cSAnilkumar Kolli }; 409de2ad43SCarl Huang 419de2ad43SCarl Huang const struct ath11k_hw_ops qca6390_ops = { 429de2ad43SCarl Huang .get_hw_mac_from_pdev_id = ath11k_hw_ipq8074_mac_from_pdev_id, 439de2ad43SCarl Huang }; 4434d5a3a8SKalle Valo 4534d5a3a8SKalle Valo #define ATH11K_TX_RING_MASK_0 0x1 4634d5a3a8SKalle Valo #define ATH11K_TX_RING_MASK_1 0x2 4734d5a3a8SKalle Valo #define ATH11K_TX_RING_MASK_2 0x4 4834d5a3a8SKalle Valo 4934d5a3a8SKalle Valo #define ATH11K_RX_RING_MASK_0 0x1 5034d5a3a8SKalle Valo #define ATH11K_RX_RING_MASK_1 0x2 5134d5a3a8SKalle Valo #define ATH11K_RX_RING_MASK_2 0x4 5234d5a3a8SKalle Valo #define ATH11K_RX_RING_MASK_3 0x8 5334d5a3a8SKalle Valo 5434d5a3a8SKalle Valo #define ATH11K_RX_ERR_RING_MASK_0 0x1 5534d5a3a8SKalle Valo 5634d5a3a8SKalle Valo #define ATH11K_RX_WBM_REL_RING_MASK_0 0x1 5734d5a3a8SKalle Valo 5834d5a3a8SKalle Valo #define ATH11K_REO_STATUS_RING_MASK_0 0x1 5934d5a3a8SKalle Valo 6034d5a3a8SKalle Valo #define ATH11K_RXDMA2HOST_RING_MASK_0 0x1 6134d5a3a8SKalle Valo #define ATH11K_RXDMA2HOST_RING_MASK_1 0x2 6234d5a3a8SKalle Valo #define ATH11K_RXDMA2HOST_RING_MASK_2 0x4 6334d5a3a8SKalle Valo 6434d5a3a8SKalle Valo #define ATH11K_HOST2RXDMA_RING_MASK_0 0x1 6534d5a3a8SKalle Valo #define ATH11K_HOST2RXDMA_RING_MASK_1 0x2 6634d5a3a8SKalle Valo #define ATH11K_HOST2RXDMA_RING_MASK_2 0x4 6734d5a3a8SKalle Valo 6834d5a3a8SKalle Valo #define ATH11K_RX_MON_STATUS_RING_MASK_0 0x1 6934d5a3a8SKalle Valo #define ATH11K_RX_MON_STATUS_RING_MASK_1 0x2 7034d5a3a8SKalle Valo #define ATH11K_RX_MON_STATUS_RING_MASK_2 0x4 7134d5a3a8SKalle Valo 7234d5a3a8SKalle Valo const struct ath11k_hw_ring_mask ath11k_hw_ring_mask_ipq8074 = { 7334d5a3a8SKalle Valo .tx = { 7434d5a3a8SKalle Valo ATH11K_TX_RING_MASK_0, 7534d5a3a8SKalle Valo ATH11K_TX_RING_MASK_1, 7634d5a3a8SKalle Valo ATH11K_TX_RING_MASK_2, 7734d5a3a8SKalle Valo }, 7834d5a3a8SKalle Valo .rx_mon_status = { 7934d5a3a8SKalle Valo 0, 0, 0, 0, 8034d5a3a8SKalle Valo ATH11K_RX_MON_STATUS_RING_MASK_0, 8134d5a3a8SKalle Valo ATH11K_RX_MON_STATUS_RING_MASK_1, 8234d5a3a8SKalle Valo ATH11K_RX_MON_STATUS_RING_MASK_2, 8334d5a3a8SKalle Valo }, 8434d5a3a8SKalle Valo .rx = { 8534d5a3a8SKalle Valo 0, 0, 0, 0, 0, 0, 0, 8634d5a3a8SKalle Valo ATH11K_RX_RING_MASK_0, 8734d5a3a8SKalle Valo ATH11K_RX_RING_MASK_1, 8834d5a3a8SKalle Valo ATH11K_RX_RING_MASK_2, 8934d5a3a8SKalle Valo ATH11K_RX_RING_MASK_3, 9034d5a3a8SKalle Valo }, 9134d5a3a8SKalle Valo .rx_err = { 9234d5a3a8SKalle Valo ATH11K_RX_ERR_RING_MASK_0, 9334d5a3a8SKalle Valo }, 9434d5a3a8SKalle Valo .rx_wbm_rel = { 9534d5a3a8SKalle Valo ATH11K_RX_WBM_REL_RING_MASK_0, 9634d5a3a8SKalle Valo }, 9734d5a3a8SKalle Valo .reo_status = { 9834d5a3a8SKalle Valo ATH11K_REO_STATUS_RING_MASK_0, 9934d5a3a8SKalle Valo }, 10034d5a3a8SKalle Valo .rxdma2host = { 10134d5a3a8SKalle Valo ATH11K_RXDMA2HOST_RING_MASK_0, 10234d5a3a8SKalle Valo ATH11K_RXDMA2HOST_RING_MASK_1, 10334d5a3a8SKalle Valo ATH11K_RXDMA2HOST_RING_MASK_2, 10434d5a3a8SKalle Valo }, 10534d5a3a8SKalle Valo .host2rxdma = { 10634d5a3a8SKalle Valo ATH11K_HOST2RXDMA_RING_MASK_0, 10734d5a3a8SKalle Valo ATH11K_HOST2RXDMA_RING_MASK_1, 10834d5a3a8SKalle Valo ATH11K_HOST2RXDMA_RING_MASK_2, 10934d5a3a8SKalle Valo }, 11034d5a3a8SKalle Valo }; 11134d5a3a8SKalle Valo 1126976433cSCarl Huang const struct ath11k_hw_regs ipq8074_regs = { 1136976433cSCarl Huang /* SW2TCL(x) R0 ring configuration address */ 1146976433cSCarl Huang .hal_tcl1_ring_base_lsb = 0x00000510, 1156976433cSCarl Huang .hal_tcl1_ring_base_msb = 0x00000514, 1166976433cSCarl Huang .hal_tcl1_ring_id = 0x00000518, 1176976433cSCarl Huang .hal_tcl1_ring_misc = 0x00000520, 1186976433cSCarl Huang .hal_tcl1_ring_tp_addr_lsb = 0x0000052c, 1196976433cSCarl Huang .hal_tcl1_ring_tp_addr_msb = 0x00000530, 1206976433cSCarl Huang .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000540, 1216976433cSCarl Huang .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000544, 1226976433cSCarl Huang .hal_tcl1_ring_msi1_base_lsb = 0x00000558, 1236976433cSCarl Huang .hal_tcl1_ring_msi1_base_msb = 0x0000055c, 1246976433cSCarl Huang .hal_tcl1_ring_msi1_data = 0x00000560, 1256976433cSCarl Huang .hal_tcl2_ring_base_lsb = 0x00000568, 1266976433cSCarl Huang .hal_tcl_ring_base_lsb = 0x00000618, 1276976433cSCarl Huang 1286976433cSCarl Huang /* TCL STATUS ring address */ 1296976433cSCarl Huang .hal_tcl_status_ring_base_lsb = 0x00000720, 1306976433cSCarl Huang 1316976433cSCarl Huang /* REO2SW(x) R0 ring configuration address */ 1326976433cSCarl Huang .hal_reo1_ring_base_lsb = 0x0000029c, 1336976433cSCarl Huang .hal_reo1_ring_base_msb = 0x000002a0, 1346976433cSCarl Huang .hal_reo1_ring_id = 0x000002a4, 1356976433cSCarl Huang .hal_reo1_ring_misc = 0x000002ac, 1366976433cSCarl Huang .hal_reo1_ring_hp_addr_lsb = 0x000002b0, 1376976433cSCarl Huang .hal_reo1_ring_hp_addr_msb = 0x000002b4, 1386976433cSCarl Huang .hal_reo1_ring_producer_int_setup = 0x000002c0, 1396976433cSCarl Huang .hal_reo1_ring_msi1_base_lsb = 0x000002e4, 1406976433cSCarl Huang .hal_reo1_ring_msi1_base_msb = 0x000002e8, 1416976433cSCarl Huang .hal_reo1_ring_msi1_data = 0x000002ec, 1426976433cSCarl Huang .hal_reo2_ring_base_lsb = 0x000002f4, 1436976433cSCarl Huang .hal_reo1_aging_thresh_ix_0 = 0x00000564, 1446976433cSCarl Huang .hal_reo1_aging_thresh_ix_1 = 0x00000568, 1456976433cSCarl Huang .hal_reo1_aging_thresh_ix_2 = 0x0000056c, 1466976433cSCarl Huang .hal_reo1_aging_thresh_ix_3 = 0x00000570, 1476976433cSCarl Huang 1486976433cSCarl Huang /* REO2SW(x) R2 ring pointers (head/tail) address */ 1496976433cSCarl Huang .hal_reo1_ring_hp = 0x00003038, 1506976433cSCarl Huang .hal_reo1_ring_tp = 0x0000303c, 1516976433cSCarl Huang .hal_reo2_ring_hp = 0x00003040, 1526976433cSCarl Huang 1536976433cSCarl Huang /* REO2TCL R0 ring configuration address */ 1546976433cSCarl Huang .hal_reo_tcl_ring_base_lsb = 0x000003fc, 1556976433cSCarl Huang .hal_reo_tcl_ring_hp = 0x00003058, 1566976433cSCarl Huang 1576976433cSCarl Huang /* REO status address */ 1586976433cSCarl Huang .hal_reo_status_ring_base_lsb = 0x00000504, 1596976433cSCarl Huang .hal_reo_status_hp = 0x00003070, 1606976433cSCarl Huang 1616976433cSCarl Huang }; 1626976433cSCarl Huang 1636976433cSCarl Huang const struct ath11k_hw_regs qca6390_regs = { 1646976433cSCarl Huang /* SW2TCL(x) R0 ring configuration address */ 1656976433cSCarl Huang .hal_tcl1_ring_base_lsb = 0x00000684, 1666976433cSCarl Huang .hal_tcl1_ring_base_msb = 0x00000688, 1676976433cSCarl Huang .hal_tcl1_ring_id = 0x0000068c, 1686976433cSCarl Huang .hal_tcl1_ring_misc = 0x00000694, 1696976433cSCarl Huang .hal_tcl1_ring_tp_addr_lsb = 0x000006a0, 1706976433cSCarl Huang .hal_tcl1_ring_tp_addr_msb = 0x000006a4, 1716976433cSCarl Huang .hal_tcl1_ring_consumer_int_setup_ix0 = 0x000006b4, 1726976433cSCarl Huang .hal_tcl1_ring_consumer_int_setup_ix1 = 0x000006b8, 1736976433cSCarl Huang .hal_tcl1_ring_msi1_base_lsb = 0x000006cc, 1746976433cSCarl Huang .hal_tcl1_ring_msi1_base_msb = 0x000006d0, 1756976433cSCarl Huang .hal_tcl1_ring_msi1_data = 0x000006d4, 1766976433cSCarl Huang .hal_tcl2_ring_base_lsb = 0x000006dc, 1776976433cSCarl Huang .hal_tcl_ring_base_lsb = 0x0000078c, 1786976433cSCarl Huang 1796976433cSCarl Huang /* TCL STATUS ring address */ 1806976433cSCarl Huang .hal_tcl_status_ring_base_lsb = 0x00000894, 1816976433cSCarl Huang 1826976433cSCarl Huang /* REO2SW(x) R0 ring configuration address */ 1836976433cSCarl Huang .hal_reo1_ring_base_lsb = 0x00000244, 1846976433cSCarl Huang .hal_reo1_ring_base_msb = 0x00000248, 1856976433cSCarl Huang .hal_reo1_ring_id = 0x0000024c, 1866976433cSCarl Huang .hal_reo1_ring_misc = 0x00000254, 1876976433cSCarl Huang .hal_reo1_ring_hp_addr_lsb = 0x00000258, 1886976433cSCarl Huang .hal_reo1_ring_hp_addr_msb = 0x0000025c, 1896976433cSCarl Huang .hal_reo1_ring_producer_int_setup = 0x00000268, 1906976433cSCarl Huang .hal_reo1_ring_msi1_base_lsb = 0x0000028c, 1916976433cSCarl Huang .hal_reo1_ring_msi1_base_msb = 0x00000290, 1926976433cSCarl Huang .hal_reo1_ring_msi1_data = 0x00000294, 1936976433cSCarl Huang .hal_reo2_ring_base_lsb = 0x0000029c, 1946976433cSCarl Huang .hal_reo1_aging_thresh_ix_0 = 0x0000050c, 1956976433cSCarl Huang .hal_reo1_aging_thresh_ix_1 = 0x00000510, 1966976433cSCarl Huang .hal_reo1_aging_thresh_ix_2 = 0x00000514, 1976976433cSCarl Huang .hal_reo1_aging_thresh_ix_3 = 0x00000518, 1986976433cSCarl Huang 1996976433cSCarl Huang /* REO2SW(x) R2 ring pointers (head/tail) address */ 2006976433cSCarl Huang .hal_reo1_ring_hp = 0x00003030, 2016976433cSCarl Huang .hal_reo1_ring_tp = 0x00003034, 2026976433cSCarl Huang .hal_reo2_ring_hp = 0x00003038, 2036976433cSCarl Huang 2046976433cSCarl Huang /* REO2TCL R0 ring configuration address */ 2056976433cSCarl Huang .hal_reo_tcl_ring_base_lsb = 0x000003a4, 2066976433cSCarl Huang .hal_reo_tcl_ring_hp = 0x00003050, 2076976433cSCarl Huang 2086976433cSCarl Huang /* REO status address */ 2096976433cSCarl Huang .hal_reo_status_ring_base_lsb = 0x000004ac, 2106976433cSCarl Huang .hal_reo_status_hp = 0x00003068, 2116976433cSCarl Huang }; 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