1d5c65159SKalle Valo /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2d5c65159SKalle Valo /* 3d5c65159SKalle Valo * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4*7636c9a6SManikanta Pubbisetty * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. 5d5c65159SKalle Valo */ 6d5c65159SKalle Valo 7d5c65159SKalle Valo #ifndef ATH11K_HAL_TX_H 8d5c65159SKalle Valo #define ATH11K_HAL_TX_H 9d5c65159SKalle Valo 10d5c65159SKalle Valo #include "hal_desc.h" 1127143fa9SGovind Singh #include "core.h" 12d5c65159SKalle Valo 13d5c65159SKalle Valo #define HAL_TX_ADDRX_EN 1 14d5c65159SKalle Valo #define HAL_TX_ADDRY_EN 2 15d5c65159SKalle Valo 160f37fbf4SAnilkumar Kolli #define HAL_TX_ADDR_SEARCH_DEFAULT 0 170f37fbf4SAnilkumar Kolli #define HAL_TX_ADDR_SEARCH_INDEX 1 18d5c65159SKalle Valo 19d5c65159SKalle Valo struct hal_tx_info { 20d5c65159SKalle Valo u16 meta_data_flags; /* %HAL_TCL_DATA_CMD_INFO0_META_ */ 21d5c65159SKalle Valo u8 ring_id; 22d5c65159SKalle Valo u32 desc_id; 23d5c65159SKalle Valo enum hal_tcl_desc_type type; 24d5c65159SKalle Valo enum hal_tcl_encap_type encap_type; 25d5c65159SKalle Valo dma_addr_t paddr; 26d5c65159SKalle Valo u32 data_len; 27d5c65159SKalle Valo u32 pkt_offset; 28d5c65159SKalle Valo enum hal_encrypt_type encrypt_type; 29d5c65159SKalle Valo u32 flags0; /* %HAL_TCL_DATA_CMD_INFO1_ */ 30d5c65159SKalle Valo u32 flags1; /* %HAL_TCL_DATA_CMD_INFO2_ */ 31d5c65159SKalle Valo u16 addr_search_flags; /* %HAL_TCL_DATA_CMD_INFO0_ADDR(X/Y)_ */ 32d5c65159SKalle Valo u16 bss_ast_hash; 334b965be5SKarthikeyan Periyasamy u16 bss_ast_idx; 34d5c65159SKalle Valo u8 tid; 35d5c65159SKalle Valo u8 search_type; /* %HAL_TX_ADDR_SEARCH_ */ 36d5c65159SKalle Valo u8 lmac_id; 37d5c65159SKalle Valo u8 dscp_tid_tbl_idx; 386fe6f68fSKarthikeyan Periyasamy bool enable_mesh; 39*7636c9a6SManikanta Pubbisetty u8 rbm_id; 40d5c65159SKalle Valo }; 41d5c65159SKalle Valo 42d5c65159SKalle Valo /* TODO: Check if the actual desc macros can be used instead */ 43d5c65159SKalle Valo #define HAL_TX_STATUS_FLAGS_FIRST_MSDU BIT(0) 44d5c65159SKalle Valo #define HAL_TX_STATUS_FLAGS_LAST_MSDU BIT(1) 45d5c65159SKalle Valo #define HAL_TX_STATUS_FLAGS_MSDU_IN_AMSDU BIT(2) 46d5c65159SKalle Valo #define HAL_TX_STATUS_FLAGS_RATE_STATS_VALID BIT(3) 47d5c65159SKalle Valo #define HAL_TX_STATUS_FLAGS_RATE_LDPC BIT(4) 48d5c65159SKalle Valo #define HAL_TX_STATUS_FLAGS_RATE_STBC BIT(5) 49d5c65159SKalle Valo #define HAL_TX_STATUS_FLAGS_OFDMA BIT(6) 50d5c65159SKalle Valo 51d5c65159SKalle Valo #define HAL_TX_STATUS_DESC_LEN sizeof(struct hal_wbm_release_ring) 52d5c65159SKalle Valo 53d5c65159SKalle Valo /* Tx status parsed from srng desc */ 54d5c65159SKalle Valo struct hal_tx_status { 55d5c65159SKalle Valo enum hal_wbm_rel_src_module buf_rel_source; 56d5c65159SKalle Valo enum hal_wbm_tqm_rel_reason status; 57d5c65159SKalle Valo u8 ack_rssi; 58d5c65159SKalle Valo u32 flags; /* %HAL_TX_STATUS_FLAGS_ */ 59d5c65159SKalle Valo u32 ppdu_id; 60d5c65159SKalle Valo u8 try_cnt; 61d5c65159SKalle Valo u8 tid; 62d5c65159SKalle Valo u16 peer_id; 638cfa7ef8SJohn Crispin u32 rate_stats; 64d5c65159SKalle Valo }; 65d5c65159SKalle Valo 66d5c65159SKalle Valo void ath11k_hal_tx_cmd_desc_setup(struct ath11k_base *ab, void *cmd, 67d5c65159SKalle Valo struct hal_tx_info *ti); 68d5c65159SKalle Valo void ath11k_hal_tx_set_dscp_tid_map(struct ath11k_base *ab, int id); 69d5c65159SKalle Valo int ath11k_hal_reo_cmd_send(struct ath11k_base *ab, struct hal_srng *srng, 70d5c65159SKalle Valo enum hal_reo_cmd_type type, 71d5c65159SKalle Valo struct ath11k_hal_reo_cmd *cmd); 72d5c65159SKalle Valo void ath11k_hal_tx_init_data_ring(struct ath11k_base *ab, 73d5c65159SKalle Valo struct hal_srng *srng); 74d5c65159SKalle Valo #endif 75