1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #include "hal_desc.h" 7 #include "hal.h" 8 #include "hal_tx.h" 9 #include "hif.h" 10 11 #define DSCP_TID_MAP_TBL_ENTRY_SIZE 64 12 13 /* dscp_tid_map - Default DSCP-TID mapping 14 * 15 * DSCP TID 16 * 000000 0 17 * 001000 1 18 * 010000 2 19 * 011000 3 20 * 100000 4 21 * 101000 5 22 * 110000 6 23 * 111000 7 24 */ 25 static const u8 dscp_tid_map[DSCP_TID_MAP_TBL_ENTRY_SIZE] = { 26 0, 0, 0, 0, 0, 0, 0, 0, 27 1, 1, 1, 1, 1, 1, 1, 1, 28 2, 2, 2, 2, 2, 2, 2, 2, 29 3, 3, 3, 3, 3, 3, 3, 3, 30 4, 4, 4, 4, 4, 4, 4, 4, 31 5, 5, 5, 5, 5, 5, 5, 5, 32 6, 6, 6, 6, 6, 6, 6, 6, 33 7, 7, 7, 7, 7, 7, 7, 7, 34 }; 35 36 void ath11k_hal_tx_cmd_desc_setup(struct ath11k_base *ab, void *cmd, 37 struct hal_tx_info *ti) 38 { 39 struct hal_tcl_data_cmd *tcl_cmd = (struct hal_tcl_data_cmd *)cmd; 40 41 tcl_cmd->buf_addr_info.info0 = 42 FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, ti->paddr); 43 tcl_cmd->buf_addr_info.info1 = 44 FIELD_PREP(BUFFER_ADDR_INFO1_ADDR, 45 ((uint64_t)ti->paddr >> HAL_ADDR_MSB_REG_SHIFT)); 46 tcl_cmd->buf_addr_info.info1 |= 47 FIELD_PREP(BUFFER_ADDR_INFO1_RET_BUF_MGR, 48 (ti->ring_id + HAL_RX_BUF_RBM_SW0_BM)) | 49 FIELD_PREP(BUFFER_ADDR_INFO1_SW_COOKIE, ti->desc_id); 50 51 tcl_cmd->info0 = 52 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_DESC_TYPE, ti->type) | 53 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ENCAP_TYPE, ti->encap_type) | 54 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ENCRYPT_TYPE, 55 ti->encrypt_type) | 56 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_SEARCH_TYPE, 57 ti->search_type) | 58 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ADDR_EN, 59 ti->addr_search_flags) | 60 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_CMD_NUM, 61 ti->meta_data_flags); 62 63 tcl_cmd->info1 = ti->flags0 | 64 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_DATA_LEN, ti->data_len) | 65 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_PKT_OFFSET, ti->pkt_offset); 66 67 tcl_cmd->info2 = ti->flags1 | 68 FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_TID, ti->tid) | 69 FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_LMAC_ID, ti->lmac_id); 70 71 tcl_cmd->info3 = FIELD_PREP(HAL_TCL_DATA_CMD_INFO3_DSCP_TID_TABLE_IDX, 72 ti->dscp_tid_tbl_idx) | 73 FIELD_PREP(HAL_TCL_DATA_CMD_INFO3_SEARCH_INDEX, 74 ti->bss_ast_hash); 75 tcl_cmd->info4 = 0; 76 } 77 78 void ath11k_hal_tx_set_dscp_tid_map(struct ath11k_base *ab, int id) 79 { 80 u32 ctrl_reg_val; 81 u32 addr; 82 u8 hw_map_val[HAL_DSCP_TID_TBL_SIZE]; 83 int i; 84 u32 value; 85 int cnt = 0; 86 87 ctrl_reg_val = ath11k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + 88 HAL_TCL1_RING_CMN_CTRL_REG); 89 /* Enable read/write access */ 90 ctrl_reg_val |= HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN; 91 ath11k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + 92 HAL_TCL1_RING_CMN_CTRL_REG, ctrl_reg_val); 93 94 addr = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_DSCP_TID_MAP + 95 (4 * id * (HAL_DSCP_TID_TBL_SIZE / 4)); 96 97 /* Configure each DSCP-TID mapping in three bits there by configure 98 * three bytes in an iteration. 99 */ 100 for (i = 0; i < DSCP_TID_MAP_TBL_ENTRY_SIZE; i += 8) { 101 value = FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP0, 102 dscp_tid_map[i]) | 103 FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP1, 104 dscp_tid_map[i + 1]) | 105 FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP2, 106 dscp_tid_map[i + 2]) | 107 FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP3, 108 dscp_tid_map[i + 3]) | 109 FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP4, 110 dscp_tid_map[i + 4]) | 111 FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP5, 112 dscp_tid_map[i + 5]) | 113 FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP6, 114 dscp_tid_map[i + 6]) | 115 FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP7, 116 dscp_tid_map[i + 7]); 117 memcpy(&hw_map_val[cnt], (u8 *)&value, 3); 118 cnt += 3; 119 } 120 121 for (i = 0; i < HAL_DSCP_TID_TBL_SIZE; i += 4) { 122 ath11k_hif_write32(ab, addr, *(u32 *)&hw_map_val[i]); 123 addr += 4; 124 } 125 126 /* Disable read/write access */ 127 ctrl_reg_val = ath11k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + 128 HAL_TCL1_RING_CMN_CTRL_REG); 129 ctrl_reg_val &= ~HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN; 130 ath11k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + 131 HAL_TCL1_RING_CMN_CTRL_REG, 132 ctrl_reg_val); 133 } 134 135 void ath11k_hal_tx_init_data_ring(struct ath11k_base *ab, struct hal_srng *srng) 136 { 137 struct hal_srng_params params; 138 struct hal_tlv_hdr *tlv; 139 int i, entry_size; 140 u8 *desc; 141 142 memset(¶ms, 0, sizeof(params)); 143 144 entry_size = ath11k_hal_srng_get_entrysize(HAL_TCL_DATA); 145 ath11k_hal_srng_get_params(ab, srng, ¶ms); 146 desc = (u8 *)params.ring_base_vaddr; 147 148 for (i = 0; i < params.num_entries; i++) { 149 tlv = (struct hal_tlv_hdr *)desc; 150 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_TCL_DATA_CMD) | 151 FIELD_PREP(HAL_TLV_HDR_LEN, 152 sizeof(struct hal_tcl_data_cmd)); 153 desc += entry_size; 154 } 155 } 156