1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #include "ahb.h" 7 #include "hal.h" 8 #include "hal_tx.h" 9 10 #define DSCP_TID_MAP_TBL_ENTRY_SIZE 64 11 12 /* dscp_tid_map - Default DSCP-TID mapping 13 * 14 * DSCP TID 15 * 000000 0 16 * 001000 1 17 * 010000 2 18 * 011000 3 19 * 100000 4 20 * 101000 5 21 * 110000 6 22 * 111000 7 23 */ 24 static const u8 dscp_tid_map[DSCP_TID_MAP_TBL_ENTRY_SIZE] = { 25 0, 0, 0, 0, 0, 0, 0, 0, 26 1, 1, 1, 1, 1, 1, 1, 1, 27 2, 2, 2, 2, 2, 2, 2, 2, 28 3, 3, 3, 3, 3, 3, 3, 3, 29 4, 4, 4, 4, 4, 4, 4, 4, 30 5, 5, 5, 5, 5, 5, 5, 5, 31 6, 6, 6, 6, 6, 6, 6, 6, 32 7, 7, 7, 7, 7, 7, 7, 7, 33 }; 34 35 void ath11k_hal_tx_cmd_desc_setup(struct ath11k_base *ab, void *cmd, 36 struct hal_tx_info *ti) 37 { 38 struct hal_tcl_data_cmd *tcl_cmd = (struct hal_tcl_data_cmd *)cmd; 39 40 tcl_cmd->buf_addr_info.info0 = 41 FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, ti->paddr); 42 tcl_cmd->buf_addr_info.info1 = 43 FIELD_PREP(BUFFER_ADDR_INFO1_ADDR, 44 ((uint64_t)ti->paddr >> HAL_ADDR_MSB_REG_SHIFT)); 45 tcl_cmd->buf_addr_info.info1 |= 46 FIELD_PREP(BUFFER_ADDR_INFO1_RET_BUF_MGR, 47 (ti->ring_id + HAL_RX_BUF_RBM_SW0_BM)) | 48 FIELD_PREP(BUFFER_ADDR_INFO1_SW_COOKIE, ti->desc_id); 49 50 tcl_cmd->info0 = 51 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_DESC_TYPE, ti->type) | 52 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ENCAP_TYPE, ti->encap_type) | 53 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ENCRYPT_TYPE, 54 ti->encrypt_type) | 55 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_SEARCH_TYPE, 56 ti->search_type) | 57 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ADDR_EN, 58 ti->addr_search_flags) | 59 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_CMD_NUM, 60 ti->meta_data_flags); 61 62 tcl_cmd->info1 = ti->flags0 | 63 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_DATA_LEN, ti->data_len) | 64 FIELD_PREP(HAL_TCL_DATA_CMD_INFO1_PKT_OFFSET, ti->pkt_offset); 65 66 tcl_cmd->info2 = ti->flags1 | 67 FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_TID, ti->tid) | 68 FIELD_PREP(HAL_TCL_DATA_CMD_INFO2_LMAC_ID, ti->lmac_id); 69 70 tcl_cmd->info3 = FIELD_PREP(HAL_TCL_DATA_CMD_INFO3_DSCP_TID_TABLE_IDX, 71 ti->dscp_tid_tbl_idx) | 72 FIELD_PREP(HAL_TCL_DATA_CMD_INFO3_SEARCH_INDEX, 73 ti->bss_ast_hash); 74 } 75 76 /* Commit the descriptor to hardware */ 77 void ath11k_hal_tx_desc_sync(void *tx_desc_cached, void *hw_desc) 78 { 79 memcpy(hw_desc + sizeof(struct hal_tlv_hdr), tx_desc_cached, 80 sizeof(struct hal_tcl_data_cmd)); 81 } 82 83 /* Get the descriptor status from hardware */ 84 void ath11k_hal_tx_status_desc_sync(void *hw_desc, void *local_desc) 85 { 86 memcpy(local_desc, hw_desc, HAL_TX_STATUS_DESC_LEN); 87 } 88 89 void ath11k_hal_tx_status_parse(struct ath11k_base *ab, 90 struct hal_wbm_release_ring *desc, 91 struct hal_tx_status *ts) 92 { 93 ts->buf_rel_source = 94 FIELD_GET(HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE, desc->info0); 95 if (ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_FW && 96 ts->buf_rel_source != HAL_WBM_REL_SRC_MODULE_TQM) 97 return; 98 99 ts->desc_id = FIELD_GET(BUFFER_ADDR_INFO1_SW_COOKIE, 100 desc->buf_addr_info.info1); 101 102 if (ts->buf_rel_source == HAL_WBM_REL_SRC_MODULE_FW) 103 return; 104 105 ts->status = FIELD_GET(HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON, 106 desc->info0); 107 ts->ppdu_id = FIELD_GET(HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER, 108 desc->info1); 109 ts->try_cnt = FIELD_GET(HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT, 110 desc->info1); 111 112 ts->ack_rssi = FIELD_GET(HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI, 113 desc->info2); 114 if (desc->info2 & HAL_WBM_RELEASE_INFO2_FIRST_MSDU) 115 ts->flags |= HAL_TX_STATUS_FLAGS_FIRST_MSDU; 116 117 if (desc->info2 & HAL_WBM_RELEASE_INFO2_LAST_MSDU) 118 ts->flags |= HAL_TX_STATUS_FLAGS_LAST_MSDU; 119 120 if (desc->info2 & HAL_WBM_RELEASE_INFO2_MSDU_IN_AMSDU) 121 ts->flags |= HAL_TX_STATUS_FLAGS_MSDU_IN_AMSDU; 122 123 ts->peer_id = FIELD_GET(HAL_WBM_RELEASE_INFO3_PEER_ID, desc->info3); 124 ts->tid = FIELD_GET(HAL_WBM_RELEASE_INFO3_TID, desc->info3); 125 126 if (!(desc->rate_stats.info0 & HAL_TX_RATE_STATS_INFO0_VALID)) 127 return; 128 129 ts->flags |= HAL_TX_STATUS_FLAGS_RATE_STATS_VALID; 130 ts->tsf = desc->rate_stats.tsf; 131 ts->bw = FIELD_GET(HAL_TX_RATE_STATS_INFO0_BW, desc->rate_stats.info0); 132 ts->pkt_type = FIELD_GET(HAL_TX_RATE_STATS_INFO0_PKT_TYPE, 133 desc->rate_stats.info0); 134 if (desc->rate_stats.info0 & HAL_TX_RATE_STATS_INFO0_STBC) 135 ts->flags |= HAL_TX_STATUS_FLAGS_RATE_STBC; 136 if (desc->rate_stats.info0 & HAL_TX_RATE_STATS_INFO0_LDPC) 137 ts->flags |= HAL_TX_STATUS_FLAGS_RATE_LDPC; 138 if (desc->rate_stats.info0 & HAL_TX_RATE_STATS_INFO0_OFDMA_TX) 139 ts->flags |= HAL_TX_STATUS_FLAGS_OFDMA; 140 141 ts->sgi = FIELD_GET(HAL_TX_RATE_STATS_INFO0_SGI, 142 desc->rate_stats.info0); 143 ts->mcs = FIELD_GET(HAL_TX_RATE_STATS_INFO0_MCS, 144 desc->rate_stats.info0); 145 ts->num_tones_in_ru = FIELD_GET(HAL_TX_RATE_STATS_INFO0_TONES_IN_RU, 146 desc->rate_stats.info0); 147 } 148 149 void ath11k_hal_tx_set_dscp_tid_map(struct ath11k_base *ab, int id) 150 { 151 u32 ctrl_reg_val; 152 u32 addr; 153 u8 hw_map_val[HAL_DSCP_TID_TBL_SIZE]; 154 int i; 155 u32 value; 156 int cnt = 0; 157 158 ctrl_reg_val = ath11k_ahb_read32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + 159 HAL_TCL1_RING_CMN_CTRL_REG); 160 /* Enable read/write access */ 161 ctrl_reg_val |= HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN; 162 ath11k_ahb_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + 163 HAL_TCL1_RING_CMN_CTRL_REG, ctrl_reg_val); 164 165 addr = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_DSCP_TID_MAP + 166 (4 * id * (HAL_DSCP_TID_TBL_SIZE / 4)); 167 168 /* Configure each DSCP-TID mapping in three bits there by configure 169 * three bytes in an iteration. 170 */ 171 for (i = 0; i < DSCP_TID_MAP_TBL_ENTRY_SIZE; i += 8) { 172 value = FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP0, 173 dscp_tid_map[i]) | 174 FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP1, 175 dscp_tid_map[i + 1]) | 176 FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP2, 177 dscp_tid_map[i + 2]) | 178 FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP3, 179 dscp_tid_map[i + 3]) | 180 FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP4, 181 dscp_tid_map[i + 4]) | 182 FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP5, 183 dscp_tid_map[i + 5]) | 184 FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP6, 185 dscp_tid_map[i + 6]) | 186 FIELD_PREP(HAL_TCL1_RING_FIELD_DSCP_TID_MAP7, 187 dscp_tid_map[i + 7]); 188 memcpy(&hw_map_val[cnt], (u8 *)&value, 3); 189 cnt += 3; 190 } 191 192 for (i = 0; i < HAL_DSCP_TID_TBL_SIZE; i += 4) { 193 ath11k_ahb_write32(ab, addr, *(u32 *)&hw_map_val[i]); 194 addr += 4; 195 } 196 197 /* Disable read/write access */ 198 ctrl_reg_val = ath11k_ahb_read32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + 199 HAL_TCL1_RING_CMN_CTRL_REG); 200 ctrl_reg_val &= ~HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN; 201 ath11k_ahb_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + 202 HAL_TCL1_RING_CMN_CTRL_REG, 203 ctrl_reg_val); 204 } 205 206 void ath11k_hal_tx_init_data_ring(struct ath11k_base *ab, struct hal_srng *srng) 207 { 208 struct hal_srng_params params; 209 struct hal_tlv_hdr *tlv; 210 int i, entry_size; 211 u8 *desc; 212 213 memset(¶ms, 0, sizeof(params)); 214 215 entry_size = ath11k_hal_srng_get_entrysize(HAL_TCL_DATA); 216 ath11k_hal_srng_get_params(ab, srng, ¶ms); 217 desc = (u8 *)params.ring_base_vaddr; 218 219 for (i = 0; i < params.num_entries; i++) { 220 tlv = (struct hal_tlv_hdr *)desc; 221 tlv->tl = FIELD_PREP(HAL_TLV_HDR_TAG, HAL_TCL_DATA_CMD) | 222 FIELD_PREP(HAL_TLV_HDR_LEN, 223 sizeof(struct hal_tcl_data_cmd)); 224 desc += entry_size; 225 } 226 } 227