1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4  */
5 
6 #ifndef ATH11K_HAL_RX_H
7 #define ATH11K_HAL_RX_H
8 
9 struct hal_rx_wbm_rel_info {
10 	u32 cookie;
11 	enum hal_wbm_rel_src_module err_rel_src;
12 	enum hal_reo_dest_ring_push_reason push_reason;
13 	u32 err_code;
14 	bool first_msdu;
15 	bool last_msdu;
16 };
17 
18 #define HAL_INVALID_PEERID 0xffff
19 #define VHT_SIG_SU_NSS_MASK 0x7
20 
21 #define HAL_RX_MAX_MCS 12
22 #define HAL_RX_MAX_NSS 8
23 
24 struct hal_rx_mon_status_tlv_hdr {
25 	u32 hdr;
26 	u8 value[];
27 };
28 
29 enum hal_rx_su_mu_coding {
30 	HAL_RX_SU_MU_CODING_BCC,
31 	HAL_RX_SU_MU_CODING_LDPC,
32 	HAL_RX_SU_MU_CODING_MAX,
33 };
34 
35 enum hal_rx_gi {
36 	HAL_RX_GI_0_8_US,
37 	HAL_RX_GI_0_4_US,
38 	HAL_RX_GI_1_6_US,
39 	HAL_RX_GI_3_2_US,
40 	HAL_RX_GI_MAX,
41 };
42 
43 enum hal_rx_bw {
44 	HAL_RX_BW_20MHZ,
45 	HAL_RX_BW_40MHZ,
46 	HAL_RX_BW_80MHZ,
47 	HAL_RX_BW_160MHZ,
48 	HAL_RX_BW_MAX,
49 };
50 
51 enum hal_rx_preamble {
52 	HAL_RX_PREAMBLE_11A,
53 	HAL_RX_PREAMBLE_11B,
54 	HAL_RX_PREAMBLE_11N,
55 	HAL_RX_PREAMBLE_11AC,
56 	HAL_RX_PREAMBLE_11AX,
57 	HAL_RX_PREAMBLE_MAX,
58 };
59 
60 enum hal_rx_reception_type {
61 	HAL_RX_RECEPTION_TYPE_SU,
62 	HAL_RX_RECEPTION_TYPE_MU_MIMO,
63 	HAL_RX_RECEPTION_TYPE_MU_OFDMA,
64 	HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO,
65 	HAL_RX_RECEPTION_TYPE_MAX,
66 };
67 
68 #define HAL_TLV_STATUS_PPDU_NOT_DONE            0
69 #define HAL_TLV_STATUS_PPDU_DONE                1
70 #define HAL_TLV_STATUS_BUF_DONE                 2
71 #define HAL_TLV_STATUS_PPDU_NON_STD_DONE        3
72 #define HAL_RX_FCS_LEN                          4
73 
74 enum hal_rx_mon_status {
75 	HAL_RX_MON_STATUS_PPDU_NOT_DONE,
76 	HAL_RX_MON_STATUS_PPDU_DONE,
77 	HAL_RX_MON_STATUS_BUF_DONE,
78 };
79 
80 struct hal_rx_mon_ppdu_info {
81 	u32 ppdu_id;
82 	u32 ppdu_ts;
83 	u32 num_mpdu_fcs_ok;
84 	u32 num_mpdu_fcs_err;
85 	u32 preamble_type;
86 	u16 chan_num;
87 	u16 tcp_msdu_count;
88 	u16 tcp_ack_msdu_count;
89 	u16 udp_msdu_count;
90 	u16 other_msdu_count;
91 	u16 peer_id;
92 	u8 rate;
93 	u8 mcs;
94 	u8 nss;
95 	u8 bw;
96 	u8 is_stbc;
97 	u8 gi;
98 	u8 ldpc;
99 	u8 beamformed;
100 	u8 rssi_comb;
101 	u8 tid;
102 	u8 dcm;
103 	u8 ru_alloc;
104 	u8 reception_type;
105 	u64 rx_duration;
106 };
107 
108 #define HAL_RX_PPDU_START_INFO0_PPDU_ID		GENMASK(15, 0)
109 
110 struct hal_rx_ppdu_start {
111 	__le32 info0;
112 	__le32 chan_num;
113 	__le32 ppdu_start_ts;
114 } __packed;
115 
116 #define HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR	GENMASK(25, 16)
117 
118 #define HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK	GENMASK(8, 0)
119 #define HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID		BIT(9)
120 #define HAL_RX_PPDU_END_USER_STATS_INFO1_QOS_CTRL_VALID		BIT(10)
121 #define HAL_RX_PPDU_END_USER_STATS_INFO1_HT_CTRL_VALID		BIT(11)
122 #define HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE		GENMASK(23, 20)
123 
124 #define HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX		GENMASK(15, 0)
125 #define HAL_RX_PPDU_END_USER_STATS_INFO2_FRAME_CTRL		GENMASK(31, 16)
126 
127 #define HAL_RX_PPDU_END_USER_STATS_INFO3_QOS_CTRL		GENMASK(31, 16)
128 
129 #define HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT		GENMASK(15, 0)
130 #define HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT		GENMASK(31, 16)
131 
132 #define HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT		GENMASK(15, 0)
133 #define HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT	GENMASK(31, 16)
134 
135 #define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP		GENMASK(15, 0)
136 #define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_EOSP_BITMAP	GENMASK(31, 16)
137 
138 struct hal_rx_ppdu_end_user_stats {
139 	__le32 rsvd0[2];
140 	__le32 info0;
141 	__le32 info1;
142 	__le32 info2;
143 	__le32 info3;
144 	__le32 ht_ctrl;
145 	__le32 rsvd1[2];
146 	__le32 info4;
147 	__le32 info5;
148 	__le32 info6;
149 	__le32 rsvd2[11];
150 } __packed;
151 
152 #define HAL_RX_HT_SIG_INFO_INFO0_MCS		GENMASK(6, 0)
153 #define HAL_RX_HT_SIG_INFO_INFO0_BW		BIT(7)
154 
155 #define HAL_RX_HT_SIG_INFO_INFO1_STBC		GENMASK(5, 4)
156 #define HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING	BIT(6)
157 #define HAL_RX_HT_SIG_INFO_INFO1_GI		BIT(7)
158 
159 struct hal_rx_ht_sig_info {
160 	__le32 info0;
161 	__le32 info1;
162 } __packed;
163 
164 #define HAL_RX_LSIG_B_INFO_INFO0_RATE	GENMASK(3, 0)
165 #define HAL_RX_LSIG_B_INFO_INFO0_LEN	GENMASK(15, 4)
166 
167 struct hal_rx_lsig_b_info {
168 	__le32 info0;
169 } __packed;
170 
171 #define HAL_RX_LSIG_A_INFO_INFO0_RATE		GENMASK(3, 0)
172 #define HAL_RX_LSIG_A_INFO_INFO0_LEN		GENMASK(16, 5)
173 #define HAL_RX_LSIG_A_INFO_INFO0_PKT_TYPE	GENMASK(27, 24)
174 
175 struct hal_rx_lsig_a_info {
176 	__le32 info0;
177 } __packed;
178 
179 #define HAL_RX_VHT_SIG_A_INFO_INFO0_BW		GENMASK(1, 0)
180 #define HAL_RX_VHT_SIG_A_INFO_INFO0_STBC	BIT(3)
181 #define HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID	GENMASK(9, 4)
182 #define HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS	GENMASK(21, 10)
183 
184 #define HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING		GENMASK(1, 0)
185 #define HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING	BIT(2)
186 #define HAL_RX_VHT_SIG_A_INFO_INFO1_MCS			GENMASK(7, 4)
187 #define HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED		BIT(8)
188 
189 struct hal_rx_vht_sig_a_info {
190 	__le32 info0;
191 	__le32 info1;
192 } __packed;
193 
194 enum hal_rx_vht_sig_a_gi_setting {
195 	HAL_RX_VHT_SIG_A_NORMAL_GI = 0,
196 	HAL_RX_VHT_SIG_A_SHORT_GI = 1,
197 	HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY = 3,
198 };
199 
200 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS	GENMASK(6, 3)
201 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM		BIT(7)
202 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW	GENMASK(20, 19)
203 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE	GENMASK(22, 21)
204 #define HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS		GENMASK(25, 23)
205 
206 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING		BIT(7)
207 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC		BIT(9)
208 #define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF		BIT(10)
209 
210 struct hal_rx_he_sig_a_su_info {
211 	__le32 info0;
212 	__le32 info1;
213 } __packed;
214 
215 #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_TRANSMIT_BW	GENMASK(17, 15)
216 #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO0_CP_LTF_SIZE	GENMASK(24, 23)
217 
218 #define HAL_RX_HE_SIG_A_MU_DL_INFO_INFO1_STBC		BIT(12)
219 
220 struct hal_rx_he_sig_a_mu_dl_info {
221 	__le32 info0;
222 	__le32 info1;
223 } __packed;
224 
225 #define HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION	GENMASK(7, 0)
226 
227 struct hal_rx_he_sig_b1_mu_info {
228 	__le32 info0;
229 } __packed;
230 
231 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS		GENMASK(18, 15)
232 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING	BIT(20)
233 #define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS		GENMASK(31, 29)
234 
235 struct hal_rx_he_sig_b2_mu_info {
236 	__le32 info0;
237 } __packed;
238 
239 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS	GENMASK(13, 11)
240 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF	BIT(19)
241 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS	GENMASK(18, 15)
242 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM	BIT(19)
243 #define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING	BIT(20)
244 
245 struct hal_rx_he_sig_b2_ofdma_info {
246 	__le32 info0;
247 } __packed;
248 
249 #define HAL_RX_PHYRX_RSSI_LEGACY_INFO_INFO1_RSSI_COMB	GENMASK(15, 8)
250 
251 struct hal_rx_phyrx_rssi_legacy_info {
252 	__le32 rsvd[35];
253 	__le32 info0;
254 } __packed;
255 
256 #define HAL_RX_MPDU_INFO_INFO0_PEERID	GENMASK(31, 16)
257 struct hal_rx_mpdu_info {
258 	__le32 rsvd0;
259 	__le32 info0;
260 	__le32 rsvd1[21];
261 } __packed;
262 
263 #define HAL_RX_PPDU_END_DURATION	GENMASK(23, 0)
264 struct hal_rx_ppdu_end_duration {
265 	__le32 rsvd0[9];
266 	__le32 info0;
267 	__le32 rsvd1[4];
268 } __packed;
269 
270 struct hal_rx_rxpcu_classification_overview {
271 	u32 rsvd0;
272 } __packed;
273 
274 struct hal_rx_msdu_desc_info {
275 	u32 msdu_flags;
276 	u16 msdu_len; /* 14 bits for length */
277 };
278 
279 #define HAL_RX_NUM_MSDU_DESC 6
280 struct hal_rx_msdu_list {
281 	struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC];
282 	u32 sw_cookie[HAL_RX_NUM_MSDU_DESC];
283 	u8 rbm[HAL_RX_NUM_MSDU_DESC];
284 };
285 
286 void ath11k_hal_reo_status_queue_stats(struct ath11k_base *ab, u32 *reo_desc,
287 				       struct hal_reo_status *status);
288 void ath11k_hal_reo_flush_queue_status(struct ath11k_base *ab, u32 *reo_desc,
289 				       struct hal_reo_status *status);
290 void ath11k_hal_reo_flush_cache_status(struct ath11k_base *ab, u32 *reo_desc,
291 				       struct hal_reo_status *status);
292 void ath11k_hal_reo_flush_cache_status(struct ath11k_base *ab, u32 *reo_desc,
293 				       struct hal_reo_status *status);
294 void ath11k_hal_reo_unblk_cache_status(struct ath11k_base *ab, u32 *reo_desc,
295 				       struct hal_reo_status *status);
296 void ath11k_hal_reo_flush_timeout_list_status(struct ath11k_base *ab,
297 					      u32 *reo_desc,
298 					      struct hal_reo_status *status);
299 void ath11k_hal_reo_desc_thresh_reached_status(struct ath11k_base *ab,
300 					       u32 *reo_desc,
301 					       struct hal_reo_status *status);
302 void ath11k_hal_reo_update_rx_reo_queue_status(struct ath11k_base *ab,
303 					       u32 *reo_desc,
304 					       struct hal_reo_status *status);
305 int ath11k_hal_reo_process_status(u8 *reo_desc, u8 *status);
306 void ath11k_hal_rx_msdu_link_info_get(void *link_desc, u32 *num_msdus,
307 				      u32 *msdu_cookies,
308 				      enum hal_rx_buf_return_buf_manager *rbm);
309 void ath11k_hal_rx_msdu_link_desc_set(struct ath11k_base *ab, void *desc,
310 				      void *link_desc,
311 				      enum hal_wbm_rel_bm_act action);
312 void ath11k_hal_rx_buf_addr_info_set(void *desc, dma_addr_t paddr,
313 				     u32 cookie, u8 manager);
314 void ath11k_hal_rx_buf_addr_info_get(void *desc, dma_addr_t *paddr,
315 				     u32 *cookie, u8 *rbm);
316 int ath11k_hal_desc_reo_parse_err(struct ath11k_base *ab, u32 *rx_desc,
317 				  dma_addr_t *paddr, u32 *desc_bank);
318 int ath11k_hal_wbm_desc_parse_err(struct ath11k_base *ab, void *desc,
319 				  struct hal_rx_wbm_rel_info *rel_info);
320 void ath11k_hal_rx_reo_ent_paddr_get(struct ath11k_base *ab, void *desc,
321 				     dma_addr_t *paddr, u32 *desc_bank);
322 void ath11k_hal_rx_reo_ent_buf_paddr_get(void *rx_desc,
323 					 dma_addr_t *paddr, u32 *sw_cookie,
324 					 void **pp_buf_addr_info, u8 *rbm,
325 					 u32 *msdu_cnt);
326 enum hal_rx_mon_status
327 ath11k_hal_rx_parse_mon_status(struct ath11k_base *ab,
328 			       struct hal_rx_mon_ppdu_info *ppdu_info,
329 			       struct sk_buff *skb);
330 
331 static inline u32 ath11k_he_ru_tones_to_nl80211_he_ru_alloc(u16 ru_tones)
332 {
333 	u32 ret = 0;
334 
335 	switch (ru_tones) {
336 	case RU_26:
337 		ret = NL80211_RATE_INFO_HE_RU_ALLOC_26;
338 		break;
339 	case RU_52:
340 		ret = NL80211_RATE_INFO_HE_RU_ALLOC_52;
341 		break;
342 	case RU_106:
343 		ret = NL80211_RATE_INFO_HE_RU_ALLOC_106;
344 		break;
345 	case RU_242:
346 		ret = NL80211_RATE_INFO_HE_RU_ALLOC_242;
347 		break;
348 	case RU_484:
349 		ret = NL80211_RATE_INFO_HE_RU_ALLOC_484;
350 		break;
351 	case RU_996:
352 		ret = NL80211_RATE_INFO_HE_RU_ALLOC_996;
353 		break;
354 	}
355 	return ret;
356 }
357 
358 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0 0xDDBEEF
359 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1 0xADBEEF
360 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2 0xBDBEEF
361 #define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3 0xCDBEEF
362 #endif
363