1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 #include "core.h" 6 7 #ifndef ATH11K_HAL_DESC_H 8 #define ATH11K_HAL_DESC_H 9 10 #define BUFFER_ADDR_INFO0_ADDR GENMASK(31, 0) 11 12 #define BUFFER_ADDR_INFO1_ADDR GENMASK(7, 0) 13 #define BUFFER_ADDR_INFO1_RET_BUF_MGR GENMASK(10, 8) 14 #define BUFFER_ADDR_INFO1_SW_COOKIE GENMASK(31, 11) 15 16 struct ath11k_buffer_addr { 17 u32 info0; 18 u32 info1; 19 } __packed; 20 21 /* ath11k_buffer_addr 22 * 23 * info0 24 * Address (lower 32 bits) of the msdu buffer or msdu extension 25 * descriptor or Link descriptor 26 * 27 * addr 28 * Address (upper 8 bits) of the msdu buffer or msdu extension 29 * descriptor or Link descriptor 30 * 31 * return_buffer_manager (RBM) 32 * Consumer: WBM 33 * Producer: SW/FW 34 * Indicates to which buffer manager the buffer or MSDU_EXTENSION 35 * descriptor or link descriptor that is being pointed to shall be 36 * returned after the frame has been processed. It is used by WBM 37 * for routing purposes. 38 * 39 * Values are defined in enum %HAL_RX_BUF_RBM_ 40 * 41 * sw_buffer_cookie 42 * Cookie field exclusively used by SW. HW ignores the contents, 43 * accept that it passes the programmed value on to other 44 * descriptors together with the physical address. 45 * 46 * Field can be used by SW to for example associate the buffers 47 * physical address with the virtual address. 48 */ 49 50 enum hal_tlv_tag { 51 HAL_MACTX_CBF_START = 0 /* 0x0 */, 52 HAL_PHYRX_DATA = 1 /* 0x1 */, 53 HAL_PHYRX_CBF_DATA_RESP = 2 /* 0x2 */, 54 HAL_PHYRX_ABORT_REQUEST = 3 /* 0x3 */, 55 HAL_PHYRX_USER_ABORT_NOTIFICATION = 4 /* 0x4 */, 56 HAL_MACTX_DATA_RESP = 5 /* 0x5 */, 57 HAL_MACTX_CBF_DATA = 6 /* 0x6 */, 58 HAL_MACTX_CBF_DONE = 7 /* 0x7 */, 59 HAL_MACRX_CBF_READ_REQUEST = 8 /* 0x8 */, 60 HAL_MACRX_CBF_DATA_REQUEST = 9 /* 0x9 */, 61 HAL_MACRX_EXPECT_NDP_RECEPTION = 10 /* 0xa */, 62 HAL_MACRX_FREEZE_CAPTURE_CHANNEL = 11 /* 0xb */, 63 HAL_MACRX_NDP_TIMEOUT = 12 /* 0xc */, 64 HAL_MACRX_ABORT_ACK = 13 /* 0xd */, 65 HAL_MACRX_REQ_IMPLICIT_FB = 14 /* 0xe */, 66 HAL_MACRX_CHAIN_MASK = 15 /* 0xf */, 67 HAL_MACRX_NAP_USER = 16 /* 0x10 */, 68 HAL_MACRX_ABORT_REQUEST = 17 /* 0x11 */, 69 HAL_PHYTX_OTHER_TRANSMIT_INFO16 = 18 /* 0x12 */, 70 HAL_PHYTX_ABORT_ACK = 19 /* 0x13 */, 71 HAL_PHYTX_ABORT_REQUEST = 20 /* 0x14 */, 72 HAL_PHYTX_PKT_END = 21 /* 0x15 */, 73 HAL_PHYTX_PPDU_HEADER_INFO_REQUEST = 22 /* 0x16 */, 74 HAL_PHYTX_REQUEST_CTRL_INFO = 23 /* 0x17 */, 75 HAL_PHYTX_DATA_REQUEST = 24 /* 0x18 */, 76 HAL_PHYTX_BF_CV_LOADING_DONE = 25 /* 0x19 */, 77 HAL_PHYTX_NAP_ACK = 26 /* 0x1a */, 78 HAL_PHYTX_NAP_DONE = 27 /* 0x1b */, 79 HAL_PHYTX_OFF_ACK = 28 /* 0x1c */, 80 HAL_PHYTX_ON_ACK = 29 /* 0x1d */, 81 HAL_PHYTX_SYNTH_OFF_ACK = 30 /* 0x1e */, 82 HAL_PHYTX_DEBUG16 = 31 /* 0x1f */, 83 HAL_MACTX_ABORT_REQUEST = 32 /* 0x20 */, 84 HAL_MACTX_ABORT_ACK = 33 /* 0x21 */, 85 HAL_MACTX_PKT_END = 34 /* 0x22 */, 86 HAL_MACTX_PRE_PHY_DESC = 35 /* 0x23 */, 87 HAL_MACTX_BF_PARAMS_COMMON = 36 /* 0x24 */, 88 HAL_MACTX_BF_PARAMS_PER_USER = 37 /* 0x25 */, 89 HAL_MACTX_PREFETCH_CV = 38 /* 0x26 */, 90 HAL_MACTX_USER_DESC_COMMON = 39 /* 0x27 */, 91 HAL_MACTX_USER_DESC_PER_USER = 40 /* 0x28 */, 92 HAL_EXAMPLE_USER_TLV_16 = 41 /* 0x29 */, 93 HAL_EXAMPLE_TLV_16 = 42 /* 0x2a */, 94 HAL_MACTX_PHY_OFF = 43 /* 0x2b */, 95 HAL_MACTX_PHY_ON = 44 /* 0x2c */, 96 HAL_MACTX_SYNTH_OFF = 45 /* 0x2d */, 97 HAL_MACTX_EXPECT_CBF_COMMON = 46 /* 0x2e */, 98 HAL_MACTX_EXPECT_CBF_PER_USER = 47 /* 0x2f */, 99 HAL_MACTX_PHY_DESC = 48 /* 0x30 */, 100 HAL_MACTX_L_SIG_A = 49 /* 0x31 */, 101 HAL_MACTX_L_SIG_B = 50 /* 0x32 */, 102 HAL_MACTX_HT_SIG = 51 /* 0x33 */, 103 HAL_MACTX_VHT_SIG_A = 52 /* 0x34 */, 104 HAL_MACTX_VHT_SIG_B_SU20 = 53 /* 0x35 */, 105 HAL_MACTX_VHT_SIG_B_SU40 = 54 /* 0x36 */, 106 HAL_MACTX_VHT_SIG_B_SU80 = 55 /* 0x37 */, 107 HAL_MACTX_VHT_SIG_B_SU160 = 56 /* 0x38 */, 108 HAL_MACTX_VHT_SIG_B_MU20 = 57 /* 0x39 */, 109 HAL_MACTX_VHT_SIG_B_MU40 = 58 /* 0x3a */, 110 HAL_MACTX_VHT_SIG_B_MU80 = 59 /* 0x3b */, 111 HAL_MACTX_VHT_SIG_B_MU160 = 60 /* 0x3c */, 112 HAL_MACTX_SERVICE = 61 /* 0x3d */, 113 HAL_MACTX_HE_SIG_A_SU = 62 /* 0x3e */, 114 HAL_MACTX_HE_SIG_A_MU_DL = 63 /* 0x3f */, 115 HAL_MACTX_HE_SIG_A_MU_UL = 64 /* 0x40 */, 116 HAL_MACTX_HE_SIG_B1_MU = 65 /* 0x41 */, 117 HAL_MACTX_HE_SIG_B2_MU = 66 /* 0x42 */, 118 HAL_MACTX_HE_SIG_B2_OFDMA = 67 /* 0x43 */, 119 HAL_MACTX_DELETE_CV = 68 /* 0x44 */, 120 HAL_MACTX_MU_UPLINK_COMMON = 69 /* 0x45 */, 121 HAL_MACTX_MU_UPLINK_USER_SETUP = 70 /* 0x46 */, 122 HAL_MACTX_OTHER_TRANSMIT_INFO = 71 /* 0x47 */, 123 HAL_MACTX_PHY_NAP = 72 /* 0x48 */, 124 HAL_MACTX_DEBUG = 73 /* 0x49 */, 125 HAL_PHYRX_ABORT_ACK = 74 /* 0x4a */, 126 HAL_PHYRX_GENERATED_CBF_DETAILS = 75 /* 0x4b */, 127 HAL_PHYRX_RSSI_LEGACY = 76 /* 0x4c */, 128 HAL_PHYRX_RSSI_HT = 77 /* 0x4d */, 129 HAL_PHYRX_USER_INFO = 78 /* 0x4e */, 130 HAL_PHYRX_PKT_END = 79 /* 0x4f */, 131 HAL_PHYRX_DEBUG = 80 /* 0x50 */, 132 HAL_PHYRX_CBF_TRANSFER_DONE = 81 /* 0x51 */, 133 HAL_PHYRX_CBF_TRANSFER_ABORT = 82 /* 0x52 */, 134 HAL_PHYRX_L_SIG_A = 83 /* 0x53 */, 135 HAL_PHYRX_L_SIG_B = 84 /* 0x54 */, 136 HAL_PHYRX_HT_SIG = 85 /* 0x55 */, 137 HAL_PHYRX_VHT_SIG_A = 86 /* 0x56 */, 138 HAL_PHYRX_VHT_SIG_B_SU20 = 87 /* 0x57 */, 139 HAL_PHYRX_VHT_SIG_B_SU40 = 88 /* 0x58 */, 140 HAL_PHYRX_VHT_SIG_B_SU80 = 89 /* 0x59 */, 141 HAL_PHYRX_VHT_SIG_B_SU160 = 90 /* 0x5a */, 142 HAL_PHYRX_VHT_SIG_B_MU20 = 91 /* 0x5b */, 143 HAL_PHYRX_VHT_SIG_B_MU40 = 92 /* 0x5c */, 144 HAL_PHYRX_VHT_SIG_B_MU80 = 93 /* 0x5d */, 145 HAL_PHYRX_VHT_SIG_B_MU160 = 94 /* 0x5e */, 146 HAL_PHYRX_HE_SIG_A_SU = 95 /* 0x5f */, 147 HAL_PHYRX_HE_SIG_A_MU_DL = 96 /* 0x60 */, 148 HAL_PHYRX_HE_SIG_A_MU_UL = 97 /* 0x61 */, 149 HAL_PHYRX_HE_SIG_B1_MU = 98 /* 0x62 */, 150 HAL_PHYRX_HE_SIG_B2_MU = 99 /* 0x63 */, 151 HAL_PHYRX_HE_SIG_B2_OFDMA = 100 /* 0x64 */, 152 HAL_PHYRX_OTHER_RECEIVE_INFO = 101 /* 0x65 */, 153 HAL_PHYRX_COMMON_USER_INFO = 102 /* 0x66 */, 154 HAL_PHYRX_DATA_DONE = 103 /* 0x67 */, 155 HAL_RECEIVE_RSSI_INFO = 104 /* 0x68 */, 156 HAL_RECEIVE_USER_INFO = 105 /* 0x69 */, 157 HAL_MIMO_CONTROL_INFO = 106 /* 0x6a */, 158 HAL_RX_LOCATION_INFO = 107 /* 0x6b */, 159 HAL_COEX_TX_REQ = 108 /* 0x6c */, 160 HAL_DUMMY = 109 /* 0x6d */, 161 HAL_RX_TIMING_OFFSET_INFO = 110 /* 0x6e */, 162 HAL_EXAMPLE_TLV_32_NAME = 111 /* 0x6f */, 163 HAL_MPDU_LIMIT = 112 /* 0x70 */, 164 HAL_NA_LENGTH_END = 113 /* 0x71 */, 165 HAL_OLE_BUF_STATUS = 114 /* 0x72 */, 166 HAL_PCU_PPDU_SETUP_DONE = 115 /* 0x73 */, 167 HAL_PCU_PPDU_SETUP_END = 116 /* 0x74 */, 168 HAL_PCU_PPDU_SETUP_INIT = 117 /* 0x75 */, 169 HAL_PCU_PPDU_SETUP_START = 118 /* 0x76 */, 170 HAL_PDG_FES_SETUP = 119 /* 0x77 */, 171 HAL_PDG_RESPONSE = 120 /* 0x78 */, 172 HAL_PDG_TX_REQ = 121 /* 0x79 */, 173 HAL_SCH_WAIT_INSTR = 122 /* 0x7a */, 174 HAL_SCHEDULER_TLV = 123 /* 0x7b */, 175 HAL_TQM_FLOW_EMPTY_STATUS = 124 /* 0x7c */, 176 HAL_TQM_FLOW_NOT_EMPTY_STATUS = 125 /* 0x7d */, 177 HAL_TQM_GEN_MPDU_LENGTH_LIST = 126 /* 0x7e */, 178 HAL_TQM_GEN_MPDU_LENGTH_LIST_STATUS = 127 /* 0x7f */, 179 HAL_TQM_GEN_MPDUS = 128 /* 0x80 */, 180 HAL_TQM_GEN_MPDUS_STATUS = 129 /* 0x81 */, 181 HAL_TQM_REMOVE_MPDU = 130 /* 0x82 */, 182 HAL_TQM_REMOVE_MPDU_STATUS = 131 /* 0x83 */, 183 HAL_TQM_REMOVE_MSDU = 132 /* 0x84 */, 184 HAL_TQM_REMOVE_MSDU_STATUS = 133 /* 0x85 */, 185 HAL_TQM_UPDATE_TX_MPDU_COUNT = 134 /* 0x86 */, 186 HAL_TQM_WRITE_CMD = 135 /* 0x87 */, 187 HAL_OFDMA_TRIGGER_DETAILS = 136 /* 0x88 */, 188 HAL_TX_DATA = 137 /* 0x89 */, 189 HAL_TX_FES_SETUP = 138 /* 0x8a */, 190 HAL_RX_PACKET = 139 /* 0x8b */, 191 HAL_EXPECTED_RESPONSE = 140 /* 0x8c */, 192 HAL_TX_MPDU_END = 141 /* 0x8d */, 193 HAL_TX_MPDU_START = 142 /* 0x8e */, 194 HAL_TX_MSDU_END = 143 /* 0x8f */, 195 HAL_TX_MSDU_START = 144 /* 0x90 */, 196 HAL_TX_SW_MODE_SETUP = 145 /* 0x91 */, 197 HAL_TXPCU_BUFFER_STATUS = 146 /* 0x92 */, 198 HAL_TXPCU_USER_BUFFER_STATUS = 147 /* 0x93 */, 199 HAL_DATA_TO_TIME_CONFIG = 148 /* 0x94 */, 200 HAL_EXAMPLE_USER_TLV_32 = 149 /* 0x95 */, 201 HAL_MPDU_INFO = 150 /* 0x96 */, 202 HAL_PDG_USER_SETUP = 151 /* 0x97 */, 203 HAL_TX_11AH_SETUP = 152 /* 0x98 */, 204 HAL_REO_UPDATE_RX_REO_QUEUE_STATUS = 153 /* 0x99 */, 205 HAL_TX_PEER_ENTRY = 154 /* 0x9a */, 206 HAL_TX_RAW_OR_NATIVE_FRAME_SETUP = 155 /* 0x9b */, 207 HAL_EXAMPLE_STRUCT_NAME = 156 /* 0x9c */, 208 HAL_PCU_PPDU_SETUP_END_INFO = 157 /* 0x9d */, 209 HAL_PPDU_RATE_SETTING = 158 /* 0x9e */, 210 HAL_PROT_RATE_SETTING = 159 /* 0x9f */, 211 HAL_RX_MPDU_DETAILS = 160 /* 0xa0 */, 212 HAL_EXAMPLE_USER_TLV_42 = 161 /* 0xa1 */, 213 HAL_RX_MSDU_LINK = 162 /* 0xa2 */, 214 HAL_RX_REO_QUEUE = 163 /* 0xa3 */, 215 HAL_ADDR_SEARCH_ENTRY = 164 /* 0xa4 */, 216 HAL_SCHEDULER_CMD = 165 /* 0xa5 */, 217 HAL_TX_FLUSH = 166 /* 0xa6 */, 218 HAL_TQM_ENTRANCE_RING = 167 /* 0xa7 */, 219 HAL_TX_DATA_WORD = 168 /* 0xa8 */, 220 HAL_TX_MPDU_DETAILS = 169 /* 0xa9 */, 221 HAL_TX_MPDU_LINK = 170 /* 0xaa */, 222 HAL_TX_MPDU_LINK_PTR = 171 /* 0xab */, 223 HAL_TX_MPDU_QUEUE_HEAD = 172 /* 0xac */, 224 HAL_TX_MPDU_QUEUE_EXT = 173 /* 0xad */, 225 HAL_TX_MPDU_QUEUE_EXT_PTR = 174 /* 0xae */, 226 HAL_TX_MSDU_DETAILS = 175 /* 0xaf */, 227 HAL_TX_MSDU_EXTENSION = 176 /* 0xb0 */, 228 HAL_TX_MSDU_FLOW = 177 /* 0xb1 */, 229 HAL_TX_MSDU_LINK = 178 /* 0xb2 */, 230 HAL_TX_MSDU_LINK_ENTRY_PTR = 179 /* 0xb3 */, 231 HAL_RESPONSE_RATE_SETTING = 180 /* 0xb4 */, 232 HAL_TXPCU_BUFFER_BASICS = 181 /* 0xb5 */, 233 HAL_UNIFORM_DESCRIPTOR_HEADER = 182 /* 0xb6 */, 234 HAL_UNIFORM_TQM_CMD_HEADER = 183 /* 0xb7 */, 235 HAL_UNIFORM_TQM_STATUS_HEADER = 184 /* 0xb8 */, 236 HAL_USER_RATE_SETTING = 185 /* 0xb9 */, 237 HAL_WBM_BUFFER_RING = 186 /* 0xba */, 238 HAL_WBM_LINK_DESCRIPTOR_RING = 187 /* 0xbb */, 239 HAL_WBM_RELEASE_RING = 188 /* 0xbc */, 240 HAL_TX_FLUSH_REQ = 189 /* 0xbd */, 241 HAL_RX_MSDU_DETAILS = 190 /* 0xbe */, 242 HAL_TQM_WRITE_CMD_STATUS = 191 /* 0xbf */, 243 HAL_TQM_GET_MPDU_QUEUE_STATS = 192 /* 0xc0 */, 244 HAL_TQM_GET_MSDU_FLOW_STATS = 193 /* 0xc1 */, 245 HAL_EXAMPLE_USER_CTLV_32 = 194 /* 0xc2 */, 246 HAL_TX_FES_STATUS_START = 195 /* 0xc3 */, 247 HAL_TX_FES_STATUS_USER_PPDU = 196 /* 0xc4 */, 248 HAL_TX_FES_STATUS_USER_RESPONSE = 197 /* 0xc5 */, 249 HAL_TX_FES_STATUS_END = 198 /* 0xc6 */, 250 HAL_RX_TRIG_INFO = 199 /* 0xc7 */, 251 HAL_RXPCU_TX_SETUP_CLEAR = 200 /* 0xc8 */, 252 HAL_RX_FRAME_BITMAP_REQ = 201 /* 0xc9 */, 253 HAL_RX_FRAME_BITMAP_ACK = 202 /* 0xca */, 254 HAL_COEX_RX_STATUS = 203 /* 0xcb */, 255 HAL_RX_START_PARAM = 204 /* 0xcc */, 256 HAL_RX_PPDU_START = 205 /* 0xcd */, 257 HAL_RX_PPDU_END = 206 /* 0xce */, 258 HAL_RX_MPDU_START = 207 /* 0xcf */, 259 HAL_RX_MPDU_END = 208 /* 0xd0 */, 260 HAL_RX_MSDU_START = 209 /* 0xd1 */, 261 HAL_RX_MSDU_END = 210 /* 0xd2 */, 262 HAL_RX_ATTENTION = 211 /* 0xd3 */, 263 HAL_RECEIVED_RESPONSE_INFO = 212 /* 0xd4 */, 264 HAL_RX_PHY_SLEEP = 213 /* 0xd5 */, 265 HAL_RX_HEADER = 214 /* 0xd6 */, 266 HAL_RX_PEER_ENTRY = 215 /* 0xd7 */, 267 HAL_RX_FLUSH = 216 /* 0xd8 */, 268 HAL_RX_RESPONSE_REQUIRED_INFO = 217 /* 0xd9 */, 269 HAL_RX_FRAMELESS_BAR_DETAILS = 218 /* 0xda */, 270 HAL_TQM_GET_MPDU_QUEUE_STATS_STATUS = 219 /* 0xdb */, 271 HAL_TQM_GET_MSDU_FLOW_STATS_STATUS = 220 /* 0xdc */, 272 HAL_TX_CBF_INFO = 221 /* 0xdd */, 273 HAL_PCU_PPDU_SETUP_USER = 222 /* 0xde */, 274 HAL_RX_MPDU_PCU_START = 223 /* 0xdf */, 275 HAL_RX_PM_INFO = 224 /* 0xe0 */, 276 HAL_RX_USER_PPDU_END = 225 /* 0xe1 */, 277 HAL_RX_PRE_PPDU_START = 226 /* 0xe2 */, 278 HAL_RX_PREAMBLE = 227 /* 0xe3 */, 279 HAL_TX_FES_SETUP_COMPLETE = 228 /* 0xe4 */, 280 HAL_TX_LAST_MPDU_FETCHED = 229 /* 0xe5 */, 281 HAL_TXDMA_STOP_REQUEST = 230 /* 0xe6 */, 282 HAL_RXPCU_SETUP = 231 /* 0xe7 */, 283 HAL_RXPCU_USER_SETUP = 232 /* 0xe8 */, 284 HAL_TX_FES_STATUS_ACK_OR_BA = 233 /* 0xe9 */, 285 HAL_TQM_ACKED_MPDU = 234 /* 0xea */, 286 HAL_COEX_TX_RESP = 235 /* 0xeb */, 287 HAL_COEX_TX_STATUS = 236 /* 0xec */, 288 HAL_MACTX_COEX_PHY_CTRL = 237 /* 0xed */, 289 HAL_COEX_STATUS_BROADCAST = 238 /* 0xee */, 290 HAL_RESPONSE_START_STATUS = 239 /* 0xef */, 291 HAL_RESPONSE_END_STATUS = 240 /* 0xf0 */, 292 HAL_CRYPTO_STATUS = 241 /* 0xf1 */, 293 HAL_RECEIVED_TRIGGER_INFO = 242 /* 0xf2 */, 294 HAL_REO_ENTRANCE_RING = 243 /* 0xf3 */, 295 HAL_RX_MPDU_LINK = 244 /* 0xf4 */, 296 HAL_COEX_TX_STOP_CTRL = 245 /* 0xf5 */, 297 HAL_RX_PPDU_ACK_REPORT = 246 /* 0xf6 */, 298 HAL_RX_PPDU_NO_ACK_REPORT = 247 /* 0xf7 */, 299 HAL_SCH_COEX_STATUS = 248 /* 0xf8 */, 300 HAL_SCHEDULER_COMMAND_STATUS = 249 /* 0xf9 */, 301 HAL_SCHEDULER_RX_PPDU_NO_RESPONSE_STATUS = 250 /* 0xfa */, 302 HAL_TX_FES_STATUS_PROT = 251 /* 0xfb */, 303 HAL_TX_FES_STATUS_START_PPDU = 252 /* 0xfc */, 304 HAL_TX_FES_STATUS_START_PROT = 253 /* 0xfd */, 305 HAL_TXPCU_PHYTX_DEBUG32 = 254 /* 0xfe */, 306 HAL_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 = 255 /* 0xff */, 307 HAL_TX_MPDU_COUNT_TRANSFER_END = 256 /* 0x100 */, 308 HAL_WHO_ANCHOR_OFFSET = 257 /* 0x101 */, 309 HAL_WHO_ANCHOR_VALUE = 258 /* 0x102 */, 310 HAL_WHO_CCE_INFO = 259 /* 0x103 */, 311 HAL_WHO_COMMIT = 260 /* 0x104 */, 312 HAL_WHO_COMMIT_DONE = 261 /* 0x105 */, 313 HAL_WHO_FLUSH = 262 /* 0x106 */, 314 HAL_WHO_L2_LLC = 263 /* 0x107 */, 315 HAL_WHO_L2_PAYLOAD = 264 /* 0x108 */, 316 HAL_WHO_L3_CHECKSUM = 265 /* 0x109 */, 317 HAL_WHO_L3_INFO = 266 /* 0x10a */, 318 HAL_WHO_L4_CHECKSUM = 267 /* 0x10b */, 319 HAL_WHO_L4_INFO = 268 /* 0x10c */, 320 HAL_WHO_MSDU = 269 /* 0x10d */, 321 HAL_WHO_MSDU_MISC = 270 /* 0x10e */, 322 HAL_WHO_PACKET_DATA = 271 /* 0x10f */, 323 HAL_WHO_PACKET_HDR = 272 /* 0x110 */, 324 HAL_WHO_PPDU_END = 273 /* 0x111 */, 325 HAL_WHO_PPDU_START = 274 /* 0x112 */, 326 HAL_WHO_TSO = 275 /* 0x113 */, 327 HAL_WHO_WMAC_HEADER_PV0 = 276 /* 0x114 */, 328 HAL_WHO_WMAC_HEADER_PV1 = 277 /* 0x115 */, 329 HAL_WHO_WMAC_IV = 278 /* 0x116 */, 330 HAL_MPDU_INFO_END = 279 /* 0x117 */, 331 HAL_MPDU_INFO_BITMAP = 280 /* 0x118 */, 332 HAL_TX_QUEUE_EXTENSION = 281 /* 0x119 */, 333 HAL_RX_PEER_ENTRY_DETAILS = 282 /* 0x11a */, 334 HAL_RX_REO_QUEUE_REFERENCE = 283 /* 0x11b */, 335 HAL_RX_REO_QUEUE_EXT = 284 /* 0x11c */, 336 HAL_SCHEDULER_SELFGEN_RESPONSE_STATUS = 285 /* 0x11d */, 337 HAL_TQM_UPDATE_TX_MPDU_COUNT_STATUS = 286 /* 0x11e */, 338 HAL_TQM_ACKED_MPDU_STATUS = 287 /* 0x11f */, 339 HAL_TQM_ADD_MSDU_STATUS = 288 /* 0x120 */, 340 HAL_RX_MPDU_LINK_PTR = 289 /* 0x121 */, 341 HAL_REO_DESTINATION_RING = 290 /* 0x122 */, 342 HAL_TQM_LIST_GEN_DONE = 291 /* 0x123 */, 343 HAL_WHO_TERMINATE = 292 /* 0x124 */, 344 HAL_TX_LAST_MPDU_END = 293 /* 0x125 */, 345 HAL_TX_CV_DATA = 294 /* 0x126 */, 346 HAL_TCL_ENTRANCE_FROM_PPE_RING = 295 /* 0x127 */, 347 HAL_PPDU_TX_END = 296 /* 0x128 */, 348 HAL_PROT_TX_END = 297 /* 0x129 */, 349 HAL_PDG_RESPONSE_RATE_SETTING = 298 /* 0x12a */, 350 HAL_MPDU_INFO_GLOBAL_END = 299 /* 0x12b */, 351 HAL_TQM_SCH_INSTR_GLOBAL_END = 300 /* 0x12c */, 352 HAL_RX_PPDU_END_USER_STATS = 301 /* 0x12d */, 353 HAL_RX_PPDU_END_USER_STATS_EXT = 302 /* 0x12e */, 354 HAL_NO_ACK_REPORT = 303 /* 0x12f */, 355 HAL_ACK_REPORT = 304 /* 0x130 */, 356 HAL_UNIFORM_REO_CMD_HEADER = 305 /* 0x131 */, 357 HAL_REO_GET_QUEUE_STATS = 306 /* 0x132 */, 358 HAL_REO_FLUSH_QUEUE = 307 /* 0x133 */, 359 HAL_REO_FLUSH_CACHE = 308 /* 0x134 */, 360 HAL_REO_UNBLOCK_CACHE = 309 /* 0x135 */, 361 HAL_UNIFORM_REO_STATUS_HEADER = 310 /* 0x136 */, 362 HAL_REO_GET_QUEUE_STATS_STATUS = 311 /* 0x137 */, 363 HAL_REO_FLUSH_QUEUE_STATUS = 312 /* 0x138 */, 364 HAL_REO_FLUSH_CACHE_STATUS = 313 /* 0x139 */, 365 HAL_REO_UNBLOCK_CACHE_STATUS = 314 /* 0x13a */, 366 HAL_TQM_FLUSH_CACHE = 315 /* 0x13b */, 367 HAL_TQM_UNBLOCK_CACHE = 316 /* 0x13c */, 368 HAL_TQM_FLUSH_CACHE_STATUS = 317 /* 0x13d */, 369 HAL_TQM_UNBLOCK_CACHE_STATUS = 318 /* 0x13e */, 370 HAL_RX_PPDU_END_STATUS_DONE = 319 /* 0x13f */, 371 HAL_RX_STATUS_BUFFER_DONE = 320 /* 0x140 */, 372 HAL_BUFFER_ADDR_INFO = 321 /* 0x141 */, 373 HAL_RX_MSDU_DESC_INFO = 322 /* 0x142 */, 374 HAL_RX_MPDU_DESC_INFO = 323 /* 0x143 */, 375 HAL_TCL_DATA_CMD = 324 /* 0x144 */, 376 HAL_TCL_GSE_CMD = 325 /* 0x145 */, 377 HAL_TCL_EXIT_BASE = 326 /* 0x146 */, 378 HAL_TCL_COMPACT_EXIT_RING = 327 /* 0x147 */, 379 HAL_TCL_REGULAR_EXIT_RING = 328 /* 0x148 */, 380 HAL_TCL_EXTENDED_EXIT_RING = 329 /* 0x149 */, 381 HAL_UPLINK_COMMON_INFO = 330 /* 0x14a */, 382 HAL_UPLINK_USER_SETUP_INFO = 331 /* 0x14b */, 383 HAL_TX_DATA_SYNC = 332 /* 0x14c */, 384 HAL_PHYRX_CBF_READ_REQUEST_ACK = 333 /* 0x14d */, 385 HAL_TCL_STATUS_RING = 334 /* 0x14e */, 386 HAL_TQM_GET_MPDU_HEAD_INFO = 335 /* 0x14f */, 387 HAL_TQM_SYNC_CMD = 336 /* 0x150 */, 388 HAL_TQM_GET_MPDU_HEAD_INFO_STATUS = 337 /* 0x151 */, 389 HAL_TQM_SYNC_CMD_STATUS = 338 /* 0x152 */, 390 HAL_TQM_THRESHOLD_DROP_NOTIFICATION_STATUS = 339 /* 0x153 */, 391 HAL_TQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 340 /* 0x154 */, 392 HAL_REO_FLUSH_TIMEOUT_LIST = 341 /* 0x155 */, 393 HAL_REO_FLUSH_TIMEOUT_LIST_STATUS = 342 /* 0x156 */, 394 HAL_REO_TO_PPE_RING = 343 /* 0x157 */, 395 HAL_RX_MPDU_INFO = 344 /* 0x158 */, 396 HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 345 /* 0x159 */, 397 HAL_SCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS = 346 /* 0x15a */, 398 HAL_EXAMPLE_USER_TLV_32_NAME = 347 /* 0x15b */, 399 HAL_RX_PPDU_START_USER_INFO = 348 /* 0x15c */, 400 HAL_RX_RXPCU_CLASSIFICATION_OVERVIEW = 349 /* 0x15d */, 401 HAL_RX_RING_MASK = 350 /* 0x15e */, 402 HAL_WHO_CLASSIFY_INFO = 351 /* 0x15f */, 403 HAL_TXPT_CLASSIFY_INFO = 352 /* 0x160 */, 404 HAL_RXPT_CLASSIFY_INFO = 353 /* 0x161 */, 405 HAL_TX_FLOW_SEARCH_ENTRY = 354 /* 0x162 */, 406 HAL_RX_FLOW_SEARCH_ENTRY = 355 /* 0x163 */, 407 HAL_RECEIVED_TRIGGER_INFO_DETAILS = 356 /* 0x164 */, 408 HAL_COEX_MAC_NAP = 357 /* 0x165 */, 409 HAL_MACRX_ABORT_REQUEST_INFO = 358 /* 0x166 */, 410 HAL_MACTX_ABORT_REQUEST_INFO = 359 /* 0x167 */, 411 HAL_PHYRX_ABORT_REQUEST_INFO = 360 /* 0x168 */, 412 HAL_PHYTX_ABORT_REQUEST_INFO = 361 /* 0x169 */, 413 HAL_RXPCU_PPDU_END_INFO = 362 /* 0x16a */, 414 HAL_WHO_MESH_CONTROL = 363 /* 0x16b */, 415 HAL_L_SIG_A_INFO = 364 /* 0x16c */, 416 HAL_L_SIG_B_INFO = 365 /* 0x16d */, 417 HAL_HT_SIG_INFO = 366 /* 0x16e */, 418 HAL_VHT_SIG_A_INFO = 367 /* 0x16f */, 419 HAL_VHT_SIG_B_SU20_INFO = 368 /* 0x170 */, 420 HAL_VHT_SIG_B_SU40_INFO = 369 /* 0x171 */, 421 HAL_VHT_SIG_B_SU80_INFO = 370 /* 0x172 */, 422 HAL_VHT_SIG_B_SU160_INFO = 371 /* 0x173 */, 423 HAL_VHT_SIG_B_MU20_INFO = 372 /* 0x174 */, 424 HAL_VHT_SIG_B_MU40_INFO = 373 /* 0x175 */, 425 HAL_VHT_SIG_B_MU80_INFO = 374 /* 0x176 */, 426 HAL_VHT_SIG_B_MU160_INFO = 375 /* 0x177 */, 427 HAL_SERVICE_INFO = 376 /* 0x178 */, 428 HAL_HE_SIG_A_SU_INFO = 377 /* 0x179 */, 429 HAL_HE_SIG_A_MU_DL_INFO = 378 /* 0x17a */, 430 HAL_HE_SIG_A_MU_UL_INFO = 379 /* 0x17b */, 431 HAL_HE_SIG_B1_MU_INFO = 380 /* 0x17c */, 432 HAL_HE_SIG_B2_MU_INFO = 381 /* 0x17d */, 433 HAL_HE_SIG_B2_OFDMA_INFO = 382 /* 0x17e */, 434 HAL_PDG_SW_MODE_BW_START = 383 /* 0x17f */, 435 HAL_PDG_SW_MODE_BW_END = 384 /* 0x180 */, 436 HAL_PDG_WAIT_FOR_MAC_REQUEST = 385 /* 0x181 */, 437 HAL_PDG_WAIT_FOR_PHY_REQUEST = 386 /* 0x182 */, 438 HAL_SCHEDULER_END = 387 /* 0x183 */, 439 HAL_PEER_TABLE_ENTRY = 388 /* 0x184 */, 440 HAL_SW_PEER_INFO = 389 /* 0x185 */, 441 HAL_RXOLE_CCE_CLASSIFY_INFO = 390 /* 0x186 */, 442 HAL_TCL_CCE_CLASSIFY_INFO = 391 /* 0x187 */, 443 HAL_RXOLE_CCE_INFO = 392 /* 0x188 */, 444 HAL_TCL_CCE_INFO = 393 /* 0x189 */, 445 HAL_TCL_CCE_SUPERRULE = 394 /* 0x18a */, 446 HAL_CCE_RULE = 395 /* 0x18b */, 447 HAL_RX_PPDU_START_DROPPED = 396 /* 0x18c */, 448 HAL_RX_PPDU_END_DROPPED = 397 /* 0x18d */, 449 HAL_RX_PPDU_END_STATUS_DONE_DROPPED = 398 /* 0x18e */, 450 HAL_RX_MPDU_START_DROPPED = 399 /* 0x18f */, 451 HAL_RX_MSDU_START_DROPPED = 400 /* 0x190 */, 452 HAL_RX_MSDU_END_DROPPED = 401 /* 0x191 */, 453 HAL_RX_MPDU_END_DROPPED = 402 /* 0x192 */, 454 HAL_RX_ATTENTION_DROPPED = 403 /* 0x193 */, 455 HAL_TXPCU_USER_SETUP = 404 /* 0x194 */, 456 HAL_RXPCU_USER_SETUP_EXT = 405 /* 0x195 */, 457 HAL_CE_SRC_DESC = 406 /* 0x196 */, 458 HAL_CE_STAT_DESC = 407 /* 0x197 */, 459 HAL_RXOLE_CCE_SUPERRULE = 408 /* 0x198 */, 460 HAL_TX_RATE_STATS_INFO = 409 /* 0x199 */, 461 HAL_CMD_PART_0_END = 410 /* 0x19a */, 462 HAL_MACTX_SYNTH_ON = 411 /* 0x19b */, 463 HAL_SCH_CRITICAL_TLV_REFERENCE = 412 /* 0x19c */, 464 HAL_TQM_MPDU_GLOBAL_START = 413 /* 0x19d */, 465 HAL_EXAMPLE_TLV_32 = 414 /* 0x19e */, 466 HAL_TQM_UPDATE_TX_MSDU_FLOW = 415 /* 0x19f */, 467 HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD = 416 /* 0x1a0 */, 468 HAL_TQM_UPDATE_TX_MSDU_FLOW_STATUS = 417 /* 0x1a1 */, 469 HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS = 418 /* 0x1a2 */, 470 HAL_REO_UPDATE_RX_REO_QUEUE = 419 /* 0x1a3 */, 471 HAL_CE_DST_DESC = 420 /* 0x1a4 */, 472 HAL_TLV_BASE = 511 /* 0x1ff */, 473 }; 474 475 #define HAL_TLV_HDR_TAG GENMASK(9, 1) 476 #define HAL_TLV_HDR_LEN GENMASK(25, 10) 477 478 #define HAL_TLV_ALIGN 4 479 480 struct hal_tlv_hdr { 481 u32 tl; 482 u8 value[]; 483 } __packed; 484 485 #define RX_MPDU_DESC_INFO0_MSDU_COUNT GENMASK(7, 0) 486 #define RX_MPDU_DESC_INFO0_SEQ_NUM GENMASK(19, 8) 487 #define RX_MPDU_DESC_INFO0_FRAG_FLAG BIT(20) 488 #define RX_MPDU_DESC_INFO0_MPDU_RETRY BIT(21) 489 #define RX_MPDU_DESC_INFO0_AMPDU_FLAG BIT(22) 490 #define RX_MPDU_DESC_INFO0_BAR_FRAME BIT(23) 491 #define RX_MPDU_DESC_INFO0_VALID_PN BIT(24) 492 #define RX_MPDU_DESC_INFO0_VALID_SA BIT(25) 493 #define RX_MPDU_DESC_INFO0_SA_IDX_TIMEOUT BIT(26) 494 #define RX_MPDU_DESC_INFO0_VALID_DA BIT(27) 495 #define RX_MPDU_DESC_INFO0_DA_MCBC BIT(28) 496 #define RX_MPDU_DESC_INFO0_DA_IDX_TIMEOUT BIT(29) 497 #define RX_MPDU_DESC_INFO0_RAW_MPDU BIT(30) 498 499 #define RX_MPDU_DESC_META_DATA_PEER_ID GENMASK(15, 0) 500 501 struct rx_mpdu_desc { 502 u32 info0; /* %RX_MPDU_DESC_INFO */ 503 u32 meta_data; 504 } __packed; 505 506 /* rx_mpdu_desc 507 * Producer: RXDMA 508 * Consumer: REO/SW/FW 509 * 510 * msdu_count 511 * The number of MSDUs within the MPDU 512 * 513 * mpdu_sequence_number 514 * The field can have two different meanings based on the setting 515 * of field 'bar_frame'. If 'bar_frame' is set, it means the MPDU 516 * start sequence number from the BAR frame otherwise it means 517 * the MPDU sequence number of the received frame. 518 * 519 * fragment_flag 520 * When set, this MPDU is a fragment and REO should forward this 521 * fragment MPDU to the REO destination ring without any reorder 522 * checks, pn checks or bitmap update. This implies that REO is 523 * forwarding the pointer to the MSDU link descriptor. 524 * 525 * mpdu_retry_bit 526 * The retry bit setting from the MPDU header of the received frame 527 * 528 * ampdu_flag 529 * Indicates the MPDU was received as part of an A-MPDU. 530 * 531 * bar_frame 532 * Indicates the received frame is a BAR frame. After processing, 533 * this frame shall be pushed to SW or deleted. 534 * 535 * valid_pn 536 * When not set, REO will not perform a PN sequence number check. 537 * 538 * valid_sa 539 * Indicates OLE found a valid SA entry for all MSDUs in this MPDU. 540 * 541 * sa_idx_timeout 542 * Indicates, at least 1 MSDU within the MPDU has an unsuccessful 543 * MAC source address search due to the expiration of search timer. 544 * 545 * valid_da 546 * When set, OLE found a valid DA entry for all MSDUs in this MPDU. 547 * 548 * da_mcbc 549 * Field Only valid if valid_da is set. Indicates at least one of 550 * the DA addresses is a Multicast or Broadcast address. 551 * 552 * da_idx_timeout 553 * Indicates, at least 1 MSDU within the MPDU has an unsuccessful 554 * MAC destination address search due to the expiration of search 555 * timer. 556 * 557 * raw_mpdu 558 * Field only valid when first_msdu_in_mpdu_flag is set. Indicates 559 * the contents in the MSDU buffer contains a 'RAW' MPDU. 560 */ 561 562 enum hal_rx_msdu_desc_reo_dest_ind { 563 HAL_RX_MSDU_DESC_REO_DEST_IND_TCL, 564 HAL_RX_MSDU_DESC_REO_DEST_IND_SW1, 565 HAL_RX_MSDU_DESC_REO_DEST_IND_SW2, 566 HAL_RX_MSDU_DESC_REO_DEST_IND_SW3, 567 HAL_RX_MSDU_DESC_REO_DEST_IND_SW4, 568 HAL_RX_MSDU_DESC_REO_DEST_IND_RELEASE, 569 HAL_RX_MSDU_DESC_REO_DEST_IND_FW, 570 }; 571 572 #define RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU BIT(0) 573 #define RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU BIT(1) 574 #define RX_MSDU_DESC_INFO0_MSDU_CONTINUATION BIT(2) 575 #define RX_MSDU_DESC_INFO0_MSDU_LENGTH GENMASK(16, 3) 576 #define RX_MSDU_DESC_INFO0_REO_DEST_IND GENMASK(21, 17) 577 #define RX_MSDU_DESC_INFO0_MSDU_DROP BIT(22) 578 #define RX_MSDU_DESC_INFO0_VALID_SA BIT(23) 579 #define RX_MSDU_DESC_INFO0_SA_IDX_TIMEOUT BIT(24) 580 #define RX_MSDU_DESC_INFO0_VALID_DA BIT(25) 581 #define RX_MSDU_DESC_INFO0_DA_MCBC BIT(26) 582 #define RX_MSDU_DESC_INFO0_DA_IDX_TIMEOUT BIT(27) 583 584 #define HAL_RX_MSDU_PKT_LENGTH_GET(val) \ 585 (FIELD_GET(RX_MSDU_DESC_INFO0_MSDU_LENGTH, (val))) 586 587 struct rx_msdu_desc { 588 u32 info0; 589 u32 rsvd0; 590 } __packed; 591 592 /* rx_msdu_desc 593 * 594 * first_msdu_in_mpdu 595 * Indicates first msdu in mpdu. 596 * 597 * last_msdu_in_mpdu 598 * Indicates last msdu in mpdu. This flag can be true only when 599 * 'Msdu_continuation' set to 0. This implies that when an msdu 600 * is spread out over multiple buffers and thus msdu_continuation 601 * is set, only for the very last buffer of the msdu, can the 602 * 'last_msdu_in_mpdu' be set. 603 * 604 * When both first_msdu_in_mpdu and last_msdu_in_mpdu are set, 605 * the MPDU that this MSDU belongs to only contains a single MSDU. 606 * 607 * msdu_continuation 608 * When set, this MSDU buffer was not able to hold the entire MSDU. 609 * The next buffer will therefor contain additional information 610 * related to this MSDU. 611 * 612 * msdu_length 613 * Field is only valid in combination with the 'first_msdu_in_mpdu' 614 * being set. Full MSDU length in bytes after decapsulation. This 615 * field is still valid for MPDU frames without A-MSDU. It still 616 * represents MSDU length after decapsulation Or in case of RAW 617 * MPDUs, it indicates the length of the entire MPDU (without FCS 618 * field). 619 * 620 * reo_destination_indication 621 * The id of the reo exit ring where the msdu frame shall push 622 * after (MPDU level) reordering has finished. Values are defined 623 * in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_. 624 * 625 * msdu_drop 626 * Indicates that REO shall drop this MSDU and not forward it to 627 * any other ring. 628 * 629 * valid_sa 630 * Indicates OLE found a valid SA entry for this MSDU. 631 * 632 * sa_idx_timeout 633 * Indicates, an unsuccessful MAC source address search due to 634 * the expiration of search timer for this MSDU. 635 * 636 * valid_da 637 * When set, OLE found a valid DA entry for this MSDU. 638 * 639 * da_mcbc 640 * Field Only valid if valid_da is set. Indicates the DA address 641 * is a Multicast or Broadcast address for this MSDU. 642 * 643 * da_idx_timeout 644 * Indicates, an unsuccessful MAC destination address search due 645 * to the expiration of search timer fot this MSDU. 646 */ 647 648 enum hal_reo_dest_ring_buffer_type { 649 HAL_REO_DEST_RING_BUFFER_TYPE_MSDU, 650 HAL_REO_DEST_RING_BUFFER_TYPE_LINK_DESC, 651 }; 652 653 enum hal_reo_dest_ring_push_reason { 654 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED, 655 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION, 656 }; 657 658 enum hal_reo_dest_ring_error_code { 659 HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO, 660 HAL_REO_DEST_RING_ERROR_CODE_DESC_INVALID, 661 HAL_REO_DEST_RING_ERROR_CODE_AMPDU_IN_NON_BA, 662 HAL_REO_DEST_RING_ERROR_CODE_NON_BA_DUPLICATE, 663 HAL_REO_DEST_RING_ERROR_CODE_BA_DUPLICATE, 664 HAL_REO_DEST_RING_ERROR_CODE_FRAME_2K_JUMP, 665 HAL_REO_DEST_RING_ERROR_CODE_BAR_2K_JUMP, 666 HAL_REO_DEST_RING_ERROR_CODE_FRAME_OOR, 667 HAL_REO_DEST_RING_ERROR_CODE_BAR_OOR, 668 HAL_REO_DEST_RING_ERROR_CODE_NO_BA_SESSION, 669 HAL_REO_DEST_RING_ERROR_CODE_FRAME_SN_EQUALS_SSN, 670 HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED, 671 HAL_REO_DEST_RING_ERROR_CODE_2K_ERR_FLAG_SET, 672 HAL_REO_DEST_RING_ERROR_CODE_PN_ERR_FLAG_SET, 673 HAL_REO_DEST_RING_ERROR_CODE_DESC_BLOCKED, 674 HAL_REO_DEST_RING_ERROR_CODE_MAX, 675 }; 676 677 #define HAL_REO_DEST_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 678 #define HAL_REO_DEST_RING_INFO0_BUFFER_TYPE BIT(8) 679 #define HAL_REO_DEST_RING_INFO0_PUSH_REASON GENMASK(10, 9) 680 #define HAL_REO_DEST_RING_INFO0_ERROR_CODE GENMASK(15, 11) 681 #define HAL_REO_DEST_RING_INFO0_RX_QUEUE_NUM GENMASK(31, 16) 682 683 #define HAL_REO_DEST_RING_INFO1_REORDER_INFO_VALID BIT(0) 684 #define HAL_REO_DEST_RING_INFO1_REORDER_OPCODE GENMASK(4, 1) 685 #define HAL_REO_DEST_RING_INFO1_REORDER_SLOT_IDX GENMASK(12, 5) 686 687 #define HAL_REO_DEST_RING_INFO2_RING_ID GENMASK(27, 20) 688 #define HAL_REO_DEST_RING_INFO2_LOOPING_COUNT GENMASK(31, 28) 689 690 struct hal_reo_dest_ring { 691 struct ath11k_buffer_addr buf_addr_info; 692 struct rx_mpdu_desc rx_mpdu_info; 693 struct rx_msdu_desc rx_msdu_info; 694 u32 queue_addr_lo; 695 u32 info0; /* %HAL_REO_DEST_RING_INFO0_ */ 696 u32 info1; /* %HAL_REO_DEST_RING_INFO1_ */ 697 u32 rsvd0; 698 u32 rsvd1; 699 u32 rsvd2; 700 u32 rsvd3; 701 u32 rsvd4; 702 u32 rsvd5; 703 u32 info2; /* %HAL_REO_DEST_RING_INFO2_ */ 704 } __packed; 705 706 /* hal_reo_dest_ring 707 * 708 * Producer: RXDMA 709 * Consumer: REO/SW/FW 710 * 711 * buf_addr_info 712 * Details of the physical address of a buffer or MSDU 713 * link descriptor. 714 * 715 * rx_mpdu_info 716 * General information related to the MPDU that is passed 717 * on from REO entrance ring to the REO destination ring. 718 * 719 * rx_msdu_info 720 * General information related to the MSDU that is passed 721 * on from RXDMA all the way to the REO destination ring. 722 * 723 * queue_addr_lo 724 * Address (lower 32 bits) of the REO queue descriptor. 725 * 726 * queue_addr_hi 727 * Address (upper 8 bits) of the REO queue descriptor. 728 * 729 * buffer_type 730 * Indicates the type of address provided in the buf_addr_info. 731 * Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_. 732 * 733 * push_reason 734 * Reason for pushing this frame to this exit ring. Values are 735 * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_. 736 * 737 * error_code 738 * Valid only when 'push_reason' is set. All error codes are 739 * defined in enum %HAL_REO_DEST_RING_ERROR_CODE_. 740 * 741 * rx_queue_num 742 * Indicates the REO MPDU reorder queue id from which this frame 743 * originated. 744 * 745 * reorder_info_valid 746 * When set, REO has been instructed to not perform the actual 747 * re-ordering of frames for this queue, but just to insert 748 * the reorder opcodes. 749 * 750 * reorder_opcode 751 * Field is valid when 'reorder_info_valid' is set. This field is 752 * always valid for debug purpose as well. 753 * 754 * reorder_slot_idx 755 * Valid only when 'reorder_info_valid' is set. 756 * 757 * ring_id 758 * The buffer pointer ring id. 759 * 0 - Idle ring 760 * 1 - N refers to other rings. 761 * 762 * looping_count 763 * Indicates the number of times the producer of entries into 764 * this ring has looped around the ring. 765 */ 766 767 enum hal_reo_entr_rxdma_ecode { 768 HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR, 769 HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR, 770 HAL_REO_ENTR_RING_RXDMA_ECODE_FCS_ERR, 771 HAL_REO_ENTR_RING_RXDMA_ECODE_DECRYPT_ERR, 772 HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR, 773 HAL_REO_ENTR_RING_RXDMA_ECODE_UNECRYPTED_ERR, 774 HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LEN_ERR, 775 HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LIMIT_ERR, 776 HAL_REO_ENTR_RING_RXDMA_ECODE_WIFI_PARSE_ERR, 777 HAL_REO_ENTR_RING_RXDMA_ECODE_AMSDU_PARSE_ERR, 778 HAL_REO_ENTR_RING_RXDMA_ECODE_SA_TIMEOUT_ERR, 779 HAL_REO_ENTR_RING_RXDMA_ECODE_DA_TIMEOUT_ERR, 780 HAL_REO_ENTR_RING_RXDMA_ECODE_FLOW_TIMEOUT_ERR, 781 HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR, 782 HAL_REO_ENTR_RING_RXDMA_ECODE_MAX, 783 }; 784 785 #define HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 786 #define HAL_REO_ENTR_RING_INFO0_MPDU_BYTE_COUNT GENMASK(21, 8) 787 #define HAL_REO_ENTR_RING_INFO0_DEST_IND GENMASK(26, 22) 788 #define HAL_REO_ENTR_RING_INFO0_FRAMELESS_BAR BIT(27) 789 790 #define HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON GENMASK(1, 0) 791 #define HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE GENMASK(6, 2) 792 793 struct hal_reo_entrance_ring { 794 struct ath11k_buffer_addr buf_addr_info; 795 struct rx_mpdu_desc rx_mpdu_info; 796 u32 queue_addr_lo; 797 u32 info0; /* %HAL_REO_ENTR_RING_INFO0_ */ 798 u32 info1; /* %HAL_REO_ENTR_RING_INFO1_ */ 799 u32 info2; /* %HAL_REO_DEST_RING_INFO2_ */ 800 801 } __packed; 802 803 /* hal_reo_entrance_ring 804 * 805 * Producer: RXDMA 806 * Consumer: REO 807 * 808 * buf_addr_info 809 * Details of the physical address of a buffer or MSDU 810 * link descriptor. 811 * 812 * rx_mpdu_info 813 * General information related to the MPDU that is passed 814 * on from REO entrance ring to the REO destination ring. 815 * 816 * queue_addr_lo 817 * Address (lower 32 bits) of the REO queue descriptor. 818 * 819 * queue_addr_hi 820 * Address (upper 8 bits) of the REO queue descriptor. 821 * 822 * mpdu_byte_count 823 * An approximation of the number of bytes received in this MPDU. 824 * Used to keeps stats on the amount of data flowing 825 * through a queue. 826 * 827 * reo_destination_indication 828 * The id of the reo exit ring where the msdu frame shall push 829 * after (MPDU level) reordering has finished. Values are defined 830 * in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_. 831 * 832 * frameless_bar 833 * Indicates that this REO entrance ring struct contains BAR info 834 * from a multi TID BAR frame. The original multi TID BAR frame 835 * itself contained all the REO info for the first TID, but all 836 * the subsequent TID info and their linkage to the REO descriptors 837 * is passed down as 'frameless' BAR info. 838 * 839 * The only fields valid in this descriptor when this bit is set 840 * are queue_addr_lo, queue_addr_hi, mpdu_sequence_number, 841 * bar_frame and peer_meta_data. 842 * 843 * rxdma_push_reason 844 * Reason for pushing this frame to this exit ring. Values are 845 * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_. 846 * 847 * rxdma_error_code 848 * Valid only when 'push_reason' is set. All error codes are 849 * defined in enum %HAL_REO_ENTR_RING_RXDMA_ECODE_. 850 * 851 * ring_id 852 * The buffer pointer ring id. 853 * 0 - Idle ring 854 * 1 - N refers to other rings. 855 * 856 * looping_count 857 * Indicates the number of times the producer of entries into 858 * this ring has looped around the ring. 859 */ 860 861 #define HAL_SW_MON_RING_INFO0_RXDMA_PUSH_REASON GENMASK(1, 0) 862 #define HAL_SW_MON_RING_INFO0_RXDMA_ERROR_CODE GENMASK(6, 2) 863 #define HAL_SW_MON_RING_INFO0_MPDU_FRAG_NUMBER GENMASK(10, 7) 864 #define HAL_SW_MON_RING_INFO0_FRAMELESS_BAR BIT(11) 865 #define HAL_SW_MON_RING_INFO0_STATUS_BUF_CNT GENMASK(15, 12) 866 #define HAL_SW_MON_RING_INFO0_END_OF_PPDU BIT(16) 867 868 #define HAL_SW_MON_RING_INFO1_PHY_PPDU_ID GENMASK(15, 0) 869 #define HAL_SW_MON_RING_INFO1_RING_ID GENMASK(27, 20) 870 #define HAL_SW_MON_RING_INFO1_LOOPING_COUNT GENMASK(31, 28) 871 872 struct hal_sw_monitor_ring { 873 struct ath11k_buffer_addr buf_addr_info; 874 struct rx_mpdu_desc rx_mpdu_info; 875 struct ath11k_buffer_addr status_buf_addr_info; 876 u32 info0; 877 u32 info1; 878 } __packed; 879 880 #define HAL_REO_CMD_HDR_INFO0_CMD_NUMBER GENMASK(15, 0) 881 #define HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED BIT(16) 882 883 struct hal_reo_cmd_hdr { 884 u32 info0; 885 } __packed; 886 887 #define HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 888 #define HAL_REO_GET_QUEUE_STATS_INFO0_CLEAR_STATS BIT(8) 889 890 struct hal_reo_get_queue_stats { 891 struct hal_reo_cmd_hdr cmd; 892 u32 queue_addr_lo; 893 u32 info0; 894 u32 rsvd0[6]; 895 } __packed; 896 897 /* hal_reo_get_queue_stats 898 * Producer: SW 899 * Consumer: REO 900 * 901 * cmd 902 * Details for command execution tracking purposes. 903 * 904 * queue_addr_lo 905 * Address (lower 32 bits) of the REO queue descriptor. 906 * 907 * queue_addr_hi 908 * Address (upper 8 bits) of the REO queue descriptor. 909 * 910 * clear_stats 911 * Clear stats settings. When set, Clear the stats after 912 * generating the status. 913 * 914 * Following stats will be cleared. 915 * Timeout_count 916 * Forward_due_to_bar_count 917 * Duplicate_count 918 * Frames_in_order_count 919 * BAR_received_count 920 * MPDU_Frames_processed_count 921 * MSDU_Frames_processed_count 922 * Total_processed_byte_count 923 * Late_receive_MPDU_count 924 * window_jump_2k 925 * Hole_count 926 */ 927 928 #define HAL_REO_FLUSH_QUEUE_INFO0_DESC_ADDR_HI GENMASK(7, 0) 929 #define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_DESC_ADDR BIT(8) 930 #define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_RESRC_IDX GENMASK(10, 9) 931 932 struct hal_reo_flush_queue { 933 struct hal_reo_cmd_hdr cmd; 934 u32 desc_addr_lo; 935 u32 info0; 936 u32 rsvd0[6]; 937 } __packed; 938 939 #define HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI GENMASK(7, 0) 940 #define HAL_REO_FLUSH_CACHE_INFO0_FWD_ALL_MPDUS BIT(8) 941 #define HAL_REO_FLUSH_CACHE_INFO0_RELEASE_BLOCK_IDX BIT(9) 942 #define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX GENMASK(11, 10) 943 #define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE BIT(12) 944 #define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE BIT(13) 945 #define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL BIT(14) 946 947 struct hal_reo_flush_cache { 948 struct hal_reo_cmd_hdr cmd; 949 u32 cache_addr_lo; 950 u32 info0; 951 u32 rsvd0[6]; 952 } __packed; 953 954 #define HAL_TCL_DATA_CMD_INFO0_DESC_TYPE BIT(0) 955 #define HAL_TCL_DATA_CMD_INFO0_EPD BIT(1) 956 #define HAL_TCL_DATA_CMD_INFO0_ENCAP_TYPE GENMASK(3, 2) 957 #define HAL_TCL_DATA_CMD_INFO0_ENCRYPT_TYPE GENMASK(7, 4) 958 #define HAL_TCL_DATA_CMD_INFO0_SRC_BUF_SWAP BIT(8) 959 #define HAL_TCL_DATA_CMD_INFO0_LNK_META_SWAP BIT(9) 960 #define HAL_TCL_DATA_CMD_INFO0_SEARCH_TYPE GENMASK(13, 12) 961 #define HAL_TCL_DATA_CMD_INFO0_ADDR_EN GENMASK(15, 14) 962 #define HAL_TCL_DATA_CMD_INFO0_CMD_NUM GENMASK(31, 16) 963 964 #define HAL_TCL_DATA_CMD_INFO1_DATA_LEN GENMASK(15, 0) 965 #define HAL_TCL_DATA_CMD_INFO1_IP4_CKSUM_EN BIT(16) 966 #define HAL_TCL_DATA_CMD_INFO1_UDP4_CKSUM_EN BIT(17) 967 #define HAL_TCL_DATA_CMD_INFO1_UDP6_CKSUM_EN BIT(18) 968 #define HAL_TCL_DATA_CMD_INFO1_TCP4_CKSUM_EN BIT(19) 969 #define HAL_TCL_DATA_CMD_INFO1_TCP6_CKSUM_EN BIT(20) 970 #define HAL_TCL_DATA_CMD_INFO1_TO_FW BIT(21) 971 #define HAL_TCL_DATA_CMD_INFO1_PKT_OFFSET GENMASK(31, 23) 972 973 #define HAL_TCL_DATA_CMD_INFO2_BUF_TIMESTAMP GENMASK(18, 0) 974 #define HAL_TCL_DATA_CMD_INFO2_BUF_T_VALID BIT(19) 975 #define HAL_IPQ8074_TCL_DATA_CMD_INFO2_MESH_ENABLE BIT(20) 976 #define HAL_TCL_DATA_CMD_INFO2_TID_OVERWRITE BIT(21) 977 #define HAL_TCL_DATA_CMD_INFO2_TID GENMASK(25, 22) 978 #define HAL_TCL_DATA_CMD_INFO2_LMAC_ID GENMASK(27, 26) 979 980 #define HAL_TCL_DATA_CMD_INFO3_DSCP_TID_TABLE_IDX GENMASK(5, 0) 981 #define HAL_TCL_DATA_CMD_INFO3_SEARCH_INDEX GENMASK(25, 6) 982 #define HAL_TCL_DATA_CMD_INFO3_CACHE_SET_NUM GENMASK(29, 26) 983 #define HAL_QCN9074_TCL_DATA_CMD_INFO3_MESH_ENABLE GENMASK(31, 30) 984 985 #define HAL_TCL_DATA_CMD_INFO4_RING_ID GENMASK(27, 20) 986 #define HAL_TCL_DATA_CMD_INFO4_LOOPING_COUNT GENMASK(31, 28) 987 988 enum hal_encrypt_type { 989 HAL_ENCRYPT_TYPE_WEP_40, 990 HAL_ENCRYPT_TYPE_WEP_104, 991 HAL_ENCRYPT_TYPE_TKIP_NO_MIC, 992 HAL_ENCRYPT_TYPE_WEP_128, 993 HAL_ENCRYPT_TYPE_TKIP_MIC, 994 HAL_ENCRYPT_TYPE_WAPI, 995 HAL_ENCRYPT_TYPE_CCMP_128, 996 HAL_ENCRYPT_TYPE_OPEN, 997 HAL_ENCRYPT_TYPE_CCMP_256, 998 HAL_ENCRYPT_TYPE_GCMP_128, 999 HAL_ENCRYPT_TYPE_AES_GCMP_256, 1000 HAL_ENCRYPT_TYPE_WAPI_GCM_SM4, 1001 }; 1002 1003 enum hal_tcl_encap_type { 1004 HAL_TCL_ENCAP_TYPE_RAW, 1005 HAL_TCL_ENCAP_TYPE_NATIVE_WIFI, 1006 HAL_TCL_ENCAP_TYPE_ETHERNET, 1007 HAL_TCL_ENCAP_TYPE_802_3 = 3, 1008 }; 1009 1010 enum hal_tcl_desc_type { 1011 HAL_TCL_DESC_TYPE_BUFFER, 1012 HAL_TCL_DESC_TYPE_EXT_DESC, 1013 }; 1014 1015 enum hal_wbm_htt_tx_comp_status { 1016 HAL_WBM_REL_HTT_TX_COMP_STATUS_OK, 1017 HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP, 1018 HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL, 1019 HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ, 1020 HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT, 1021 HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY, 1022 }; 1023 1024 struct hal_tcl_data_cmd { 1025 struct ath11k_buffer_addr buf_addr_info; 1026 u32 info0; 1027 u32 info1; 1028 u32 info2; 1029 u32 info3; 1030 u32 info4; 1031 } __packed; 1032 1033 /* hal_tcl_data_cmd 1034 * 1035 * buf_addr_info 1036 * Details of the physical address of a buffer or MSDU 1037 * link descriptor. 1038 * 1039 * desc_type 1040 * Indicates the type of address provided in the buf_addr_info. 1041 * Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_. 1042 * 1043 * epd 1044 * When this bit is set then input packet is an EPD type. 1045 * 1046 * encap_type 1047 * Indicates the encapsulation that HW will perform. Values are 1048 * defined in enum %HAL_TCL_ENCAP_TYPE_. 1049 * 1050 * encrypt_type 1051 * Field only valid for encap_type: RAW 1052 * Values are defined in enum %HAL_ENCRYPT_TYPE_. 1053 * 1054 * src_buffer_swap 1055 * Treats source memory (packet buffer) organization as big-endian. 1056 * 1'b0: Source memory is little endian 1057 * 1'b1: Source memory is big endian 1058 * 1059 * link_meta_swap 1060 * Treats link descriptor and Metadata as big-endian. 1061 * 1'b0: memory is little endian 1062 * 1'b1: memory is big endian 1063 * 1064 * search_type 1065 * Search type select 1066 * 0 - Normal search, 1 - Index based address search, 1067 * 2 - Index based flow search 1068 * 1069 * addrx_en 1070 * addry_en 1071 * Address X/Y search enable in ASE correspondingly. 1072 * 1'b0: Search disable 1073 * 1'b1: Search Enable 1074 * 1075 * cmd_num 1076 * This number can be used to match against status. 1077 * 1078 * data_length 1079 * MSDU length in case of direct descriptor. Length of link 1080 * extension descriptor in case of Link extension descriptor. 1081 * 1082 * *_checksum_en 1083 * Enable checksum replacement for ipv4, udp_over_ipv4, ipv6, 1084 * udp_over_ipv6, tcp_over_ipv4 and tcp_over_ipv6. 1085 * 1086 * to_fw 1087 * Forward packet to FW along with classification result. The 1088 * packet will not be forward to TQM when this bit is set. 1089 * 1'b0: Use classification result to forward the packet. 1090 * 1'b1: Override classification result & forward packet only to fw 1091 * 1092 * packet_offset 1093 * Packet offset from Metadata in case of direct buffer descriptor. 1094 * 1095 * buffer_timestamp 1096 * buffer_timestamp_valid 1097 * Frame system entrance timestamp. It shall be filled by first 1098 * module (SW, TCL or TQM) that sees the frames first. 1099 * 1100 * mesh_enable 1101 * For raw WiFi frames, this indicates transmission to a mesh STA, 1102 * enabling the interpretation of the 'Mesh Control Present' bit 1103 * (bit 8) of QoS Control. 1104 * For native WiFi frames, this indicates that a 'Mesh Control' 1105 * field is present between the header and the LLC. 1106 * 1107 * hlos_tid_overwrite 1108 * 1109 * When set, TCL shall ignore the IP DSCP and VLAN PCP 1110 * fields and use HLOS_TID as the final TID. Otherwise TCL 1111 * shall consider the DSCP and PCP fields as well as HLOS_TID 1112 * and choose a final TID based on the configured priority 1113 * 1114 * hlos_tid 1115 * HLOS MSDU priority 1116 * Field is used when HLOS_TID_overwrite is set. 1117 * 1118 * lmac_id 1119 * TCL uses this LMAC_ID in address search, i.e, while 1120 * finding matching entry for the packet in AST corresponding 1121 * to given LMAC_ID 1122 * 1123 * If LMAC ID is all 1s (=> value 3), it indicates wildcard 1124 * match for any MAC 1125 * 1126 * dscp_tid_table_num 1127 * DSCP to TID mapping table number that need to be used 1128 * for the MSDU. 1129 * 1130 * search_index 1131 * The index that will be used for index based address or 1132 * flow search. The field is valid when 'search_type' is 1 or 2. 1133 * 1134 * cache_set_num 1135 * 1136 * Cache set number that should be used to cache the index 1137 * based search results, for address and flow search. This 1138 * value should be equal to LSB four bits of the hash value of 1139 * match data, in case of search index points to an entry which 1140 * may be used in content based search also. The value can be 1141 * anything when the entry pointed by search index will not be 1142 * used for content based search. 1143 * 1144 * ring_id 1145 * The buffer pointer ring ID. 1146 * 0 refers to the IDLE ring 1147 * 1 - N refers to other rings 1148 * 1149 * looping_count 1150 * 1151 * A count value that indicates the number of times the 1152 * producer of entries into the Ring has looped around the 1153 * ring. 1154 * 1155 * At initialization time, this value is set to 0. On the 1156 * first loop, this value is set to 1. After the max value is 1157 * reached allowed by the number of bits for this field, the 1158 * count value continues with 0 again. 1159 * 1160 * In case SW is the consumer of the ring entries, it can 1161 * use this field to figure out up to where the producer of 1162 * entries has created new entries. This eliminates the need to 1163 * check where the head pointer' of the ring is located once 1164 * the SW starts processing an interrupt indicating that new 1165 * entries have been put into this ring... 1166 * 1167 * Also note that SW if it wants only needs to look at the 1168 * LSB bit of this count value. 1169 */ 1170 1171 #define HAL_TCL_DESC_LEN sizeof(struct hal_tcl_data_cmd) 1172 1173 enum hal_tcl_gse_ctrl { 1174 HAL_TCL_GSE_CTRL_RD_STAT, 1175 HAL_TCL_GSE_CTRL_SRCH_DIS, 1176 HAL_TCL_GSE_CTRL_WR_BK_SINGLE, 1177 HAL_TCL_GSE_CTRL_WR_BK_ALL, 1178 HAL_TCL_GSE_CTRL_INVAL_SINGLE, 1179 HAL_TCL_GSE_CTRL_INVAL_ALL, 1180 HAL_TCL_GSE_CTRL_WR_BK_INVAL_SINGLE, 1181 HAL_TCL_GSE_CTRL_WR_BK_INVAL_ALL, 1182 HAL_TCL_GSE_CTRL_CLR_STAT_SINGLE, 1183 }; 1184 1185 /* hal_tcl_gse_ctrl 1186 * 1187 * rd_stat 1188 * Report or Read statistics 1189 * srch_dis 1190 * Search disable. Report only Hash. 1191 * wr_bk_single 1192 * Write Back single entry 1193 * wr_bk_all 1194 * Write Back entire cache entry 1195 * inval_single 1196 * Invalidate single cache entry 1197 * inval_all 1198 * Invalidate entire cache 1199 * wr_bk_inval_single 1200 * Write back and invalidate single entry in cache 1201 * wr_bk_inval_all 1202 * Write back and invalidate entire cache 1203 * clr_stat_single 1204 * Clear statistics for single entry 1205 */ 1206 1207 #define HAL_TCL_GSE_CMD_INFO0_CTRL_BUF_ADDR_HI GENMASK(7, 0) 1208 #define HAL_TCL_GSE_CMD_INFO0_GSE_CTRL GENMASK(11, 8) 1209 #define HAL_TCL_GSE_CMD_INFO0_GSE_SEL BIT(12) 1210 #define HAL_TCL_GSE_CMD_INFO0_STATUS_DEST_RING_ID BIT(13) 1211 #define HAL_TCL_GSE_CMD_INFO0_SWAP BIT(14) 1212 1213 #define HAL_TCL_GSE_CMD_INFO1_RING_ID GENMASK(27, 20) 1214 #define HAL_TCL_GSE_CMD_INFO1_LOOPING_COUNT GENMASK(31, 28) 1215 1216 struct hal_tcl_gse_cmd { 1217 u32 ctrl_buf_addr_lo; 1218 u32 info0; 1219 u32 meta_data[2]; 1220 u32 rsvd0[2]; 1221 u32 info1; 1222 } __packed; 1223 1224 /* hal_tcl_gse_cmd 1225 * 1226 * ctrl_buf_addr_lo, ctrl_buf_addr_hi 1227 * Address of a control buffer containing additional info needed 1228 * for this command execution. 1229 * 1230 * gse_ctrl 1231 * GSE control operations. This includes cache operations and table 1232 * entry statistics read/clear operation. Values are defined in 1233 * enum %HAL_TCL_GSE_CTRL. 1234 * 1235 * gse_sel 1236 * To select the ASE/FSE to do the operation mention by GSE_ctrl. 1237 * 0: FSE select 1: ASE select 1238 * 1239 * status_destination_ring_id 1240 * TCL status ring to which the GSE status needs to be send. 1241 * 1242 * swap 1243 * Bit to enable byte swapping of contents of buffer. 1244 * 1245 * meta_data 1246 * Meta data to be returned in the status descriptor 1247 */ 1248 1249 enum hal_tcl_cache_op_res { 1250 HAL_TCL_CACHE_OP_RES_DONE, 1251 HAL_TCL_CACHE_OP_RES_NOT_FOUND, 1252 HAL_TCL_CACHE_OP_RES_TIMEOUT, 1253 }; 1254 1255 #define HAL_TCL_STATUS_RING_INFO0_GSE_CTRL GENMASK(3, 0) 1256 #define HAL_TCL_STATUS_RING_INFO0_GSE_SEL BIT(4) 1257 #define HAL_TCL_STATUS_RING_INFO0_CACHE_OP_RES GENMASK(6, 5) 1258 #define HAL_TCL_STATUS_RING_INFO0_MSDU_CNT GENMASK(31, 8) 1259 1260 #define HAL_TCL_STATUS_RING_INFO1_HASH_IDX GENMASK(19, 0) 1261 1262 #define HAL_TCL_STATUS_RING_INFO2_RING_ID GENMASK(27, 20) 1263 #define HAL_TCL_STATUS_RING_INFO2_LOOPING_COUNT GENMASK(31, 28) 1264 1265 struct hal_tcl_status_ring { 1266 u32 info0; 1267 u32 msdu_byte_count; 1268 u32 msdu_timestamp; 1269 u32 meta_data[2]; 1270 u32 info1; 1271 u32 rsvd0; 1272 u32 info2; 1273 } __packed; 1274 1275 /* hal_tcl_status_ring 1276 * 1277 * gse_ctrl 1278 * GSE control operations. This includes cache operations and table 1279 * entry statistics read/clear operation. Values are defined in 1280 * enum %HAL_TCL_GSE_CTRL. 1281 * 1282 * gse_sel 1283 * To select the ASE/FSE to do the operation mention by GSE_ctrl. 1284 * 0: FSE select 1: ASE select 1285 * 1286 * cache_op_res 1287 * Cache operation result. Values are defined in enum 1288 * %HAL_TCL_CACHE_OP_RES_. 1289 * 1290 * msdu_cnt 1291 * msdu_byte_count 1292 * MSDU count of Entry and MSDU byte count for entry 1. 1293 * 1294 * hash_indx 1295 * Hash value of the entry in case of search failed or disabled. 1296 */ 1297 1298 #define HAL_CE_SRC_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0) 1299 #define HAL_CE_SRC_DESC_ADDR_INFO_HASH_EN BIT(8) 1300 #define HAL_CE_SRC_DESC_ADDR_INFO_BYTE_SWAP BIT(9) 1301 #define HAL_CE_SRC_DESC_ADDR_INFO_DEST_SWAP BIT(10) 1302 #define HAL_CE_SRC_DESC_ADDR_INFO_GATHER BIT(11) 1303 #define HAL_CE_SRC_DESC_ADDR_INFO_LEN GENMASK(31, 16) 1304 1305 #define HAL_CE_SRC_DESC_META_INFO_DATA GENMASK(15, 0) 1306 1307 #define HAL_CE_SRC_DESC_FLAGS_RING_ID GENMASK(27, 20) 1308 #define HAL_CE_SRC_DESC_FLAGS_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT 1309 1310 struct hal_ce_srng_src_desc { 1311 u32 buffer_addr_low; 1312 u32 buffer_addr_info; /* %HAL_CE_SRC_DESC_ADDR_INFO_ */ 1313 u32 meta_info; /* %HAL_CE_SRC_DESC_META_INFO_ */ 1314 u32 flags; /* %HAL_CE_SRC_DESC_FLAGS_ */ 1315 } __packed; 1316 1317 /* 1318 * hal_ce_srng_src_desc 1319 * 1320 * buffer_addr_lo 1321 * LSB 32 bits of the 40 Bit Pointer to the source buffer 1322 * 1323 * buffer_addr_hi 1324 * MSB 8 bits of the 40 Bit Pointer to the source buffer 1325 * 1326 * toeplitz_en 1327 * Enable generation of 32-bit Toeplitz-LFSR hash for 1328 * data transfer. In case of gather field in first source 1329 * ring entry of the gather copy cycle in taken into account. 1330 * 1331 * src_swap 1332 * Treats source memory organization as big-endian. For 1333 * each dword read (4 bytes), the byte 0 is swapped with byte 3 1334 * and byte 1 is swapped with byte 2. 1335 * In case of gather field in first source ring entry of 1336 * the gather copy cycle in taken into account. 1337 * 1338 * dest_swap 1339 * Treats destination memory organization as big-endian. 1340 * For each dword write (4 bytes), the byte 0 is swapped with 1341 * byte 3 and byte 1 is swapped with byte 2. 1342 * In case of gather field in first source ring entry of 1343 * the gather copy cycle in taken into account. 1344 * 1345 * gather 1346 * Enables gather of multiple copy engine source 1347 * descriptors to one destination. 1348 * 1349 * ce_res_0 1350 * Reserved 1351 * 1352 * 1353 * length 1354 * Length of the buffer in units of octets of the current 1355 * descriptor 1356 * 1357 * fw_metadata 1358 * Meta data used by FW. 1359 * In case of gather field in first source ring entry of 1360 * the gather copy cycle in taken into account. 1361 * 1362 * ce_res_1 1363 * Reserved 1364 * 1365 * ce_res_2 1366 * Reserved 1367 * 1368 * ring_id 1369 * The buffer pointer ring ID. 1370 * 0 refers to the IDLE ring 1371 * 1 - N refers to other rings 1372 * Helps with debugging when dumping ring contents. 1373 * 1374 * looping_count 1375 * A count value that indicates the number of times the 1376 * producer of entries into the Ring has looped around the 1377 * ring. 1378 * 1379 * At initialization time, this value is set to 0. On the 1380 * first loop, this value is set to 1. After the max value is 1381 * reached allowed by the number of bits for this field, the 1382 * count value continues with 0 again. 1383 * 1384 * In case SW is the consumer of the ring entries, it can 1385 * use this field to figure out up to where the producer of 1386 * entries has created new entries. This eliminates the need to 1387 * check where the head pointer' of the ring is located once 1388 * the SW starts processing an interrupt indicating that new 1389 * entries have been put into this ring... 1390 * 1391 * Also note that SW if it wants only needs to look at the 1392 * LSB bit of this count value. 1393 */ 1394 1395 #define HAL_CE_DEST_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0) 1396 #define HAL_CE_DEST_DESC_ADDR_INFO_RING_ID GENMASK(27, 20) 1397 #define HAL_CE_DEST_DESC_ADDR_INFO_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT 1398 1399 struct hal_ce_srng_dest_desc { 1400 u32 buffer_addr_low; 1401 u32 buffer_addr_info; /* %HAL_CE_DEST_DESC_ADDR_INFO_ */ 1402 } __packed; 1403 1404 /* hal_ce_srng_dest_desc 1405 * 1406 * dst_buffer_low 1407 * LSB 32 bits of the 40 Bit Pointer to the Destination 1408 * buffer 1409 * 1410 * dst_buffer_high 1411 * MSB 8 bits of the 40 Bit Pointer to the Destination 1412 * buffer 1413 * 1414 * ce_res_4 1415 * Reserved 1416 * 1417 * ring_id 1418 * The buffer pointer ring ID. 1419 * 0 refers to the IDLE ring 1420 * 1 - N refers to other rings 1421 * Helps with debugging when dumping ring contents. 1422 * 1423 * looping_count 1424 * A count value that indicates the number of times the 1425 * producer of entries into the Ring has looped around the 1426 * ring. 1427 * 1428 * At initialization time, this value is set to 0. On the 1429 * first loop, this value is set to 1. After the max value is 1430 * reached allowed by the number of bits for this field, the 1431 * count value continues with 0 again. 1432 * 1433 * In case SW is the consumer of the ring entries, it can 1434 * use this field to figure out up to where the producer of 1435 * entries has created new entries. This eliminates the need to 1436 * check where the head pointer' of the ring is located once 1437 * the SW starts processing an interrupt indicating that new 1438 * entries have been put into this ring... 1439 * 1440 * Also note that SW if it wants only needs to look at the 1441 * LSB bit of this count value. 1442 */ 1443 1444 #define HAL_CE_DST_STATUS_DESC_FLAGS_HASH_EN BIT(8) 1445 #define HAL_CE_DST_STATUS_DESC_FLAGS_BYTE_SWAP BIT(9) 1446 #define HAL_CE_DST_STATUS_DESC_FLAGS_DEST_SWAP BIT(10) 1447 #define HAL_CE_DST_STATUS_DESC_FLAGS_GATHER BIT(11) 1448 #define HAL_CE_DST_STATUS_DESC_FLAGS_LEN GENMASK(31, 16) 1449 1450 #define HAL_CE_DST_STATUS_DESC_META_INFO_DATA GENMASK(15, 0) 1451 #define HAL_CE_DST_STATUS_DESC_META_INFO_RING_ID GENMASK(27, 20) 1452 #define HAL_CE_DST_STATUS_DESC_META_INFO_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT 1453 1454 struct hal_ce_srng_dst_status_desc { 1455 u32 flags; /* %HAL_CE_DST_STATUS_DESC_FLAGS_ */ 1456 u32 toeplitz_hash0; 1457 u32 toeplitz_hash1; 1458 u32 meta_info; /* HAL_CE_DST_STATUS_DESC_META_INFO_ */ 1459 } __packed; 1460 1461 /* hal_ce_srng_dst_status_desc 1462 * 1463 * ce_res_5 1464 * Reserved 1465 * 1466 * toeplitz_en 1467 * 1468 * src_swap 1469 * Source memory buffer swapped 1470 * 1471 * dest_swap 1472 * Destination memory buffer swapped 1473 * 1474 * gather 1475 * Gather of multiple copy engine source descriptors to one 1476 * destination enabled 1477 * 1478 * ce_res_6 1479 * Reserved 1480 * 1481 * length 1482 * Sum of all the Lengths of the source descriptor in the 1483 * gather chain 1484 * 1485 * toeplitz_hash_0 1486 * 32 LS bits of 64 bit Toeplitz LFSR hash result 1487 * 1488 * toeplitz_hash_1 1489 * 32 MS bits of 64 bit Toeplitz LFSR hash result 1490 * 1491 * fw_metadata 1492 * Meta data used by FW 1493 * In case of gather field in first source ring entry of 1494 * the gather copy cycle in taken into account. 1495 * 1496 * ce_res_7 1497 * Reserved 1498 * 1499 * ring_id 1500 * The buffer pointer ring ID. 1501 * 0 refers to the IDLE ring 1502 * 1 - N refers to other rings 1503 * Helps with debugging when dumping ring contents. 1504 * 1505 * looping_count 1506 * A count value that indicates the number of times the 1507 * producer of entries into the Ring has looped around the 1508 * ring. 1509 * 1510 * At initialization time, this value is set to 0. On the 1511 * first loop, this value is set to 1. After the max value is 1512 * reached allowed by the number of bits for this field, the 1513 * count value continues with 0 again. 1514 * 1515 * In case SW is the consumer of the ring entries, it can 1516 * use this field to figure out up to where the producer of 1517 * entries has created new entries. This eliminates the need to 1518 * check where the head pointer' of the ring is located once 1519 * the SW starts processing an interrupt indicating that new 1520 * entries have been put into this ring... 1521 * 1522 * Also note that SW if it wants only needs to look at the 1523 * LSB bit of this count value. 1524 */ 1525 1526 #define HAL_TX_RATE_STATS_INFO0_VALID BIT(0) 1527 #define HAL_TX_RATE_STATS_INFO0_BW GENMASK(2, 1) 1528 #define HAL_TX_RATE_STATS_INFO0_PKT_TYPE GENMASK(6, 3) 1529 #define HAL_TX_RATE_STATS_INFO0_STBC BIT(7) 1530 #define HAL_TX_RATE_STATS_INFO0_LDPC BIT(8) 1531 #define HAL_TX_RATE_STATS_INFO0_SGI GENMASK(10, 9) 1532 #define HAL_TX_RATE_STATS_INFO0_MCS GENMASK(14, 11) 1533 #define HAL_TX_RATE_STATS_INFO0_OFDMA_TX BIT(15) 1534 #define HAL_TX_RATE_STATS_INFO0_TONES_IN_RU GENMASK(27, 16) 1535 1536 enum hal_tx_rate_stats_bw { 1537 HAL_TX_RATE_STATS_BW_20, 1538 HAL_TX_RATE_STATS_BW_40, 1539 HAL_TX_RATE_STATS_BW_80, 1540 HAL_TX_RATE_STATS_BW_160, 1541 }; 1542 1543 enum hal_tx_rate_stats_pkt_type { 1544 HAL_TX_RATE_STATS_PKT_TYPE_11A, 1545 HAL_TX_RATE_STATS_PKT_TYPE_11B, 1546 HAL_TX_RATE_STATS_PKT_TYPE_11N, 1547 HAL_TX_RATE_STATS_PKT_TYPE_11AC, 1548 HAL_TX_RATE_STATS_PKT_TYPE_11AX, 1549 }; 1550 1551 enum hal_tx_rate_stats_sgi { 1552 HAL_TX_RATE_STATS_SGI_08US, 1553 HAL_TX_RATE_STATS_SGI_04US, 1554 HAL_TX_RATE_STATS_SGI_16US, 1555 HAL_TX_RATE_STATS_SGI_32US, 1556 }; 1557 1558 struct hal_tx_rate_stats { 1559 u32 info0; 1560 u32 tsf; 1561 } __packed; 1562 1563 struct hal_wbm_link_desc { 1564 struct ath11k_buffer_addr buf_addr_info; 1565 } __packed; 1566 1567 /* hal_wbm_link_desc 1568 * 1569 * Producer: WBM 1570 * Consumer: WBM 1571 * 1572 * buf_addr_info 1573 * Details of the physical address of a buffer or MSDU 1574 * link descriptor. 1575 */ 1576 1577 enum hal_wbm_rel_src_module { 1578 HAL_WBM_REL_SRC_MODULE_TQM, 1579 HAL_WBM_REL_SRC_MODULE_RXDMA, 1580 HAL_WBM_REL_SRC_MODULE_REO, 1581 HAL_WBM_REL_SRC_MODULE_FW, 1582 HAL_WBM_REL_SRC_MODULE_SW, 1583 }; 1584 1585 enum hal_wbm_rel_desc_type { 1586 HAL_WBM_REL_DESC_TYPE_REL_MSDU, 1587 HAL_WBM_REL_DESC_TYPE_MSDU_LINK, 1588 HAL_WBM_REL_DESC_TYPE_MPDU_LINK, 1589 HAL_WBM_REL_DESC_TYPE_MSDU_EXT, 1590 HAL_WBM_REL_DESC_TYPE_QUEUE_EXT, 1591 }; 1592 1593 /* hal_wbm_rel_desc_type 1594 * 1595 * msdu_buffer 1596 * The address points to an MSDU buffer 1597 * 1598 * msdu_link_descriptor 1599 * The address points to an Tx MSDU link descriptor 1600 * 1601 * mpdu_link_descriptor 1602 * The address points to an MPDU link descriptor 1603 * 1604 * msdu_ext_descriptor 1605 * The address points to an MSDU extension descriptor 1606 * 1607 * queue_ext_descriptor 1608 * The address points to an TQM queue extension descriptor. WBM should 1609 * treat this is the same way as a link descriptor. 1610 */ 1611 1612 enum hal_wbm_rel_bm_act { 1613 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE, 1614 HAL_WBM_REL_BM_ACT_REL_MSDU, 1615 }; 1616 1617 /* hal_wbm_rel_bm_act 1618 * 1619 * put_in_idle_list 1620 * Put the buffer or descriptor back in the idle list. In case of MSDU or 1621 * MDPU link descriptor, BM does not need to check to release any 1622 * individual MSDU buffers. 1623 * 1624 * release_msdu_list 1625 * This BM action can only be used in combination with desc_type being 1626 * msdu_link_descriptor. Field first_msdu_index points out which MSDU 1627 * pointer in the MSDU link descriptor is the first of an MPDU that is 1628 * released. BM shall release all the MSDU buffers linked to this first 1629 * MSDU buffer pointer. All related MSDU buffer pointer entries shall be 1630 * set to value 0, which represents the 'NULL' pointer. When all MSDU 1631 * buffer pointers in the MSDU link descriptor are 'NULL', the MSDU link 1632 * descriptor itself shall also be released. 1633 */ 1634 1635 #define HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE GENMASK(2, 0) 1636 #define HAL_WBM_RELEASE_INFO0_BM_ACTION GENMASK(5, 3) 1637 #define HAL_WBM_RELEASE_INFO0_DESC_TYPE GENMASK(8, 6) 1638 #define HAL_WBM_RELEASE_INFO0_FIRST_MSDU_IDX GENMASK(12, 9) 1639 #define HAL_WBM_RELEASE_INFO0_TQM_RELEASE_REASON GENMASK(16, 13) 1640 #define HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON GENMASK(18, 17) 1641 #define HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE GENMASK(23, 19) 1642 #define HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON GENMASK(25, 24) 1643 #define HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE GENMASK(30, 26) 1644 #define HAL_WBM_RELEASE_INFO0_WBM_INTERNAL_ERROR BIT(31) 1645 1646 #define HAL_WBM_RELEASE_INFO1_TQM_STATUS_NUMBER GENMASK(23, 0) 1647 #define HAL_WBM_RELEASE_INFO1_TRANSMIT_COUNT GENMASK(30, 24) 1648 1649 #define HAL_WBM_RELEASE_INFO2_ACK_FRAME_RSSI GENMASK(7, 0) 1650 #define HAL_WBM_RELEASE_INFO2_SW_REL_DETAILS_VALID BIT(8) 1651 #define HAL_WBM_RELEASE_INFO2_FIRST_MSDU BIT(9) 1652 #define HAL_WBM_RELEASE_INFO2_LAST_MSDU BIT(10) 1653 #define HAL_WBM_RELEASE_INFO2_MSDU_IN_AMSDU BIT(11) 1654 #define HAL_WBM_RELEASE_INFO2_FW_TX_NOTIF_FRAME BIT(12) 1655 #define HAL_WBM_RELEASE_INFO2_BUFFER_TIMESTAMP GENMASK(31, 13) 1656 1657 #define HAL_WBM_RELEASE_INFO3_PEER_ID GENMASK(15, 0) 1658 #define HAL_WBM_RELEASE_INFO3_TID GENMASK(19, 16) 1659 #define HAL_WBM_RELEASE_INFO3_RING_ID GENMASK(27, 20) 1660 #define HAL_WBM_RELEASE_INFO3_LOOPING_COUNT GENMASK(31, 28) 1661 1662 #define HAL_WBM_REL_HTT_TX_COMP_INFO0_STATUS GENMASK(12, 9) 1663 #define HAL_WBM_REL_HTT_TX_COMP_INFO0_REINJ_REASON GENMASK(16, 13) 1664 #define HAL_WBM_REL_HTT_TX_COMP_INFO0_EXP_FRAME BIT(17) 1665 1666 struct hal_wbm_release_ring { 1667 struct ath11k_buffer_addr buf_addr_info; 1668 u32 info0; 1669 u32 info1; 1670 u32 info2; 1671 struct hal_tx_rate_stats rate_stats; 1672 u32 info3; 1673 } __packed; 1674 1675 /* hal_wbm_release_ring 1676 * 1677 * Producer: SW/TQM/RXDMA/REO/SWITCH 1678 * Consumer: WBM/SW/FW 1679 * 1680 * HTT tx status is overlayed on wbm_release ring on 4-byte words 2, 3, 4 and 5 1681 * for software based completions. 1682 * 1683 * buf_addr_info 1684 * Details of the physical address of the buffer or link descriptor. 1685 * 1686 * release_source_module 1687 * Indicates which module initiated the release of this buffer/descriptor. 1688 * Values are defined in enum %HAL_WBM_REL_SRC_MODULE_. 1689 * 1690 * bm_action 1691 * Field only valid when the field return_buffer_manager in 1692 * Released_buff_or_desc_addr_info indicates: 1693 * WBM_IDLE_BUF_LIST / WBM_IDLE_DESC_LIST 1694 * Values are defined in enum %HAL_WBM_REL_BM_ACT_. 1695 * 1696 * buffer_or_desc_type 1697 * Field only valid when WBM is marked as the return_buffer_manager in 1698 * the Released_Buffer_address_info. Indicates that type of buffer or 1699 * descriptor is being released. Values are in enum %HAL_WBM_REL_DESC_TYPE. 1700 * 1701 * first_msdu_index 1702 * Field only valid for the bm_action release_msdu_list. The index of the 1703 * first MSDU in an MSDU link descriptor all belonging to the same MPDU. 1704 * 1705 * tqm_release_reason 1706 * Field only valid when Release_source_module is set to release_source_TQM 1707 * Release reasons are defined in enum %HAL_WBM_TQM_REL_REASON_. 1708 * 1709 * rxdma_push_reason 1710 * reo_push_reason 1711 * Indicates why rxdma/reo pushed the frame to this ring and values are 1712 * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_. 1713 * 1714 * rxdma_error_code 1715 * Field only valid when 'rxdma_push_reason' set to 'error_detected'. 1716 * Values are defined in enum %HAL_REO_ENTR_RING_RXDMA_ECODE_. 1717 * 1718 * reo_error_code 1719 * Field only valid when 'reo_push_reason' set to 'error_detected'. Values 1720 * are defined in enum %HAL_REO_DEST_RING_ERROR_CODE_. 1721 * 1722 * wbm_internal_error 1723 * Is set when WBM got a buffer pointer but the action was to push it to 1724 * the idle link descriptor ring or do link related activity OR 1725 * Is set when WBM got a link buffer pointer but the action was to push it 1726 * to the buffer descriptor ring. 1727 * 1728 * tqm_status_number 1729 * The value in this field is equal to tqm_cmd_number in TQM command. It is 1730 * used to correlate the statu with TQM commands. Only valid when 1731 * release_source_module is TQM. 1732 * 1733 * transmit_count 1734 * The number of times the frame has been transmitted, valid only when 1735 * release source in TQM. 1736 * 1737 * ack_frame_rssi 1738 * This field is only valid when the source is TQM. If this frame is 1739 * removed as the result of the reception of an ACK or BA, this field 1740 * indicates the RSSI of the received ACK or BA frame. 1741 * 1742 * sw_release_details_valid 1743 * This is set when WMB got a 'release_msdu_list' command from TQM and 1744 * return buffer manager is not WMB. WBM will then de-aggregate all MSDUs 1745 * and pass them one at a time on to the 'buffer owner'. 1746 * 1747 * first_msdu 1748 * Field only valid when SW_release_details_valid is set. 1749 * When set, this MSDU is the first MSDU pointed to in the 1750 * 'release_msdu_list' command. 1751 * 1752 * last_msdu 1753 * Field only valid when SW_release_details_valid is set. 1754 * When set, this MSDU is the last MSDU pointed to in the 1755 * 'release_msdu_list' command. 1756 * 1757 * msdu_part_of_amsdu 1758 * Field only valid when SW_release_details_valid is set. 1759 * When set, this MSDU was part of an A-MSDU in MPDU 1760 * 1761 * fw_tx_notify_frame 1762 * Field only valid when SW_release_details_valid is set. 1763 * 1764 * buffer_timestamp 1765 * Field only valid when SW_release_details_valid is set. 1766 * This is the Buffer_timestamp field from the 1767 * Timestamp in units of 1024 us 1768 * 1769 * struct hal_tx_rate_stats rate_stats 1770 * Details for command execution tracking purposes. 1771 * 1772 * sw_peer_id 1773 * tid 1774 * Field only valid when Release_source_module is set to 1775 * release_source_TQM 1776 * 1777 * 1) Release of msdu buffer due to drop_frame = 1. Flow is 1778 * not fetched and hence sw_peer_id and tid = 0 1779 * 1780 * buffer_or_desc_type = e_num 0 1781 * MSDU_rel_buffertqm_release_reason = e_num 1 1782 * tqm_rr_rem_cmd_rem 1783 * 1784 * 2) Release of msdu buffer due to Flow is not fetched and 1785 * hence sw_peer_id and tid = 0 1786 * 1787 * buffer_or_desc_type = e_num 0 1788 * MSDU_rel_buffertqm_release_reason = e_num 1 1789 * tqm_rr_rem_cmd_rem 1790 * 1791 * 3) Release of msdu link due to remove_mpdu or acked_mpdu 1792 * command. 1793 * 1794 * buffer_or_desc_type = e_num1 1795 * msdu_link_descriptortqm_release_reason can be:e_num 1 1796 * tqm_rr_rem_cmd_reme_num 2 tqm_rr_rem_cmd_tx 1797 * e_num 3 tqm_rr_rem_cmd_notxe_num 4 tqm_rr_rem_cmd_aged 1798 * 1799 * This field represents the TID from the TX_MSDU_FLOW 1800 * descriptor or TX_MPDU_QUEUE descriptor 1801 * 1802 * rind_id 1803 * For debugging. 1804 * This field is filled in by the SRNG module. 1805 * It help to identify the ring that is being looked 1806 * 1807 * looping_count 1808 * A count value that indicates the number of times the 1809 * producer of entries into the Buffer Manager Ring has looped 1810 * around the ring. 1811 * 1812 * At initialization time, this value is set to 0. On the 1813 * first loop, this value is set to 1. After the max value is 1814 * reached allowed by the number of bits for this field, the 1815 * count value continues with 0 again. 1816 * 1817 * In case SW is the consumer of the ring entries, it can 1818 * use this field to figure out up to where the producer of 1819 * entries has created new entries. This eliminates the need to 1820 * check where the head pointer' of the ring is located once 1821 * the SW starts processing an interrupt indicating that new 1822 * entries have been put into this ring... 1823 * 1824 * Also note that SW if it wants only needs to look at the 1825 * LSB bit of this count value. 1826 */ 1827 1828 /** 1829 * enum hal_wbm_tqm_rel_reason - TQM release reason code 1830 * @HAL_WBM_TQM_REL_REASON_FRAME_ACKED: ACK or BACK received for the frame 1831 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU: Command remove_mpdus initiated by SW 1832 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX: Command remove transmitted_mpdus 1833 * initiated by sw. 1834 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_NOTX: Command remove untransmitted_mpdus 1835 * initiated by sw. 1836 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES: Command remove aged msdus or 1837 * mpdus. 1838 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1: Remove command initiated by 1839 * fw with fw_reason1. 1840 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2: Remove command initiated by 1841 * fw with fw_reason2. 1842 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3: Remove command initiated by 1843 * fw with fw_reason3. 1844 */ 1845 enum hal_wbm_tqm_rel_reason { 1846 HAL_WBM_TQM_REL_REASON_FRAME_ACKED, 1847 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU, 1848 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX, 1849 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_NOTX, 1850 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES, 1851 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1, 1852 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2, 1853 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3, 1854 }; 1855 1856 struct hal_wbm_buffer_ring { 1857 struct ath11k_buffer_addr buf_addr_info; 1858 }; 1859 1860 enum hal_desc_owner { 1861 HAL_DESC_OWNER_WBM, 1862 HAL_DESC_OWNER_SW, 1863 HAL_DESC_OWNER_TQM, 1864 HAL_DESC_OWNER_RXDMA, 1865 HAL_DESC_OWNER_REO, 1866 HAL_DESC_OWNER_SWITCH, 1867 }; 1868 1869 enum hal_desc_buf_type { 1870 HAL_DESC_BUF_TYPE_TX_MSDU_LINK, 1871 HAL_DESC_BUF_TYPE_TX_MPDU_LINK, 1872 HAL_DESC_BUF_TYPE_TX_MPDU_QUEUE_HEAD, 1873 HAL_DESC_BUF_TYPE_TX_MPDU_QUEUE_EXT, 1874 HAL_DESC_BUF_TYPE_TX_FLOW, 1875 HAL_DESC_BUF_TYPE_TX_BUFFER, 1876 HAL_DESC_BUF_TYPE_RX_MSDU_LINK, 1877 HAL_DESC_BUF_TYPE_RX_MPDU_LINK, 1878 HAL_DESC_BUF_TYPE_RX_REO_QUEUE, 1879 HAL_DESC_BUF_TYPE_RX_REO_QUEUE_EXT, 1880 HAL_DESC_BUF_TYPE_RX_BUFFER, 1881 HAL_DESC_BUF_TYPE_IDLE_LINK, 1882 }; 1883 1884 #define HAL_DESC_REO_OWNED 4 1885 #define HAL_DESC_REO_QUEUE_DESC 8 1886 #define HAL_DESC_REO_QUEUE_EXT_DESC 9 1887 #define HAL_DESC_REO_NON_QOS_TID 16 1888 1889 #define HAL_DESC_HDR_INFO0_OWNER GENMASK(3, 0) 1890 #define HAL_DESC_HDR_INFO0_BUF_TYPE GENMASK(7, 4) 1891 #define HAL_DESC_HDR_INFO0_DBG_RESERVED GENMASK(31, 8) 1892 1893 struct hal_desc_header { 1894 u32 info0; 1895 } __packed; 1896 1897 struct hal_rx_mpdu_link_ptr { 1898 struct ath11k_buffer_addr addr_info; 1899 } __packed; 1900 1901 struct hal_rx_msdu_details { 1902 struct ath11k_buffer_addr buf_addr_info; 1903 struct rx_msdu_desc rx_msdu_info; 1904 } __packed; 1905 1906 #define HAL_RX_MSDU_LNK_INFO0_RX_QUEUE_NUMBER GENMASK(15, 0) 1907 #define HAL_RX_MSDU_LNK_INFO0_FIRST_MSDU_LNK BIT(16) 1908 1909 struct hal_rx_msdu_link { 1910 struct hal_desc_header desc_hdr; 1911 struct ath11k_buffer_addr buf_addr_info; 1912 u32 info0; 1913 u32 pn[4]; 1914 struct hal_rx_msdu_details msdu_link[6]; 1915 } __packed; 1916 1917 struct hal_rx_reo_queue_ext { 1918 struct hal_desc_header desc_hdr; 1919 u32 rsvd; 1920 struct hal_rx_mpdu_link_ptr mpdu_link[15]; 1921 } __packed; 1922 1923 /* hal_rx_reo_queue_ext 1924 * Consumer: REO 1925 * Producer: REO 1926 * 1927 * descriptor_header 1928 * Details about which module owns this struct. 1929 * 1930 * mpdu_link 1931 * Pointer to the next MPDU_link descriptor in the MPDU queue. 1932 */ 1933 1934 enum hal_rx_reo_queue_pn_size { 1935 HAL_RX_REO_QUEUE_PN_SIZE_24, 1936 HAL_RX_REO_QUEUE_PN_SIZE_48, 1937 HAL_RX_REO_QUEUE_PN_SIZE_128, 1938 }; 1939 1940 #define HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER GENMASK(15, 0) 1941 1942 #define HAL_RX_REO_QUEUE_INFO0_VLD BIT(0) 1943 #define HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER GENMASK(2, 1) 1944 #define HAL_RX_REO_QUEUE_INFO0_DIS_DUP_DETECTION BIT(3) 1945 #define HAL_RX_REO_QUEUE_INFO0_SOFT_REORDER_EN BIT(4) 1946 #define HAL_RX_REO_QUEUE_INFO0_AC GENMASK(6, 5) 1947 #define HAL_RX_REO_QUEUE_INFO0_BAR BIT(7) 1948 #define HAL_RX_REO_QUEUE_INFO0_RETRY BIT(8) 1949 #define HAL_RX_REO_QUEUE_INFO0_CHECK_2K_MODE BIT(9) 1950 #define HAL_RX_REO_QUEUE_INFO0_OOR_MODE BIT(10) 1951 #define HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE GENMASK(18, 11) 1952 #define HAL_RX_REO_QUEUE_INFO0_PN_CHECK BIT(19) 1953 #define HAL_RX_REO_QUEUE_INFO0_EVEN_PN BIT(20) 1954 #define HAL_RX_REO_QUEUE_INFO0_UNEVEN_PN BIT(21) 1955 #define HAL_RX_REO_QUEUE_INFO0_PN_HANDLE_ENABLE BIT(22) 1956 #define HAL_RX_REO_QUEUE_INFO0_PN_SIZE GENMASK(24, 23) 1957 #define HAL_RX_REO_QUEUE_INFO0_IGNORE_AMPDU_FLG BIT(25) 1958 1959 #define HAL_RX_REO_QUEUE_INFO1_SVLD BIT(0) 1960 #define HAL_RX_REO_QUEUE_INFO1_SSN GENMASK(12, 1) 1961 #define HAL_RX_REO_QUEUE_INFO1_CURRENT_IDX GENMASK(20, 13) 1962 #define HAL_RX_REO_QUEUE_INFO1_SEQ_2K_ERR BIT(21) 1963 #define HAL_RX_REO_QUEUE_INFO1_PN_ERR BIT(22) 1964 #define HAL_RX_REO_QUEUE_INFO1_PN_VALID BIT(31) 1965 1966 #define HAL_RX_REO_QUEUE_INFO2_MPDU_COUNT GENMASK(6, 0) 1967 #define HAL_RX_REO_QUEUE_INFO2_MSDU_COUNT (31, 7) 1968 1969 #define HAL_RX_REO_QUEUE_INFO3_TIMEOUT_COUNT GENMASK(9, 4) 1970 #define HAL_RX_REO_QUEUE_INFO3_FWD_DUE_TO_BAR_CNT GENMASK(15, 10) 1971 #define HAL_RX_REO_QUEUE_INFO3_DUPLICATE_COUNT GENMASK(31, 16) 1972 1973 #define HAL_RX_REO_QUEUE_INFO4_FRAME_IN_ORD_COUNT GENMASK(23, 0) 1974 #define HAL_RX_REO_QUEUE_INFO4_BAR_RECVD_COUNT GENMASK(31, 24) 1975 1976 #define HAL_RX_REO_QUEUE_INFO5_LATE_RX_MPDU_COUNT GENMASK(11, 0) 1977 #define HAL_RX_REO_QUEUE_INFO5_WINDOW_JUMP_2K GENMASK(15, 12) 1978 #define HAL_RX_REO_QUEUE_INFO5_HOLE_COUNT GENMASK(31, 16) 1979 1980 struct hal_rx_reo_queue { 1981 struct hal_desc_header desc_hdr; 1982 u32 rx_queue_num; 1983 u32 info0; 1984 u32 info1; 1985 u32 pn[4]; 1986 u32 last_rx_enqueue_timestamp; 1987 u32 last_rx_dequeue_timestamp; 1988 u32 next_aging_queue[2]; 1989 u32 prev_aging_queue[2]; 1990 u32 rx_bitmap[8]; 1991 u32 info2; 1992 u32 info3; 1993 u32 info4; 1994 u32 processed_mpdus; 1995 u32 processed_msdus; 1996 u32 processed_total_bytes; 1997 u32 info5; 1998 u32 rsvd[3]; 1999 struct hal_rx_reo_queue_ext ext_desc[]; 2000 } __packed; 2001 2002 /* hal_rx_reo_queue 2003 * 2004 * descriptor_header 2005 * Details about which module owns this struct. Note that sub field 2006 * Buffer_type shall be set to receive_reo_queue_descriptor. 2007 * 2008 * receive_queue_number 2009 * Indicates the MPDU queue ID to which this MPDU link descriptor belongs. 2010 * 2011 * vld 2012 * Valid bit indicating a session is established and the queue descriptor 2013 * is valid. 2014 * associated_link_descriptor_counter 2015 * Indicates which of the 3 link descriptor counters shall be incremented 2016 * or decremented when link descriptors are added or removed from this 2017 * flow queue. 2018 * disable_duplicate_detection 2019 * When set, do not perform any duplicate detection. 2020 * soft_reorder_enable 2021 * When set, REO has been instructed to not perform the actual re-ordering 2022 * of frames for this queue, but just to insert the reorder opcodes. 2023 * ac 2024 * Indicates the access category of the queue descriptor. 2025 * bar 2026 * Indicates if BAR has been received. 2027 * retry 2028 * Retry bit is checked if this bit is set. 2029 * chk_2k_mode 2030 * Indicates what type of operation is expected from Reo when the received 2031 * frame SN falls within the 2K window. 2032 * oor_mode 2033 * Indicates what type of operation is expected when the received frame 2034 * falls within the OOR window. 2035 * ba_window_size 2036 * Indicates the negotiated (window size + 1). Max of 256 bits. 2037 * 2038 * A value 255 means 256 bitmap, 63 means 64 bitmap, 0 (means non-BA 2039 * session, with window size of 0). The 3 values here are the main values 2040 * validated, but other values should work as well. 2041 * 2042 * A BA window size of 0 (=> one frame entry bitmat), means that there is 2043 * no additional rx_reo_queue_ext desc. following rx_reo_queue in memory. 2044 * A BA window size of 1 - 105, means that there is 1 rx_reo_queue_ext. 2045 * A BA window size of 106 - 210, means that there are 2 rx_reo_queue_ext. 2046 * A BA window size of 211 - 256, means that there are 3 rx_reo_queue_ext. 2047 * pn_check_needed, pn_shall_be_even, pn_shall_be_uneven, pn_handling_enable, 2048 * pn_size 2049 * REO shall perform the PN increment check, even number check, uneven 2050 * number check, PN error check and size of the PN field check. 2051 * ignore_ampdu_flag 2052 * REO shall ignore the ampdu_flag on entrance descriptor for this queue. 2053 * 2054 * svld 2055 * Sequence number in next field is valid one. 2056 * ssn 2057 * Starting Sequence number of the session. 2058 * current_index 2059 * Points to last forwarded packet 2060 * seq_2k_error_detected_flag 2061 * REO has detected a 2k error jump in the sequence number and from that 2062 * moment forward, all new frames are forwarded directly to FW, without 2063 * duplicate detect, reordering, etc. 2064 * pn_error_detected_flag 2065 * REO has detected a PN error. 2066 */ 2067 2068 #define HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 2069 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RX_QUEUE_NUM BIT(8) 2070 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_VLD BIT(9) 2071 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_ASSOC_LNK_DESC_CNT BIT(10) 2072 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_DIS_DUP_DETECTION BIT(11) 2073 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SOFT_REORDER_EN BIT(12) 2074 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC BIT(13) 2075 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BAR BIT(14) 2076 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RETRY BIT(15) 2077 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_CHECK_2K_MODE BIT(16) 2078 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_OOR_MODE BIT(17) 2079 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BA_WINDOW_SIZE BIT(18) 2080 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_CHECK BIT(19) 2081 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_EVEN_PN BIT(20) 2082 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_UNEVEN_PN BIT(21) 2083 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_HANDLE_ENABLE BIT(22) 2084 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_SIZE BIT(23) 2085 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_IGNORE_AMPDU_FLG BIT(24) 2086 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SVLD BIT(25) 2087 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SSN BIT(26) 2088 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SEQ_2K_ERR BIT(27) 2089 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_ERR BIT(28) 2090 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_VALID BIT(29) 2091 #define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN BIT(30) 2092 2093 #define HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER GENMASK(15, 0) 2094 #define HAL_REO_UPD_RX_QUEUE_INFO1_VLD BIT(16) 2095 #define HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER GENMASK(18, 17) 2096 #define HAL_REO_UPD_RX_QUEUE_INFO1_DIS_DUP_DETECTION BIT(19) 2097 #define HAL_REO_UPD_RX_QUEUE_INFO1_SOFT_REORDER_EN BIT(20) 2098 #define HAL_REO_UPD_RX_QUEUE_INFO1_AC GENMASK(22, 21) 2099 #define HAL_REO_UPD_RX_QUEUE_INFO1_BAR BIT(23) 2100 #define HAL_REO_UPD_RX_QUEUE_INFO1_RETRY BIT(24) 2101 #define HAL_REO_UPD_RX_QUEUE_INFO1_CHECK_2K_MODE BIT(25) 2102 #define HAL_REO_UPD_RX_QUEUE_INFO1_OOR_MODE BIT(26) 2103 #define HAL_REO_UPD_RX_QUEUE_INFO1_PN_CHECK BIT(27) 2104 #define HAL_REO_UPD_RX_QUEUE_INFO1_EVEN_PN BIT(28) 2105 #define HAL_REO_UPD_RX_QUEUE_INFO1_UNEVEN_PN BIT(29) 2106 #define HAL_REO_UPD_RX_QUEUE_INFO1_PN_HANDLE_ENABLE BIT(30) 2107 #define HAL_REO_UPD_RX_QUEUE_INFO1_IGNORE_AMPDU_FLG BIT(31) 2108 2109 #define HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE GENMASK(7, 0) 2110 #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE GENMASK(9, 8) 2111 #define HAL_REO_UPD_RX_QUEUE_INFO2_SVLD BIT(10) 2112 #define HAL_REO_UPD_RX_QUEUE_INFO2_SSN GENMASK(22, 11) 2113 #define HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR BIT(23) 2114 #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR BIT(24) 2115 #define HAL_REO_UPD_RX_QUEUE_INFO2_PN_VALID BIT(25) 2116 2117 struct hal_reo_update_rx_queue { 2118 struct hal_reo_cmd_hdr cmd; 2119 u32 queue_addr_lo; 2120 u32 info0; 2121 u32 info1; 2122 u32 info2; 2123 u32 pn[4]; 2124 } __packed; 2125 2126 #define HAL_REO_UNBLOCK_CACHE_INFO0_UNBLK_CACHE BIT(0) 2127 #define HAL_REO_UNBLOCK_CACHE_INFO0_RESOURCE_IDX GENMASK(2, 1) 2128 2129 struct hal_reo_unblock_cache { 2130 struct hal_reo_cmd_hdr cmd; 2131 u32 info0; 2132 u32 rsvd[7]; 2133 } __packed; 2134 2135 enum hal_reo_exec_status { 2136 HAL_REO_EXEC_STATUS_SUCCESS, 2137 HAL_REO_EXEC_STATUS_BLOCKED, 2138 HAL_REO_EXEC_STATUS_FAILED, 2139 HAL_REO_EXEC_STATUS_RESOURCE_BLOCKED, 2140 }; 2141 2142 #define HAL_REO_STATUS_HDR_INFO0_STATUS_NUM GENMASK(15, 0) 2143 #define HAL_REO_STATUS_HDR_INFO0_EXEC_TIME GENMASK(25, 16) 2144 #define HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS GENMASK(27, 26) 2145 2146 struct hal_reo_status_hdr { 2147 u32 info0; 2148 u32 timestamp; 2149 } __packed; 2150 2151 /* hal_reo_status_hdr 2152 * Producer: REO 2153 * Consumer: SW 2154 * 2155 * status_num 2156 * The value in this field is equal to value of the reo command 2157 * number. This field helps to correlate the statuses with the REO 2158 * commands. 2159 * 2160 * execution_time (in us) 2161 * The amount of time REO took to excecute the command. Note that 2162 * this time does not include the duration of the command waiting 2163 * in the command ring, before the execution started. 2164 * 2165 * execution_status 2166 * Execution status of the command. Values are defined in 2167 * enum %HAL_REO_EXEC_STATUS_. 2168 */ 2169 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN GENMASK(11, 0) 2170 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX GENMASK(19, 12) 2171 2172 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT GENMASK(6, 0) 2173 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT GENMASK(31, 7) 2174 2175 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT GENMASK(9, 4) 2176 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT GENMASK(15, 10) 2177 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT GENMASK(31, 16) 2178 2179 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT GENMASK(23, 0) 2180 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT GENMASK(31, 24) 2181 2182 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU GENMASK(11, 0) 2183 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_WINDOW_JMP2K GENMASK(15, 12) 2184 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT GENMASK(31, 16) 2185 2186 #define HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT GENMASK(31, 28) 2187 2188 struct hal_reo_get_queue_stats_status { 2189 struct hal_reo_status_hdr hdr; 2190 u32 info0; 2191 u32 pn[4]; 2192 u32 last_rx_enqueue_timestamp; 2193 u32 last_rx_dequeue_timestamp; 2194 u32 rx_bitmap[8]; 2195 u32 info1; 2196 u32 info2; 2197 u32 info3; 2198 u32 num_mpdu_frames; 2199 u32 num_msdu_frames; 2200 u32 total_bytes; 2201 u32 info4; 2202 u32 info5; 2203 } __packed; 2204 2205 /* hal_reo_get_queue_stats_status 2206 * Producer: REO 2207 * Consumer: SW 2208 * 2209 * status_hdr 2210 * Details that can link this status with the original command. It 2211 * also contains info on how long REO took to execute this command. 2212 * 2213 * ssn 2214 * Starting Sequence number of the session, this changes whenever 2215 * window moves (can be filled by SW then maintained by REO). 2216 * 2217 * current_index 2218 * Points to last forwarded packet. 2219 * 2220 * pn 2221 * Bits of the PN number. 2222 * 2223 * last_rx_enqueue_timestamp 2224 * last_rx_dequeue_timestamp 2225 * Timestamp of arrival of the last MPDU for this queue and 2226 * Timestamp of forwarding an MPDU accordingly. 2227 * 2228 * rx_bitmap 2229 * When a bit is set, the corresponding frame is currently held 2230 * in the re-order queue. The bitmap is Fully managed by HW. 2231 * 2232 * current_mpdu_count 2233 * current_msdu_count 2234 * The number of MPDUs and MSDUs in the queue. 2235 * 2236 * timeout_count 2237 * The number of times REO started forwarding frames even though 2238 * there is a hole in the bitmap. Forwarding reason is timeout. 2239 * 2240 * forward_due_to_bar_count 2241 * The number of times REO started forwarding frames even though 2242 * there is a hole in the bitmap. Fwd reason is reception of BAR. 2243 * 2244 * duplicate_count 2245 * The number of duplicate frames that have been detected. 2246 * 2247 * frames_in_order_count 2248 * The number of frames that have been received in order (without 2249 * a hole that prevented them from being forwarded immediately). 2250 * 2251 * bar_received_count 2252 * The number of times a BAR frame is received. 2253 * 2254 * mpdu_frames_processed_count 2255 * msdu_frames_processed_count 2256 * The total number of MPDU/MSDU frames that have been processed. 2257 * 2258 * total_bytes 2259 * An approximation of the number of bytes received for this queue. 2260 * 2261 * late_receive_mpdu_count 2262 * The number of MPDUs received after the window had already moved 2263 * on. The 'late' sequence window is defined as 2264 * (Window SSN - 256) - (Window SSN - 1). 2265 * 2266 * window_jump_2k 2267 * The number of times the window moved more than 2K 2268 * 2269 * hole_count 2270 * The number of times a hole was created in the receive bitmap. 2271 * 2272 * looping_count 2273 * A count value that indicates the number of times the producer of 2274 * entries into this Ring has looped around the ring. 2275 */ 2276 2277 #define HAL_REO_STATUS_LOOP_CNT GENMASK(31, 28) 2278 2279 #define HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED BIT(0) 2280 #define HAL_REO_FLUSH_QUEUE_INFO0_RSVD GENMASK(31, 1) 2281 #define HAL_REO_FLUSH_QUEUE_INFO1_RSVD GENMASK(27, 0) 2282 2283 struct hal_reo_flush_queue_status { 2284 struct hal_reo_status_hdr hdr; 2285 u32 info0; 2286 u32 rsvd0[21]; 2287 u32 info1; 2288 } __packed; 2289 2290 /* hal_reo_flush_queue_status 2291 * Producer: REO 2292 * Consumer: SW 2293 * 2294 * status_hdr 2295 * Details that can link this status with the original command. It 2296 * also contains info on how long REO took to execute this command. 2297 * 2298 * error_detected 2299 * Status of blocking resource 2300 * 2301 * 0 - No error has been detected while executing this command 2302 * 1 - Error detected. The resource to be used for blocking was 2303 * already in use. 2304 * 2305 * looping_count 2306 * A count value that indicates the number of times the producer of 2307 * entries into this Ring has looped around the ring. 2308 */ 2309 2310 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR BIT(0) 2311 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE GENMASK(2, 1) 2312 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_STATUS_HIT BIT(8) 2313 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE GENMASK(11, 9) 2314 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID GENMASK(15, 12) 2315 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR GENMASK(17, 16) 2316 #define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT GENMASK(25, 18) 2317 2318 struct hal_reo_flush_cache_status { 2319 struct hal_reo_status_hdr hdr; 2320 u32 info0; 2321 u32 rsvd0[21]; 2322 u32 info1; 2323 } __packed; 2324 2325 /* hal_reo_flush_cache_status 2326 * Producer: REO 2327 * Consumer: SW 2328 * 2329 * status_hdr 2330 * Details that can link this status with the original command. It 2331 * also contains info on how long REO took to execute this command. 2332 * 2333 * error_detected 2334 * Status for blocking resource handling 2335 * 2336 * 0 - No error has been detected while executing this command 2337 * 1 - An error in the blocking resource management was detected 2338 * 2339 * block_error_details 2340 * only valid when error_detected is set 2341 * 2342 * 0 - No blocking related errors found 2343 * 1 - Blocking resource is already in use 2344 * 2 - Resource requested to be unblocked, was not blocked 2345 * 2346 * cache_controller_flush_status_hit 2347 * The status that the cache controller returned on executing the 2348 * flush command. 2349 * 2350 * 0 - miss; 1 - hit 2351 * 2352 * cache_controller_flush_status_desc_type 2353 * Flush descriptor type 2354 * 2355 * cache_controller_flush_status_client_id 2356 * Module who made the flush request 2357 * 2358 * In REO, this is always 0 2359 * 2360 * cache_controller_flush_status_error 2361 * Error condition 2362 * 2363 * 0 - No error found 2364 * 1 - HW interface is still busy 2365 * 2 - Line currently locked. Used for one line flush command 2366 * 3 - At least one line is still locked. 2367 * Used for cache flush command. 2368 * 2369 * cache_controller_flush_count 2370 * The number of lines that were actually flushed out 2371 * 2372 * looping_count 2373 * A count value that indicates the number of times the producer of 2374 * entries into this Ring has looped around the ring. 2375 */ 2376 2377 #define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR BIT(0) 2378 #define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_TYPE BIT(1) 2379 2380 struct hal_reo_unblock_cache_status { 2381 struct hal_reo_status_hdr hdr; 2382 u32 info0; 2383 u32 rsvd0[21]; 2384 u32 info1; 2385 } __packed; 2386 2387 /* hal_reo_unblock_cache_status 2388 * Producer: REO 2389 * Consumer: SW 2390 * 2391 * status_hdr 2392 * Details that can link this status with the original command. It 2393 * also contains info on how long REO took to execute this command. 2394 * 2395 * error_detected 2396 * 0 - No error has been detected while executing this command 2397 * 1 - The blocking resource was not in use, and therefore it could 2398 * not be unblocked. 2399 * 2400 * unblock_type 2401 * Reference to the type of unblock command 2402 * 0 - Unblock a blocking resource 2403 * 1 - The entire cache usage is unblock 2404 * 2405 * looping_count 2406 * A count value that indicates the number of times the producer of 2407 * entries into this Ring has looped around the ring. 2408 */ 2409 2410 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR BIT(0) 2411 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_LIST_EMPTY BIT(1) 2412 2413 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT GENMASK(15, 0) 2414 #define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT GENMASK(31, 16) 2415 2416 struct hal_reo_flush_timeout_list_status { 2417 struct hal_reo_status_hdr hdr; 2418 u32 info0; 2419 u32 info1; 2420 u32 rsvd0[20]; 2421 u32 info2; 2422 } __packed; 2423 2424 /* hal_reo_flush_timeout_list_status 2425 * Producer: REO 2426 * Consumer: SW 2427 * 2428 * status_hdr 2429 * Details that can link this status with the original command. It 2430 * also contains info on how long REO took to execute this command. 2431 * 2432 * error_detected 2433 * 0 - No error has been detected while executing this command 2434 * 1 - Command not properly executed and returned with error 2435 * 2436 * timeout_list_empty 2437 * When set, REO has depleted the timeout list and all entries are 2438 * gone. 2439 * 2440 * release_desc_count 2441 * Producer: SW; Consumer: REO 2442 * The number of link descriptor released 2443 * 2444 * forward_buf_count 2445 * Producer: SW; Consumer: REO 2446 * The number of buffers forwarded to the REO destination rings 2447 * 2448 * looping_count 2449 * A count value that indicates the number of times the producer of 2450 * entries into this Ring has looped around the ring. 2451 */ 2452 2453 #define HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX GENMASK(1, 0) 2454 #define HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0 GENMASK(23, 0) 2455 #define HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1 GENMASK(23, 0) 2456 #define HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2 GENMASK(23, 0) 2457 #define HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM GENMASK(25, 0) 2458 2459 struct hal_reo_desc_thresh_reached_status { 2460 struct hal_reo_status_hdr hdr; 2461 u32 info0; 2462 u32 info1; 2463 u32 info2; 2464 u32 info3; 2465 u32 info4; 2466 u32 rsvd0[17]; 2467 u32 info5; 2468 } __packed; 2469 2470 /* hal_reo_desc_thresh_reached_status 2471 * Producer: REO 2472 * Consumer: SW 2473 * 2474 * status_hdr 2475 * Details that can link this status with the original command. It 2476 * also contains info on how long REO took to execute this command. 2477 * 2478 * threshold_index 2479 * The index of the threshold register whose value got reached 2480 * 2481 * link_descriptor_counter0 2482 * link_descriptor_counter1 2483 * link_descriptor_counter2 2484 * link_descriptor_counter_sum 2485 * Value of the respective counters at generation of this message 2486 * 2487 * looping_count 2488 * A count value that indicates the number of times the producer of 2489 * entries into this Ring has looped around the ring. 2490 */ 2491 2492 #endif /* ATH11K_HAL_DESC_H */ 2493