1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef ATH11K_HAL_H 7 #define ATH11K_HAL_H 8 9 #include "hal_desc.h" 10 #include "rx_desc.h" 11 12 struct ath11k_base; 13 14 #define HAL_LINK_DESC_SIZE (32 << 2) 15 #define HAL_LINK_DESC_ALIGN 128 16 #define HAL_NUM_MPDUS_PER_LINK_DESC 6 17 #define HAL_NUM_TX_MSDUS_PER_LINK_DESC 7 18 #define HAL_NUM_RX_MSDUS_PER_LINK_DESC 6 19 #define HAL_NUM_MPDU_LINKS_PER_QUEUE_DESC 12 20 #define HAL_MAX_AVAIL_BLK_RES 3 21 22 #define HAL_RING_BASE_ALIGN 8 23 24 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX 32704 25 /* TODO: Check with hw team on the supported scatter buf size */ 26 #define HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE 8 27 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE (HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX - \ 28 HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE) 29 30 #define HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX 48 31 #define HAL_DSCP_TID_TBL_SIZE 24 32 33 /* calculate the register address from bar0 of shadow register x */ 34 #define SHADOW_BASE_ADDRESS 0x00003024 35 #define SHADOW_NUM_REGISTERS 36 36 37 /* WCSS Relative address */ 38 #define HAL_SEQ_WCSS_UMAC_REO_REG 0x00a38000 39 #define HAL_SEQ_WCSS_UMAC_TCL_REG 0x00a44000 40 #define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG 0x00a00000 41 #define HAL_SEQ_WCSS_UMAC_CE0_DST_REG 0x00a01000 42 #define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG 0x00a02000 43 #define HAL_SEQ_WCSS_UMAC_CE1_DST_REG 0x00a03000 44 #define HAL_SEQ_WCSS_UMAC_WBM_REG 0x00a34000 45 46 /* SW2TCL(x) R0 ring configuration address */ 47 #define HAL_TCL1_RING_CMN_CTRL_REG 0x00000014 48 #define HAL_TCL1_RING_DSCP_TID_MAP 0x0000002c 49 #define HAL_TCL1_RING_BASE_LSB 0x00000510 50 #define HAL_TCL1_RING_BASE_MSB 0x00000514 51 #define HAL_TCL1_RING_ID 0x00000518 52 #define HAL_TCL1_RING_MISC 0x00000520 53 #define HAL_TCL1_RING_TP_ADDR_LSB 0x0000052c 54 #define HAL_TCL1_RING_TP_ADDR_MSB 0x00000530 55 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0 0x00000540 56 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1 0x00000544 57 #define HAL_TCL1_RING_MSI1_BASE_LSB 0x00000558 58 #define HAL_TCL1_RING_MSI1_BASE_MSB 0x0000055c 59 #define HAL_TCL1_RING_MSI1_DATA 0x00000560 60 #define HAL_TCL2_RING_BASE_LSB 0x00000568 61 #define HAL_TCL_RING_BASE_LSB 0x00000618 62 63 #define HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET \ 64 (HAL_TCL1_RING_MSI1_BASE_LSB - HAL_TCL1_RING_BASE_LSB) 65 #define HAL_TCL1_RING_MSI1_BASE_MSB_OFFSET \ 66 (HAL_TCL1_RING_MSI1_BASE_MSB - HAL_TCL1_RING_BASE_LSB) 67 #define HAL_TCL1_RING_MSI1_DATA_OFFSET \ 68 (HAL_TCL1_RING_MSI1_DATA - HAL_TCL1_RING_BASE_LSB) 69 #define HAL_TCL1_RING_BASE_MSB_OFFSET \ 70 (HAL_TCL1_RING_BASE_MSB - HAL_TCL1_RING_BASE_LSB) 71 #define HAL_TCL1_RING_ID_OFFSET \ 72 (HAL_TCL1_RING_ID - HAL_TCL1_RING_BASE_LSB) 73 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET \ 74 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0 - HAL_TCL1_RING_BASE_LSB) 75 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET \ 76 (HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1 - HAL_TCL1_RING_BASE_LSB) 77 #define HAL_TCL1_RING_TP_ADDR_LSB_OFFSET \ 78 (HAL_TCL1_RING_TP_ADDR_LSB - HAL_TCL1_RING_BASE_LSB) 79 #define HAL_TCL1_RING_TP_ADDR_MSB_OFFSET \ 80 (HAL_TCL1_RING_TP_ADDR_MSB - HAL_TCL1_RING_BASE_LSB) 81 #define HAL_TCL1_RING_MISC_OFFSET \ 82 (HAL_TCL1_RING_MISC - HAL_TCL1_RING_BASE_LSB) 83 84 /* SW2TCL(x) R2 ring pointers (head/tail) address */ 85 #define HAL_TCL1_RING_HP 0x00002000 86 #define HAL_TCL1_RING_TP 0x00002004 87 #define HAL_TCL2_RING_HP 0x00002008 88 #define HAL_TCL_RING_HP 0x00002018 89 90 #define HAL_TCL1_RING_TP_OFFSET \ 91 (HAL_TCL1_RING_TP - HAL_TCL1_RING_HP) 92 93 /* TCL STATUS ring address */ 94 #define HAL_TCL_STATUS_RING_BASE_LSB 0x00000720 95 #define HAL_TCL_STATUS_RING_HP 0x00002030 96 97 /* REO2SW(x) R0 ring configuration address */ 98 #define HAL_REO1_GEN_ENABLE 0x00000000 99 #define HAL_REO1_DEST_RING_CTRL_IX_0 0x00000004 100 #define HAL_REO1_DEST_RING_CTRL_IX_1 0x00000008 101 #define HAL_REO1_DEST_RING_CTRL_IX_2 0x0000000c 102 #define HAL_REO1_DEST_RING_CTRL_IX_3 0x00000010 103 #define HAL_REO1_RING_BASE_LSB 0x0000029c 104 #define HAL_REO1_RING_BASE_MSB 0x000002a0 105 #define HAL_REO1_RING_ID 0x000002a4 106 #define HAL_REO1_RING_MISC 0x000002ac 107 #define HAL_REO1_RING_HP_ADDR_LSB 0x000002b0 108 #define HAL_REO1_RING_HP_ADDR_MSB 0x000002b4 109 #define HAL_REO1_RING_PRODUCER_INT_SETUP 0x000002c0 110 #define HAL_REO1_RING_MSI1_BASE_LSB 0x000002e4 111 #define HAL_REO1_RING_MSI1_BASE_MSB 0x000002e8 112 #define HAL_REO1_RING_MSI1_DATA 0x000002ec 113 #define HAL_REO2_RING_BASE_LSB 0x000002f4 114 #define HAL_REO1_AGING_THRESH_IX_0 0x00000564 115 #define HAL_REO1_AGING_THRESH_IX_1 0x00000568 116 #define HAL_REO1_AGING_THRESH_IX_2 0x0000056c 117 #define HAL_REO1_AGING_THRESH_IX_3 0x00000570 118 119 #define HAL_REO1_RING_MSI1_BASE_LSB_OFFSET \ 120 (HAL_REO1_RING_MSI1_BASE_LSB - HAL_REO1_RING_BASE_LSB) 121 #define HAL_REO1_RING_MSI1_BASE_MSB_OFFSET \ 122 (HAL_REO1_RING_MSI1_BASE_MSB - HAL_REO1_RING_BASE_LSB) 123 #define HAL_REO1_RING_MSI1_DATA_OFFSET \ 124 (HAL_REO1_RING_MSI1_DATA - HAL_REO1_RING_BASE_LSB) 125 #define HAL_REO1_RING_BASE_MSB_OFFSET \ 126 (HAL_REO1_RING_BASE_MSB - HAL_REO1_RING_BASE_LSB) 127 #define HAL_REO1_RING_ID_OFFSET (HAL_REO1_RING_ID - HAL_REO1_RING_BASE_LSB) 128 #define HAL_REO1_RING_PRODUCER_INT_SETUP_OFFSET \ 129 (HAL_REO1_RING_PRODUCER_INT_SETUP - HAL_REO1_RING_BASE_LSB) 130 #define HAL_REO1_RING_HP_ADDR_LSB_OFFSET \ 131 (HAL_REO1_RING_HP_ADDR_LSB - HAL_REO1_RING_BASE_LSB) 132 #define HAL_REO1_RING_HP_ADDR_MSB_OFFSET \ 133 (HAL_REO1_RING_HP_ADDR_MSB - HAL_REO1_RING_BASE_LSB) 134 #define HAL_REO1_RING_MISC_OFFSET (HAL_REO1_RING_MISC - HAL_REO1_RING_BASE_LSB) 135 136 /* REO2SW(x) R2 ring pointers (head/tail) address */ 137 #define HAL_REO1_RING_HP 0x00003038 138 #define HAL_REO1_RING_TP 0x0000303c 139 #define HAL_REO2_RING_HP 0x00003040 140 141 #define HAL_REO1_RING_TP_OFFSET (HAL_REO1_RING_TP - HAL_REO1_RING_HP) 142 143 /* REO2TCL R0 ring configuration address */ 144 #define HAL_REO_TCL_RING_BASE_LSB 0x000003fc 145 146 /* REO2TCL R2 ring pointer (head/tail) address */ 147 #define HAL_REO_TCL_RING_HP 0x00003058 148 149 /* REO CMD R0 address */ 150 #define HAL_REO_CMD_RING_BASE_LSB 0x00000194 151 152 /* REO CMD R2 address */ 153 #define HAL_REO_CMD_HP 0x00003020 154 155 /* SW2REO R0 address */ 156 #define HAL_SW2REO_RING_BASE_LSB 0x000001ec 157 158 /* SW2REO R2 address */ 159 #define HAL_SW2REO_RING_HP 0x00003028 160 161 /* CE ring R0 address */ 162 #define HAL_CE_DST_RING_BASE_LSB 0x00000000 163 #define HAL_CE_DST_STATUS_RING_BASE_LSB 0x00000058 164 #define HAL_CE_DST_RING_CTRL 0x000000b0 165 166 /* CE ring R2 address */ 167 #define HAL_CE_DST_RING_HP 0x00000400 168 #define HAL_CE_DST_STATUS_RING_HP 0x00000408 169 170 /* REO status address */ 171 #define HAL_REO_STATUS_RING_BASE_LSB 0x00000504 172 #define HAL_REO_STATUS_HP 0x00003070 173 174 /* WBM Idle R0 address */ 175 #define HAL_WBM_IDLE_LINK_RING_BASE_LSB 0x00000860 176 #define HAL_WBM_IDLE_LINK_RING_MISC_ADDR 0x00000870 177 #define HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR 0x00000048 178 #define HAL_WBM_R0_IDLE_LIST_SIZE_ADDR 0x0000004c 179 #define HAL_WBM_SCATTERED_RING_BASE_LSB 0x00000058 180 #define HAL_WBM_SCATTERED_RING_BASE_MSB 0x0000005c 181 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0 0x00000068 182 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1 0x0000006c 183 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0 0x00000078 184 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1 0x0000007c 185 #define HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR 0x00000084 186 187 /* WBM Idle R2 address */ 188 #define HAL_WBM_IDLE_LINK_RING_HP 0x000030b0 189 190 /* SW2WBM R0 release address */ 191 #define HAL_WBM_RELEASE_RING_BASE_LSB 0x000001d8 192 193 /* SW2WBM R2 release address */ 194 #define HAL_WBM_RELEASE_RING_HP 0x00003018 195 196 /* WBM2SW R0 release address */ 197 #define HAL_WBM0_RELEASE_RING_BASE_LSB 0x00000910 198 #define HAL_WBM1_RELEASE_RING_BASE_LSB 0x00000968 199 200 /* WBM2SW R2 release address */ 201 #define HAL_WBM0_RELEASE_RING_HP 0x000030c0 202 #define HAL_WBM1_RELEASE_RING_HP 0x000030c8 203 204 /* TCL ring feild mask and offset */ 205 #define HAL_TCL1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8) 206 #define HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0) 207 #define HAL_TCL1_RING_ID_ENTRY_SIZE GENMASK(7, 0) 208 #define HAL_TCL1_RING_MISC_MSI_LOOPCNT_DISABLE BIT(1) 209 #define HAL_TCL1_RING_MISC_MSI_SWAP BIT(3) 210 #define HAL_TCL1_RING_MISC_HOST_FW_SWAP BIT(4) 211 #define HAL_TCL1_RING_MISC_DATA_TLV_SWAP BIT(5) 212 #define HAL_TCL1_RING_MISC_SRNG_ENABLE BIT(6) 213 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_INTR_TMR_THOLD GENMASK(31, 16) 214 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD GENMASK(14, 0) 215 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD GENMASK(15, 0) 216 #define HAL_TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8) 217 #define HAL_TCL1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0) 218 #define HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN BIT(17) 219 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP GENMASK(31, 0) 220 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP0 GENMASK(2, 0) 221 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP1 GENMASK(5, 3) 222 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP2 GENMASK(8, 6) 223 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP3 GENMASK(11, 9) 224 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP4 GENMASK(14, 12) 225 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP5 GENMASK(17, 15) 226 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP6 GENMASK(20, 18) 227 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP7 GENMASK(23, 21) 228 229 /* REO ring feild mask and offset */ 230 #define HAL_REO1_RING_BASE_MSB_RING_SIZE GENMASK(27, 8) 231 #define HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB GENMASK(7, 0) 232 #define HAL_REO1_RING_ID_RING_ID GENMASK(15, 8) 233 #define HAL_REO1_RING_ID_ENTRY_SIZE GENMASK(7, 0) 234 #define HAL_REO1_RING_MISC_MSI_SWAP BIT(3) 235 #define HAL_REO1_RING_MISC_HOST_FW_SWAP BIT(4) 236 #define HAL_REO1_RING_MISC_DATA_TLV_SWAP BIT(5) 237 #define HAL_REO1_RING_MISC_SRNG_ENABLE BIT(6) 238 #define HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD GENMASK(31, 16) 239 #define HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD GENMASK(14, 0) 240 #define HAL_REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE BIT(8) 241 #define HAL_REO1_RING_MSI1_BASE_MSB_ADDR GENMASK(7, 0) 242 #define HAL_REO1_GEN_ENABLE_FRAG_DST_RING GENMASK(25, 23) 243 #define HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE BIT(2) 244 #define HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE BIT(3) 245 246 /* CE ring bit field mask and shift */ 247 #define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN GENMASK(15, 0) 248 249 #define HAL_ADDR_LSB_REG_MASK 0xffffffff 250 251 #define HAL_ADDR_MSB_REG_SHIFT 32 252 253 /* WBM ring bit field mask and shift */ 254 #define HAL_WBM_LINK_DESC_IDLE_LIST_MODE BIT(1) 255 #define HAL_WBM_SCATTER_BUFFER_SIZE GENMASK(10, 2) 256 #define HAL_WBM_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST GENMASK(31, 16) 257 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32 GENMASK(7, 0) 258 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG GENMASK(31, 8) 259 260 #define HAL_WBM_SCATTERED_DESC_HEAD_P_OFFSET_IX1 GENMASK(20, 8) 261 #define HAL_WBM_SCATTERED_DESC_TAIL_P_OFFSET_IX1 GENMASK(20, 8) 262 263 #define BASE_ADDR_MATCH_TAG_VAL 0x5 264 265 #define HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE 0x000fffff 266 #define HAL_REO_REO2TCL_RING_BASE_MSB_RING_SIZE 0x000fffff 267 #define HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE 0x0000ffff 268 #define HAL_REO_CMD_RING_BASE_MSB_RING_SIZE 0x0000ffff 269 #define HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 270 #define HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE 0x000fffff 271 #define HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE 0x000fffff 272 #define HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 273 #define HAL_CE_SRC_RING_BASE_MSB_RING_SIZE 0x0000ffff 274 #define HAL_CE_DST_RING_BASE_MSB_RING_SIZE 0x0000ffff 275 #define HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE 0x0000ffff 276 #define HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE 0x0000ffff 277 #define HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE 0x0000ffff 278 #define HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE 0x000fffff 279 #define HAL_RXDMA_RING_MAX_SIZE 0x0000ffff 280 281 #define HAL_RX_DESC_SIZE (sizeof(struct hal_rx_desc)) 282 283 /* Add any other errors here and return them in 284 * ath11k_hal_rx_desc_get_err(). 285 */ 286 287 enum hal_srng_ring_id { 288 HAL_SRNG_RING_ID_REO2SW1 = 0, 289 HAL_SRNG_RING_ID_REO2SW2, 290 HAL_SRNG_RING_ID_REO2SW3, 291 HAL_SRNG_RING_ID_REO2SW4, 292 HAL_SRNG_RING_ID_REO2TCL, 293 HAL_SRNG_RING_ID_SW2REO, 294 295 HAL_SRNG_RING_ID_REO_CMD = 8, 296 HAL_SRNG_RING_ID_REO_STATUS, 297 298 HAL_SRNG_RING_ID_SW2TCL1 = 16, 299 HAL_SRNG_RING_ID_SW2TCL2, 300 HAL_SRNG_RING_ID_SW2TCL3, 301 HAL_SRNG_RING_ID_SW2TCL4, 302 303 HAL_SRNG_RING_ID_SW2TCL_CMD = 24, 304 HAL_SRNG_RING_ID_TCL_STATUS, 305 306 HAL_SRNG_RING_ID_CE0_SRC = 32, 307 HAL_SRNG_RING_ID_CE1_SRC, 308 HAL_SRNG_RING_ID_CE2_SRC, 309 HAL_SRNG_RING_ID_CE3_SRC, 310 HAL_SRNG_RING_ID_CE4_SRC, 311 HAL_SRNG_RING_ID_CE5_SRC, 312 HAL_SRNG_RING_ID_CE6_SRC, 313 HAL_SRNG_RING_ID_CE7_SRC, 314 HAL_SRNG_RING_ID_CE8_SRC, 315 HAL_SRNG_RING_ID_CE9_SRC, 316 HAL_SRNG_RING_ID_CE10_SRC, 317 HAL_SRNG_RING_ID_CE11_SRC, 318 319 HAL_SRNG_RING_ID_CE0_DST = 56, 320 HAL_SRNG_RING_ID_CE1_DST, 321 HAL_SRNG_RING_ID_CE2_DST, 322 HAL_SRNG_RING_ID_CE3_DST, 323 HAL_SRNG_RING_ID_CE4_DST, 324 HAL_SRNG_RING_ID_CE5_DST, 325 HAL_SRNG_RING_ID_CE6_DST, 326 HAL_SRNG_RING_ID_CE7_DST, 327 HAL_SRNG_RING_ID_CE8_DST, 328 HAL_SRNG_RING_ID_CE9_DST, 329 HAL_SRNG_RING_ID_CE10_DST, 330 HAL_SRNG_RING_ID_CE11_DST, 331 332 HAL_SRNG_RING_ID_CE0_DST_STATUS = 80, 333 HAL_SRNG_RING_ID_CE1_DST_STATUS, 334 HAL_SRNG_RING_ID_CE2_DST_STATUS, 335 HAL_SRNG_RING_ID_CE3_DST_STATUS, 336 HAL_SRNG_RING_ID_CE4_DST_STATUS, 337 HAL_SRNG_RING_ID_CE5_DST_STATUS, 338 HAL_SRNG_RING_ID_CE6_DST_STATUS, 339 HAL_SRNG_RING_ID_CE7_DST_STATUS, 340 HAL_SRNG_RING_ID_CE8_DST_STATUS, 341 HAL_SRNG_RING_ID_CE9_DST_STATUS, 342 HAL_SRNG_RING_ID_CE10_DST_STATUS, 343 HAL_SRNG_RING_ID_CE11_DST_STATUS, 344 345 HAL_SRNG_RING_ID_WBM_IDLE_LINK = 104, 346 HAL_SRNG_RING_ID_WBM_SW_RELEASE, 347 HAL_SRNG_RING_ID_WBM2SW0_RELEASE, 348 HAL_SRNG_RING_ID_WBM2SW1_RELEASE, 349 HAL_SRNG_RING_ID_WBM2SW2_RELEASE, 350 HAL_SRNG_RING_ID_WBM2SW3_RELEASE, 351 352 HAL_SRNG_RING_ID_UMAC_ID_END = 127, 353 HAL_SRNG_RING_ID_LMAC1_ID_START, 354 355 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF = HAL_SRNG_RING_ID_LMAC1_ID_START, 356 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_BUF, 357 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA2_BUF, 358 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_STATBUF, 359 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_STATBUF, 360 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW0, 361 HAL_SRNG_RING_ID_WMAC1_RXDMA2SW1, 362 HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_DESC, 363 HAL_SRNG_RING_ID_RXDMA_DIR_BUF, 364 365 HAL_SRNG_RING_ID_LMAC1_ID_END = 143 366 }; 367 368 /* SRNG registers are split into two groups R0 and R2 */ 369 #define HAL_SRNG_REG_GRP_R0 0 370 #define HAL_SRNG_REG_GRP_R2 1 371 #define HAL_SRNG_NUM_REG_GRP 2 372 373 #define HAL_SRNG_NUM_LMACS 3 374 #define HAL_SRNG_REO_EXCEPTION HAL_SRNG_RING_ID_REO2SW1 375 #define HAL_SRNG_RINGS_PER_LMAC (HAL_SRNG_RING_ID_LMAC1_ID_END - \ 376 HAL_SRNG_RING_ID_LMAC1_ID_START) 377 #define HAL_SRNG_NUM_LMAC_RINGS (HAL_SRNG_NUM_LMACS * HAL_SRNG_RINGS_PER_LMAC) 378 #define HAL_SRNG_RING_ID_MAX (HAL_SRNG_RING_ID_UMAC_ID_END + \ 379 HAL_SRNG_NUM_LMAC_RINGS) 380 381 enum hal_ring_type { 382 HAL_REO_DST, 383 HAL_REO_EXCEPTION, 384 HAL_REO_REINJECT, 385 HAL_REO_CMD, 386 HAL_REO_STATUS, 387 HAL_TCL_DATA, 388 HAL_TCL_CMD, 389 HAL_TCL_STATUS, 390 HAL_CE_SRC, 391 HAL_CE_DST, 392 HAL_CE_DST_STATUS, 393 HAL_WBM_IDLE_LINK, 394 HAL_SW2WBM_RELEASE, 395 HAL_WBM2SW_RELEASE, 396 HAL_RXDMA_BUF, 397 HAL_RXDMA_DST, 398 HAL_RXDMA_MONITOR_BUF, 399 HAL_RXDMA_MONITOR_STATUS, 400 HAL_RXDMA_MONITOR_DST, 401 HAL_RXDMA_MONITOR_DESC, 402 HAL_RXDMA_DIR_BUF, 403 HAL_MAX_RING_TYPES, 404 }; 405 406 #define HAL_RX_MAX_BA_WINDOW 256 407 408 #define HAL_DEFAULT_REO_TIMEOUT_USEC (40 * 1000) 409 410 /** 411 * enum hal_reo_cmd_type: Enum for REO command type 412 * @CMD_GET_QUEUE_STATS: Get REO queue status/stats 413 * @CMD_FLUSH_QUEUE: Flush all frames in REO queue 414 * @CMD_FLUSH_CACHE: Flush descriptor entries in the cache 415 * @CMD_UNBLOCK_CACHE: Unblock a descriptor's address that was blocked 416 * earlier with a 'REO_FLUSH_CACHE' command 417 * @CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list 418 * @CMD_UPDATE_RX_REO_QUEUE: Update REO queue settings 419 */ 420 enum hal_reo_cmd_type { 421 HAL_REO_CMD_GET_QUEUE_STATS = 0, 422 HAL_REO_CMD_FLUSH_QUEUE = 1, 423 HAL_REO_CMD_FLUSH_CACHE = 2, 424 HAL_REO_CMD_UNBLOCK_CACHE = 3, 425 HAL_REO_CMD_FLUSH_TIMEOUT_LIST = 4, 426 HAL_REO_CMD_UPDATE_RX_QUEUE = 5, 427 }; 428 429 /** 430 * enum hal_reo_cmd_status: Enum for execution status of REO command 431 * @HAL_REO_CMD_SUCCESS: Command has successfully executed 432 * @HAL_REO_CMD_BLOCKED: Command could not be executed as the queue 433 * or cache was blocked 434 * @HAL_REO_CMD_FAILED: Command execution failed, could be due to 435 * invalid queue desc 436 * @HAL_REO_CMD_RESOURCE_BLOCKED: 437 * @HAL_REO_CMD_DRAIN: 438 */ 439 enum hal_reo_cmd_status { 440 HAL_REO_CMD_SUCCESS = 0, 441 HAL_REO_CMD_BLOCKED = 1, 442 HAL_REO_CMD_FAILED = 2, 443 HAL_REO_CMD_RESOURCE_BLOCKED = 3, 444 HAL_REO_CMD_DRAIN = 0xff, 445 }; 446 447 struct hal_wbm_idle_scatter_list { 448 dma_addr_t paddr; 449 struct hal_wbm_link_desc *vaddr; 450 }; 451 452 struct hal_srng_params { 453 dma_addr_t ring_base_paddr; 454 u32 *ring_base_vaddr; 455 int num_entries; 456 u32 intr_batch_cntr_thres_entries; 457 u32 intr_timer_thres_us; 458 u32 flags; 459 u32 max_buffer_len; 460 u32 low_threshold; 461 462 /* Add more params as needed */ 463 }; 464 465 enum hal_srng_dir { 466 HAL_SRNG_DIR_SRC, 467 HAL_SRNG_DIR_DST 468 }; 469 470 /* srng flags */ 471 #define HAL_SRNG_FLAGS_MSI_SWAP 0x00000008 472 #define HAL_SRNG_FLAGS_RING_PTR_SWAP 0x00000010 473 #define HAL_SRNG_FLAGS_DATA_TLV_SWAP 0x00000020 474 #define HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN 0x00010000 475 #define HAL_SRNG_FLAGS_MSI_INTR 0x00020000 476 #define HAL_SRNG_FLAGS_LMAC_RING 0x80000000 477 478 #define HAL_SRNG_TLV_HDR_TAG GENMASK(9, 1) 479 #define HAL_SRNG_TLV_HDR_LEN GENMASK(25, 10) 480 481 /* Common SRNG ring structure for source and destination rings */ 482 struct hal_srng { 483 /* Unique SRNG ring ID */ 484 u8 ring_id; 485 486 /* Ring initialization done */ 487 u8 initialized; 488 489 /* Interrupt/MSI value assigned to this ring */ 490 int irq; 491 492 /* Physical base address of the ring */ 493 dma_addr_t ring_base_paddr; 494 495 /* Virtual base address of the ring */ 496 u32 *ring_base_vaddr; 497 498 /* Number of entries in ring */ 499 u32 num_entries; 500 501 /* Ring size */ 502 u32 ring_size; 503 504 /* Ring size mask */ 505 u32 ring_size_mask; 506 507 /* Size of ring entry */ 508 u32 entry_size; 509 510 /* Interrupt timer threshold - in micro seconds */ 511 u32 intr_timer_thres_us; 512 513 /* Interrupt batch counter threshold - in number of ring entries */ 514 u32 intr_batch_cntr_thres_entries; 515 516 /* MSI Address */ 517 dma_addr_t msi_addr; 518 519 /* MSI data */ 520 u32 msi_data; 521 522 /* Misc flags */ 523 u32 flags; 524 525 /* Lock for serializing ring index updates */ 526 spinlock_t lock; 527 528 /* Start offset of SRNG register groups for this ring 529 * TBD: See if this is required - register address can be derived 530 * from ring ID 531 */ 532 u32 hwreg_base[HAL_SRNG_NUM_REG_GRP]; 533 534 u64 timestamp; 535 536 /* Source or Destination ring */ 537 enum hal_srng_dir ring_dir; 538 539 union { 540 struct { 541 /* SW tail pointer */ 542 u32 tp; 543 544 /* Shadow head pointer location to be updated by HW */ 545 volatile u32 *hp_addr; 546 547 /* Cached head pointer */ 548 u32 cached_hp; 549 550 /* Tail pointer location to be updated by SW - This 551 * will be a register address and need not be 552 * accessed through SW structure 553 */ 554 u32 *tp_addr; 555 556 /* Current SW loop cnt */ 557 u32 loop_cnt; 558 559 /* max transfer size */ 560 u16 max_buffer_length; 561 562 /* head pointer at access end */ 563 u32 last_hp; 564 } dst_ring; 565 566 struct { 567 /* SW head pointer */ 568 u32 hp; 569 570 /* SW reap head pointer */ 571 u32 reap_hp; 572 573 /* Shadow tail pointer location to be updated by HW */ 574 u32 *tp_addr; 575 576 /* Cached tail pointer */ 577 u32 cached_tp; 578 579 /* Head pointer location to be updated by SW - This 580 * will be a register address and need not be accessed 581 * through SW structure 582 */ 583 u32 *hp_addr; 584 585 /* Low threshold - in number of ring entries */ 586 u32 low_threshold; 587 588 /* tail pointer at access end */ 589 u32 last_tp; 590 } src_ring; 591 } u; 592 }; 593 594 /* Interrupt mitigation - Batch threshold in terms of numer of frames */ 595 #define HAL_SRNG_INT_BATCH_THRESHOLD_TX 256 596 #define HAL_SRNG_INT_BATCH_THRESHOLD_RX 128 597 #define HAL_SRNG_INT_BATCH_THRESHOLD_OTHER 1 598 599 /* Interrupt mitigation - timer threshold in us */ 600 #define HAL_SRNG_INT_TIMER_THRESHOLD_TX 1000 601 #define HAL_SRNG_INT_TIMER_THRESHOLD_RX 500 602 #define HAL_SRNG_INT_TIMER_THRESHOLD_OTHER 1000 603 604 /* HW SRNG configuration table */ 605 struct hal_srng_config { 606 int start_ring_id; 607 u16 max_rings; 608 u16 entry_size; 609 u32 reg_start[HAL_SRNG_NUM_REG_GRP]; 610 u16 reg_size[HAL_SRNG_NUM_REG_GRP]; 611 u8 lmac_ring; 612 enum hal_srng_dir ring_dir; 613 u32 max_size; 614 }; 615 616 /** 617 * enum hal_rx_buf_return_buf_manager 618 * 619 * @HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list 620 * @HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST: Descriptor returned to WBM idle 621 * descriptor list. 622 * @HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW 623 * @HAL_RX_BUF_RBM_SW0_BM: For Tx completion -- returned to host 624 * @HAL_RX_BUF_RBM_SW1_BM: For Tx completion -- returned to host 625 * @HAL_RX_BUF_RBM_SW2_BM: For Tx completion -- returned to host 626 * @HAL_RX_BUF_RBM_SW3_BM: For Rx release -- returned to host 627 */ 628 629 enum hal_rx_buf_return_buf_manager { 630 HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST, 631 HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST, 632 HAL_RX_BUF_RBM_FW_BM, 633 HAL_RX_BUF_RBM_SW0_BM, 634 HAL_RX_BUF_RBM_SW1_BM, 635 HAL_RX_BUF_RBM_SW2_BM, 636 HAL_RX_BUF_RBM_SW3_BM, 637 }; 638 639 #define HAL_SRNG_DESC_LOOP_CNT 0xf0000000 640 641 #define HAL_REO_CMD_FLG_NEED_STATUS BIT(0) 642 #define HAL_REO_CMD_FLG_STATS_CLEAR BIT(1) 643 #define HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER BIT(2) 644 #define HAL_REO_CMD_FLG_FLUSH_RELEASE_BLOCKING BIT(3) 645 #define HAL_REO_CMD_FLG_FLUSH_NO_INVAL BIT(4) 646 #define HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS BIT(5) 647 #define HAL_REO_CMD_FLG_FLUSH_ALL BIT(6) 648 #define HAL_REO_CMD_FLG_UNBLK_RESOURCE BIT(7) 649 #define HAL_REO_CMD_FLG_UNBLK_CACHE BIT(8) 650 651 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO0_UPD_* feilds */ 652 #define HAL_REO_CMD_UPD0_RX_QUEUE_NUM BIT(8) 653 #define HAL_REO_CMD_UPD0_VLD BIT(9) 654 #define HAL_REO_CMD_UPD0_ALDC BIT(10) 655 #define HAL_REO_CMD_UPD0_DIS_DUP_DETECTION BIT(11) 656 #define HAL_REO_CMD_UPD0_SOFT_REORDER_EN BIT(12) 657 #define HAL_REO_CMD_UPD0_AC BIT(13) 658 #define HAL_REO_CMD_UPD0_BAR BIT(14) 659 #define HAL_REO_CMD_UPD0_RETRY BIT(15) 660 #define HAL_REO_CMD_UPD0_CHECK_2K_MODE BIT(16) 661 #define HAL_REO_CMD_UPD0_OOR_MODE BIT(17) 662 #define HAL_REO_CMD_UPD0_BA_WINDOW_SIZE BIT(18) 663 #define HAL_REO_CMD_UPD0_PN_CHECK BIT(19) 664 #define HAL_REO_CMD_UPD0_EVEN_PN BIT(20) 665 #define HAL_REO_CMD_UPD0_UNEVEN_PN BIT(21) 666 #define HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE BIT(22) 667 #define HAL_REO_CMD_UPD0_PN_SIZE BIT(23) 668 #define HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG BIT(24) 669 #define HAL_REO_CMD_UPD0_SVLD BIT(25) 670 #define HAL_REO_CMD_UPD0_SSN BIT(26) 671 #define HAL_REO_CMD_UPD0_SEQ_2K_ERR BIT(27) 672 #define HAL_REO_CMD_UPD0_PN_ERR BIT(28) 673 #define HAL_REO_CMD_UPD0_PN_VALID BIT(29) 674 #define HAL_REO_CMD_UPD0_PN BIT(30) 675 676 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO1_* feilds */ 677 #define HAL_REO_CMD_UPD1_VLD BIT(16) 678 #define HAL_REO_CMD_UPD1_ALDC GENMASK(18, 17) 679 #define HAL_REO_CMD_UPD1_DIS_DUP_DETECTION BIT(19) 680 #define HAL_REO_CMD_UPD1_SOFT_REORDER_EN BIT(20) 681 #define HAL_REO_CMD_UPD1_AC GENMASK(22, 21) 682 #define HAL_REO_CMD_UPD1_BAR BIT(23) 683 #define HAL_REO_CMD_UPD1_RETRY BIT(24) 684 #define HAL_REO_CMD_UPD1_CHECK_2K_MODE BIT(25) 685 #define HAL_REO_CMD_UPD1_OOR_MODE BIT(26) 686 #define HAL_REO_CMD_UPD1_PN_CHECK BIT(27) 687 #define HAL_REO_CMD_UPD1_EVEN_PN BIT(28) 688 #define HAL_REO_CMD_UPD1_UNEVEN_PN BIT(29) 689 #define HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE BIT(30) 690 #define HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG BIT(31) 691 692 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO2_* feilds */ 693 #define HAL_REO_CMD_UPD2_SVLD BIT(10) 694 #define HAL_REO_CMD_UPD2_SSN GENMASK(22, 11) 695 #define HAL_REO_CMD_UPD2_SEQ_2K_ERR BIT(23) 696 #define HAL_REO_CMD_UPD2_PN_ERR BIT(24) 697 698 #define HAL_REO_DEST_RING_CTRL_HASH_RING_MAP GENMASK(31, 8) 699 700 struct ath11k_hal_reo_cmd { 701 u32 addr_lo; 702 u32 flag; 703 u32 upd0; 704 u32 upd1; 705 u32 upd2; 706 u32 pn[4]; 707 u16 rx_queue_num; 708 u16 min_rel; 709 u16 min_fwd; 710 u8 addr_hi; 711 u8 ac_list; 712 u8 blocking_idx; 713 u16 ba_window_size; 714 u8 pn_size; 715 }; 716 717 enum hal_pn_type { 718 HAL_PN_TYPE_NONE, 719 HAL_PN_TYPE_WPA, 720 HAL_PN_TYPE_WAPI_EVEN, 721 HAL_PN_TYPE_WAPI_UNEVEN, 722 }; 723 724 enum hal_ce_desc { 725 HAL_CE_DESC_SRC, 726 HAL_CE_DESC_DST, 727 HAL_CE_DESC_DST_STATUS, 728 }; 729 730 #define HAL_HASH_ROUTING_RING_TCL 0 731 #define HAL_HASH_ROUTING_RING_SW1 1 732 #define HAL_HASH_ROUTING_RING_SW2 2 733 #define HAL_HASH_ROUTING_RING_SW3 3 734 #define HAL_HASH_ROUTING_RING_SW4 4 735 #define HAL_HASH_ROUTING_RING_REL 5 736 #define HAL_HASH_ROUTING_RING_FW 6 737 738 struct hal_reo_status_header { 739 u16 cmd_num; 740 enum hal_reo_cmd_status cmd_status; 741 u16 cmd_exe_time; 742 u32 timestamp; 743 }; 744 745 struct hal_reo_status_queue_stats { 746 u16 ssn; 747 u16 curr_idx; 748 u32 pn[4]; 749 u32 last_rx_queue_ts; 750 u32 last_rx_dequeue_ts; 751 u32 rx_bitmap[8]; /* Bitmap from 0-255 */ 752 u32 curr_mpdu_cnt; 753 u32 curr_msdu_cnt; 754 u16 fwd_due_to_bar_cnt; 755 u16 dup_cnt; 756 u32 frames_in_order_cnt; 757 u32 num_mpdu_processed_cnt; 758 u32 num_msdu_processed_cnt; 759 u32 total_num_processed_byte_cnt; 760 u32 late_rx_mpdu_cnt; 761 u32 reorder_hole_cnt; 762 u8 timeout_cnt; 763 u8 bar_rx_cnt; 764 u8 num_window_2k_jump_cnt; 765 }; 766 767 struct hal_reo_status_flush_queue { 768 bool err_detected; 769 }; 770 771 enum hal_reo_status_flush_cache_err_code { 772 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_SUCCESS, 773 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_IN_USE, 774 HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_NOT_FOUND, 775 }; 776 777 struct hal_reo_status_flush_cache { 778 bool err_detected; 779 enum hal_reo_status_flush_cache_err_code err_code; 780 bool cache_controller_flush_status_hit; 781 u8 cache_controller_flush_status_desc_type; 782 u8 cache_controller_flush_status_client_id; 783 u8 cache_controller_flush_status_err; 784 u8 cache_controller_flush_status_cnt; 785 }; 786 787 enum hal_reo_status_unblock_cache_type { 788 HAL_REO_STATUS_UNBLOCK_BLOCKING_RESOURCE, 789 HAL_REO_STATUS_UNBLOCK_ENTIRE_CACHE_USAGE, 790 }; 791 792 struct hal_reo_status_unblock_cache { 793 bool err_detected; 794 enum hal_reo_status_unblock_cache_type unblock_type; 795 }; 796 797 struct hal_reo_status_flush_timeout_list { 798 bool err_detected; 799 bool list_empty; 800 u16 release_desc_cnt; 801 u16 fwd_buf_cnt; 802 }; 803 804 enum hal_reo_threshold_idx { 805 HAL_REO_THRESHOLD_IDX_DESC_COUNTER0, 806 HAL_REO_THRESHOLD_IDX_DESC_COUNTER1, 807 HAL_REO_THRESHOLD_IDX_DESC_COUNTER2, 808 HAL_REO_THRESHOLD_IDX_DESC_COUNTER_SUM, 809 }; 810 811 struct hal_reo_status_desc_thresh_reached { 812 enum hal_reo_threshold_idx threshold_idx; 813 u32 link_desc_counter0; 814 u32 link_desc_counter1; 815 u32 link_desc_counter2; 816 u32 link_desc_counter_sum; 817 }; 818 819 struct hal_reo_status { 820 struct hal_reo_status_header uniform_hdr; 821 u8 loop_cnt; 822 union { 823 struct hal_reo_status_queue_stats queue_stats; 824 struct hal_reo_status_flush_queue flush_queue; 825 struct hal_reo_status_flush_cache flush_cache; 826 struct hal_reo_status_unblock_cache unblock_cache; 827 struct hal_reo_status_flush_timeout_list timeout_list; 828 struct hal_reo_status_desc_thresh_reached desc_thresh_reached; 829 } u; 830 }; 831 832 /** 833 * HAL context to be used to access SRNG APIs (currently used by data path 834 * and transport (CE) modules) 835 */ 836 struct ath11k_hal { 837 /* HAL internal state for all SRNG rings. 838 */ 839 struct hal_srng srng_list[HAL_SRNG_RING_ID_MAX]; 840 841 /* SRNG configuration table */ 842 const struct hal_srng_config *srng_config; 843 844 /* Remote pointer memory for HW/FW updates */ 845 struct { 846 u32 *vaddr; 847 dma_addr_t paddr; 848 } rdp; 849 850 /* Shared memory for ring pointer updates from host to FW */ 851 struct { 852 u32 *vaddr; 853 dma_addr_t paddr; 854 } wrp; 855 856 /* Available REO blocking resources bitmap */ 857 u8 avail_blk_resource; 858 859 u8 current_blk_index; 860 861 /* shadow register configuration */ 862 u32 shadow_reg_addr[SHADOW_NUM_REGISTERS]; 863 int num_shadow_reg_configured; 864 }; 865 866 u32 ath11k_hal_reo_qdesc_size(u32 ba_window_size, u8 tid); 867 void ath11k_hal_reo_qdesc_setup(void *vaddr, int tid, u32 ba_window_size, 868 u32 start_seq, enum hal_pn_type type); 869 void ath11k_hal_reo_init_cmd_ring(struct ath11k_base *ab, 870 struct hal_srng *srng); 871 void ath11k_hal_reo_hw_setup(struct ath11k_base *ab, u32 ring_hash_map); 872 void ath11k_hal_setup_link_idle_list(struct ath11k_base *ab, 873 struct hal_wbm_idle_scatter_list *sbuf, 874 u32 nsbufs, u32 tot_link_desc, 875 u32 end_offset); 876 877 dma_addr_t ath11k_hal_srng_get_tp_addr(struct ath11k_base *ab, 878 struct hal_srng *srng); 879 dma_addr_t ath11k_hal_srng_get_hp_addr(struct ath11k_base *ab, 880 struct hal_srng *srng); 881 void ath11k_hal_set_link_desc_addr(struct hal_wbm_link_desc *desc, u32 cookie, 882 dma_addr_t paddr); 883 u32 ath11k_hal_ce_get_desc_size(enum hal_ce_desc type); 884 void ath11k_hal_ce_src_set_desc(void *buf, dma_addr_t paddr, u32 len, u32 id, 885 u8 byte_swap_data); 886 void ath11k_hal_ce_dst_set_desc(void *buf, dma_addr_t paddr); 887 u32 ath11k_hal_ce_dst_status_get_length(void *buf); 888 int ath11k_hal_srng_get_entrysize(u32 ring_type); 889 int ath11k_hal_srng_get_max_entries(u32 ring_type); 890 void ath11k_hal_srng_get_params(struct ath11k_base *ab, struct hal_srng *srng, 891 struct hal_srng_params *params); 892 u32 *ath11k_hal_srng_dst_get_next_entry(struct ath11k_base *ab, 893 struct hal_srng *srng); 894 u32 *ath11k_hal_srng_dst_peek(struct ath11k_base *ab, struct hal_srng *srng); 895 int ath11k_hal_srng_dst_num_free(struct ath11k_base *ab, struct hal_srng *srng, 896 bool sync_hw_ptr); 897 u32 *ath11k_hal_srng_src_peek(struct ath11k_base *ab, struct hal_srng *srng); 898 u32 *ath11k_hal_srng_src_get_next_reaped(struct ath11k_base *ab, 899 struct hal_srng *srng); 900 u32 *ath11k_hal_srng_src_reap_next(struct ath11k_base *ab, 901 struct hal_srng *srng); 902 u32 *ath11k_hal_srng_src_get_next_entry(struct ath11k_base *ab, 903 struct hal_srng *srng); 904 int ath11k_hal_srng_src_num_free(struct ath11k_base *ab, struct hal_srng *srng, 905 bool sync_hw_ptr); 906 void ath11k_hal_srng_access_begin(struct ath11k_base *ab, 907 struct hal_srng *srng); 908 void ath11k_hal_srng_access_end(struct ath11k_base *ab, struct hal_srng *srng); 909 int ath11k_hal_srng_setup(struct ath11k_base *ab, enum hal_ring_type type, 910 int ring_num, int mac_id, 911 struct hal_srng_params *params); 912 int ath11k_hal_srng_init(struct ath11k_base *ath11k); 913 void ath11k_hal_srng_deinit(struct ath11k_base *ath11k); 914 void ath11k_hal_dump_srng_stats(struct ath11k_base *ab); 915 916 #endif 917