xref: /openbmc/linux/drivers/net/wireless/ath/ath11k/hal.h (revision 867e6d38)
1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
2 /*
3  * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4  */
5 
6 #ifndef ATH11K_HAL_H
7 #define ATH11K_HAL_H
8 
9 #include "hal_desc.h"
10 #include "rx_desc.h"
11 
12 struct ath11k_base;
13 
14 #define HAL_LINK_DESC_SIZE			(32 << 2)
15 #define HAL_LINK_DESC_ALIGN			128
16 #define HAL_NUM_MPDUS_PER_LINK_DESC		6
17 #define HAL_NUM_TX_MSDUS_PER_LINK_DESC		7
18 #define HAL_NUM_RX_MSDUS_PER_LINK_DESC		6
19 #define HAL_NUM_MPDU_LINKS_PER_QUEUE_DESC	12
20 #define HAL_MAX_AVAIL_BLK_RES			3
21 
22 #define HAL_RING_BASE_ALIGN	8
23 
24 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX	32704
25 /* TODO: Check with hw team on the supported scatter buf size */
26 #define HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE	8
27 #define HAL_WBM_IDLE_SCATTER_BUF_SIZE (HAL_WBM_IDLE_SCATTER_BUF_SIZE_MAX - \
28 				       HAL_WBM_IDLE_SCATTER_NEXT_PTR_SIZE)
29 
30 #define HAL_DSCP_TID_MAP_TBL_NUM_ENTRIES_MAX	48
31 #define HAL_DSCP_TID_TBL_SIZE			24
32 
33 /* calculate the register address from bar0 of shadow register x */
34 #define HAL_SHADOW_BASE_ADDR			0x000008fc
35 #define HAL_SHADOW_NUM_REGS			36
36 #define HAL_HP_OFFSET_IN_REG_START		1
37 #define HAL_OFFSET_FROM_HP_TO_TP		4
38 
39 #define HAL_SHADOW_REG(x) (HAL_SHADOW_BASE_ADDR + (4 * (x)))
40 
41 /* WCSS Relative address */
42 #define HAL_SEQ_WCSS_UMAC_OFFSET		0x00a00000
43 #define HAL_SEQ_WCSS_UMAC_REO_REG		0x00a38000
44 #define HAL_SEQ_WCSS_UMAC_TCL_REG		0x00a44000
45 #define HAL_SEQ_WCSS_UMAC_CE0_SRC_REG(x) \
46 		(ab->hw_params.regs->hal_seq_wcss_umac_ce0_src_reg)
47 #define HAL_SEQ_WCSS_UMAC_CE0_DST_REG(x) \
48 		(ab->hw_params.regs->hal_seq_wcss_umac_ce0_dst_reg)
49 #define HAL_SEQ_WCSS_UMAC_CE1_SRC_REG(x) \
50 		(ab->hw_params.regs->hal_seq_wcss_umac_ce1_src_reg)
51 #define HAL_SEQ_WCSS_UMAC_CE1_DST_REG(x) \
52 		(ab->hw_params.regs->hal_seq_wcss_umac_ce1_dst_reg)
53 #define HAL_SEQ_WCSS_UMAC_WBM_REG		0x00a34000
54 
55 #define HAL_CE_WFSS_CE_REG_BASE			0x01b80000
56 #define HAL_WLAON_REG_BASE			0x01f80000
57 
58 /* SW2TCL(x) R0 ring configuration address */
59 #define HAL_TCL1_RING_CMN_CTRL_REG		0x00000014
60 #define HAL_TCL1_RING_DSCP_TID_MAP		0x0000002c
61 #define HAL_TCL1_RING_BASE_LSB(ab)		ab->hw_params.regs->hal_tcl1_ring_base_lsb
62 #define HAL_TCL1_RING_BASE_MSB(ab)		ab->hw_params.regs->hal_tcl1_ring_base_msb
63 #define HAL_TCL1_RING_ID(ab)			ab->hw_params.regs->hal_tcl1_ring_id
64 #define HAL_TCL1_RING_MISC(ab)			ab->hw_params.regs->hal_tcl1_ring_misc
65 #define HAL_TCL1_RING_TP_ADDR_LSB(ab) \
66 	ab->hw_params.regs->hal_tcl1_ring_tp_addr_lsb
67 #define HAL_TCL1_RING_TP_ADDR_MSB(ab) \
68 	ab->hw_params.regs->hal_tcl1_ring_tp_addr_msb
69 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(ab) \
70 	ab->hw_params.regs->hal_tcl1_ring_consumer_int_setup_ix0
71 #define HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(ab) \
72 	ab->hw_params.regs->hal_tcl1_ring_consumer_int_setup_ix1
73 #define HAL_TCL1_RING_MSI1_BASE_LSB(ab) \
74 	ab->hw_params.regs->hal_tcl1_ring_msi1_base_lsb
75 #define HAL_TCL1_RING_MSI1_BASE_MSB(ab) \
76 	ab->hw_params.regs->hal_tcl1_ring_msi1_base_msb
77 #define HAL_TCL1_RING_MSI1_DATA(ab) \
78 	ab->hw_params.regs->hal_tcl1_ring_msi1_data
79 #define HAL_TCL2_RING_BASE_LSB(ab)		ab->hw_params.regs->hal_tcl2_ring_base_lsb
80 #define HAL_TCL_RING_BASE_LSB(ab)		ab->hw_params.regs->hal_tcl_ring_base_lsb
81 
82 #define HAL_TCL1_RING_MSI1_BASE_LSB_OFFSET(ab)				\
83 	(HAL_TCL1_RING_MSI1_BASE_LSB(ab) - HAL_TCL1_RING_BASE_LSB(ab))
84 #define HAL_TCL1_RING_MSI1_BASE_MSB_OFFSET(ab)				\
85 	(HAL_TCL1_RING_MSI1_BASE_MSB(ab) - HAL_TCL1_RING_BASE_LSB(ab))
86 #define HAL_TCL1_RING_MSI1_DATA_OFFSET(ab)				\
87 	(HAL_TCL1_RING_MSI1_DATA(ab) - HAL_TCL1_RING_BASE_LSB(ab))
88 #define HAL_TCL1_RING_BASE_MSB_OFFSET(ab)				\
89 	(HAL_TCL1_RING_BASE_MSB(ab) - HAL_TCL1_RING_BASE_LSB(ab))
90 #define HAL_TCL1_RING_ID_OFFSET(ab)				\
91 	(HAL_TCL1_RING_ID(ab) - HAL_TCL1_RING_BASE_LSB(ab))
92 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_OFFSET(ab)			\
93 	(HAL_TCL1_RING_CONSUMER_INT_SETUP_IX0(ab) - HAL_TCL1_RING_BASE_LSB(ab))
94 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_OFFSET(ab) \
95 		(HAL_TCL1_RING_CONSUMER_INT_SETUP_IX1(ab) - HAL_TCL1_RING_BASE_LSB(ab))
96 #define HAL_TCL1_RING_TP_ADDR_LSB_OFFSET(ab) \
97 		(HAL_TCL1_RING_TP_ADDR_LSB(ab) - HAL_TCL1_RING_BASE_LSB(ab))
98 #define HAL_TCL1_RING_TP_ADDR_MSB_OFFSET(ab) \
99 		(HAL_TCL1_RING_TP_ADDR_MSB(ab) - HAL_TCL1_RING_BASE_LSB(ab))
100 #define HAL_TCL1_RING_MISC_OFFSET(ab) \
101 		(HAL_TCL1_RING_MISC(ab) - HAL_TCL1_RING_BASE_LSB(ab))
102 
103 /* SW2TCL(x) R2 ring pointers (head/tail) address */
104 #define HAL_TCL1_RING_HP			0x00002000
105 #define HAL_TCL1_RING_TP			0x00002004
106 #define HAL_TCL2_RING_HP			0x00002008
107 #define HAL_TCL_RING_HP				0x00002018
108 
109 #define HAL_TCL1_RING_TP_OFFSET \
110 		(HAL_TCL1_RING_TP - HAL_TCL1_RING_HP)
111 
112 /* TCL STATUS ring address */
113 #define HAL_TCL_STATUS_RING_BASE_LSB(ab) \
114 	ab->hw_params.regs->hal_tcl_status_ring_base_lsb
115 #define HAL_TCL_STATUS_RING_HP			0x00002030
116 
117 /* REO2SW(x) R0 ring configuration address */
118 #define HAL_REO1_GEN_ENABLE			0x00000000
119 #define HAL_REO1_DEST_RING_CTRL_IX_0		0x00000004
120 #define HAL_REO1_DEST_RING_CTRL_IX_1		0x00000008
121 #define HAL_REO1_DEST_RING_CTRL_IX_2		0x0000000c
122 #define HAL_REO1_DEST_RING_CTRL_IX_3		0x00000010
123 #define HAL_REO1_RING_BASE_LSB(ab)		ab->hw_params.regs->hal_reo1_ring_base_lsb
124 #define HAL_REO1_RING_BASE_MSB(ab)		ab->hw_params.regs->hal_reo1_ring_base_msb
125 #define HAL_REO1_RING_ID(ab)			ab->hw_params.regs->hal_reo1_ring_id
126 #define HAL_REO1_RING_MISC(ab)			ab->hw_params.regs->hal_reo1_ring_misc
127 #define HAL_REO1_RING_HP_ADDR_LSB(ab) \
128 	ab->hw_params.regs->hal_reo1_ring_hp_addr_lsb
129 #define HAL_REO1_RING_HP_ADDR_MSB(ab) \
130 	ab->hw_params.regs->hal_reo1_ring_hp_addr_msb
131 #define HAL_REO1_RING_PRODUCER_INT_SETUP(ab) \
132 	ab->hw_params.regs->hal_reo1_ring_producer_int_setup
133 #define HAL_REO1_RING_MSI1_BASE_LSB(ab) \
134 	ab->hw_params.regs->hal_reo1_ring_msi1_base_lsb
135 #define HAL_REO1_RING_MSI1_BASE_MSB(ab) \
136 	ab->hw_params.regs->hal_reo1_ring_msi1_base_msb
137 #define HAL_REO1_RING_MSI1_DATA(ab) \
138 	ab->hw_params.regs->hal_reo1_ring_msi1_data
139 #define HAL_REO2_RING_BASE_LSB(ab)		ab->hw_params.regs->hal_reo2_ring_base_lsb
140 #define HAL_REO1_AGING_THRESH_IX_0(ab) \
141 	ab->hw_params.regs->hal_reo1_aging_thresh_ix_0
142 #define HAL_REO1_AGING_THRESH_IX_1(ab) \
143 	ab->hw_params.regs->hal_reo1_aging_thresh_ix_1
144 #define HAL_REO1_AGING_THRESH_IX_2(ab) \
145 	ab->hw_params.regs->hal_reo1_aging_thresh_ix_2
146 #define HAL_REO1_AGING_THRESH_IX_3(ab) \
147 	ab->hw_params.regs->hal_reo1_aging_thresh_ix_3
148 
149 #define HAL_REO1_RING_MSI1_BASE_LSB_OFFSET(ab) \
150 		(HAL_REO1_RING_MSI1_BASE_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab))
151 #define HAL_REO1_RING_MSI1_BASE_MSB_OFFSET(ab) \
152 		(HAL_REO1_RING_MSI1_BASE_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab))
153 #define HAL_REO1_RING_MSI1_DATA_OFFSET(ab) \
154 		(HAL_REO1_RING_MSI1_DATA(ab) - HAL_REO1_RING_BASE_LSB(ab))
155 #define HAL_REO1_RING_BASE_MSB_OFFSET(ab) \
156 		(HAL_REO1_RING_BASE_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab))
157 #define HAL_REO1_RING_ID_OFFSET(ab) (HAL_REO1_RING_ID(ab) - HAL_REO1_RING_BASE_LSB(ab))
158 #define HAL_REO1_RING_PRODUCER_INT_SETUP_OFFSET(ab) \
159 		(HAL_REO1_RING_PRODUCER_INT_SETUP(ab) - HAL_REO1_RING_BASE_LSB(ab))
160 #define HAL_REO1_RING_HP_ADDR_LSB_OFFSET(ab) \
161 		(HAL_REO1_RING_HP_ADDR_LSB(ab) - HAL_REO1_RING_BASE_LSB(ab))
162 #define HAL_REO1_RING_HP_ADDR_MSB_OFFSET(ab) \
163 		(HAL_REO1_RING_HP_ADDR_MSB(ab) - HAL_REO1_RING_BASE_LSB(ab))
164 #define HAL_REO1_RING_MISC_OFFSET(ab) \
165 	(HAL_REO1_RING_MISC(ab) - HAL_REO1_RING_BASE_LSB(ab))
166 
167 /* REO2SW(x) R2 ring pointers (head/tail) address */
168 #define HAL_REO1_RING_HP(ab)			ab->hw_params.regs->hal_reo1_ring_hp
169 #define HAL_REO1_RING_TP(ab)			ab->hw_params.regs->hal_reo1_ring_tp
170 #define HAL_REO2_RING_HP(ab)			ab->hw_params.regs->hal_reo2_ring_hp
171 
172 #define HAL_REO1_RING_TP_OFFSET(ab)	(HAL_REO1_RING_TP(ab) - HAL_REO1_RING_HP(ab))
173 
174 /* REO2TCL R0 ring configuration address */
175 #define HAL_REO_TCL_RING_BASE_LSB(ab) \
176 	ab->hw_params.regs->hal_reo_tcl_ring_base_lsb
177 
178 /* REO2TCL R2 ring pointer (head/tail) address */
179 #define HAL_REO_TCL_RING_HP(ab)			ab->hw_params.regs->hal_reo_tcl_ring_hp
180 
181 /* REO CMD R0 address */
182 #define HAL_REO_CMD_RING_BASE_LSB		0x00000194
183 
184 /* REO CMD R2 address */
185 #define HAL_REO_CMD_HP				0x00003020
186 
187 /* SW2REO R0 address */
188 #define HAL_SW2REO_RING_BASE_LSB		0x000001ec
189 
190 /* SW2REO R2 address */
191 #define HAL_SW2REO_RING_HP			0x00003028
192 
193 /* CE ring R0 address */
194 #define HAL_CE_DST_RING_BASE_LSB		0x00000000
195 #define HAL_CE_DST_STATUS_RING_BASE_LSB		0x00000058
196 #define HAL_CE_DST_RING_CTRL			0x000000b0
197 
198 /* CE ring R2 address */
199 #define HAL_CE_DST_RING_HP			0x00000400
200 #define HAL_CE_DST_STATUS_RING_HP		0x00000408
201 
202 /* REO status address */
203 #define HAL_REO_STATUS_RING_BASE_LSB(ab) \
204 	ab->hw_params.regs->hal_reo_status_ring_base_lsb
205 #define HAL_REO_STATUS_HP(ab)			ab->hw_params.regs->hal_reo_status_hp
206 
207 /* WBM Idle R0 address */
208 #define HAL_WBM_IDLE_LINK_RING_BASE_LSB(x) \
209 		(ab->hw_params.regs->hal_wbm_idle_link_ring_base_lsb)
210 #define HAL_WBM_IDLE_LINK_RING_MISC_ADDR(x) \
211 		(ab->hw_params.regs->hal_wbm_idle_link_ring_misc)
212 #define HAL_WBM_R0_IDLE_LIST_CONTROL_ADDR	0x00000048
213 #define HAL_WBM_R0_IDLE_LIST_SIZE_ADDR		0x0000004c
214 #define HAL_WBM_SCATTERED_RING_BASE_LSB		0x00000058
215 #define HAL_WBM_SCATTERED_RING_BASE_MSB		0x0000005c
216 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX0 0x00000068
217 #define HAL_WBM_SCATTERED_DESC_PTR_HEAD_INFO_IX1 0x0000006c
218 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX0 0x00000078
219 #define HAL_WBM_SCATTERED_DESC_PTR_TAIL_INFO_IX1 0x0000007c
220 #define HAL_WBM_SCATTERED_DESC_PTR_HP_ADDR	 0x00000084
221 
222 /* WBM Idle R2 address */
223 #define HAL_WBM_IDLE_LINK_RING_HP		0x000030b0
224 
225 /* SW2WBM R0 release address */
226 #define HAL_WBM_RELEASE_RING_BASE_LSB(x) \
227 		(ab->hw_params.regs->hal_wbm_release_ring_base_lsb)
228 
229 /* SW2WBM R2 release address */
230 #define HAL_WBM_RELEASE_RING_HP			0x00003018
231 
232 /* WBM2SW R0 release address */
233 #define HAL_WBM0_RELEASE_RING_BASE_LSB(x) \
234 		(ab->hw_params.regs->hal_wbm0_release_ring_base_lsb)
235 #define HAL_WBM1_RELEASE_RING_BASE_LSB(x) \
236 		(ab->hw_params.regs->hal_wbm1_release_ring_base_lsb)
237 
238 /* WBM2SW R2 release address */
239 #define HAL_WBM0_RELEASE_RING_HP		0x000030c0
240 #define HAL_WBM1_RELEASE_RING_HP		0x000030c8
241 
242 /* TCL ring feild mask and offset */
243 #define HAL_TCL1_RING_BASE_MSB_RING_SIZE		GENMASK(27, 8)
244 #define HAL_TCL1_RING_BASE_MSB_RING_BASE_ADDR_MSB	GENMASK(7, 0)
245 #define HAL_TCL1_RING_ID_ENTRY_SIZE			GENMASK(7, 0)
246 #define HAL_TCL1_RING_MISC_MSI_LOOPCNT_DISABLE		BIT(1)
247 #define HAL_TCL1_RING_MISC_MSI_SWAP			BIT(3)
248 #define HAL_TCL1_RING_MISC_HOST_FW_SWAP			BIT(4)
249 #define HAL_TCL1_RING_MISC_DATA_TLV_SWAP		BIT(5)
250 #define HAL_TCL1_RING_MISC_SRNG_ENABLE			BIT(6)
251 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_INTR_TMR_THOLD   GENMASK(31, 16)
252 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX0_BATCH_COUNTER_THOLD GENMASK(14, 0)
253 #define HAL_TCL1_RING_CONSR_INT_SETUP_IX1_LOW_THOLD	GENMASK(15, 0)
254 #define HAL_TCL1_RING_MSI1_BASE_MSB_MSI1_ENABLE		BIT(8)
255 #define HAL_TCL1_RING_MSI1_BASE_MSB_ADDR		GENMASK(7, 0)
256 #define HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN	BIT(17)
257 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP		GENMASK(31, 0)
258 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP0		GENMASK(2, 0)
259 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP1		GENMASK(5, 3)
260 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP2		GENMASK(8, 6)
261 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP3		GENMASK(11, 9)
262 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP4		GENMASK(14, 12)
263 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP5		GENMASK(17, 15)
264 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP6		GENMASK(20, 18)
265 #define HAL_TCL1_RING_FIELD_DSCP_TID_MAP7		GENMASK(23, 21)
266 
267 /* REO ring feild mask and offset */
268 #define HAL_REO1_RING_BASE_MSB_RING_SIZE		GENMASK(27, 8)
269 #define HAL_REO1_RING_BASE_MSB_RING_BASE_ADDR_MSB	GENMASK(7, 0)
270 #define HAL_REO1_RING_ID_RING_ID			GENMASK(15, 8)
271 #define HAL_REO1_RING_ID_ENTRY_SIZE			GENMASK(7, 0)
272 #define HAL_REO1_RING_MISC_MSI_SWAP			BIT(3)
273 #define HAL_REO1_RING_MISC_HOST_FW_SWAP			BIT(4)
274 #define HAL_REO1_RING_MISC_DATA_TLV_SWAP		BIT(5)
275 #define HAL_REO1_RING_MISC_SRNG_ENABLE			BIT(6)
276 #define HAL_REO1_RING_PRDR_INT_SETUP_INTR_TMR_THOLD	GENMASK(31, 16)
277 #define HAL_REO1_RING_PRDR_INT_SETUP_BATCH_COUNTER_THOLD GENMASK(14, 0)
278 #define HAL_REO1_RING_MSI1_BASE_MSB_MSI1_ENABLE		BIT(8)
279 #define HAL_REO1_RING_MSI1_BASE_MSB_ADDR		GENMASK(7, 0)
280 #define HAL_REO1_GEN_ENABLE_FRAG_DST_RING		GENMASK(25, 23)
281 #define HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE		BIT(2)
282 #define HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE		BIT(3)
283 
284 /* CE ring bit field mask and shift */
285 #define HAL_CE_DST_R0_DEST_CTRL_MAX_LEN			GENMASK(15, 0)
286 
287 #define HAL_ADDR_LSB_REG_MASK				0xffffffff
288 
289 #define HAL_ADDR_MSB_REG_SHIFT				32
290 
291 /* WBM ring bit field mask and shift */
292 #define HAL_WBM_LINK_DESC_IDLE_LIST_MODE		BIT(1)
293 #define HAL_WBM_SCATTER_BUFFER_SIZE			GENMASK(10, 2)
294 #define HAL_WBM_SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST GENMASK(31, 16)
295 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_39_32	GENMASK(7, 0)
296 #define HAL_WBM_SCATTERED_DESC_MSB_BASE_ADDR_MATCH_TAG	GENMASK(31, 8)
297 
298 #define HAL_WBM_SCATTERED_DESC_HEAD_P_OFFSET_IX1	GENMASK(20, 8)
299 #define HAL_WBM_SCATTERED_DESC_TAIL_P_OFFSET_IX1	GENMASK(20, 8)
300 
301 #define BASE_ADDR_MATCH_TAG_VAL 0x5
302 
303 #define HAL_REO_REO2SW1_RING_BASE_MSB_RING_SIZE		0x000fffff
304 #define HAL_REO_REO2TCL_RING_BASE_MSB_RING_SIZE		0x000fffff
305 #define HAL_REO_SW2REO_RING_BASE_MSB_RING_SIZE		0x0000ffff
306 #define HAL_REO_CMD_RING_BASE_MSB_RING_SIZE		0x0000ffff
307 #define HAL_REO_STATUS_RING_BASE_MSB_RING_SIZE		0x0000ffff
308 #define HAL_SW2TCL1_RING_BASE_MSB_RING_SIZE		0x000fffff
309 #define HAL_SW2TCL1_CMD_RING_BASE_MSB_RING_SIZE		0x000fffff
310 #define HAL_TCL_STATUS_RING_BASE_MSB_RING_SIZE		0x0000ffff
311 #define HAL_CE_SRC_RING_BASE_MSB_RING_SIZE		0x0000ffff
312 #define HAL_CE_DST_RING_BASE_MSB_RING_SIZE		0x0000ffff
313 #define HAL_CE_DST_STATUS_RING_BASE_MSB_RING_SIZE	0x0000ffff
314 #define HAL_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE	0x0000ffff
315 #define HAL_SW2WBM_RELEASE_RING_BASE_MSB_RING_SIZE	0x0000ffff
316 #define HAL_WBM2SW_RELEASE_RING_BASE_MSB_RING_SIZE	0x000fffff
317 #define HAL_RXDMA_RING_MAX_SIZE				0x0000ffff
318 
319 /* Add any other errors here and return them in
320  * ath11k_hal_rx_desc_get_err().
321  */
322 
323 enum hal_srng_ring_id {
324 	HAL_SRNG_RING_ID_REO2SW1 = 0,
325 	HAL_SRNG_RING_ID_REO2SW2,
326 	HAL_SRNG_RING_ID_REO2SW3,
327 	HAL_SRNG_RING_ID_REO2SW4,
328 	HAL_SRNG_RING_ID_REO2TCL,
329 	HAL_SRNG_RING_ID_SW2REO,
330 
331 	HAL_SRNG_RING_ID_REO_CMD = 8,
332 	HAL_SRNG_RING_ID_REO_STATUS,
333 
334 	HAL_SRNG_RING_ID_SW2TCL1 = 16,
335 	HAL_SRNG_RING_ID_SW2TCL2,
336 	HAL_SRNG_RING_ID_SW2TCL3,
337 	HAL_SRNG_RING_ID_SW2TCL4,
338 
339 	HAL_SRNG_RING_ID_SW2TCL_CMD = 24,
340 	HAL_SRNG_RING_ID_TCL_STATUS,
341 
342 	HAL_SRNG_RING_ID_CE0_SRC = 32,
343 	HAL_SRNG_RING_ID_CE1_SRC,
344 	HAL_SRNG_RING_ID_CE2_SRC,
345 	HAL_SRNG_RING_ID_CE3_SRC,
346 	HAL_SRNG_RING_ID_CE4_SRC,
347 	HAL_SRNG_RING_ID_CE5_SRC,
348 	HAL_SRNG_RING_ID_CE6_SRC,
349 	HAL_SRNG_RING_ID_CE7_SRC,
350 	HAL_SRNG_RING_ID_CE8_SRC,
351 	HAL_SRNG_RING_ID_CE9_SRC,
352 	HAL_SRNG_RING_ID_CE10_SRC,
353 	HAL_SRNG_RING_ID_CE11_SRC,
354 
355 	HAL_SRNG_RING_ID_CE0_DST = 56,
356 	HAL_SRNG_RING_ID_CE1_DST,
357 	HAL_SRNG_RING_ID_CE2_DST,
358 	HAL_SRNG_RING_ID_CE3_DST,
359 	HAL_SRNG_RING_ID_CE4_DST,
360 	HAL_SRNG_RING_ID_CE5_DST,
361 	HAL_SRNG_RING_ID_CE6_DST,
362 	HAL_SRNG_RING_ID_CE7_DST,
363 	HAL_SRNG_RING_ID_CE8_DST,
364 	HAL_SRNG_RING_ID_CE9_DST,
365 	HAL_SRNG_RING_ID_CE10_DST,
366 	HAL_SRNG_RING_ID_CE11_DST,
367 
368 	HAL_SRNG_RING_ID_CE0_DST_STATUS = 80,
369 	HAL_SRNG_RING_ID_CE1_DST_STATUS,
370 	HAL_SRNG_RING_ID_CE2_DST_STATUS,
371 	HAL_SRNG_RING_ID_CE3_DST_STATUS,
372 	HAL_SRNG_RING_ID_CE4_DST_STATUS,
373 	HAL_SRNG_RING_ID_CE5_DST_STATUS,
374 	HAL_SRNG_RING_ID_CE6_DST_STATUS,
375 	HAL_SRNG_RING_ID_CE7_DST_STATUS,
376 	HAL_SRNG_RING_ID_CE8_DST_STATUS,
377 	HAL_SRNG_RING_ID_CE9_DST_STATUS,
378 	HAL_SRNG_RING_ID_CE10_DST_STATUS,
379 	HAL_SRNG_RING_ID_CE11_DST_STATUS,
380 
381 	HAL_SRNG_RING_ID_WBM_IDLE_LINK = 104,
382 	HAL_SRNG_RING_ID_WBM_SW_RELEASE,
383 	HAL_SRNG_RING_ID_WBM2SW0_RELEASE,
384 	HAL_SRNG_RING_ID_WBM2SW1_RELEASE,
385 	HAL_SRNG_RING_ID_WBM2SW2_RELEASE,
386 	HAL_SRNG_RING_ID_WBM2SW3_RELEASE,
387 
388 	HAL_SRNG_RING_ID_UMAC_ID_END = 127,
389 	HAL_SRNG_RING_ID_LMAC1_ID_START,
390 
391 	HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_BUF = HAL_SRNG_RING_ID_LMAC1_ID_START,
392 	HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_BUF,
393 	HAL_SRNG_RING_ID_WMAC1_SW2RXDMA2_BUF,
394 	HAL_SRNG_RING_ID_WMAC1_SW2RXDMA0_STATBUF,
395 	HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_STATBUF,
396 	HAL_SRNG_RING_ID_WMAC1_RXDMA2SW0,
397 	HAL_SRNG_RING_ID_WMAC1_RXDMA2SW1,
398 	HAL_SRNG_RING_ID_WMAC1_SW2RXDMA1_DESC,
399 	HAL_SRNG_RING_ID_RXDMA_DIR_BUF,
400 
401 	HAL_SRNG_RING_ID_LMAC1_ID_END = 143
402 };
403 
404 /* SRNG registers are split into two groups R0 and R2 */
405 #define HAL_SRNG_REG_GRP_R0	0
406 #define HAL_SRNG_REG_GRP_R2	1
407 #define HAL_SRNG_NUM_REG_GRP    2
408 
409 #define HAL_SRNG_NUM_LMACS      3
410 #define HAL_SRNG_REO_EXCEPTION  HAL_SRNG_RING_ID_REO2SW1
411 #define HAL_SRNG_RINGS_PER_LMAC (HAL_SRNG_RING_ID_LMAC1_ID_END - \
412 				 HAL_SRNG_RING_ID_LMAC1_ID_START)
413 #define HAL_SRNG_NUM_LMAC_RINGS (HAL_SRNG_NUM_LMACS * HAL_SRNG_RINGS_PER_LMAC)
414 #define HAL_SRNG_RING_ID_MAX    (HAL_SRNG_RING_ID_UMAC_ID_END + \
415 				 HAL_SRNG_NUM_LMAC_RINGS)
416 
417 enum hal_ring_type {
418 	HAL_REO_DST,
419 	HAL_REO_EXCEPTION,
420 	HAL_REO_REINJECT,
421 	HAL_REO_CMD,
422 	HAL_REO_STATUS,
423 	HAL_TCL_DATA,
424 	HAL_TCL_CMD,
425 	HAL_TCL_STATUS,
426 	HAL_CE_SRC,
427 	HAL_CE_DST,
428 	HAL_CE_DST_STATUS,
429 	HAL_WBM_IDLE_LINK,
430 	HAL_SW2WBM_RELEASE,
431 	HAL_WBM2SW_RELEASE,
432 	HAL_RXDMA_BUF,
433 	HAL_RXDMA_DST,
434 	HAL_RXDMA_MONITOR_BUF,
435 	HAL_RXDMA_MONITOR_STATUS,
436 	HAL_RXDMA_MONITOR_DST,
437 	HAL_RXDMA_MONITOR_DESC,
438 	HAL_RXDMA_DIR_BUF,
439 	HAL_MAX_RING_TYPES,
440 };
441 
442 #define HAL_RX_MAX_BA_WINDOW	256
443 
444 #define HAL_DEFAULT_REO_TIMEOUT_USEC		(40 * 1000)
445 
446 /**
447  * enum hal_reo_cmd_type: Enum for REO command type
448  * @CMD_GET_QUEUE_STATS: Get REO queue status/stats
449  * @CMD_FLUSH_QUEUE: Flush all frames in REO queue
450  * @CMD_FLUSH_CACHE: Flush descriptor entries in the cache
451  * @CMD_UNBLOCK_CACHE: Unblock a descriptor's address that was blocked
452  *      earlier with a 'REO_FLUSH_CACHE' command
453  * @CMD_FLUSH_TIMEOUT_LIST: Flush buffers/descriptors from timeout list
454  * @CMD_UPDATE_RX_REO_QUEUE: Update REO queue settings
455  */
456 enum hal_reo_cmd_type {
457 	HAL_REO_CMD_GET_QUEUE_STATS     = 0,
458 	HAL_REO_CMD_FLUSH_QUEUE         = 1,
459 	HAL_REO_CMD_FLUSH_CACHE         = 2,
460 	HAL_REO_CMD_UNBLOCK_CACHE       = 3,
461 	HAL_REO_CMD_FLUSH_TIMEOUT_LIST  = 4,
462 	HAL_REO_CMD_UPDATE_RX_QUEUE     = 5,
463 };
464 
465 /**
466  * enum hal_reo_cmd_status: Enum for execution status of REO command
467  * @HAL_REO_CMD_SUCCESS: Command has successfully executed
468  * @HAL_REO_CMD_BLOCKED: Command could not be executed as the queue
469  *			 or cache was blocked
470  * @HAL_REO_CMD_FAILED: Command execution failed, could be due to
471  *			invalid queue desc
472  * @HAL_REO_CMD_RESOURCE_BLOCKED:
473  * @HAL_REO_CMD_DRAIN:
474  */
475 enum hal_reo_cmd_status {
476 	HAL_REO_CMD_SUCCESS		= 0,
477 	HAL_REO_CMD_BLOCKED		= 1,
478 	HAL_REO_CMD_FAILED		= 2,
479 	HAL_REO_CMD_RESOURCE_BLOCKED	= 3,
480 	HAL_REO_CMD_DRAIN		= 0xff,
481 };
482 
483 struct hal_wbm_idle_scatter_list {
484 	dma_addr_t paddr;
485 	struct hal_wbm_link_desc *vaddr;
486 };
487 
488 struct hal_srng_params {
489 	dma_addr_t ring_base_paddr;
490 	u32 *ring_base_vaddr;
491 	int num_entries;
492 	u32 intr_batch_cntr_thres_entries;
493 	u32 intr_timer_thres_us;
494 	u32 flags;
495 	u32 max_buffer_len;
496 	u32 low_threshold;
497 	dma_addr_t msi_addr;
498 	u32 msi_data;
499 
500 	/* Add more params as needed */
501 };
502 
503 enum hal_srng_dir {
504 	HAL_SRNG_DIR_SRC,
505 	HAL_SRNG_DIR_DST
506 };
507 
508 /* srng flags */
509 #define HAL_SRNG_FLAGS_MSI_SWAP			0x00000008
510 #define HAL_SRNG_FLAGS_RING_PTR_SWAP		0x00000010
511 #define HAL_SRNG_FLAGS_DATA_TLV_SWAP		0x00000020
512 #define HAL_SRNG_FLAGS_LOW_THRESH_INTR_EN	0x00010000
513 #define HAL_SRNG_FLAGS_MSI_INTR			0x00020000
514 #define HAL_SRNG_FLAGS_LMAC_RING		0x80000000
515 
516 #define HAL_SRNG_TLV_HDR_TAG		GENMASK(9, 1)
517 #define HAL_SRNG_TLV_HDR_LEN		GENMASK(25, 10)
518 
519 /* Common SRNG ring structure for source and destination rings */
520 struct hal_srng {
521 	/* Unique SRNG ring ID */
522 	u8 ring_id;
523 
524 	/* Ring initialization done */
525 	u8 initialized;
526 
527 	/* Interrupt/MSI value assigned to this ring */
528 	int irq;
529 
530 	/* Physical base address of the ring */
531 	dma_addr_t ring_base_paddr;
532 
533 	/* Virtual base address of the ring */
534 	u32 *ring_base_vaddr;
535 
536 	/* Number of entries in ring */
537 	u32 num_entries;
538 
539 	/* Ring size */
540 	u32 ring_size;
541 
542 	/* Ring size mask */
543 	u32 ring_size_mask;
544 
545 	/* Size of ring entry */
546 	u32 entry_size;
547 
548 	/* Interrupt timer threshold - in micro seconds */
549 	u32 intr_timer_thres_us;
550 
551 	/* Interrupt batch counter threshold - in number of ring entries */
552 	u32 intr_batch_cntr_thres_entries;
553 
554 	/* MSI Address */
555 	dma_addr_t msi_addr;
556 
557 	/* MSI data */
558 	u32 msi_data;
559 
560 	/* Misc flags */
561 	u32 flags;
562 
563 	/* Lock for serializing ring index updates */
564 	spinlock_t lock;
565 
566 	/* Start offset of SRNG register groups for this ring
567 	 * TBD: See if this is required - register address can be derived
568 	 * from ring ID
569 	 */
570 	u32 hwreg_base[HAL_SRNG_NUM_REG_GRP];
571 
572 	u64 timestamp;
573 
574 	/* Source or Destination ring */
575 	enum hal_srng_dir ring_dir;
576 
577 	union {
578 		struct {
579 			/* SW tail pointer */
580 			u32 tp;
581 
582 			/* Shadow head pointer location to be updated by HW */
583 			volatile u32 *hp_addr;
584 
585 			/* Cached head pointer */
586 			u32 cached_hp;
587 
588 			/* Tail pointer location to be updated by SW - This
589 			 * will be a register address and need not be
590 			 * accessed through SW structure
591 			 */
592 			u32 *tp_addr;
593 
594 			/* Current SW loop cnt */
595 			u32 loop_cnt;
596 
597 			/* max transfer size */
598 			u16 max_buffer_length;
599 
600 			/* head pointer at access end */
601 			u32 last_hp;
602 		} dst_ring;
603 
604 		struct {
605 			/* SW head pointer */
606 			u32 hp;
607 
608 			/* SW reap head pointer */
609 			u32 reap_hp;
610 
611 			/* Shadow tail pointer location to be updated by HW */
612 			u32 *tp_addr;
613 
614 			/* Cached tail pointer */
615 			u32 cached_tp;
616 
617 			/* Head pointer location to be updated by SW - This
618 			 * will be a register address and need not be accessed
619 			 * through SW structure
620 			 */
621 			u32 *hp_addr;
622 
623 			/* Low threshold - in number of ring entries */
624 			u32 low_threshold;
625 
626 			/* tail pointer at access end */
627 			u32 last_tp;
628 		} src_ring;
629 	} u;
630 };
631 
632 /* Interrupt mitigation - Batch threshold in terms of numer of frames */
633 #define HAL_SRNG_INT_BATCH_THRESHOLD_TX 256
634 #define HAL_SRNG_INT_BATCH_THRESHOLD_RX 128
635 #define HAL_SRNG_INT_BATCH_THRESHOLD_OTHER 1
636 
637 /* Interrupt mitigation - timer threshold in us */
638 #define HAL_SRNG_INT_TIMER_THRESHOLD_TX 1000
639 #define HAL_SRNG_INT_TIMER_THRESHOLD_RX 500
640 #define HAL_SRNG_INT_TIMER_THRESHOLD_OTHER 256
641 
642 /* HW SRNG configuration table */
643 struct hal_srng_config {
644 	int start_ring_id;
645 	u16 max_rings;
646 	u16 entry_size;
647 	u32 reg_start[HAL_SRNG_NUM_REG_GRP];
648 	u16 reg_size[HAL_SRNG_NUM_REG_GRP];
649 	u8 lmac_ring;
650 	enum hal_srng_dir ring_dir;
651 	u32 max_size;
652 };
653 
654 /**
655  * enum hal_rx_buf_return_buf_manager
656  *
657  * @HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST: Buffer returned to WBM idle buffer list
658  * @HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST: Descriptor returned to WBM idle
659  *	descriptor list.
660  * @HAL_RX_BUF_RBM_FW_BM: Buffer returned to FW
661  * @HAL_RX_BUF_RBM_SW0_BM: For Tx completion -- returned to host
662  * @HAL_RX_BUF_RBM_SW1_BM: For Tx completion -- returned to host
663  * @HAL_RX_BUF_RBM_SW2_BM: For Tx completion -- returned to host
664  * @HAL_RX_BUF_RBM_SW3_BM: For Rx release -- returned to host
665  */
666 
667 enum hal_rx_buf_return_buf_manager {
668 	HAL_RX_BUF_RBM_WBM_IDLE_BUF_LIST,
669 	HAL_RX_BUF_RBM_WBM_IDLE_DESC_LIST,
670 	HAL_RX_BUF_RBM_FW_BM,
671 	HAL_RX_BUF_RBM_SW0_BM,
672 	HAL_RX_BUF_RBM_SW1_BM,
673 	HAL_RX_BUF_RBM_SW2_BM,
674 	HAL_RX_BUF_RBM_SW3_BM,
675 };
676 
677 #define HAL_SRNG_DESC_LOOP_CNT		0xf0000000
678 
679 #define HAL_REO_CMD_FLG_NEED_STATUS		BIT(0)
680 #define HAL_REO_CMD_FLG_STATS_CLEAR		BIT(1)
681 #define HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER	BIT(2)
682 #define HAL_REO_CMD_FLG_FLUSH_RELEASE_BLOCKING	BIT(3)
683 #define HAL_REO_CMD_FLG_FLUSH_NO_INVAL		BIT(4)
684 #define HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS	BIT(5)
685 #define HAL_REO_CMD_FLG_FLUSH_ALL		BIT(6)
686 #define HAL_REO_CMD_FLG_UNBLK_RESOURCE		BIT(7)
687 #define HAL_REO_CMD_FLG_UNBLK_CACHE		BIT(8)
688 
689 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO0_UPD_* feilds */
690 #define HAL_REO_CMD_UPD0_RX_QUEUE_NUM		BIT(8)
691 #define HAL_REO_CMD_UPD0_VLD			BIT(9)
692 #define HAL_REO_CMD_UPD0_ALDC			BIT(10)
693 #define HAL_REO_CMD_UPD0_DIS_DUP_DETECTION	BIT(11)
694 #define HAL_REO_CMD_UPD0_SOFT_REORDER_EN	BIT(12)
695 #define HAL_REO_CMD_UPD0_AC			BIT(13)
696 #define HAL_REO_CMD_UPD0_BAR			BIT(14)
697 #define HAL_REO_CMD_UPD0_RETRY			BIT(15)
698 #define HAL_REO_CMD_UPD0_CHECK_2K_MODE		BIT(16)
699 #define HAL_REO_CMD_UPD0_OOR_MODE		BIT(17)
700 #define HAL_REO_CMD_UPD0_BA_WINDOW_SIZE		BIT(18)
701 #define HAL_REO_CMD_UPD0_PN_CHECK		BIT(19)
702 #define HAL_REO_CMD_UPD0_EVEN_PN		BIT(20)
703 #define HAL_REO_CMD_UPD0_UNEVEN_PN		BIT(21)
704 #define HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE	BIT(22)
705 #define HAL_REO_CMD_UPD0_PN_SIZE		BIT(23)
706 #define HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG	BIT(24)
707 #define HAL_REO_CMD_UPD0_SVLD			BIT(25)
708 #define HAL_REO_CMD_UPD0_SSN			BIT(26)
709 #define HAL_REO_CMD_UPD0_SEQ_2K_ERR		BIT(27)
710 #define HAL_REO_CMD_UPD0_PN_ERR			BIT(28)
711 #define HAL_REO_CMD_UPD0_PN_VALID		BIT(29)
712 #define HAL_REO_CMD_UPD0_PN			BIT(30)
713 
714 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO1_* feilds */
715 #define HAL_REO_CMD_UPD1_VLD			BIT(16)
716 #define HAL_REO_CMD_UPD1_ALDC			GENMASK(18, 17)
717 #define HAL_REO_CMD_UPD1_DIS_DUP_DETECTION	BIT(19)
718 #define HAL_REO_CMD_UPD1_SOFT_REORDER_EN	BIT(20)
719 #define HAL_REO_CMD_UPD1_AC			GENMASK(22, 21)
720 #define HAL_REO_CMD_UPD1_BAR			BIT(23)
721 #define HAL_REO_CMD_UPD1_RETRY			BIT(24)
722 #define HAL_REO_CMD_UPD1_CHECK_2K_MODE		BIT(25)
723 #define HAL_REO_CMD_UPD1_OOR_MODE		BIT(26)
724 #define HAL_REO_CMD_UPD1_PN_CHECK		BIT(27)
725 #define HAL_REO_CMD_UPD1_EVEN_PN		BIT(28)
726 #define HAL_REO_CMD_UPD1_UNEVEN_PN		BIT(29)
727 #define HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE	BIT(30)
728 #define HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG	BIT(31)
729 
730 /* Should be matching with HAL_REO_UPD_RX_QUEUE_INFO2_* feilds */
731 #define HAL_REO_CMD_UPD2_SVLD			BIT(10)
732 #define HAL_REO_CMD_UPD2_SSN			GENMASK(22, 11)
733 #define HAL_REO_CMD_UPD2_SEQ_2K_ERR		BIT(23)
734 #define HAL_REO_CMD_UPD2_PN_ERR			BIT(24)
735 
736 #define HAL_REO_DEST_RING_CTRL_HASH_RING_MAP	GENMASK(31, 8)
737 
738 struct ath11k_hal_reo_cmd {
739 	u32 addr_lo;
740 	u32 flag;
741 	u32 upd0;
742 	u32 upd1;
743 	u32 upd2;
744 	u32 pn[4];
745 	u16 rx_queue_num;
746 	u16 min_rel;
747 	u16 min_fwd;
748 	u8 addr_hi;
749 	u8 ac_list;
750 	u8 blocking_idx;
751 	u16 ba_window_size;
752 	u8 pn_size;
753 };
754 
755 enum hal_pn_type {
756 	HAL_PN_TYPE_NONE,
757 	HAL_PN_TYPE_WPA,
758 	HAL_PN_TYPE_WAPI_EVEN,
759 	HAL_PN_TYPE_WAPI_UNEVEN,
760 };
761 
762 enum hal_ce_desc {
763 	HAL_CE_DESC_SRC,
764 	HAL_CE_DESC_DST,
765 	HAL_CE_DESC_DST_STATUS,
766 };
767 
768 #define HAL_HASH_ROUTING_RING_TCL 0
769 #define HAL_HASH_ROUTING_RING_SW1 1
770 #define HAL_HASH_ROUTING_RING_SW2 2
771 #define HAL_HASH_ROUTING_RING_SW3 3
772 #define HAL_HASH_ROUTING_RING_SW4 4
773 #define HAL_HASH_ROUTING_RING_REL 5
774 #define HAL_HASH_ROUTING_RING_FW  6
775 
776 struct hal_reo_status_header {
777 	u16 cmd_num;
778 	enum hal_reo_cmd_status cmd_status;
779 	u16 cmd_exe_time;
780 	u32 timestamp;
781 };
782 
783 struct hal_reo_status_queue_stats {
784 	u16 ssn;
785 	u16 curr_idx;
786 	u32 pn[4];
787 	u32 last_rx_queue_ts;
788 	u32 last_rx_dequeue_ts;
789 	u32 rx_bitmap[8]; /* Bitmap from 0-255 */
790 	u32 curr_mpdu_cnt;
791 	u32 curr_msdu_cnt;
792 	u16 fwd_due_to_bar_cnt;
793 	u16 dup_cnt;
794 	u32 frames_in_order_cnt;
795 	u32 num_mpdu_processed_cnt;
796 	u32 num_msdu_processed_cnt;
797 	u32 total_num_processed_byte_cnt;
798 	u32 late_rx_mpdu_cnt;
799 	u32 reorder_hole_cnt;
800 	u8 timeout_cnt;
801 	u8 bar_rx_cnt;
802 	u8 num_window_2k_jump_cnt;
803 };
804 
805 struct hal_reo_status_flush_queue {
806 	bool err_detected;
807 };
808 
809 enum hal_reo_status_flush_cache_err_code {
810 	HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_SUCCESS,
811 	HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_IN_USE,
812 	HAL_REO_STATUS_FLUSH_CACHE_ERR_CODE_NOT_FOUND,
813 };
814 
815 struct hal_reo_status_flush_cache {
816 	bool err_detected;
817 	enum hal_reo_status_flush_cache_err_code err_code;
818 	bool cache_controller_flush_status_hit;
819 	u8 cache_controller_flush_status_desc_type;
820 	u8 cache_controller_flush_status_client_id;
821 	u8 cache_controller_flush_status_err;
822 	u8 cache_controller_flush_status_cnt;
823 };
824 
825 enum hal_reo_status_unblock_cache_type {
826 	HAL_REO_STATUS_UNBLOCK_BLOCKING_RESOURCE,
827 	HAL_REO_STATUS_UNBLOCK_ENTIRE_CACHE_USAGE,
828 };
829 
830 struct hal_reo_status_unblock_cache {
831 	bool err_detected;
832 	enum hal_reo_status_unblock_cache_type unblock_type;
833 };
834 
835 struct hal_reo_status_flush_timeout_list {
836 	bool err_detected;
837 	bool list_empty;
838 	u16 release_desc_cnt;
839 	u16 fwd_buf_cnt;
840 };
841 
842 enum hal_reo_threshold_idx {
843 	HAL_REO_THRESHOLD_IDX_DESC_COUNTER0,
844 	HAL_REO_THRESHOLD_IDX_DESC_COUNTER1,
845 	HAL_REO_THRESHOLD_IDX_DESC_COUNTER2,
846 	HAL_REO_THRESHOLD_IDX_DESC_COUNTER_SUM,
847 };
848 
849 struct hal_reo_status_desc_thresh_reached {
850 	enum hal_reo_threshold_idx threshold_idx;
851 	u32 link_desc_counter0;
852 	u32 link_desc_counter1;
853 	u32 link_desc_counter2;
854 	u32 link_desc_counter_sum;
855 };
856 
857 struct hal_reo_status {
858 	struct hal_reo_status_header uniform_hdr;
859 	u8 loop_cnt;
860 	union {
861 		struct hal_reo_status_queue_stats queue_stats;
862 		struct hal_reo_status_flush_queue flush_queue;
863 		struct hal_reo_status_flush_cache flush_cache;
864 		struct hal_reo_status_unblock_cache unblock_cache;
865 		struct hal_reo_status_flush_timeout_list timeout_list;
866 		struct hal_reo_status_desc_thresh_reached desc_thresh_reached;
867 	} u;
868 };
869 
870 /**
871  * HAL context to be used to access SRNG APIs (currently used by data path
872  * and transport (CE) modules)
873  */
874 struct ath11k_hal {
875 	/* HAL internal state for all SRNG rings.
876 	 */
877 	struct hal_srng srng_list[HAL_SRNG_RING_ID_MAX];
878 
879 	/* SRNG configuration table */
880 	struct hal_srng_config *srng_config;
881 
882 	/* Remote pointer memory for HW/FW updates */
883 	struct {
884 		u32 *vaddr;
885 		dma_addr_t paddr;
886 	} rdp;
887 
888 	/* Shared memory for ring pointer updates from host to FW */
889 	struct {
890 		u32 *vaddr;
891 		dma_addr_t paddr;
892 	} wrp;
893 
894 	/* Available REO blocking resources bitmap */
895 	u8 avail_blk_resource;
896 
897 	u8 current_blk_index;
898 
899 	/* shadow register configuration */
900 	u32 shadow_reg_addr[HAL_SHADOW_NUM_REGS];
901 	int num_shadow_reg_configured;
902 };
903 
904 u32 ath11k_hal_reo_qdesc_size(u32 ba_window_size, u8 tid);
905 void ath11k_hal_reo_qdesc_setup(void *vaddr, int tid, u32 ba_window_size,
906 				u32 start_seq, enum hal_pn_type type);
907 void ath11k_hal_reo_init_cmd_ring(struct ath11k_base *ab,
908 				  struct hal_srng *srng);
909 void ath11k_hal_reo_hw_setup(struct ath11k_base *ab, u32 ring_hash_map);
910 void ath11k_hal_setup_link_idle_list(struct ath11k_base *ab,
911 				     struct hal_wbm_idle_scatter_list *sbuf,
912 				     u32 nsbufs, u32 tot_link_desc,
913 				     u32 end_offset);
914 
915 dma_addr_t ath11k_hal_srng_get_tp_addr(struct ath11k_base *ab,
916 				       struct hal_srng *srng);
917 dma_addr_t ath11k_hal_srng_get_hp_addr(struct ath11k_base *ab,
918 				       struct hal_srng *srng);
919 void ath11k_hal_set_link_desc_addr(struct hal_wbm_link_desc *desc, u32 cookie,
920 				   dma_addr_t paddr);
921 u32 ath11k_hal_ce_get_desc_size(enum hal_ce_desc type);
922 void ath11k_hal_ce_src_set_desc(void *buf, dma_addr_t paddr, u32 len, u32 id,
923 				u8 byte_swap_data);
924 void ath11k_hal_ce_dst_set_desc(void *buf, dma_addr_t paddr);
925 u32 ath11k_hal_ce_dst_status_get_length(void *buf);
926 int ath11k_hal_srng_get_entrysize(struct ath11k_base *ab, u32 ring_type);
927 int ath11k_hal_srng_get_max_entries(struct ath11k_base *ab, u32 ring_type);
928 void ath11k_hal_srng_get_params(struct ath11k_base *ab, struct hal_srng *srng,
929 				struct hal_srng_params *params);
930 u32 *ath11k_hal_srng_dst_get_next_entry(struct ath11k_base *ab,
931 					struct hal_srng *srng);
932 u32 *ath11k_hal_srng_dst_peek(struct ath11k_base *ab, struct hal_srng *srng);
933 int ath11k_hal_srng_dst_num_free(struct ath11k_base *ab, struct hal_srng *srng,
934 				 bool sync_hw_ptr);
935 u32 *ath11k_hal_srng_src_peek(struct ath11k_base *ab, struct hal_srng *srng);
936 u32 *ath11k_hal_srng_src_get_next_reaped(struct ath11k_base *ab,
937 					 struct hal_srng *srng);
938 u32 *ath11k_hal_srng_src_reap_next(struct ath11k_base *ab,
939 				   struct hal_srng *srng);
940 u32 *ath11k_hal_srng_src_get_next_entry(struct ath11k_base *ab,
941 					struct hal_srng *srng);
942 int ath11k_hal_srng_src_num_free(struct ath11k_base *ab, struct hal_srng *srng,
943 				 bool sync_hw_ptr);
944 void ath11k_hal_srng_access_begin(struct ath11k_base *ab,
945 				  struct hal_srng *srng);
946 void ath11k_hal_srng_access_end(struct ath11k_base *ab, struct hal_srng *srng);
947 int ath11k_hal_srng_setup(struct ath11k_base *ab, enum hal_ring_type type,
948 			  int ring_num, int mac_id,
949 			  struct hal_srng_params *params);
950 int ath11k_hal_srng_init(struct ath11k_base *ath11k);
951 void ath11k_hal_srng_deinit(struct ath11k_base *ath11k);
952 void ath11k_hal_dump_srng_stats(struct ath11k_base *ab);
953 void ath11k_hal_srng_get_shadow_config(struct ath11k_base *ab,
954 				       u32 **cfg, u32 *len);
955 int ath11k_hal_srng_update_shadow_config(struct ath11k_base *ab,
956 					 enum hal_ring_type ring_type,
957 					int ring_num);
958 void ath11k_hal_srng_shadow_config(struct ath11k_base *ab);
959 void ath11k_hal_srng_shadow_update_hp_tp(struct ath11k_base *ab,
960 					 struct hal_srng *srng);
961 #endif
962